Peak current and programming time optimization through cyclically correlated voltage ramp targets and timing control

Abstract

This invention discloses an apparatus comprising a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry communicating with the plurality of control lines. The control circuitry is configured to, during a first period of a control line pre-charging phase, charge one or more unselected control lines among the plurality of control lines for a certain period of time using an regulated charging current, based at least in part on predicted parasitic capacitances associated with the programming state of the control lines; and during a second period of the control line pre-charging phase, charge one or more unselected bit lines to a disabled voltage level using an unregulated charging current.

Description

Technical Field

[0001] This technology relates to electrical storage devices. More specifically, this disclosure relates to systems and methods for optimizing peak current and minimizing the impact of programming time during cyclic correlation control of voltage ramp targets. Background Technology

[0002] In some computing systems, such as solid-state memory or data storage systems, high peak current levels can adversely affect performance and / or efficiency. While existing methods have been attempted to reduce peak current levels during programming, they typically introduce undesirable side effects, such as a significant increase in programming time, which in turn significantly slows down the operation of memory components.

[0003] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, and so on. In EEPROM or NAND flash array architectures, memory cells can be arranged in a matrix of rows and columns, such that the gate of each memory cell is coupled to a word line via a row. Memory cells can be arranged together in a string, such that the memory cells in a given string are coupled together in series from source to drain between a common source line and a common bit line. More specifically, one of the most challenging issues in current NAND flash memory design is reducing peak current consumption (peak ICC), as it can lead to a drop in peak power, which can cause failures in NAND flash memory. However, previous methods for reducing peak ICC have also introduced unacceptable performance degradation, particularly by increasing the programming time of the affected memory device and reducing operational performance. Summary of the Invention

[0004] An apparatus is provided comprising a plurality of solid-state memory elements, a plurality of control lines coupled to the plurality of solid-state memory elements, and control circuitry communicating with the plurality of control lines. The control circuitry is configured to, during a first phase of a control line pre-charge stage, charge one or more unselected control lines among the plurality of control lines for a certain period of time using an regulated charging current, based at least in part on predicted parasitic capacitances associated with the programming state of the control lines; and during a second phase of the control line pre-charge stage, charge one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

[0005] This disclosure provides various aspects of the threshold detection parameter V HSATGTCyclic adjustments are made to allow for reduction of large peak ICC current spikes, while optimizing total programming time at a lower tprog cost than non-dynamic methods. Aspects of this disclosure utilize analysis of potential data patterns on the control line to predict the bit-line capacitive load for each cycle of the programming cycle, and then apply a regulated to unregulated charging threshold parameter V to each pulse differently based on the expected capacitance. HSATGT .

[0006] A non-volatile memory device is provided, having a plurality of memory cells electrically coupled to a plurality of bit lines; and control circuitry coupled to the plurality of memory cells and configured to perform the following steps: determining cycle-dependent programming adjustment parameters based on programming cycles of the plurality of memory cells; performing programming and verification operations on the plurality of memory cells modified by the cycle-dependent programming adjustment parameters; and wherein the cycle-dependent programming adjustment parameters are determined based on the relative capacitances of the plurality of bit lines electrically connected to the plurality of memory cells. The control circuitry may provide any desired functionality, including being further configured to perform the following steps: determining the position of a programming cycle in a programming cycle sequence to complete the programming operations on the plurality of memory cells, and wherein the determination of the cycle-dependent programming adjustment parameters is further based on the position of the cycle within the programming cycle sequence. Furthermore, in non-volatile memory devices, the position of a loop within the programming control circuit sequence can be determined to be one of the following: a start segment, an intermediate segment, or an end segment. If the loop position is within the start segment, the adjustment parameter is set to a first lower value; if the loop position is within the intermediate segment, the adjustment parameter is set to a higher value; and if the loop position is within the end segment, the adjustment parameter is set to a second lower value. The relative capacitance of multiple bit lines can be determined in any desired manner, such as based on the configuration of the disable voltage or programming voltage assigned to the multiple bit lines respectively. Furthermore, the relative capacitance of multiple bit lines can also be determined based on the corresponding programming states of multiple memory cells.

[0007] Various aspects of this disclosure reduce the peak ICC current of the memory device. In this regard, modifying the programming and verification operations for multiple memory cells can result in a reduction in the peak current utilization of the memory device. Furthermore, any parameters used by the memory device or its control system can be adjusted to provide operational improvements, at least for peak current management and timing / operation management. In one aspect, programming adjustment parameters include a voltage detection threshold for prohibiting voltage charging of a corresponding bit line; in another aspect, programming adjustment parameters include a bit line equalization time value for the programming recovery period of the programming cycle; and in yet another aspect, programming adjustment parameters include a bit line setting for the read voltage time value for the programming verification / read period of the programming cycle. Cyclic programming adjustment parameters can be based on the voltage threshold state of at least one memory cell in the memory cells of the memory device. In addition to the storage devices described above, the method disclosed herein can describe steps for controlling a non-volatile memory device including a plurality of memory cells electrically coupled to a plurality of bit lines, and control circuitry coupled to the plurality of memory cells. The method includes: determining cycle-dependent programming adjustment parameters based on programming cycles of the plurality of memory cells; performing programming and verification operations on the plurality of memory cells modified by the cycle-dependent programming adjustment parameters; and wherein the cycle-dependent programming adjustment parameters are determined based on the relative capacitances of the plurality of bit lines electrically connected to the plurality of memory cells. The control circuitry may provide any desired functionality, including being further configured to perform the following steps: determining the position of a programming cycle in a programming cycle sequence to complete the programming operations on the plurality of memory cells, and wherein the determination of the cycle-dependent programming adjustment parameters is further based on the position of the cycle within the programming cycle sequence. Furthermore, in non-volatile memory devices, the position of a loop within the programming control circuit sequence can be determined to be one of the following: a start segment, an intermediate segment, or an end segment. If the loop position is within the start segment, the adjustment parameter is set to a first lower value; if the loop position is within the intermediate segment, the adjustment parameter is set to a higher value; and if the loop position is within the end segment, the adjustment parameter is set to a second lower value. The relative capacitance of multiple bit lines can be determined in any desired manner, such as based on the configuration of the disable voltage or programming voltage assigned to the multiple bit lines respectively. Furthermore, the relative capacitance of multiple bit lines can also be determined based on the corresponding programming states of multiple memory cells. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of this disclosure and, together with the specification, serve to explain its principles. Where convenient, the same reference numerals will be used throughout the drawings to refer to the same or similar elements.

[0009] Figure 1A A block diagram of an exemplary memory device is shown.

[0010] Figure 1B A block diagram of an exemplary control circuit is shown, including a programming circuit, a counting circuit, and a determining circuit.

[0011] Figure 2 A schematic diagram of three memory string architectures based on the principles of this disclosure is shown.

[0012] Figure 3 A block of memory cells in an exemplary two-dimensional configuration of the memory array of Figure 1 is depicted.

[0013] Figure 4A A cross-sectional view of an exemplary charge-trapping memory cell in a NAND string is shown.

[0014] Figure 4B It shows the line 429 Figure 4A A cross-sectional view of the structure.

[0015] Figure 5A An exemplary block diagram of the sensing block SB1 in Figure 1 is shown.

[0016] Figure 5B Another exemplary block diagram of the sensing block SB1 in Figure 1 is shown.

[0017] Figure 6A An exemplary block diagram of the sensing block SB1 in Figure 1 is shown.

[0018] Figure 6B Another exemplary block diagram of the sensing block SB1 in Figure 1 is shown.

[0019] Figure 6C It is a block diagram of a sensing circuit according to one or more implementation schemes.

[0020] Figure 6D This is another exemplary block diagram according to one or more embodiments of the present disclosure, which illustrates a schematic diagram of a charge pump circuit.

[0021] Figure 7A A perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of Figure 1 is shown.

[0022] Figure 7B It shows Figure 7A An exemplary cross-sectional view of a portion of a block.

[0023] Figure 7C It shows Figure 7B A graph showing the diameter of memory holes in a stack.

[0024] Figure 7D It shows Figure 7B A close-up view of the stacked area 622.

[0025] Figure 8A It shows Figure 7B A top view of an exemplary stacked word line layer WLL0.

[0026] Figure 8B It shows Figure 7B A top view of an exemplary top dielectric layer DL19 of the stack.

[0027] Figure 9A It shows Figure 8A An example NAND string in sub-blocks SBa to SBd.

[0028] Figure 9B Another exemplary view of the NAND string in the sub-block is shown.

[0029] Figure 9C The distribution of Vth of memory cells is shown in an exemplary one-pass programming operation with four data states.

[0030] Figure 9D The distribution of Vth of memory cells is shown in an exemplary one-pass programming operation with eight data states.

[0031] Figure 9E The distribution of Vth of memory cells is shown in an exemplary one-pass programming operation with sixteen data states.

[0032] Figure 10 The waveform of an exemplary programming operation is shown.

[0033] Figure 11A A graph is shown, illustrating exemplary current distribution curves within multiple programming cycles for solid-state memory programming operations.

[0034] Figure 11B A graph is shown, illustrating the analog bit line / control line load capacitance plotted by a programmed loop.

[0035] Figure 11C A current distribution curve for programming operation is shown according to one or more aspects of this disclosure.

[0036] Figure 11D It shows Figure 11C A segment view of the curve graph, which includes Figure 11C The subset of programming loops shown illustrates the relationship between the current peak of the memory device of this disclosure and the programming phase.

[0037] Figure 12A and Figure 12B Additional details on voltage level transitions within selected portions of the programming loop are provided.

[0038] Figure 13A The diagram shows a close-up ICC current distribution curve for a portion of the programming cycle, particularly a portion of the early stages of the programming cycle.

[0039] Figure 13B The diagram shows a portion of the programming cycle, specifically a portion of the cycle in the middle segment of the programming cycle, with a close-up ICC current distribution curve.

[0040] Figure 14A The memory cell array and associated control circuitry of this disclosure are shown.

[0041] Figure 14B A portion of the memory cell array of this disclosure is shown, along with the associated bit line capacitances of the three bit lines.

[0042] Figure 14C The memory cell array of this disclosure and the associated bit line capacitance of the five bit lines are shown.

[0043] Figure 14D A formula table is provided for predicting bit line parasitic capacitance based on the current bit line disabled or programmed configuration.

[0044] Figure 15 The processing flow of this disclosure is shown.

[0045] Figure 16 Another processing flow of this disclosure is shown.

[0046] Figure 17 Another processing flow of this disclosure is shown.

[0047] Figure 18 Another processing flow of this disclosure is shown.

[0048] Figure 19 Another processing flow of this disclosure is shown.

[0049] Figure 20 Another processing flow of this disclosure is shown. Detailed Implementation

[0050] The following discussion relates to various embodiments of this disclosure. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of this disclosure (including the claims) is limited to that embodiment.

[0051] As described, non-volatile memory (NVMemory) systems are a type of memory that retains stored information without requiring an external power source. NVOMemory is widely used in various electronic devices and standalone memory devices. For example, NVOMemory can be found in laptops, digital audio players, digital cameras, smartphones, video games, scientific instruments, industrial robots, medical electronic devices, solid-state drives, USB drives, memory cards, etc. NVOMemory can be programmed / reprogrammed and erased electrically.

[0052] Examples of non-volatile memory systems include flash memory, such as NAND flash or NOR flash. NAND flash memory structures typically arrange multiple memory cell transistors (e.g., floating-gate transistors or charge-trapping transistors) in series with two select gates (e.g., a drain-side select gate and a source-side select gate) between the two select gates. The series-connected memory cell transistors and select gates can be referred to as a NAND string. To reduce the cost per bit, the size of NAND flash memory can be reduced. Furthermore, in EEPROM or flash NAND array architectures, memory cells can be arranged in a matrix of rows and columns such that the gate of each memory cell is coupled to a word line via a row. Memory cells can be arranged together in a string array such that the memory cells in a given string are coupled together in series from source to drain between a common source line and a common control line or bit line. For the purposes of this disclosure, the term "bit line" is generally considered to be a type of control line, and therefore these terms are used interchangeably.

[0053] One of the most challenging issues in current flash memory design is reducing peak current consumption (peak ICC), which can lead to a drop in peak power and consequently, failure in the flash memory. More specifically, in the case of multiple concurrently operating flash memories in a memory device, the peak ICC is multiplied by the number of concurrently operating flash memories. Therefore, reducing the peak ICC of each flash memory can help the memory device operate within the host's peak current limits.

[0054] Peak current management may be required or desired to ensure that solid-state memory devices meet necessary or desired current specifications that are related to the average current consumption during programming and / or read operations. Therefore, excessively high current spikes can increase the average current consumption at data points during programming operations. Furthermore, the absolute peak current, as defined by the highest current level consumed during programming or read operations, can also represent an important or critical specification or characteristic of the solid-state memory device, where excessively high peak current levels may limit the number of solid-state memory dies that can operate in parallel due to the power burden imposed by current spikes.

[0055] To program a memory cell included in a memory string array, a programming operation is performed after the memory cell is set to an erase state to apply a series of programming voltages to the memory cell. Each programming voltage is provided in a programming cycle (also known as a program-verify iteration). For example, the programming voltage can be applied to a word line connected to the control gate of the memory cell. In one method, incremental step pulse programming is performed, where the programming voltage increases by a step size in each programming cycle. When programming of a memory cell is complete, the memory cell can be locked to prevent further programming while programming of other memory cells continues in subsequent programming cycles.

[0056] Programming a set of memory cells in a memory device typically involves applying a series of programming voltages to these cells after they have been provided in an erased state. Each programming voltage is applied in a programming cycle (also known as a program-verify iteration). For example, the programming voltage may be applied to a word line connected to the control gate of the memory cell. In one approach, incremental step-pulse programming is performed, where the programming voltage increases by a step size in each programming cycle. A verification operation can be performed after each programming voltage to determine whether the memory cell has been successfully programmed. When programming of a memory cell is complete, that memory cell can be locked to prevent further programming while programming of other memory cells continues in subsequent programming cycles.

[0057] Each memory cell can be associated with a data state based on the data written in the program command. A memory cell can be in an erase data state (referred to herein as the erase state) or can be programmed to a different data state than the erase state (referred to herein as the programming state). For example, in a one-bit memory device per cell (Single Level Cell (SLC)), there are two data states, including the erase state and a higher data state. Conversely, in a two-bit memory device per cell (Multi-Level Cell (MLC)), there are four data states, including the erase state and three programming data states, referred to as A, B, and C data states (see See...). Figure 9C In a three-bit memory device (or three-level cell (TLC)), there are eight data states, including an erase state and seven programming data states, which are referred to as A, B, C, D, E, F, and G data states (see also...). Figure 9D In a four-bit memory device per cell (quad-level cell (QLC)), there are sixteen data states, including erase state and fifteen programming data states, referred to as Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see [link to QLC]). Figure 9D ).

[0058] When a program command is issued, the written data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell will be programmed. Each memory cell is considered to have been programmed when a sensing operation determines that the associated verification voltage meets (e.g., is above) a threshold voltage (Vth). The sensing operation determines whether the memory cell has a Vth higher than the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, such that Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, such that Vth is higher than the control gate voltage.

[0059] When programming memory cells, it is important to perform the program-verification operation in a way that is both fast and controls peak ICC to prevent device failure. During the programming cycle, a certain programming clock time interval (hereinafter referred to as P7) is prone to large ICC current spikes during bit line precharge. As described in more detail below, one way to address this issue is by applying regulated current precharge control, such as that configured herein, denoted as V. HSASLOWP The parameters are altered by a control circuit that provides peak current control for the bit line to slow down the pre-charge rate of the bit line. However, by slowing the charging of the relevant bit line to an inactive state, if the regulated current continues to operate up to the maximum charge level (e.g., V), the charging rate of the bit line will be reduced. DDSA If this happens, the total programming time will be adversely affected. More typically, voltage threshold parameters (e.g., V) will also be affected. HSATGT The circuitry is configured to allow the control circuitry to switch from regulated charging to an unregulated charging configuration to shorten the charging cycle. However, as described more fully below, the selection of an ideal regulation point for the unregulated charging point is problematic. In embodiments of this disclosure, bit line charging is controlled based on statistical predictions of the effective bit line capacitance based on adjacent bit line configurations, and by controlling the application of a threshold charging transition point, as described below, allowing control of peak ICC with minimal overall impact on the device programming time tprog.

[0060] One solution is to implement multi-step verification (MSV) operation. MSV operation is a two-step operation in which a different verification voltage is applied during each step. Once the threshold voltage of the memory cell reaches the first verification voltage, the control voltage is changed to slow down the faster-programmed memory cell. However, MSV operation can lead to degraded performance (e.g., compared to a one-step programming operation) due to electromigration or interference on the memory cell. Furthermore, MSV operation is inefficient because it requires additional steps to program the memory cell.

[0061] For these reasons, and for other reasons that will become apparent to those skilled in the art upon reading this specification and the corresponding drawings, there is a need in the art for a method to create a narrow Vth distribution without reducing the programming throughput of a memory device.

[0062] Some embodiments described herein may include systems and / or methods for performing iterations of a verification operation to verify the data state of memory cells in selected word lines, wherein a fast programming verification technique or a precision-based verification technique is selected and implemented for each iteration of the verification operation. For example, the system and / or method may select a verification technique (e.g., a fast programming verification technique or a precision-based verification technique) based on the iteration of the verification operation being performed, based on whether the location of the memory cell is part of the upper or lower tail of the natural threshold voltage distribution (NVD) (e.g., using a fast programming verification technique) or part of the middle portion of the NVD (e.g., using a precision-based verification technique), etc.

[0063] The systems and / or methods described herein effectively and efficiently narrow the Vth distribution of memory cells. Furthermore, the systems and / or methods save resources (e.g., processing resources, memory resources, etc.) by reducing the programming-verification operation execution time compared to inferior systems or methods (e.g., using only fast programming-verification techniques or only using precision-based verification techniques). Reducing the total programming-verification time saves resources (e.g., power resources, processing resources, memory resources, etc.) that would otherwise be consumed in programming and verifying memory cells using only precision-based verification techniques.

[0064] In one approach, the verification voltage used to determine that a memory cell has completed programming may be referred to as the final verification voltage or the latch verification voltage. In some cases, an additional verification voltage may be used to determine that a memory cell is nearing programming completion. This additional verification voltage may be referred to as the offset verification voltage and may be lower than the final verification voltage. When a memory cell is nearing programming completion, the programming speed of the memory cell may be reduced, for example, by increasing the voltage of the corresponding bit line during one or more subsequent programming voltages. For example, in Figure 9, a memory cell to be programmed into data state A may undergo verification tests at VvAL (offset verification voltage for data state A) and VvA (final verification voltage for data state A).

[0065] Figure 1AThis is a block diagram of an example memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines via row decoder 124 and via bit lines via column decoder 132. Read / write circuitry 128 includes multiple sense blocks SB1, SB2, ..., SBp (sensing circuitry) and allows parallel reading or programming of pages of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one of the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0066] The memory structure can be a 2D memory structure or a 3D memory structure. A memory structure may include one or more memory cell arrays, including 3D arrays. A memory structure may include a monolithic three-dimensional memory structure in which multiple memory stages are formed on (but not in) a single substrate, such as a wafer, without an intervening substrate. A memory structure may include any type of non-volatile memory, monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. A memory structure may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is on or within the substrate.

[0067] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0068] Storage area 113 may be provided, for example, for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, the location of the memory cell on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector, the substrate or material constituting the contact connector, etc.

[0069] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operation. This power control module may include drivers for word lines, SGS transistors, and SGD transistors with source lines. In one approach, a sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0070] In some implementations, some of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0071] The control circuitry may include programming circuitry configured to perform programming operations on a set of memory cells, wherein the set of memory cells includes memory cells allocated to represent one of a plurality of data states, and memory cells allocated to represent another of the plurality of data states; the programming operation includes multiple programming-verification iterations; and in each programming-verification iteration, the programming circuitry performs programming on a word line, after which the programming circuitry applies a verification signal to a word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for one data state. The control circuitry may further include a determining circuit configured to determine a specific programming-verification iteration among the multiple programming-verification iterations based on an amount by which the count exceeds a threshold, in which a verification test is performed on the other data state of the memory cells allocated to represent the other data state.

[0072] For example, Figure 1B This is a block diagram of an exemplary control circuit 150 including a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0073] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may occur. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0074] The storage device includes code such as a set of instructions, and a processor can operate to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor can access the code from the storage device 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0075] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use code to control one or more memory structures. Upon power-up, processor 122c fetches boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0076] Generally speaking, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below.

[0077] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors. Other types of non-volatile memory may be used in addition to NAND flash memory.

[0078] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0079] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0080] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0081] NAND memory arrays can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or on the substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0082] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0083] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0084] A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the main surface of the substrate).

[0085] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., along the y-direction), each column having multiple memory elements. The columns can be arranged in a two-dimensional configuration, for example, in the xy-plane, resulting in a three-dimensional arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0086] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0087] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or may have intervening layers between memory device classes.

[0088] Additionally, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0089] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0090] Those skilled in the art will recognize that this technology is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but covers all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0091] Figure 2 Schematic diagrams of exemplary BiCS memory architectures utilizing interleaved memory strings are shown. For example, reference numeral 201 shows a schematic diagram of an exemplary BiCS 4 memory architecture, reference numeral 203 shows a schematic diagram of an exemplary BiCS 5 memory architecture, and reference numeral 205 shows a schematic diagram of an exemplary BiCS 6 memory architecture. In some embodiments, as shown, the BiCS memory architecture may include an array of interleaved NAND strings.

[0092] Referring to memory architecture 201, memory strings are shown in rows 207-0 to 207-7 of string architecture 201. A memory string may include a group of memory cells (e.g., the group of memory cells corresponds to a group of memory holes). Each row is shown as having four ends of the memory string. Memory strings may be connected to adjacent strings at the ends (not visible below this view). A first group of rows 207-0 to 207-3 is shown on the left side of dummy row 208. A second group of rows 207-4 to 207-7 is shown on the right side of dummy row 208. Dummy row 208 separates the two groups of rows in an interleaved eight-row configuration. Source line 209 is positioned at the edge of the first group and away from dummy row 208. Source line 210 is positioned at the edge of the second group and away from dummy row 208 and source line 209.

[0093] Memory architectures 203 and 205 may be similar to the memory architecture 201, except that additional groups are added. Serial architecture 203 may be twice the size of architecture 201 and may include sixteen rows of strings, with each group of four rows separated by virtual lines. Serial architecture 205 may be larger than both memory architectures 201 and 203. Serial architecture 205 may include twenty rows of strings, with each group of four rows separated by virtual lines 208.

[0094] In some implementations, memory architectures 201, 203, and / or 205 may include chips beneath the array structure. For example, memory architectures 201, 203, and / or 205 may include chips beneath the array structure, whereby control circuitry is located beneath the memory array comprising the set of memory strings. Utilizing the chips beneath the array structure, the memory strings may include direct band contacts for source lines for read and erase operations.

[0095] In some implementations, memory architecture 205 may be a BiCS 6 memory architecture. For example, in a BiCS 6 memory architecture, there may be five NAND string groups: NAND string group 212-1, NAND string group 212-2, NAND string group 212-3, and NAND string group 212-4. NAND string groups 212-0 and 212-4 may be referred to as external NAND string groups. NAND string groups 212-1, 212-2, and 212-3 may be collectively referred to as internal NAND string groups. NAND string group 212-2 may be referred to as the innermost NAND string group.

[0096] In some implementations, the BiCS 6 memory architecture can be a 3-D memory architecture comprising one or more 3-D blocks. In this case, the 3-D blocks can be logically segmented into multiple sub-blocks corresponding to NAND string groups. The 3-D blocks can also be segmented into multiple planes. Additional block descriptions are also provided herein.

[0097] While one or more embodiments involve a BiCS memory architecture, it should be understood that this is provided by way of example. In practice, the techniques described herein can be implemented on any number of different memory architectures, such as tubular BiCS (P-BiCS), vertical recessed array transistor (VRAT) architectures, and / or any other type of EEPROM or flash memory architecture.

[0098] Figure 3 A block of memory cells is shown in an exemplary two-dimensional configuration of the memory array 126 of FIG1. ​​The memory array may include a plurality of blocks. Each exemplary block 300, exemplary block 310 includes a plurality of NAND strings and corresponding bit lines, such as BL0, BL1, ... shared between blocks. Each NAND string is connected at one end to a drain-select gate (SGD), and the control gate of the drain-select gate is connected via a common SGD line. The NAND strings are connected at their other end to a source-select gate, which is in turn connected to a common source line 320. Sixteen word lines, such as WL0 to WL15, extend between the source-select gate and the drain-select gate. In some cases, dummy word lines that do not contain user data may also be used in memory arrays adjacent to select-gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0099] One type of non-volatile memory that can be provided in a memory array is floating-gate memory. See also Figure 4A and Figure 4B Other types of non-volatile memory can also be used. For example, charge-trapping memory cells use non-conductive dielectric materials instead of conductive floating gates to store charge in a non-volatile manner. See also Figure 5A and Figure 5B A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the surface of a semiconducting substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are captured and stored in a limited area. This stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided with a split-gate configuration, where a doped polysilicon gate extends above a portion of the memory cell channel to form a separate selection transistor.

[0100] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over a channel between the source and drain diffusion regions. The charge for one data bit is located in the dielectric layer adjacent to the drain, and the charge for the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0101] Figure 4A A cross-sectional view of an exemplary floating-gate memory cell in a NAND string is shown. Bit lines or NAND string directions enter the page, and word lines direction is from left to right. For example, word line 424 extends across a NAND string that includes corresponding channel regions 406, 416, and 426. Memory cell 400 includes a control gate 402, a floating gate 404, a tunnel oxide layer 405, and a channel region 406. Memory cell 410 includes a control gate 412, a floating gate 414, a tunnel oxide layer 415, and a channel region 416. Memory cell 420 includes a control gate 422, a floating gate 421, a tunnel oxide layer 425, and a channel region 426. Each memory cell is in a different corresponding NAND string. A polysilicon interlayer dielectric (IPD) layer 428 is also shown. The control gate is a portion of the word line. Figure 4B A cross-sectional view along the contact line connector 429 is provided.

[0102] The control gate is wrapped around the floating gate, increasing the surface contact area between the control gate and the floating gate. This results in a higher IPD capacitance, which in turn leads to a higher coupling ratio, making programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells becomes smaller, leaving little space for the control gate and IPD between two adjacent floating gates.

[0103] As another option, such as Figure 5A and Figure 5B As shown, planar or flat memory cells have been developed in which the control gate is flat or planar; that is, the control gate is not enclosed on a floating gate, and the only contact between the control gate and the charge storage layer is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the ballistic electron transport problem, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0104] Figure 5B The contact line connector 529 is shown. Figure 5AA cross-sectional view of the structure. The NAND string 530 includes an SGS transistor 531, an exemplary memory cell 500, an exemplary memory cell 533, ..., an exemplary memory cell 534 and an exemplary memory cell 535, and an SGD transistor 536. As an example of each memory cell, memory cell 400 includes a control gate 402, an IPD layer 428, a floating gate 404 and a tunnel oxide layer 505, which are... Figure 5A Consistent. The pathways in the IPD layer of SGS and SGD transistors allow the control gate layer and floating gate layer to communicate. For example, the control gate layer and floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer can be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0105] NAND strings can be formed on a substrate including a p-type substrate region 555, an n-type well 556, and a p-type well 557. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0106] Figure 6A An exemplary block diagram of the sensing block SB1 of Figure 1 is shown. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, exemplary sensing circuits 650a, 651a, 652a, and 553a are associated with data latches 650b, 551b, 652b, and 653b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 660 in SB1 can communicate with this group of sensing circuits and latches. The sensing circuit controller may include a precharge circuit 661 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage is transmitted, for example, via a data bus 603 and a local bus such as... Figure 6B LBUS1 or LBUS2 is provided independently to each sensing circuit. In another possible method, for example via... Figure 6BThe contact line 605 in the circuit simultaneously provides a common voltage to each sensing circuit. The sensing circuit controller may also include a memory 662 and a processor 663. The memory 662 may store code executable by the processor to perform the functions described herein. These functions may include reading latches associated with the sensing circuit, setting bit values ​​in the latches, and providing a voltage to set a pre-charge level in the sensing nodes of the sensing circuit. Further example details of the sensing circuit controller and sensing circuits 650a and 651a are provided below.

[0107] For example, the sensing circuit controller can communicate with different sensing circuits in a time-multiplexed manner. In one approach, contact line 605 can be connected to a voltage clamp in each sensing circuit.

[0108] Sensing circuit 651a includes latch 651b, which includes trip latch 646, offset verification latch 647, and data status latch 648. Voltage clamp 641 can be used to set a precharge voltage at sensing node 642. Sensing node to bit line (BL) switch 643 selectively allows the sensing node to communicate with bit line 645, and voltage clamp 644 can set a voltage on the bit line. Bit line 645 is connected to one or more memory cells, such as memory cell MC2. Local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as latch 651b and voltage clamp in some cases. To communicate with sensing circuit 651a, the sensing circuit controller provides voltage to transistor 606 via contact line 601 to connect LBUS2 to DBUS.

[0109] The sensing circuit 650a may be a first sensing circuit including a first trip latch 626, and the sensing circuit 651a may be a second sensing circuit including a second trip latch 646.

[0110] Sensing circuit 650A is an example of a first sensing circuit including a first sensing node 622, wherein the first sensing circuit is associated with a first memory cell MC1 and a first bit line 625. Sensing circuit 651A is an example of a second sensing circuit including a second sensing node 642, wherein the second sensing circuit is associated with a second memory cell MC2 and a second bit line 645.

[0111] In some embodiments, a memory cell may include a tag register comprising a set of latches storing tag bits. In some embodiments, the number of tag registers may correspond to the number of data states. In some embodiments, one or more tag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the tag bits may modify associated logic of the device, such as address decoding circuitry, to select a specified cell block. Body operations (e.g., erase operations, etc.) may be performed using tags set in the tag register, or a combination of tag registers and address registers, as in implicit addressing, or alternatively by direct addressing using only address registers.

[0112] Figure 6B Another exemplary block diagram of the sensing block SB1 in Figure 1 is shown. The sensing circuit controller 660 communicates with a plurality of sensing circuits, including exemplary sensing circuits 650a and 651a, such as... Figure 6A As shown. Sensing circuit 650a includes latch 650b, which includes trip latch 626, offset verification latch 627, and data status latch 628. The sensing circuit also includes voltage clamp 621, such as a transistor, which sets a precharge voltage at sensing node 622. Sensing node to bit line (BL) switch 623 selectively allows the sensing node to communicate with bit line 625, for example, the sensing node is electrically connected to the bit line such that the sensing node voltage can decay. Bit line 625 is connected to one or more memory cells, such as memory cell MC1. Voltage clamp 624 can set the voltage on the bit line, such as during sensing operation or during programming voltage. Local bus LBUS1 allows the sensing circuit controller to communicate with components in the sensing circuit, such as latch 650b and voltage clamp in some cases. To communicate with sensing circuit 650a, the sensing circuit controller provides voltage to transistor 604 via contact line 602 to connect LBUS1 to data bus DBUS 603. Communication may include sending data to and / or receiving data from the sensing circuit.

[0113] Figure 6C It is a block diagram of a separate sensing block 675 divided into a core part (called sensing module 680) and a common part 690. According to Figure 6C The elements shown and described may include those according to the above. Figure 6A and Figure 6BThe elements described may be the same or different, and may enhance the above functionality to operate with embodiments of this disclosure. In some embodiments, a separate sensing module 680 may be provided for each bit line, or a single common section may be provided for a group of multiple sensing modules. In some embodiments, a sensing block includes a common section 690 and eight or more sensing modules 680. Each sensing module in the group of sensing modules 680 may communicate with the associated common section via a data bus 672. For further details, see U.S. Patent Application Publication 2006 / 0140007, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0114] Sensing module 680 may include sensing circuitry 670. In some embodiments, sensing circuitry 670 is configured to determine whether the conduction current in the connected bit line is above or below a predetermined threshold level. Alternatively or additionally, sensing circuitry 670 may be configured to determine whether current flows in the bit line and / or memory cell when a given threshold voltage is applied to the associated word line. In some embodiments, sensing module 680 includes sensing amplifier circuitry. Sensing module 680 may also include one or more bit line latches for setting voltage conditions on the connected bit line. For example, a predetermined state latched in bit line latch 682 may cause the connected bit line to be pulled to a programming disabled state (e.g., VDD). The disabled voltage level (VDD) is provided by a voltage source input, which may be any type of voltage (or current) source. Although referred to herein as a “bit line latch,” in some contexts it should be understood that, according to embodiments of this disclosure, such an element may be any type of sense data latch (“SDL”) that stores control line bias settings / information.

[0115] The common portion 690 of the sensing block 675 includes one or more processors 692, a set of data latches 694, and / or an input / output (I / O) interface 596 coupled between the set of data latches 694 and the data bus 620. The processors 692 can be configured to perform various calculations. For example, the processors 692 can be configured to determine data stored in the sensed memory cells and store the determined data in the set of data latches 694. The set of data latches 694 can be used to store data bits determined by the processors 692 during a read operation. The data latches 694 can also be used to store data bits imported from the data bus 620 during a programming operation. Imported data bits represent write data intended to be programmed into memory. The I / O interface 696 provides an interface between the data latches 694 and the data bus 620.

[0116] During reading or sensing, the operation of sensing block 675 may be under the control of a state machine that controls the supply of different control gate voltages to the addressed cell. As the state machine progresses through various predefined control gate voltages corresponding to various memory states supported by the memory, sensing module 680 may trip at one of these voltages, and the output will be provided from sensing module 680 to processor 692 via bus 672. At this time, processor 692 can determine the resulting memory state by considering the tripping event of the sensing module and information about the control gate voltage applied via input line 693 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latch 694. In some embodiments, bit line latch 682 is used as a latch for latching the output of sensing module 680 and as a bit line latch as described above. Bit line latch 682 may be one of a plurality of bit line latches configured to store a plurality of data bits indicating selected and unselected bit lines or other control lines among a plurality of bit lines.

[0117] During programming or verification, the data to be programmed can be stored in a set of data latches 694 from the data bus 620. The programming operation can be performed at least partially under the control of a state machine and may include a series of programming voltage pulses (with increasing magnitudes) applied to the control gate of the addressed memory cell. When the bit line is not associated with the memory cell being programmed, it can be charged to an inhibit voltage as part of a pre-charge phase before the programming pulses of the programming operation, as described in detail below, whereby the channel voltage is boosted to a high voltage when memory transistors such as M1 are in a programming inhibit mode.

[0118] Each programming pulse can be followed by a verification process to determine whether the memory cell has been programmed to the desired state. Processor 692 can monitor the verified memory state relative to the desired memory state. When both are in agreement, processor 692 can set bit-line latch 682 to pull the bit line to a programming disable voltage level, as mentioned above. This prevents further programming of the cell coupled to the bit line, even if it has undergone a programming pulse on its control gate. In some embodiments, processor 692 initially loads bit-line latch 682, and sensing circuitry sets it to a disable value during the verification process. In one embodiment, the magnitude of the disable value depends on the location of the selected word line.

[0119] Data latch stack 694 may contain a stack of data latches corresponding to sensing module 680. In some embodiments, each sensing module has 3-5 (or another number) data latches. In some embodiments, each latch is a single bit. The data latches may be implemented as shift registers, such that parallel data stored therein is converted into serial data on data bus 620 and vice versa. In one embodiment, all data latches corresponding to a read / write block of M memory cells may be connected together to form a block shift register, enabling input or output data blocks to be transmitted serially. Specifically, the read / write module group is adjusted such that each of its data latch groups sequentially shifts data into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0120] Figure 6D This is a schematic diagram of a charge pump circuit 600D according to one or more embodiments. Circuit 600D can be used in a sense amplifier. In some embodiments, circuit 600D can be used in conjunction with the sense circuit 670 shown in FIG. 4 and described above. Circuit 600D may include a bit line clamping transistor 614 coupled to a bit line. Although a single transistor 614 is shown and described, it should be understood that in some embodiments, the transistor 614 shown may represent a stack of transistors connected in series. One terminal of transistor 614 is connected to a supply voltage (also referred to herein as "VDD", and may also represent a disable voltage in some configurations). VDD may be an externally or internally supplied voltage. In some embodiments, the rate at which transistor 54 supplies voltage VDD to the bit line depends on its gate voltage.

[0121] Circuit 600D may include one or more capacitors 615. For example, capacitor 615 may have one node coupled to the gate of transistor 614 and another node coupled to a ground reference. Circuit 600D may also include or be connected to a current source 610, which may be variable in some embodiments. Current source 610 may be coupled to a node of capacitor 615 that is coupled to the gate of bit-line clamping transistor 614. Thus, the voltage supplied to the gate of transistor 614 may be controlled at least partially by charging capacitor 615 using current source 610.

[0122] A charge pump circuit 600D can be used to facilitate or ensure a constant current value supplied to the associated bit line on path 616. For example, during a controlled or constant current period in a pre-charge phase used to pre-charge the bit line to a target voltage, the charge pump circuit can be used to provide a constant current to prevent undesirable current spikes when the bit line voltage ramps up too quickly during the constant current period. To control the bit line voltage ramp rate, the gate bias on transistor 614 can be modulated by current source 610. A higher current from current source 610 causes the gate bias of transistor 614 to ramp up faster, resulting in a faster ramp of the bit line voltage. Conversely, a lower current from current source 610 causes the gate bias of transistor 614 to ramp up more slowly, resulting in a slower ramp of the bit line voltage. In some embodiments, a slower bit line charging rate can be achieved by reducing the current from current source 610 to approximately 3 / 4 of the full value of the current source. Any percentage of the full value can be used for a slower charging rate. Additionally, any number of different charging rates can exist.

[0123] While the charge pump circuit 600D is described in some contexts as providing charging current to bit lines / control lines, it should be understood that charge from circuit 600D and / or other charge pumps, or from the circuits described herein, can be used for word line charging or other control line charging. The term "charge pump circuit" can generally refer to any type or configuration of circuitry and / or apparatus configured to provide control line charging / pre-charging according to aspects of this disclosure. The charge pump circuit 600D can provide means for charging multiple control lines to a target voltage and / or means for limiting charging current from a voltage source to a managed current.

[0124] In solid-state data storage systems, different charge pumps can be used for word line charging and bit line charging, respectively. For example, the voltage source input (e.g., a battery) used for various control line charging functions can be varied for bit lines and word lines. Furthermore, the load on such circuitry can be varied for bit line and word line applications. For example, for some word line charging applications, a charge pump may advantageously support 0V to 10V, but offers relatively lower accuracy (e.g., accuracy in 0.1V steps) compared to a bit line charge pump. That is, a word line charge pump can represent a relatively strong pump with lower accuracy compared to a bit line charge pump. For bit line charge pumps, different pumps can be used for different charging stages. For example, for pre-charging, the relevant target voltage may be around, for example, 3V, while for read / verify stage charging, the voltage target may be smaller, such as around 0.5V, which may not require such a strong pump but may require higher accuracy (e.g., 0.01V accuracy).

[0125] Figure 7AThis is a perspective view of a set of blocks 700 in an exemplary three-dimensional configuration of the memory array 126 of FIG1. ​​On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and a peripheral region 704 having circuitry for use by the blocks. For example, the circuitry may include a voltage driver 705 connectable to a control gate layer of the block. In one approach, control gate layers at a common height in the blocks are commonly driven. The substrate 701 may also carry circuitry below the blocks along with one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. These blocks are formed in a middle region 702 of the memory device. In an upper region 703 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals from the circuitry. Each block includes a stacked region of memory cells, wherein the stacked alternating layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upward to the upper metal layers to form connections with conductive paths. Although four blocks are shown as an example, two or more blocks extending in the x and / or y directions can be used.

[0126] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0127] Figure 7B It shows Figure 7A An exemplary cross-sectional view of a portion of a block. The block includes a stack 710 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, an area comprising a stack of NAND strings NS1 and NS2 is shown. Each NAND string contains a memory via 718 or 719 filled with material forming memory cells adjacent to the word lines. Figure 7D The stacked region 722 is shown in more detail.

[0128] The stack includes a substrate 711, an insulating film 712 on the substrate, and a portion of a source line SL. NS1 has a source terminal 713 at the bottom 714 of the stack and a drain terminal 715 at the top 716 of the stack. Contact line connectors (e.g., slots, such as metal-filled slots) 717 and contact line connectors 720 may be provided periodically across the stack as interconnects extending through the stack, such as to connect source lines to specific contact lines above the stack. The contact line connectors may be used during word line formation and subsequently metal-filled. A portion of a bit line BL0 is also shown. A conductive via 721 connects the drain terminal 715 to BL0.

[0129] Figure 7C It shows Figure 7B A graph showing the diameter of memory holes in the stack. The vertical axis is aligned with the stack of Figure 7B and shows the width (wMH), e.g., the diameter, of memory holes 718 and 719. Figure 7A Word line layers WLL0 to WLL10 are repeated as an example, and are located at corresponding heights z0 to z10 in the stack. In such memory devices, the memory vias etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter of the memory via gradually decreases from its top to its bottom. That is, the memory via is tapered, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the via near the select gate, causing the diameter of the memory via to slightly widen before gradually decreasing from its top to its bottom.

[0130] Due to the non-uniformity of memory via width, the programming speed, including the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory via (e.g., based on the height of the memory cell in the stack). For smaller diameter memory vias, the electric field across the tunnel oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define a group of adjacent word lines with a diameter similar to the memory via (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0131] Figure 7D It shows Figure 7BA close-up view of region 722 of the stack. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 780 and 781 are provided above dummy memory cells 782 and 783 and data memory cell MC. Multiple layers may be deposited along the sidewalls (SW) of memory via 730 and / or within each word line layer (e.g., using atomic layer deposition). For example, each column (e.g., a pillar formed by material within the memory via) may include a charge trapping layer or film 763 (such as SiN or other nitrides), a tunnel layer 664, a polysilicon body or channel 765, and a dielectric core 766. The word line layer may include a blocking oxide / bulk high-k material 760, a metal blocking layer 761, and a conductive metal 762 (such as tungsten) as a control gate. For example, control gates 790, 791, 792, 793, and 794 are provided. In this example, all layers except the metal are provided within the memory vias. In other methods, some of the layers may be within the control gate layer. Additional pillars are similarly formed within the different memory vias. These pillars can form pillared active regions (AAs) of the NAND string.

[0132] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunnel layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0133] Each memory via may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each memory via is filled with the host material, and the multiple annular layers are located between the core region and the word line in each memory via.

[0134] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0135] Figure 8A It shows Figure 7BA top view of an exemplary word line layer WLL0 of a stack. As mentioned, a 3D memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0136] In a 3D memory device, a block BLK can be divided into sub-blocks, each sub-block comprising a group of NAND strings with a common SGD control line. See, for example, SGD line / control gate SGD0, SGD line / control gate SGD1, SGD line / control gate SGD2, and SGD line / control gate SGD3 in sub-blocks SBBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layer within the block can be divided into regions. Each region is within a corresponding sub-block and can extend between contact line connectors (e.g., slits) periodically formed in a stack to process the word line layer during the manufacturing process of the memory device. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between the contact line connectors should be relatively small to account for the limitations of the distance that etchant can travel laterally to remove the sacrificial material and the distance that metal can travel to fill the gaps created by removing the sacrificial material. For example, the distance between the contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of memory holes and contact line connectors should also take into account the limitations on the number of bit lines that can extend across regions when each bit line is connected to a different memory cell. After processing the word line layer, contact line connectors can optionally be metal-filled to provide interconnection across the stack.

[0137] In this example, four rows of memory holes exist between adjacent contact line connectors. A row here is a set of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are arranged in an interleaved pattern to increase the density of the memory holes. The word line layer, or word line, is divided into regions WLL0 a, WLL0 b, WLL0 c, and WLL0 d, each connected via connector 813. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 813 is then connected to a voltage driver for the word line layer. Region WLL0 a has exemplary memory holes 810 and 811 along contact line 812. Region WLL0 b has exemplary memory holes 814 and 815. Region WLL0 c has exemplary memory holes 816 and 817. Region WLL0 d has exemplary memory holes 818 and 819. Memory holes are also... Figure 8B As shown in the diagram. Each memory hole can be part of a corresponding NAND string. For example, memory holes 810, 814, 816, and 818 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0138] Each circle represents a cross-section of a memory via at a word line layer or SG layer. Exemplary circles, shown in dashed lines, represent memory cells provided by the material in the memory via and adjacent word line layers. For example, memory cells 820 and 821 are in WLL0a, memory cells 824 and 825 are in WLL0b, memory cells 826 and 827 are in WLL0c, and memory cells 828 and 829 are in WLL0d. These memory cells are at a common height in the stack.

[0139] Contact wire connectors (e.g., slots, such as metal-filled slots) 801, 802, 803, and 804 may be located between and adjacent to the edges of regions WLL0 a to WLL0 d. The contact wire connectors provide a conductive path from the bottom to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductor above the stack, where the conductor connects to a voltage driver in a peripheral region of the memory device. See also Figure 9A In order to understand Figure 8A Further details on sub-blocks SBa to SBd.

[0140] Figure 8B It shows Figure 7BA top view of an exemplary top dielectric layer DL19 of the stack. The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a corresponding voltage driver. This allows simultaneous programming of a group of memory cells in a region of the word line layer, where each memory cell resides in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to enable or disable programming during each programming voltage.

[0141] Region DL19a has exemplary memory holes 810 and 811 along contact line 812a coinciding with bit line BL0. A plurality of bit lines extend above and connect to the memory holes, as indicated by the “X” symbol. BL0 connects to a set of memory holes including memory holes 811, 815, 817, and 819. Another exemplary bit line BL1 connects to a set of memory holes including memory holes 810, 814, 816, and 818. Also shown... Figure 8A Contact wire connectors (e.g., slots, such as metal-filled slots) 801, 802, 803, and 804 extend vertically through the stack. The contact wires can be numbered sequentially from BL0 to BL23 across the DL19 layers in the x-direction.

[0142] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent row of cells adjacent to the first row at the left edge.

[0143] Figure 9A It shows Figure 8A The example NAND strings in sub-blocks SBa to SBe. Sub-blocks and Figure 7BThe structures are consistent. Conductive layers in the stack are shown for reference on the left-hand side. Each sub-block includes multiple NAND strings, with one exemplary NAND string shown. For example, SBa includes exemplary NAND string NS0, SBb includes exemplary NAND string NS1, SBc includes exemplary NAND string NS2, SBd includes exemplary NAND string NS3, and SBe includes exemplary NAND string NS4.

[0144] Additionally, NS0_SBa includes SGS transistors 900 and 901, dummy memory units 902 and 903, data memory units 904, 905, 906, 907, 908, 909, 910, 911, 912, 913, and 914, dummy memory units 915 and 916, and SGD transistors 917 and 918.

[0145] NS1_SBb includes SGS transistors 920 and 921, dummy memory units 922 and 923, data memory units 924, 925, 926, 927, 928, 929, 930, 931, 932, 933, and 934, dummy memory units 935 and 936, and SGD transistors 937 and 938.

[0146] NS2_SBc includes SGS transistors 940 and 941, dummy memory units 942 and 943, data memory units 944, 945, 946, 947, 948, 949, 950, 951, 952, 953, and 954, dummy memory units 955 and 956, and SGD transistors 957 and 958.

[0147] NS3_SBd includes SGS transistors 960 and 961, dummy memory units 962 and 963, data memory units 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, and 974, dummy memory units 975 and 976, and SGD transistors 977 and 978.

[0148] NS4_SBe includes SGS transistors 980 and 981, dummy memory units 982 and 983, data memory units 984, 985, 986, 987, 988, 989, 980, 981, 982, 983, 984, 985, and 986, as well as SGD transistors 987 and 988.

[0149] At a given height within a block, the memory cells in each sub-block are located at a common height. For example, a group of memory cells (including memory cell 904) are located in multiple memory cells formed by tapered memory holes along a stack of alternating conductive and dielectric layers. This group of memory cells is located at a specific height z0 in the stack. Another group of memory cells (including memory cell 924) connected to a word line (WLL0) is also located at a specific height. In another approach, another group of memory cells (e.g., including memory cell 912) connected to another word line (e.g., WLL8) is located at another height (z8) in the stack.

[0150] Figure 9BAnother exemplary view of the NAND strings in a sub-block is shown. The NAND strings include NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, each with 48 word lines (e.g., WL0 to WL47). Each sub-block includes a group of NAND strings that extends in the x-direction and has a common SGD line, such as SGD0, SGD1, SGD2, SGD3, or SGD4. In this simplified example, there is only one SGD transistor and one SGS transistor in each NAND string. The NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe are located in sub-blocks SBa, SBb, SBc, SBd, and SBe, respectively. Furthermore, an exemplary group of word lines G0, G1, and G2 is shown.

[0151] Figure 10 The waveform of an exemplary programming operation is shown. The horizontal axis shows the programming cycle number, and the vertical axis shows the programming voltage value and the programming verification value. The programming voltage (Vpgm) may include the word line voltage (WLVpgm) and / or the bit line voltage (BLVpgm). Generally, a programming operation may involve applying a burst of pulses to a selected word line, where the burst of pulses includes multiple program-verify (PV) iterations. The programming portion of a PV iteration includes the programming voltage, and the verification portion of a PV iteration includes one or more verification voltages.

[0152] For simplicity, a square wave is shown for each programming voltage, but other shapes are possible, such as multi-stage or ramp shapes. Furthermore, Incremental Step Pulse Programming (ISPP) is used in this example, where the programming voltage increments in each successive programming cycle. This example uses ISPP in a single programming step where programming has been completed. ISPP can also be used in each programming step of a multi-step operation. Generally, the background method for programming flash memory cells using ISPP is described in Suh et al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE International Solid State Circuits Conference, 1995, pp. 128-130, the entire disclosure of which is incorporated herein by reference for all purposes. The specific implementation of this disclosure utilizing ISPP adds many important innovative improvements over the background method of Suh et al., as further described herein.

[0153] A pulse train typically comprises programming voltages that are progressively increased in magnitude using a voltage bias (dVpgm) in each programming-verification iteration. The voltage bias can be, for example, a word line voltage bias. A new pulse train can be applied at each programming step of a multi-step programming-verification operation, starting with an initial programming voltage (e.g., initial Vpgm) and ending with a final programming voltage (e.g., final Vpgm) that does not exceed a threshold voltage Vth (e.g., a maximum allowable value). The initial programming voltage can be the same or different in different programming steps. The final programming voltage can also be the same or different in different programming steps. The voltage bias can be the same or different in different programming steps. In some cases, a smaller voltage bias is used in the final programming step to reduce the Vth distribution width.

[0154] The pulse train 1000 includes a series of programming voltages 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, and 1015 applied to a word line selected for programming and an associated set of non-volatile memory cells. In the example shown, for example, a verification voltage, two verification voltages, or three verification voltages are provided after each programming voltage, based on the number of target data states being verified. The number of target data states being verified may, for example, correspond to the number of memory cells associated with the word line. The programming voltage and the corresponding verification voltage can be separated by applying 0V to the selected word line between the programming voltage and the verification voltage.

[0155] In the example shown, an A-state verification voltage VvA (e.g., waveform or programming signal 1016) can be applied after each of the first programming voltage 1001, the second programming voltage 1002, and the third programming voltage 1003. An A-state verification voltage of VvA and a B-state verification voltage of VvB (e.g., programming signal 1017) can be applied after each of the fourth programming voltage 1004, the fifth programming voltage 1005, and the sixth programming voltage 1006. An A-state verification voltage VvA, a B-state verification voltage VvB, and a C-state verification voltage VvC (e.g., programming signal 1018) can be applied after each of the seventh programming voltage 1007 and the eighth programming voltage 1008. A B-state verification voltage VvB and a C-state verification voltage VvC (e.g., programming signal 1019) can be applied after each of the ninth programming voltage 1009, the tenth programming voltage 1010, and the eleventh programming voltage 1011. Finally, a C-state verification voltage VvC (e.g., programming signal 1020) can be applied after each of the twelfth programming voltage 1012, the thirteenth programming voltage 1013, the fourteenth programming voltage 1014, and the fifteenth programming voltage 1015.

[0156] In some embodiments, memory device 100 (e.g., using state machine 112, controller 122, and / or control circuitry 150 of control circuitry 110) may use different programming voltages and / or different programming voltage biases along with controlled rise / fall or clamping voltages to perform verification operations. In some embodiments, the programming voltage and programming voltage bias for performing the programming operation may respectively include word line voltages and word line voltage biases. Alternatively or additionally, the programming voltage and programming voltage bias for performing the programming operation may respectively include bit line voltages and bit line voltage biases.

[0157] Figure 11A This is a graph showing exemplary current distribution curves across multiple programming cycles used in solid-state memory programming operations. The graph illustrates what is typically seen in... Figure 10 The measured peak ICC currents for multiple programming cycles / periods discussed herein (as used herein, "programming cycle" and "programming period" are considered interchangeable) are shown, with the bottom axis reflecting the total time taken to fully program a selected cell of the memory device over multiple programming cycles (this programming operation time may alternatively be referred to as "tprog"). According to certain solid-state programming schemes, as described above, memory cells are progressively programmed from an erase state to a final desired state (e.g., states A, B, C, etc.). The charge state of the progressively programmed memory cell can be progressively increased over multiple programming cycles / periods until the final desired charge state is reached (typically at time "tprog"). Once the final programmed charge state of a particular memory cell is reached, the bit line associated with that particular memory cell can be latched by applying a disable voltage / bias level. As explained in more detail below, the most prominent ICC current peaks occur during the programming period, where the bit line to be placed under the disable voltage / bias is charged to the desired disable level (V). INHIBIT or V DDSA (This depends on the naming). "Prohibited voltage level" can correspond to a voltage level that is high enough to counteract the effects of a programming voltage pulse applied to a memory element associated with the corresponding control line (e.g., word line).

[0158] like Figure 11A As shown, peak ICC current levels (e.g., those identified by reference numeral 1100) from multiple programming cycles within the programming cycle tprog form a peak current envelope 1105, reaching its highest point during the middle segment of tprog. This variation in peak current ICC levels across multiple programming cycles is related to the changing capacitance when the bit line is in programming or inhibiting mode. Generally, these ICC peaks can be grouped into a start segment 1107, a middle segment 1108, or an end segment 1109, where the peak is higher but typically does not exceed a predetermined threshold (shown as horizontal line 1111), where the ICC peak may exceed the predetermined threshold 1111 in the middle segment, and where the ICC peak decreases and typically remains below the predetermined threshold 1111 in the end segment.

[0159] The shape of the peak envelope 1105 is due to several factors, including the capacitance of the bit line charged to an inactive state. See also Figure 11BIf the simulated bit line load capacitance is plotted in a programmed loop, a shape similar to the characteristic shape seen for the peak ICC curve 1105 can also be seen in the different bit line capacitances shown in the programming in the distribution curve 1105B. As previously mentioned, large peak ICC values ​​can cause memory device failures, especially those exceeding predetermined levels, such as the failure shown at 1107 in Figure 11A, and aspects of this disclosure attempt to reduce peak ICC, particularly in the intermediate high ICC segment 1108. The capacitance affecting the bit line / control line is discussed in more detail below, especially regarding... Figures 14B to 14D .

[0160] Figure 11C and Figure 11D The relationship between peak current of a memory device and programming phases is shown, including the individual programming cycles and phases within each cycle, along with the occurrence of peak ICC. Figure 11C Provides format and Figure 11D Similar graphs illustrate exemplary current distribution curves within multiple programming cycles for solid-state memory programming operations according to one or more embodiments. For example, Figure 11C The distribution curves shown correspond to programming operations in a 3-D NAND memory chip, which includes, for example, up to 96 layers or more, and is configured to implement multi-level cell (MLC), three-level cell (TLC), and / or four-level cell (QLC) programming architectures.

[0161] Figure 11D It shows Figure 11C A segment of the curve, in which Figure 11D The fragments include a subset of the programming loops related to the programming operations. Figure 11C and Figure 11D The graph illustrates three distinct phases or cycles within each programming loop, which are shown exemplarily as follows: Figure 11D The system consists of two loops, "Loop N" and "Loop N+1," and three phases: a pre-charge phase, a programming pulse phase, and a verification phase. Each phase is described in detail below. Figure 11DThe symbols are used to indicate the stages. Each stage can be further divided into more granular stages, as described below. In some specific implementations, a relatively high voltage (e.g., 20V) can be applied during the programming pulse stage to program the memory cells. Certain current peaks may occur during the first and second periods of the precharge stage, and during the verification stage, as shown in the figure. Generally, the peaks that have the greatest impact on the peak current consumption of the memory array and / or device may occur during the precharge stage, while smaller peaks may occur during the verification stage. By reducing or controlling the current peaks in the precharge and / or verification stages, the peak current consumption of the data storage device can be managed or suppressed. As explained in more detail below, embodiments of this disclosure provide methods for reducing current peaks in the precharge stage and alternative methods for reducing current peaks in later stages, such as the programming recovery stage or the read / verify stage.

[0162] For a given programming operation, such as for Figure 11C As shown in the graph of the programming operation, the pre-charge phase of the first programming cycle can be associated with a peak current 1101C, representing the highest peak current of the programming phase within the cycle. As described in detail above, the pre-charge phase of the programming cycle includes a first time period (“Time Period 1”, also seen in…) associated with a timing clock. Figure 12A and Figure 12B During this period, a constant current is used to charge the control line (e.g., the bit line) to a target voltage level, which can be a certain percentage or portion of the disable voltage level (e.g., 70%-90% of the disable voltage level, as determined by factors such as V). HSATGT (The parameters are set by programming related to loops, etc.).

[0163] Figure 12A and Figure 12B Details of voltage level transitions for memory circuit signals operating within selected portions of the programming loop are provided. Figure 12A A portion of programming cycle 1200 is shown for a specific set of cells to be programmed (e.g., pages of cells in a memory device segment of a memory array of a storage device). The voltage states of the bit lines / control lines are shown at 1220B to charge the bit lines to an inhibited voltage state (V). INHIBIT / V DDSA ), and is shown at 1220A for the bit line to be configured in programming state (V SEL / V SSThe diagram illustrates several phases of the programming cycle segment 1200, including programming phase 1233, pre-charge phase 1230, a first pre-charge period 1231 of pre-charge phase 1230, a second pre-charge period 1232 of pre-charge phase 1230, programming recovery phase 1235, and read / verify phase 1240. For clarity, Figure 12B An alternative view is provided showing time period 1 and time period 2 (1231 and 1232, respectively) of the precharge phase 1230 of bit line 1220B to be charged to the disabled state and bit line 1220A to be charged to the programmed state.

[0164] Figure 11A Each of the ICC current “spikes” shown (such as those shown at 1100) occurs at the forbidden bit line voltage to V. DDSA The inflection point / rapid ramp begins (around the bit line charging point at approximately 1225, and peaks at approximately P7, or near the end of the first phase 1231 of the pre-charge phase 1230). More specifically, given... Figures 11C to 11D and Figures 12A to 12B The first period 1231 of the pre-charge phase 1230 can be considered a "constant current period" because the current supplied to the relevant control line (i.e., the bit line to be disabled) can be maintained at a constant value for at least a portion of the first period, and this constant value can be maintained by means such as V HSASLOWP Parameters like these can be adjusted. For example, V in the range of approximately 20mA to 30mA. HSASLOWP Provides bit-line precharge current control (per plane) in programmed / soft-programmed modes (i.e., provides peak current control). Furthermore, the first period of the precharge state can be referred to as a "managed current period" or "regulated current period" in the sense that the current can be managed or regulated by some control circuitry to achieve currents up to V. HSATGT Set the desired charge level at a defined threshold point. "Managed current," "managed charging current," "regulated current," and "regulated charging current" are used herein according to their broad and general meanings, and generally refer to current flow that is managed or regulated in some way. Generally, since the current is managed during the first period of the pre-charge phase, ICC spikes are not of concern during this period of the programming cycle.

[0165] Once bit line 1231 has reached a predetermined threshold during bit line / control line charging (such as when such a threshold voltage line reaches a value determined by V...), HSATGTWhen a predetermined threshold 1225 is reached, the second period 1232 of the pre-charging phase 1230 begins. During the second period 1232 of the pre-charging process, an unlimited current is allowed to charge the desired control line (e.g., bit line) relatively quickly. Such a period may be referred to herein as an “unregulated” or “unmanaged” current period. The terms “unregulated charging current,” “unregulated current,” “unmanaged charging current,” and “uncontrolled current” are used herein according to their broad and general meanings, and generally refer to charging currents such as those used to charge the control line / bit line that are essentially unmanaged or unregulated. While the remaining charging of the control line / bit line is allowed to proceed in an unregulated manner to reach a predetermined level such as V DDSA (or alternative location, V) INHIBIT This minimizes the amount of time required, but at the cost of high ICC current spikes caused by the resulting rapid charging. Logically, one way to control this current could be to change (or increase) the threshold voltage (e.g., V) used by the control system to modify the charging of the control line / bit line from the regulated current to the unregulated current. HSATGT or V TGT This reduces the amount of unregulated / fast charging during the second phase of the pre-charge stage in the programming cycle. However, increasing V... HSATGT / V TGT The threshold increases the amount of time required for the programming cycle to complete the precharge period, and thus adversely affects the overall operating speed of the memory device.

[0166] It can be seen Figure 12A and Figure 12B This illustrates a precharge voltage applied to a control line (such as a bit line) according to one or more embodiments. The terms "control line precharge," "control line precharge stage," and "precharge" are used herein according to their broad and general meanings, and in some contexts may refer to the process used to drive the voltage / charge level of a control line (e.g., a bit line) to a target voltage level (e.g., an disable voltage level, a desired programming bias, or other voltage). Control line precharge can be used to disable programming of the associated memory element or to facilitate faster read / write operations, depending on the application. Figure 12B The graph illustrates the voltage levels of two types of control lines: (1) “selected” control line 1220B, which typically refers to a bit line selected for programming, or a memory cell on that bit line that is currently being programmed; and (2) “unselected” or “disabled” control lines (e.g., bit lines) 1220A, which typically refers to a bit line on which a memory cell is not currently being programmed, or which is currently or intended to be precharged to a disabled voltage or other target voltage level. As shown, control line 1220A can be maintained at the ground reference voltage level V throughout the entire precharge phase time period 1230.SEL or V SS At this location, the control line 1220B was not selected, which could be grounded at the reference voltage V. SEL or V SS It starts at this point and rises to a higher voltage level during the pre-charge time period, such as the disable voltage V. INHIBIT Also known as V DDSA The “prohibited voltage level” can correspond to a voltage level that is high enough to counteract the effects of a programming voltage pulse applied to the memory element associated with the corresponding control line (e.g., word line).

[0167] like Figures 12A to 12B As shown, the pre-charging process of a control line (such as a bit line) can involve multiple time periods. For example, a first time period (“Time Period 1”) 1231 may be associated with constant current control line charging. Constant current control line charging limits or controls the current draw through the line during pre-charging. By initially limiting or controlling the current draw through the control line during pre-charging, current spikes that occur during the initial time period of pre-charging can be reduced. However, because the current draw is limited, the amount of time required for the control line to be charged to the desired bias level can be greater than in the case of unrestricted or uncontrolled charging. During the first time period, the control line 1220B can be charged with a regulated or controlled current. During Time Period 1, high current consumption is mitigated by managing constant current charging.

[0168] During period 1, control line 1220B can be charged to the target voltage level V. TGT / V HSATGT Control line 1220B is charged to the target voltage level V. TGT / V HSATGT This can occur within a certain time period spanning the duration of period 1. The term "time period" is used herein according to its broad and general meaning and can refer to any duration or cycle associated with one or more periods of the pre-charging process. Figure 12A and Figure 12B The charge pump circuit associated with the curve can be configured to limit the charging current and / or keep the charging current constant during period 1, so that the first period can be considered a constant current pre-charging period. For example, in period 1, the current on control line 1220B can be limited to approximately 40mA, which can help control or prevent relatively high current spikes during the first period of pre-charging. By controlling the ramp rate of control line 1220B during period 1, peak current consumption can be reduced or controlled, at the cost of requiring additional time to reach the target voltage level V. TGT / V HSATGT .

[0169] Once the control line has reached the target threshold voltage level V TGT / VHSATGT , Figure 12B The second phase of the pre-charging process shown (“Phase 2”) may involve charging the control line 1220B without controlling or regulating the current supplied to the control line. That is, while a controlled or regulated current level can be ensured in Phase 1, such regulation or control of the current from the voltage source (e.g., disabled) to the control line may not be implemented in Phase 2.

[0170] During period 2, after point 1225, the current supplied to control line 1220B can be considered a free current because it is unrestricted or not regulated or controlled in any way. Therefore, the current on control line 1220B can be as high as possible based on the voltage difference between the voltage source and the control line, and the impedance associated with the charging path. During period 2, relatively high peak current consumption may occur, at least in part, due to the capacitive coupling between control lines (e.g., bit line to bit line), resulting in a large peak ICC, such as... Figure 11A As shown at position 1100 in the diagram.

[0171] Some specific embodiments of this disclosure provide a reduction in peak current consumption during period 1 and / or period 2 of the pre-charging process. The degree of reduction or control over peak current consumption can be determined and / or managed by controlling the delay between the start of period 1 and the start of period 2. Additionally or alternatively, this can be achieved at least in part by manipulating the target voltage level V. TGT / V HSATGT To control the degree of reduction in peak current, such as by increasing the target voltage level V. TGT / V HSATGT This extends the time period associated with time period 1.

[0172] Despite Figure 12B The term V was used in the associated description. INHIBIT / V DDSA However, it should be understood that the voltage level to which the control line is charged during pre-charging can be any bias level, such as the read voltage level. In an implementation where control line 1220B is a word line, where the word line pre-charging is combined with a voltage read operation, period 1 may involve ramping the word line voltage from approximately 0V to the read voltage associated with the unselected word line. For example, the read voltage may be approximately 6V-8V, which can consume current. Therefore, period 1 can be used to provide current control to limit peak current.

[0173] Existing techniques for controlling peak ICC have not yet addressed the modification of the threshold point 1225 for each programming loop. (See above regarding...) Figures 11A to 11BThe peak current discussed is changed via a programmed loop as the capacitance on the control line / bit line changes. This occurs during period 2 (1232) of the pre-charge period (1230) (or in...). Figure 12A The peak ICC value shown in the figure (approaching P7) is strongly cyclically correlated because the bit line capacitive load changes with the number of bit lines charged to disable mode in multiple memory cells to which programming pulses are applied. Therefore, it is difficult to set the single regulated charging current transition point (1225) to the unregulated current (and correspondingly, the single V... HSATGT (Level) to provide the "most effective point" point, thereby optimizing both peak ICC and tprog in all loops during the tprog programming cycle.

[0174] The peak ICC of the second period 1232 of the pre-charge phase 1230 of the programming cycle can be partially controlled by appropriately selecting the threshold voltage of the bit line 1220B, wherein the regulated charging current is switched to an unregulated charging current; in various embodiments of this disclosure, modification of this voltage threshold can be combined with the selected threshold voltage detection parameter V in a cyclically correlated (or more specifically, bit line capacitance correlated) manner. HSATGT This is achieved through a method that, if the detection level is set to a higher range, the peak ICC will decrease, but tprog will increase. On the other hand, if the detection level parameter is set to a lower value, the peak ICC will be high, but tprog will decrease, as shown in the following figure.

[0175] Figure 13A This illustrates a portion of the programming cycle, particularly in the early stages of the programming process within the tprog cycle (such as in the start segment). Figure 11A Figure 1300 shows the close-range ICC current distribution curves during the period (1107) or later in the programming cycle (such as during the end segment (Figure A, 1109)). The ICC output currents of both types (1310, 1320) are superimposed to illustrate the output, where in the first case corresponding to the first current distribution curve 1310, a lower threshold detection level V is used. TGT / V HSATGT For example, in V DDSA At 70.6%, and it can be seen that although a small current spike of 1310A appears in the current distribution curve 1310, the current is still well controlled. The threshold detection level V... TGT / V HSATGT Increase to a higher amount, such as V DDSA88.2% of the current distribution curve 1320 was generated with a lower ICC output in the later part of period 1, but with a delay 1330. This delay was caused by the longer transition time of the inhibit bit from the regulated charging current to the unregulated (fast) charging current. Considering the later peak 1310 corresponding to the lower threshold detection voltage scenario, the current distribution curve 1310 was generated to ensure that the current distribution curve 1310 was generated from the lower threshold detection level V. TGT / V HSATGT The reduced programming time exceeds the higher threshold detection level V TGT / V HSATGT This results in current distribution curve 1320. As mentioned elsewhere, when the threshold detection level is set to a low value, the relatively moderate rise in the ICC is due to the start or end segment ( Figure 11B This is caused by the cyclic operation within 1107B and 1109B respectively, where the bit line capacitance is lower than the middle segment ( Figure 11B ,1108B).

[0176] Figure 13B This shows a portion of the programming cycle, specifically a middle segment of the programming process in the tprog cycle (e.g., Figure 11A Figure 1300B shows the near-field ICC current distribution curve of a portion of the cycle in (1108). Similar to... Figure 13B The example shown superimposes the ICC output currents (1340, 1350) of the two types to illustrate the output, where in the first case corresponding to the first current distribution curve 1340, a lower threshold detection level V is used. TGT / V HSATGT For example, in V DDSA At 70.6%, a significant current spike of 1340A appears on the current distribution curve. The threshold detection level V... TGT / V HSATGT Increase to a higher amount, such as V DDSA 88.2% of the current distribution curve 1350, with a significantly lower ICC output in the later part of period 1, shows a decrease of approximately 12mA at the peak in the figure shown, but this is followed by an increase in the bit line charging time (8μs compared to 6μs for current distribution curve 1340), and the bit line charging occurs significantly later in time. Considering that the peak value of 1340A corresponding to the lower threshold detection voltage scenario exceeds the maximum ICC of 12mA for current distribution curve 1350, for the case of higher bit line capacitance in the middle segment, the current distribution curve 1350 is significantly lower than the peak value of 1340A for the lower threshold detection level V. TGT / V HSATGT The reduction in programming time may be unreasonable, especially when excessive peak ICC could lead to circuit failure.

[0177] As mentioned above Figure 13A and Figure 13B As shown, one way to control peak ICC is to control the charging of the bit line to reach the prohibition voltage level, since the highest ICC peak is often seen during the middle segment of device cyclic programming, where the bit line typically experiences higher capacitance. Figures 14A to 14C An exemplary memory array and the corresponding parasitic capacitances generated according to the disable / programmable state of the bit lines electrically connected to the memory array are shown.

[0178] about Figure 14A The memory cell array 1406 may include a group of memory cells MC0-MC4 connected via word lines and bit lines. Control circuitry 1404 may include a state machine capable of communicating with the memory cells in the memory cell array 1406. Selected word line (shown as WL) n The memory cells may include memory cells (MC)0, MC1, MC2, and MC3. Selected word lines may be connected to a set of bit lines, including bit lines (BL)0, BL1, BL2, and BL3. Control circuitry 1404 may use different verification techniques to verify the memory cells for different iterations of the verification operation, as will be further described herein.

[0179] like Figure 14A As shown by reference numeral 1408, control circuitry 1404 can identify a set of data states for a group of memory cells on a selected word line. In some embodiments, control circuitry 1404 can receive programming command data (e.g., from a controller associated with a non-volatile memory device), and the programming command data can specify the data state to which the memory cell and / or each corresponding memory cell will be programmed. Alternatively or additionally, control circuitry can identify the data state by performing one or more read operations (sometimes referred to as sensing operations). For example, control circuitry can perform a read operation that includes providing a signal to a data latch of the memory cell. The signal can cause the data latch to provide a return signal to control circuitry that identifies the data state. Control circuitry can perform a read operation for each corresponding memory cell connected to the selected word line. As shown by reference numeral 1410 and as described above, control circuitry 1404 can perform a programming operation to begin programming the memory cells on the selected word line.

[0180] Figure 14B This is shown in the context of bit line capacitance. Figure 14A This is part of the memory cell array 1406. As described above, parasitic capacitive coupling can occur between adjacent bit lines (represented by the parasitic equivalent capacitors 1450 and 1451 shown). When the "not selected" or "inhibited" bit line is charged to a value such as V... DDSAThe level of the unselected bit line is low, but when its adjacent bit line is grounded (indicating the programming status of the line), the coupling or load between the bit lines can be relatively high. Therefore, a relatively large amount of charge (or current) may be required to charge the unselected / inhibited bit line. Whether the unselected bit line is adjacent to the selected bit line on one or both sides also affects the amount of charge (or current) required to charge the unselected bit line. For example, when the unselected bit line is adjacent to the selected bit line on one side, the coupling capacitance between the two bit lines will receive the value of the bit line capacitance. Furthermore, when the unselected / inhibited bit line is adjacent to the selected bit line on both sides, both coupling capacitances will be charged, such as Figure 14B As shown (bit line BL1 is selected (“0”), bit line BL2 is charged to an unselected / inhibited state (“1”), and bit line 3 is shown as selected (“0”)). In this case, capacitors are applied on both sides of BL2, and each Cbl / 2 is added together to form the parasitic capacitance value Cbl. The actual value of Cbl / 2 depends on the circuit topology, semiconductor process and materials used in manufacturing, V DDSA The value varies, but in some examples it can be about pF or less. On the other hand, when an unselected bit line is positioned between two other unselected bit lines, this can be considered as not having to charge the coupling capacitance between the bit lines, and therefore no parasitic contribution occurs.

[0181] Figure 14C The diagram illustrates the case of 5 bit lines considering parasitic capacitance; more specifically, between the furthest bit lines BL0 and BL4 and the center bit line BL2. In this case, the bit lines BL0…BL4 are configured as 0 1 1 1 0, meaning the three center bit lines are in an unselected / inhibited state, and the furthest bit lines are in a programmed state. As mentioned above, when bit lines such as BL1, BL2, and BL3 are at the same potential (in this case, "1" or V), DDSA When BL1 is connected to BL2 or BL3 to BL2, the measurable parasitic capacitances generated between BL1 and BL2 or BL3 and BL2 are small and can therefore be considered zero. However, for this data pattern configuration of bit lines BL0…BL4, parasitic capacitances 1460 and 1461 are generated between BL2 and BL0 and between BL2 and BL4, respectively. Depending on the circuit geometry, process, voltage, etc., these capacitances C2bl / 2 (for two bit line parasitic capacitance equivalents) can be a fraction of approximately pF, but are still not negligible. Capacitances beyond two bit lines can also be modeled, but approximately far capacitances (e.g., “C0”) can be assigned for the average bit line configuration of the selected size memory array 1406. Figure 14DThe table illustrates capacitance calculation based on bitline configuration, and once specific values ​​for the relevant capacitance are inserted into the variables in the table, the specific capacitance for each data mode can be calculated. For example, for a TLC memory array, if we count all cells from different states, we can calculate the total probability of disabling "1" cells and programming "0" cells for each pulse, and the probability of each BL mode can be calculated. Therefore, the total capacitive load for each pulse is... Where C_bl(i) represents the capacitance of mode i, P_bl(i,n) represents the probability of mode i with pulse number n, and N_bl represents the total number of BLs. Therefore, aspects of this disclosure provide a way to determine the bitline capacitive distribution within a programming cycle (e.g., within tprog) during the programming cycle by modeling the probability distribution of certain bitline modes within the cycle that forms the programming cycle.

[0182] Therefore, in one aspect of this disclosure, the individual bit line capacitances, generated from the aforementioned cross-bit line parasitic capacitances and through statistical methods, are applied to the programming cycle to determine the average cycle capacitance for a specific memory cell type and configuration. In summary, in the early stages of the tprog programming cycle (e.g., during segment 1107 of FIG11A), when the memory cell array begins in an erase state, fewer bit lines will be in disabled / deselected mode because most memory cells will need to be programmed; therefore, many bit lines take zero / low voltage values, and low or negligible cross-bit line capacitances will be present. During this segment, lower capacitance means, as per [the previous section], [the following is a continuation of the previous section]: Figure 13A As shown and described in the relevant text, the threshold for prohibiting voltage charging, V, is reduced. HSATGT This can cause the relevant bit lines to charge to V faster. DDSA This does not cause significant current spikes, and therefore, from a performance perspective, by adjusting the voltage sensing parameter V... HSATGT This can be advantageous to reduce the transition from regulated to unregulated charge during that segment. Furthermore, during the middle segments of the programming cycle (e.g., in...) Figure 11A During segment 1108, some memory cells are becoming fully programmed, and therefore their corresponding bit lines will be placed high or disabled / deselected, thus increasing the bit line configuration (such as...). Figure 14D The bit line configurations shown at the top of the table (in the middle direction) are more likely to occur, and therefore the bit lines are more likely to have significant parasitic capacitances associated with them. Therefore, Figure 13B The current distribution curve shown is applicable to this segment of the programming cycle, and the significant capacitance-related spike in this state ensures that the voltage sensing parameter V can be adjusted upwards during this segment. HSATGTIncreasing the adjusted charge transition point to the unadjusted point can be advantageous, even if it causes a delay (at the cost of a significant saving in peak ICC). Finally, during the final segment of the programming cycle (e.g., in...) Figure 11A During segment 1109, more and more cells are being programmed, and therefore most bit lines begin to take an disable / deselect mode, interspersed with fewer "0" or select modes, thereby again reducing the parasitic capacitance associated with the specific bit line configuration within the programming cycle, and adjusting the transition voltage detection parameter V downwards during this segment. HSATGT It can reduce the delay of blocking bit line charging without causing unwanted peak ICC spikes.

[0183] The embodiments of this disclosure can determine that the transition point is located in an early segment (e.g., Figure 11A , 1107), intermediate / pre-charge segments (e.g., Figure 11A ,1108) and the final segment ( Figure 11A The position between 1109). For example, as Figure 11A and Figure 11B As shown, in one exemplary configuration, the capacitance change of the bit line charging state across programming cycles results in three roughly equal intervals based on the total number of programming cycles to complete a programming cycle (e.g., at time tprog). Therefore, once the maximum cycle count is set (explained in more detail below), the first third of the number of programming cycles can have a lower V. HSATGT The value, the middle third will have a higher V HSATGT The value, and the last third will have a lower V. HSATGT Value. For example, for a specific memory device configuration, if the maximum loop count is set to 21, then programming loops 1-7 will use a lower V. HSATGT If, for example, within the range of 65% to 75%, loops 8-13 will use V. HSATGT The setting is, for example, in the range of 85% to 95%, and cycles 1-7 will use a lower V. HSATGT Set, for example, within the range of 65% to 75%.

[0184] In yet another implementation, during the process tracking and storage of the peak ICC value for each programming cycle within the corresponding period, the controller of the memory storage device can set V within the programming cycle or a predetermined number of programming cycles (e.g., 10 cycles). HSATGT Maintain a constant level. Once the peak ICC value is tracked and recorded, the programming cycle number is correlated with the peak value in the ICC, and V can be adjusted on a per-cycle basis in future programming cycles. HSATGT (For example, for a cycle that is known to consistently exceed the maximum expected ICC level, increase V) HSATGTThis prevents peak ICC from exceeding a predetermined maximum ICC level; an exemplary predetermined maximum ICC can be set to 50mA (or any other desired maximum threshold). This regulates the current usage of the storage device to avoid unwanted ICC peaks while minimizing the impact on programming latency.

[0185] The implementation plan also provides V HSATGT Incremental changes within the programming cycle to minimize the impact on programming time tprog. In some implementations, V HSATGT The transition proceeds gradually from low to high, and then from high to low, through the early, middle, and final segments of the programming cycle discussed above. However, in various implementations, the program is switched to V upon entering the pre-charge (or middle) segment of programming. HSATGT Introduce small variations to incrementally increase V as the programming loop gets closer to the midpoint between the start and completion of the precharge / intermediate segment. HSATGT In this increasing V HSATGT During the elevation segment, V can be programmed for each consecutive loop. HSATGT Increase the increment, increase things like (V) HSATGT Max–V HSATGT The amount of (Min) / (precharge / half of the cycle in the middle segment), where V HSATGT Max is V HSATGT It can be raised to a predetermined maximum value, such as 88%, V HSATGT Min is V HSATGT The minimum value that can be reduced to, for example, 70%, and the number of cycles in half of the precharge / intermediate segment represents the number of cycles in the precharge programming segment (e.g., Figure 11A Half the number of programming cycles traversed in segment 1108 (as shown). Thus, when the programming cycle enters the pre-charge / intermediate segment 1108, V HSATGT The value will gradually increase from the minimum to the maximum, and rise to approximately the maximum value at about the midpoint of the precharge / intermediate segment 1108. Similarly, in the remaining programming loop from the midpoint of the precharge / intermediate segment 1108 to the exit point near the end segment 1109 of the precharge / intermediate segment 1108, V... HSATGT A certain amount can be incrementally reduced in each programming loop, such as (V HSATGT Max–V HSATGT Min) / (number of cycles in the precharge / intermediate segment 1108), such that when the programming cycle completes in the precharge / intermediate segment 1108 and enters the final segment 1109, V HSATGT Approaching V HSATGT Min, and continue operating on each loop until the current programming cycle ends. Thus, VHSATGT The increases and decreases have been smoother, thus reducing the impact of V. HSATGT The increase in V causes an impact on programming time tprog. Although a linear increment is described, any increment / decrement method can be used to smoothly change V. HSATGT The changes.

[0186] In yet another implementation, the controller of this disclosure utilizes bit-line data mode configuration on a per-programmable loop basis to execute from a pre-stored data mode to V. HSATGT A table lookup of a table, where V is in that table. HSATGT Directly related to the bit line equivalent capacitance (as shown, for example, in Table 14D, where V... HSATGT Not shown in the column shown, but will be related to the entry "BL EquivCap", such that the higher value of BL Equiv Cap will be equal to the higher value of V within a predetermined range. HSATGT Furthermore, a lower BLEquiv Cap value will be equal to a lower V value within a predetermined range. HSATGT This allows any pre-configured V to be stored for a specific bit line known to exhibit a specific capacitive effect on the peak ICC. HSATGT The pattern can be changed based on the table lookup value corresponding to each bit line configuration. HSATGT In relevant implementations, if, for example, the processing loop is experiencing a peak ICC value above a certain threshold (where the stored V can be increased for such bit line configurations in the table), HSATGT The value of V can then be updated by the processor of this disclosure for each bit line configuration stored in the table. HSATGT Similarly, if the peak ICC is determined to be significantly lower than the maximum expected ICC level for a specific positioning line data configuration, the stored V can be reduced. HSATGT The value of is adjusted to minimize the impact on programming time.

[0187] Figure 15The processing flow 1500 of this disclosure is illustrated. The programming process of the memory cell array of the memory device begins 1501, and 1505 programming data for the cells within the memory cell array to be programmed is loaded, and the programming cycle counter is reset. During programming, the memory cells are progressively programmed from an erased state to a final desired state (e.g., state A, B, C, etc.). The charge state of the programmed memory cell can be progressively increased over multiple programming cycles until the final desired charge state is reached. Once the final programmed charge state of the memory cell is reached, the bit line associated with that memory cell can be latched by applying a disable voltage / bias level. Generally, for multiple parallel bit lines associated with a corresponding memory cell programmed in conjunction with a programming operation, the progressive latching / disabling of the bit lines during the programming cycles of the programming operation can be considered predictable when the programming data is scrambled (also called randomized). Therefore, a table or other data structure can be predefined to map the programming cycle or cycle number to the bit line bias level variance or the expected bit line capacitance. As the programming operation iterates through multiple programming cycles, such as V... HSATGT Parameters such as these can be dynamically adjusted based on the loop count, the current loop position in the fully programmed sequence, or the predicted loop-related individual bit line capacitance; any desired operating parameters can be dynamically adjusted to reflect the current loop in the programmed operation.

[0188] Process 1500 continues to determine whether the cycle count (1510) is within a “preset range.” The “preset range” can be determined by any suitable method; in one implementation, it is determined when the cycle number is in the middle segment of a programmed cycle (such as…). Figure 11A Segment 1108 in the middle), or segments with high expected bit line capacitance in the programming loop (such as...) Figure 11B Within segment 1108B, or approximately one-third of the programming cycle used to complete the programming cycle, the loop count is within a preset range. If the loop count is within the preset range, the parameter 1525 is set to reduce the ICC peak value, as detailed above, by increasing V. HSATGT This reduces the unregulated current charging of the inhibit bit line. If the cycle count is not within the preset range, then, for example, V... HSATGTParameters such as these are set to reduce the charging time of the disabled bit lines while minimizing the total programming time. Once the parameters are set, the selected memory cells are then programmed according to the process described above 1530, with the selected cells having an increased floating gate threshold during the programming step. Once programming 1530 is complete, the cells of the memory array are read and verified to determine whether a sufficient threshold voltage has been achieved within the memory cells (therefore, future bit lines in the programming cycle need to be disabled or deselected), or whether additional programming is required to increase the cell threshold voltage to a predetermined level, as determined in step 1505; the cycle count is also incremented. If verification has passed for all involved memory cells 1540, programming ends 1550; otherwise, if the maximum cycle count has not been achieved 1545, the process continues to step 1510 to determine if the cycle count is within a preset range. Otherwise, if the maximum cycle count has been reached, the process terminates 1550.

[0189] The maximum cycle count can be determined in any suitable manner. Generally, memory devices can be pre-characterized based on their semiconductor process technology, design rules, memory cell configuration, etc., and the maximum cycle count can be determined and preset. For example, an exemplary memory cell will be able to be fully programmed within approximately 20 cycles. For this exemplary configuration, the allowed maximum cycle count can be set to a slightly higher number, such as 24. In this way, a small number of manufactured memory devices that require slightly more than 20 cycles to complete programming can be found within operating specifications, and for outlier memory devices that still cannot complete programming of some memory cells after the cycle count reaches 24, the programming cycle can be terminated and a programming failure reported, so the controller of the memory device will retire the block with the non-programmable memory cells. This method prevents the memory devices of this disclosure from getting stuck in infinite loops and experiencing unwanted voltage stress. In addition, for a specific product incorporating the features of this disclosure, the cycle count required to complete programming can be pre-assessed, and this cycle count is typically very close to a fixed number, with lifetime variation typically less than 5%. In an alternative embodiment, the controller of this disclosure maintains a counter that maintains the total number of programming cycles required to fully program a memory cell in a single programming cycle, and based on this total number of cycles, a maximum cycle count can be determined based on the actual performance of the memory device (e.g., the average of the maximum cycle count can be calculated and used as the maximum cycle count), or the maximum value of the total number of cycles can be used as the maximum cycle count value for future programming.

[0190] Figure 16The processing flow 1600 of this disclosure is illustrated, wherein aspects of this disclosure may use memory cell states to distinguish switching points for bit line charging. The programming process for the memory cell array of the memory device begins 1601, and 1605 loading programming data for the cells within the memory cell array to be programmed, and resetting the programming cycle counter. During programming, memory cells are progressively programmed from an erase state to a final desired state (e.g., state A, B, C, etc.). Process 1600 continues to determine 1610 whether to check the V of a specific programming state in a verification operation following the current programming pulse. T If the result is positive, then parameter V will be... HSATGT Set to a higher level of 1620 to reduce peak ICC, as described above; otherwise, use the first lower level of 1625. For example, in a 3-bit NAND device per cell, there are seven states (S1, S2, S3, S4, S5, S6, and S7) that need to be programmed. If the V of some states (i.e., S3 or S4) will be checked in a verification operation after the current programming pulse... T Then the PR_CLK bitline equalization time is set to be longer.

[0191] In the implementation scheme described above, when a specific state begins to be verified, a higher V is first applied at the programming loop. HSATGT And when a specific state has been programmed and is no longer verified, the initial lower V is applied again at the programming loop. HSATGT Generally speaking, for higher V HSATGT The start of the loop can also be determined by when a specific state has been programmed, and for higher V... HSATGT The end of the loop can be determined by when a specific state begins to be verified.

[0192] Once the parameters are set, the selected memory cells are then programmed according to the process described above (1630), with the selected cells having an increased floating gate threshold during the programming step. Once programming 1630 is complete, the cells of the memory array are read and verified to determine whether a sufficient threshold voltage has been achieved within the memory cells (thus requiring disabling or deselecting future bit lines in the programming cycle), or whether additional programming is needed to increase the cell threshold voltage to a predetermined level, as determined in step 1605; the cycle count is also incremented. If verification has passed for all involved memory cells (1640), programming ends (1650); otherwise, if the maximum cycle count has not been achieved (1645), the process continues to step 1610 to determine if the cycle count is within a preset range. Otherwise, if the maximum cycle count has been reached, the process terminates (1650).

[0193] Figure 17The processing flow 1700 of this disclosure is illustrated, wherein various aspects of this disclosure may use memory cell states to adjust the programming reset timing (PR_CLK timing). For example, if a certain state is under programming verification, the PR_CLK bitline equalization time is set longer to allow bitline equalization to V. CELSRCV (Prohibit bit line discharge and programming bit line charging, such as) Figure 12A (The intervals are shown in 1235). This timing is also related to bit line capacitance and has pulse-dependent characteristics due to the different levels of parasitic bit line capacitance generated by different data modes. Therefore, for some pulses with high bit line capacitive loads, the PR_CLK timing parameter can be set longer, while for other pulses with relatively small bit line capacitive loads, the PR_CLK timing can be set shorter.

[0194] The programming process for the memory cell array of the memory device begins at 1701, and at 1705, programming data for the cells within the memory cell array to be programmed is loaded, and the programming cycle counter is reset. During programming, the memory cells are progressively programmed from an erase state to the final desired state (e.g., states A, B, C, etc.). Process 1700 continues to determine at 1710 whether a particular programming state indicates that a bit line should be disabled or charged (e.g., states C or D are under programming verification). If the result is affirmative, the parameter PR_CLK is set to a longer value at 1720 to allow sufficient time for bit lines affected by higher capacitance to stabilize to V. CELSRC Otherwise, if possible, use the first lower timing of 1725 to shorten programming time.

[0195] Once the parameters are set, the selected memory cells are then programmed according to the process described above (1730), with the selected cells having an increased floating gate threshold during the programming step. Once programming (1730) is complete, the cells of the memory array are read and verified to determine if a sufficient threshold voltage has been achieved within the memory cells (thus requiring disabling or deselecting future bit lines in the programming cycle), or if additional programming is needed to increase the cell threshold voltage to a predetermined level, as determined in step 1705; the cycle count is also incremented. If verification has passed for all involved memory cells (1740), programming ends (1750); otherwise, if the maximum cycle count has not been achieved (1745), the process continues to step 1710 to determine if the cycle count is within a preset range. Otherwise, if the maximum cycle count has been reached, the process terminates (1750).

[0196] Figure 18The processing flow 1800 of this disclosure is illustrated, wherein aspects of this disclosure may use memory cell states to adjust the programming reset timing (PR_CLK timing). For example, if the current loop count is within the preset range described above, the PR_CLK bitline equalization time is set longer to allow bitline equalization to V. CELSRC (Prohibit bit line discharge and programming bit line charging, such as) Figure 12A (The intervals are shown in 1235). This timing is also related to bit line capacitance and has pulse-dependent characteristics due to the different levels of parasitic bit line capacitance generated by different data modes. Therefore, for some pulses with high bit line capacitive loads, the PR_CLK timing parameter can be set longer, while for other pulses with relatively small bit line capacitive loads, the PR_CLK timing can be set shorter.

[0197] The programming process for the memory cell array of the memory device begins at 1801, and at 1805, programming data for the cells within the memory cell array to be programmed is loaded, and the programming cycle counter is reset. During programming, the memory cells are progressively programmed from an erased state to a final desired state (e.g., state A, B, C, etc.). Process 1800 continues to determine at 1810 whether the cycle count is within a “preset range.” The “preset range” can be determined by any suitable method; in one embodiment, when the cycle number is in the middle segment of the programming cycle (such as…), the cycle count is determined. Figure 11A Segment 1108 in the middle), or segments with high expected bit line capacitance in the programming loop (such as...) Figure 11B When the loop count is within the preset range (within segment 1108B), if the result is positive, the parameter PR_CLK is set to a longer value of 1820 to allow sufficient time for the bit line affected by higher capacitance to stabilize to V. CELSRC Otherwise, if possible, use the first lower timing of 1825 to shorten programming time.

[0198] Once the parameters are set, the selected memory cells are then programmed according to the process described above (1830), with the selected cells having an increased floating gate threshold during the programming step. Once programming 1830 is complete, the cells of the memory array are read and verified to determine whether a sufficient threshold voltage has been achieved within the memory cells (thus requiring disabling or deselecting future bit lines in the programming cycle), or whether additional programming is needed to increase the cell threshold voltage to a predetermined level, as determined in step 1805; the cycle count is also incremented. If verification has passed for all involved memory cells (1840), programming ends (1850); otherwise, if the maximum cycle count has not been achieved (1845), the process continues to step 1810 to determine if the cycle count is within a preset range. Otherwise, if the maximum cycle count has been reached, the process terminates (1850).

[0199] about Figures 19 to 20 An additional embodiment of this disclosure is disclosed, which allows modification of the R_CLK verification timing parameter (bit line set to V) via programming in a loop. BL (Timing). If the bit line is not properly discharged before the read / verify phase, it will affect the bit line setting to V. BL The timing spent on level sensing (in) Figure 12A (A visual depiction can be seen in region 1240). (For example, for SLCs with 2 to 3 total programming cycles, overprogramming problems have been observed if the bit line set-up time is insufficient; for TLCs, some states under this condition have also been observed where overprogramming may occur if the bit line set-up timing does not have sufficient duration. This timing is also related to bit line capacitance and has pulse-dependent characteristics due to the different levels of parasitic bit line capacitance generated by different data modes. Therefore, for some pulses with high bit line capacitive loads, the R_CLK timing parameter can be set longer, while for other pulses with relatively small bit line capacitive loads, the R_CLK timing can be set shorter.)

[0200] about Figure 19 The programming process for the memory cell array of the memory device begins at 1901, and at 1905, programming data for the cells within the memory cell array to be programmed is loaded, and the programming cycle counter is reset. During programming, the memory cells are progressively programmed from an erase state to the final desired state (e.g., states A, B, C, etc.). Process 1900 continues to determine at 1910 whether a particular programming state indicates that a bit line should be disabled or charged (e.g., states C or D are under programming verification). If the result is affirmative, the parameter R_CLK is set to a longer value at 1920 to allow sufficient time for bit lines affected by higher capacitance to stabilize to V. BL Otherwise, if possible, use the first lower timing of 1925 to shorten programming time.

[0201] Once the parameters are set, the selected memory cells are then programmed according to the process described above (1930), with the selected cells having an increased floating gate threshold during the programming step. Once programming (1930) is complete, the cells of the memory array are read and verified to determine if a sufficient threshold voltage has been achieved within the memory cells (thus requiring disabling or deselecting future bit lines in the programming cycle), or if additional programming is needed to increase the cell threshold voltage to a predetermined level, as determined in step 1905; the cycle count is also incremented. If verification has passed for all involved memory cells (1940), programming ends (1750); otherwise, if the maximum cycle count has not been achieved (1945), the process continues to step 1910 to determine if the cycle count is within a preset range. Otherwise, if the maximum cycle count has been reached, the process terminates (1950).

[0202] Figure 20 The processing flow 2000 of this disclosure is illustrated, wherein various aspects of this disclosure may use memory cell states to adjust the programming read / verify timing (R_CLK timing). For example, if the current loop count is within the preset range described above, the PR_CLK bitline equalization time is set longer to allow bitline equalization to V. BL ( Figure 12A (Region 1240). This timing is also related to bit line capacitance and has pulse-dependent characteristics due to the different levels of parasitic bit line capacitance generated by different data modes. Therefore, for some pulses with high bit line capacitive loads, the R_CLK timing parameter can be set longer, while for other pulses with relatively small bit line capacitive loads, the R_CLK timing can be set shorter.

[0203] The programming process for the memory cell array of the memory device begins in 2001, and in 2005, programming data for the cells within the memory cell array to be programmed is loaded, and the programming cycle counter is reset. During programming, the memory cells are progressively programmed from an erased state to a final desired state (e.g., state A, B, C, etc.). Process 2000 continues to determine whether the 2000 cycle count is within a “preset range.” The “preset range” can be determined by any suitable method; in one embodiment, when the cycle number is in the middle segment of the programming cycle (such as…), the cycle count is determined. Figure 11A Segment 1108 in the middle), or segments with high expected bit line capacitance in the programming loop (such as...) Figure 11B When the loop count is within the preset range (within segment 1108B), if the result is positive, the parameter R_CLK is set to a longer value of 2020 to allow sufficient time for the bit line affected by higher capacitance to stabilize to V. BL Otherwise, if possible, use the first lower timing of 2025 to reduce programming time.

[0204] Once the parameters are set, the selected memory cells are then programmed according to the process described above (2030), with the selected cells having an increased floating gate threshold during the programming step. Once programming (2030) is complete, the cells of the memory array are read and verified to determine if a sufficient threshold voltage has been achieved within the memory cells (thus disabling or deselecting future bit lines in the programming cycle), or if additional programming is needed to increase the cell threshold voltage to a predetermined level, as determined in step 2005; the cycle count is also incremented. If verification has passed for all involved memory cells (2040), programming ends (2050); otherwise, if the maximum cycle count has not been achieved (2045), the process continues to step 2010 to determine if the cycle count is within a preset range. Otherwise, if the maximum cycle count has been reached (2050), the process terminates.

[0205] As used in this article, the verification operation can be the verification part of a programming-verification operation.

[0206] The foregoing specific embodiments of this disclosure have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best elucidate the principles of this disclosure and its practical application, thereby enabling others skilled in the art to best utilize this disclosure in various embodiments and with various modifications suitable for the particular intended use. The scope of this disclosure is intended to be defined by the appended claims.

[0207] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0208] Those skilled in the art will recognize that this technology is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but covers all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0209] The foregoing specific embodiments of this disclosure have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best elucidate the principles of this disclosure and its practical application, thereby enabling others skilled in the art to best utilize this disclosure in various embodiments and with various modifications suitable for the particular intended use. The scope of this disclosure is intended to be defined by the appended claims.

[0210] Various terms are used to refer to specific system components. Different companies may refer to components by different names—this document does not intend to distinguish between components with different names but the same function. In the following discussion and claims, the terms "including" and "comprising" are used in an open-ended manner and should therefore be understood as meaning "including but not limited to...". Furthermore, the terms "couple" or "couples" are intended to indicate indirect or direct connections. Thus, if a first device is coupled to a second device, the connection can be made either through a direct connection or through an indirect connection via other devices and connections.

[0211] Furthermore, when a layer or element is referred to as being "on" another layer or substrate, it may be directly on the other substrate layer, or an intermediary layer may also be present. Additionally, it should be understood that when a layer is referred to as being "below" another layer, it may be directly below the other layer, and one or more intermediary layers may also be present. Moreover, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intermediary layers may also be present.

[0212] As described herein, controllers include single circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), processors with control software, field-programmable gate arrays (FPGAs), or combinations thereof.

Claims

1. A non-volatile memory device, comprising: Multiple memory cells, each of which is electrically coupled to multiple bit lines; and A control circuit coupled to the plurality of memory cells and configured to program the plurality of memory cells in a programming operation comprising a plurality of programming cycles, the control circuit being further configured to: The programming loops are counted to establish a loop count for the programming loop sequence, thereby completing the programming operation. Multiple bit lines coupled to memory cells that will be prevented from further programming are pre-charged in two time periods, namely a current-limited period and a current-unlimited period. In at least one programming cycle, in response to the voltage applied to the bit line coupled to the memory cell to be prevented from further programming exceeding the target voltage, a transition occurs from the current-limited pre-charge period to the current-unlimited period. as well as If the loop count is located at the beginning of the programming loop sequence, the target voltage is set to a first lower target voltage; if the loop count is located in the middle of the programming loop sequence, the target voltage is set to a higher target voltage value; and if the loop count is located at the end of the programming loop sequence, the target voltage is set to a second lower target voltage value.

2. The non-volatile memory device of claim 1, wherein the peak current utilization of the memory device is reduced during programming operations because the target voltage depends on the cycle count.

3. The non-volatile memory device according to claim 1, wherein, The programming loop sequence comprises at least twenty programming loops, and the intermediate segments of the programming loop sequence comprise no more than six programming loops.

4. The non-volatile memory device according to claim 1, wherein, The programming operation programs the memory cells into at least three bits for each memory cell.

5. The non-volatile memory device according to claim 1, wherein, During the unrestricted current period of pre-charging, the voltage applied to the bit line coupled to the memory cell that will be prevented from further programming is increased to a disable voltage.

6. A method for controlling a non-volatile memory device, the non-volatile memory device comprising a plurality of memory cells electrically coupled to a plurality of bit lines, and comprising control circuitry coupled to the plurality of memory cells and configured to program the memory cells in a programming operation comprising a plurality of programming cycles, the method comprising the following steps: The programming loops are counted to establish a loop count for the programming loop sequence, thereby completing the programming operation. At least one bit line among the plurality of bit lines coupled to the memory cell that will be prevented from further programming is precharged in two time periods, the two time periods being a current-limited time period and a current-unlimited time period. In at least one programming cycle, in response to the voltage applied to the bit line coupled to the memory cell to be prevented from further programming exceeding a target voltage, the process transitions from the current-limited pre-charge period to the current-unlimited pre-charge period, and If the loop count is located at the beginning of the programming loop sequence, the target voltage is set to a first lower target voltage; if the loop count is located in the middle of the programming loop sequence, the target voltage is set to a higher target voltage value; and if the loop count is located at the end of the programming loop sequence, the target voltage is set to a second lower target voltage value.

7. The method of claim 6, wherein the peak current utilization of the memory device is reduced during programming operations because the target voltage depends on the cycle count.

8. The method according to claim 6, wherein, The programming loop sequence comprises at least twenty programming loops, and the intermediate segments of the programming loop sequence comprise no more than six programming loops.

9. The method according to claim 6, wherein, The programming operation programs the memory cells into at least three bits for each memory cell.

10. The method according to claim 6, wherein, During the unrestricted current period of pre-charging, the voltage applied to the bit line coupled to the memory cell that will be prevented from further programming is increased to a disable voltage.

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