A memory and a method for manufacturing the same, a storage system

Abstract

The application discloses a memory and a preparation method thereof and a storage system. A stack layer is first formed on a substrate, the stack layer comprising a first region and a second region adjacent to the first region. A patterned hard mask layer is then formed on the stack layer, the patterned hard mask layer comprising a first stop layer covering the first region, the patterned hard mask layer comprising a first opening pattern on the first stop layer and a channel hole pattern on the stack layer corresponding to the second region. Finally, the stack layer is etched based on the patterned hard mask layer to form a channel hole in the second region. The first stop layer can ensure that the stack layer of the first region is not etched. When etching the stack layer, at the junction of the region where the channel hole needs to be formed and the region where the channel hole does not need to be formed, the influence of the accumulation of residual molecules at the junction on the etching of the stack layer can be reduced, thereby improving the channel hole etching process of the edge of the second region and reducing the etching difficulty.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, and more particularly, to a memory and a preparation method thereof, and a memory system. BACKGROUND

[0002] In 3D NAND, the channel holes are arranged in an array, and are divided into multiple memory blocks or memory fingers by multiple gate line slits. Generally, multiple rows of channel holes (for example, 9 rows) can be arranged between any two adjacent gate line slits, and the spacing between the multiple rows of channel holes is equal. The channel holes adjacent to the gate line slits can be referred to as outer row holes (which can include one row or two rows or more rows).

[0003] In the etching process, the outer row holes are prone to various problems, and the etching of the channel holes is difficult. SUMMARY

[0004] Embodiments of the present application aim to provide a memory and a preparation method thereof, and a memory system, to improve the channel hole etching process of the second region edge and reduce the etching difficulty.

[0005] In a first aspect, embodiments of the present application provide a preparation method of a memory, comprising:

[0006] providing a substrate;

[0007] forming a stack layer on the substrate, the stack layer comprising a first region extending along a first direction and a second region adjacent to the first region;

[0008] forming a patterned hard mask layer on the stack layer, the patterned hard mask layer comprising a first stop layer covering the first region, the patterned hard mask layer comprising a first opening pattern on the first stop layer, and a channel hole pattern on the stack layer corresponding to the second region;

[0009] etching the stack layer based on the patterned hard mask layer to form channel holes corresponding to the channel hole pattern in the second region.

[0010] Further, the etching selectivity ratio of the first stop layer with respect to the patterned hard mask layer is less than 1.

[0011] Further, the first region is used to form a gate line slit.

[0012] Further, the stack layer further comprises a third region located at the periphery of the second region; the patterned hard mask layer comprises a second stop layer covering the third region; and the patterned hard mask layer further comprises:

[0013] a second opening pattern on the second stop layer.

[0014] Further, the first opening pattern and the second opening pattern are formed by using the same mask.

[0015] Further, the third region surrounds the second region.

[0016] Further, the step of forming the patterned hard mask layer on the stack layer comprises:

[0017] forming a hard mask layer on the stack layer, the hard mask layer having the first stop layer formed therein;

[0018] etching the hard mask layer to form the first opening pattern and the channel hole pattern.

[0019] Further, a distance between the first stop layer and a bottom surface of the hard mask layer is less than a distance between the first stop layer and a top surface of the hard mask layer.

[0020] Further, the step of forming the hard mask layer on the stack layer comprises:

[0021] forming a first hard mask layer on the stack layer;

[0022] etching the first hard mask layer to form an opening corresponding to the first region;

[0023] filling the first stop layer in the opening;

[0024] forming a second hard mask layer covering the first hard mask layer and the first stop layer.

[0025] Further, a depth of the opening is less than a thickness of the first hard mask layer.

[0026] Further, a width of the opening is greater than a width of the first region.

[0027] Further, after the step of etching the stack layer based on the patterned hard mask layer, the method for manufacturing the memory further comprises:

[0028] removing the patterned hard mask layer.

[0029] Further, the first opening pattern comprises a plurality of dummy holes on the first stop layer.

[0030] Further, the first opening pattern is a trench extending along the first direction.

[0031] Further, a material of the first stop layer comprises one of tungsten, polysilicon, silicon nitride, silicon oxynitride, and aluminum oxide.

[0032] In a second aspect, an embodiment of the present application provides a memory, comprising:

[0033] a substrate;

[0034] a stack structure located on the substrate, and comprising a first region extending along a first direction and a second region adjacent to the first region;

[0035] a plurality of channel structures penetrating the stack structure of the second region.

[0036] In a third aspect, an embodiment of the present application provides a memory system, comprising:

[0037] the memory as described in the second aspect;

[0038] a controller electrically connected with the memory, configured to control the memory to store data.

[0039] The embodiment of the present application has the beneficial effects that: a memory and a preparation method thereof, and a memory system are provided. A stack layer is first formed on a substrate. The stack layer comprises a first region extending along a first direction and a second region adjacent to the first region. A patterned hard mask layer is then formed on the stack layer. The patterned hard mask layer comprises a first stop layer covering the first region. The patterned hard mask layer comprises a first opening pattern on the first stop layer and a channel hole pattern corresponding to the second region on the stack layer. Finally, the stack layer is etched based on the patterned hard mask layer to form channel holes corresponding to the channel hole pattern in the second region. The first stop layer covering the first region can ensure that the stack layer of the first region is not etched, and only the second region is etched to form channel holes. Since the channel hole pattern is etched in the position corresponding to the second region in the formation process of the patterned hard mask layer, and the first opening pattern is etched in the position corresponding to the first region, the height difference of the patterned hard mask layer at the junction of the first region where no channel hole is needed and the second region where a channel hole is needed can be avoided. When etching the stack layer, the influence of residual molecules accumulated at the junction on the etching of the stack layer can be reduced, and the etching difficulty of the channel hole at the edge of the second region can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] The technical solutions and other beneficial effects of the present application will become apparent through the following detailed description of the specific embodiments of the present application, in conjunction with the accompanying drawings.

[0041] Figure 1 is a flowchart of a preparation method of a memory provided by an embodiment of the present application;

[0042] Figures 2a-2l is a structural schematic diagram of a memory in a preparation process provided by an embodiment of the present application;

[0043] Figures 3a-3d is a structural diagram of a memory in a manufacturing process according to another embodiment of the present application;

[0044] Figure 4 is a structural diagram of a memory according to an embodiment of the present application;

[0045] Figure 5 is a structural diagram of a memory system according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0047] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component could be termed a second component, and similarly, a second component could be termed a first component without departing from the scope of the present application.

[0048] It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements can also be present. Other words used to describe the relationship between elements should be interpreted in a like fashion.

[0049] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a thickness that is less than the thickness of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes between the top surface and the bottom surface of a continuous structure or at the top surface and the bottom surface. Layers can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed.

[0050] It should be noted that the diagrams provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the diagrams, the diagrams are not drawn according to the number, shape and size of the components in actual implementation, and the shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the component layout pattern can also be more complex.

[0051] In this document, the orientation of the memory is represented in a Cartesian coordinate system (X, Y and Z), in which the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0052] Please refer to Figure 1 , Figure 1 is a flowchart of the preparation method of the memory provided by the embodiments of the present application. Please refer to Figures 2a-2l , Figures 2a-2l is a structural diagram of the memory in the preparation process provided by the embodiments of the present application. The preparation method of the memory includes steps S1-S4.

[0053] Please refer to Figure 1 steps S1-S2 and Figure 2a .

[0054] Step S1: providing a substrate 10.

[0055] The substrate 10 can be a semiconductor substrate, for example, can be a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI) or germanium on insulator (GOI) and the like. The semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, and can also be a laminated structure, such as Si / SiGe and the like.

[0056] Step S2: forming a stack layer 20 on the substrate 10, the stack layer 20 including a first region 21 extending along a first direction and a second region 22 adjacent to the first region 21.

[0057] Specifically, the stack layer 20 is formed by alternately depositing an interlayer insulating layer 201 and an interlayer sacrificial layer 202 on the substrate 10, and the exemplary material of the interlayer insulating layer 201 can be silicon oxide, and the exemplary material of the interlayer sacrificial layer 202 can be silicon nitride, and the interlayer insulating layer 201 and the interlayer sacrificial layer 202 have different etching selectivities.

[0058] The stack layer 20 includes a first region 21 extending along a first direction (Y) and a second region 22 adjacent to the first region 21, Figure 2aThe display shows a first region 21 and two second regions 22 adjacent to the first region 21. The first region 21 is used to form a gate line slit (i.e. not to form a channel hole), and the second region 22 is used to form an array of channel holes. In this embodiment, there is a spacing region between the second region 22 and the first region 21, that is, there is a spacing region between the channel hole and the gate line slit, and the spacing region neither forms a channel hole nor forms a gate line slit.

[0059] In one embodiment, the stack layer 20 includes a plurality of first regions 21 and a second region 22 between any two adjacent first regions 21.

[0060] In one embodiment, the stack layer 20 further includes a third region 23 at the periphery of the second region 22. The third region 23 can be arranged around one side of the second region 22, or arranged around two sides of the second region 22, or arranged around three sides or the entire periphery of the second region 22. Figure 2a The third region 23 can be arranged at opposite sides of the second region 22, or arranged around the entire periphery of the second region 22.

[0061] In a specific embodiment, when the second region 22 is a core region, the third region 23 can be a staircase region. In another specific embodiment, the second region 22 can include a core region and a staircase region, and the third region 23 can be a peripheral device region or a scribe lane region.

[0062] It should be noted that neither the first region 21 nor the third region 23 forms a channel hole (both can be referred to as a non-pattern region). The second region 22 forms a channel hole (which can be referred to as a pattern region). The inventor has found that at the boundary position of the pattern region, the etching of the channel hole is prone to various problems, such as poor roundness of the channel hole, incomplete etching of the bottom of the channel hole, deformation of the channel hole, and reduction of the size of the bottom of the channel hole. Further research has shown that one of the reasons for the above problems is that a hard mask layer needs to be formed on the entire structure when etching the channel hole, and the hard mask layer above the pattern region is consumed when etching the channel hole in the pattern region. However, the non-pattern region does not need to etch the channel hole, so the hard mask layer of the non-pattern region is not consumed or is consumed slowly, and thus the height of the hard mask layer of the non-pattern region is greater than the height of the hard mask layer of the pattern region during the etching of the hard mask layer. Thus, when the channel hole etching process is performed, the residues generated by etching will accumulate at the position where the height difference of the hard mask layer exists, thereby affecting the etching of the channel hole at the boundary of the pattern region.

[0063] Please refer to step S3 in Figure 1 and Figures 2b-2j .

[0064] Step S3: A patterned hard mask layer 50B is formed on the stacked layer 20. The patterned hard mask layer 50B has a first stop layer 321 covering the first region 21. The patterned hard mask layer 50B includes a first opening pattern 51 on the first stop layer 321 and a channel hole pattern 52 on the stacked layer 20 corresponding to the second region 22.

[0065] like Figure 2g As shown, a hard mask layer 50A can be formed on the stacked layer 20 first. A first stop layer 321 is formed in the hard mask layer 50A, covering the first region 21. In one embodiment, a second stop layer 322 can also be formed in the hard mask layer 50A, covering a third region 23. Figures 2h-2j As shown, the hard mask layer 50A is then etched to form a first opening pattern 51 on the first stop layer 321 and a channel hole pattern 52 on the stacked layer 20 corresponding to the second region 22, thereby forming a patterned hard mask layer 50B including the first opening pattern 51 and the channel hole pattern 52. A second stop layer 322 covering the third region 23 is formed in the patterned hard mask layer 50B. When the second stop layer 322 is also formed in the hard mask layer 50A, etching the hard mask layer 50A can also form a second opening pattern 53 on the second stop layer 322. The second opening pattern 53 and the first opening pattern 51 are formed using the same mask through photolithography and etching processes. Therefore, the formed patterned hard mask layer 50B can also include the second opening pattern 53, and a second stop layer 322 covering the third region 23 is formed in the patterned hard mask layer 50B. The first opening pattern 51 is located in the first region 21, and the channel hole region 52 penetrates the hard mask layer 50A of the second region 22 to expose part of the structure of the stacked layer 20.

[0066] In one embodiment, the etching selectivity of the first stop layer 321 relative to the patterned hard mask layer 50B (or hard mask layer 50A) is less than 1, and the etching selectivity of the second stop layer 322 relative to the patterned hard mask layer 50B (or hard mask layer 50A) is less than 1, so that during the etching of the hard mask layer 50A, the etching process stops on or in the first stop layer 321 and the second stop layer 322, that is, the hard mask layer 50A below the first stop layer 321 and the second stop layer 322 will not be etched.

[0067] Furthermore, the hard mask layer 50A may include a first hard mask layer 31 and a second hard mask layer 33. A first stop layer 321 and a second stop layer 322 are formed in the hard mask layer 50A. The steps for forming the hard mask layer 50A are as follows: Figures 2b-2g As shown.

[0068] As shown in FIG. 4A, a first hard mask layer 31 is first formed on the stack layer 20, and then a first patterned photoresist layer 40 is formed on the first hard mask layer 31 by a photolithography process. The pattern of the first patterned photoresist layer 40 is shown in FIG. 4B. The first patterned photoresist layer 40 has a first opening 41 and a second opening 42. The first opening 41 corresponds to the first region 21, and the second opening 42 corresponds to the third region 23. Figure 2b As shown in FIG. 4A, a first hard mask layer 31 is first formed on the stack layer 20, and then a first patterned photoresist layer 40 is formed on the first hard mask layer 31 by a photolithography process. The pattern of the first patterned photoresist layer 40 is shown in FIG. 4B. The first patterned photoresist layer 40 has a first opening 41 and a second opening 42. The first opening 41 corresponds to the first region 21, and the second opening 42 corresponds to the third region 23. Figure 2c As shown in FIG. 4B, the first patterned photoresist layer 40 has a first opening 41 and a second opening 42. The first opening 41 corresponds to the first region 21, and the second opening 42 corresponds to the third region 23. Figure 2c As shown in FIG. 4B, the first patterned photoresist layer 40 has a first opening 41 and a second opening 42. The first opening 41 corresponds to the first region 21, and the second opening 42 corresponds to the third region 23. Figure 2b As shown in FIG. 4B, the first patterned photoresist layer 40 has a first opening 41 and a second opening 42. The first opening 41 corresponds to the first region 21, and the second opening 42 corresponds to the third region 23. Figure 2c The number of the first openings 41 in the first patterned photoresist layer 40 is only an example. In some embodiments, the number of the first openings 41 in the second opening 42 can be more than one.

[0069] In an embodiment, the stack layer 20 can include a plurality of first regions 21, a second region 22 between any two adjacent first regions 21, and a third region 23 on one side of the second region 22. Accordingly, as shown in FIG. 4B, the first patterned photoresist layer 40 has a plurality of first openings 41 corresponding to a plurality of gate line slits, and a second opening 42 corresponding to the third region 23. Figure 2d In an embodiment, the stack layer 20 can include a plurality of first regions 21, a second region 22 between any two adjacent first regions 21, and a third region 23 on one side of the second region 22. Accordingly, as shown in FIG. 4B, the first patterned photoresist layer 40 has a plurality of first openings 41 corresponding to a plurality of gate line slits, and a second opening 42 corresponding to the third region 23.

[0070] After the first patterned photoresist layer 40 is formed, as shown in FIG. 4C, the pattern of the first patterned photoresist layer 40 is transferred to the first hard mask layer 31. Specifically, the first hard mask layer 31 can be etched based on the first patterned photoresist layer 40 to form a third opening 311 and a fourth opening 312. The third opening 311 corresponds to the first region 21, and the fourth opening 312 corresponds to the third region 23. The depth of the third opening 311 and the fourth opening 312 is less than the thickness of the first hard mask layer 31, that is, the first hard mask layer 31 is not etched to the bottom when etching the first hard mask layer 31. That is, there is a part of the first hard mask layer 31 between the third opening 311 and the fourth opening 312 and the stack layer 20. The direction of the "depth" is perpendicular to the substrate 10, that is, parallel to the Z direction. Figure 2e In an embodiment, because the spacing region between the first region 21 and the second region 22 does not need to form a channel hole, the spacing region also needs to form a first stop layer 321, so the range of the third opening 311 can cover the first region 21 and the spacing region, that is, the width W1 of the third opening 311 is greater than the width W2 of the first region 21, but the range of the third opening 311 does not cover the second region 22. The direction of the "width" is parallel to the extension direction (X) of the first region 21.

[0071] ​

[0072] like Figure 2f As shown, a first stop layer 321 and a second stop layer 322 are deposited in the third opening 311 and the fourth opening 312. Figure 2g As shown, a second hard mask layer 33 is deposited on the first hard mask layer 31, the first stop layer 321, and the second stop layer 322. The first stop layer 321 and the second stop layer 322 can be made of the same material, and the first hard mask layer 31 and the second hard mask layer 33 can be made of the same material (e.g., carbon). The first stop layer 321 and the second stop layer 322 have different etch selectivity ratios than the first hard mask layer 31 and the second hard mask layer 33, so that the etching of the hard mask layer 50A can stop in the stop layer.

[0073] The materials of the first stop layer 321 and the second stop layer 322 may include tungsten, polysilicon, silicon nitride, silicon oxynitride, and aluminum oxide. If silicon nitride is chosen as the material for the first stop layer 321 and the second stop layer 322, the stop layer will be damaged during the etching of the channel hole. However, the hard mask layer 50A (or the first hard mask layer 31) below the stop layer can also prevent the underlying stacked layer 20 from being etched. Since the hard mask layer 50A below the stop layer may also be damaged during the etching of the channel hole, the hard mask layer 50A below the stop layer can have a certain thickness.

[0074] In one embodiment, the distance H1 between the first stop layer 321 and the bottom surface of the hard mask layer 50A is less than the distance H2 between the first stop layer 321 and the top surface of the hard mask layer 50A (approximately equal to...). Figure 2j The depth of the first opening pattern 51 in the middle). This is beneficial for improving the etching process of the channel holes at the boundary of the pattern area, and also ensures that the etching process of the hard mask layer 50A and the channel holes will not etch into the stacked layer 20 of the non-pattern area. In a specific embodiment, the thickness of the hard mask layer 50A is 3 micrometers, and the distance H1 between the first stop layer 321 and the bottom surface of the hard mask layer 50A is 0.5 to 1.5 micrometers.

[0075] like Figure 2h As shown, a second patterned photoresist layer 50 is formed on the second hard mask layer 33 using a photolithography process. The pattern of the patterned photoresist layer is as follows: Figure 2i As shown, the second patterned photoresist layer 50 has an array of openings. Figure 2jAs shown, the hard mask layer 50A is etched based on the second patterned photoresist layer 50 to form a first opening pattern 51 corresponding to the first region 21, a channel hole pattern 52 corresponding to the second region 22, and a second opening pattern 53 corresponding to the third region 23. Therefore, the formed first opening pattern 51, second opening pattern 53, and channel hole pattern 52 are all hole-shaped. The openings in the first opening pattern 51 and the second opening pattern 53 can be called virtual holes, meaning they can each include multiple virtual holes (representing that no channel hole is formed below them). The openings in the channel hole pattern 52 are used to form a channel hole below it.

[0076] When the second patterned photoresist layer 50 is a positive photoresist, the pattern of the photomask used in the photolithography process is also as follows: Figure 2i As shown, this type of photomask has a simple and regular pattern, low cost, and does not require special design. In areas where etched vias are not required or in non-patterned areas (e.g., the first region 21 and the third region 23), stop layers (including the first stop layer 321 and the second stop layer 322) block the etching of the underlying stacked layer 20. Therefore, this photomask does not require special design for special regions (e.g., regions where vias are not formed or in non-patterned areas), and it can also be used to etch the hard mask layer 50A to form an opening pattern in non-patterned areas, making the process in non-patterned areas the same as the process in the second region 22, thus avoiding differences from the second region 22 and preventing various problems.

[0077] For example, if the hard mask layer 50A is not etched in the non-patterned area, but is etched in the second region 22 to form the channel hole pattern 52, this will cause differences. For example, if the hard mask layer 50A in the non-patterned area is higher, the residual molecules will accumulate at the height difference (the junction of the second region 22 and the non-patterned area or the edge of the second region 22) when the stacked layer 20 is etched to form the channel hole. Then the etching of the channel hole at the edge of the second region 22 will be affected, resulting in various problems in the edge etching process.

[0078] Please see Figures 3a-3d , Figures 3a-3d This is a schematic diagram of the structure of a memory during its fabrication process, provided in another embodiment of the present invention.

[0079] In this embodiment, the pattern of the second patterned photoresist layer 50a is as follows: Figure 3a and Figure 3b As shown, Figure 3b yes Figure 3a A top view. The second patterned photoresist layer 50a has a fifth opening 51a corresponding to the first stop layer 321 and a sixth opening 52a corresponding to the second stop layer 322, and has an opening 53a corresponding to the second region 22. Therefore, after etching the hard mask layer 50A to form the patterned hard mask layer 50B (as shown in the top view), the patterned hard mask layer 50B is formed.Figure 3d As shown in FIG. 5, the first opening pattern 51 and the second opening pattern 53 are trenches extending along the first direction (Y).

[0080] In an embodiment, the pattern of the second patterned photoresist layer 50a is as shown in FIG. 6. Figure 3c Figure 3c As shown in FIG. 6, three fifth openings 51a and six openings 52a are arranged on one side of the second patterned photoresist layer 50a. This means that the first regions 21 can be multiple, the second regions 22 are located between any two adjacent first regions 21, and the third regions 23 can be arranged at any position outside all the second regions 22. Among them, the fifth openings 51a are trenches extending along the first direction (Y), and the sixth openings 52a are trenches extending along the X direction. Therefore, according to the above embodiments, the pattern of the mask plate corresponding to the first regions 21 and the third regions 23 can be a hole (the same as the trench hole pattern 52) or an opening similar to a trench.

[0081] Please refer to step S4 in FIG. 4 and Figure 1 . Figures 2k-2l .

[0082] Step S4: etching the stack layer 20 based on the patterned hard mask layer 50B to form trench holes 60 corresponding to the trench hole pattern 52 in the second regions 22.

[0083] Since the first stopping layer 321 and the second stopping layer 322 are formed above the first regions 21 and the third regions 23, the etching process will generally only etch the stack layer 20 of the second regions 22.

[0084] In the etching process of the trench holes 60, if the materials of the first stopping layer 321 and the second stopping layer 322 are silicon nitride, the first stopping layer 321 and the second stopping layer 322 and the patterned hard mask layer 50B will also be consumed. Since the patterned hard mask layer 50B below the first stopping layer 321 and the second stopping layer 322 has a certain thickness, after the trench holes 60 are formed, part of the patterned hard mask layer 50B remains on the stack layer 20 (as shown in FIG. 8). Figure 2k After the trench holes 60 are formed, the remaining part of the patterned hard mask layer 50B is removed by ashing and / or wet cleaning process (as shown in FIG. 9). Figure 2l

[0085] ​​The preparation method of the memory provided by the embodiment of the present application sets a stop layer corresponding to the non-pattern area (the first area 21 and the third area 23) in the hard mask layer 50A, so as to ensure that no channel hole is formed in the non-pattern area. In the process of forming the patterned hard mask layer 50B, the hard mask layer 50A corresponding to the pattern area and the non-pattern area is etched at the same time, so as to form an opening pattern corresponding to the non-pattern area and a channel hole pattern 52 corresponding to the pattern area (the second area 22), thereby avoiding the difference between the hard mask layers 50A of the two areas and reducing the process difficulty of subsequent etching of the channel hole. In particular, the etching process of the channel hole at the boundary of the pattern area can be improved, so as to reduce various problems. In addition, the embodiment of the present application does not need special mask plate design, that is, the design of the mask plate is simplified, and the risk of increasing the top size of the channel hole at the boundary of the pattern area, such as the problem of overlapping of the channel hole top or too deep etching of the channel hole bottom, can be avoided.

[0086] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of the memory provided by the embodiment of the present application.

[0087] The memory 100 includes a substrate 10, a stack structure 20a located on the substrate 10, a plurality of channel structures 60a and a gate line slit structure 211. The stack structure 20a includes a first area 21 extending along a first direction (Y) and a second area 22 adjacent to the first area 21. The plurality of channel structures 60a penetrates the stack structure 20a of the second area 22. The gate line slit structure 211 is located in the first area 21 and penetrates the stack structure 20a.

[0088] The stack structure 20a includes an interlayer insulating layer 201 and a gate layer 202a arranged alternately. The exemplary material of the interlayer insulating layer 201 can be silicon oxide, and the exemplary material of the gate layer 202a can be tungsten.

[0089] In the memory 100 provided by the embodiment of the present application, the top diameters of the plurality of channel structures 60a can be equal, that is, the top diameters of the channel structures 60a at the boundary of the second area 22 and in the middle of the second area 22 can be equal. Compared with the structure in which the top diameter of the channel structure 60a at the boundary of the second area 22 is greater than the top diameter of the channel structure 60a in the middle of the second area 22, the channel structure 60a in the embodiment of the present application does not have the problems of overlapping of the channel structure 60a at the boundary and too deep etching of the channel structure 60a at the boundary. Moreover, the design of the mask plate used in the preparation process is simple and low in cost.

[0090] Please refer to Figure 5 , Figure 5is a structural schematic diagram of a storage system provided by an embodiment of the present application. The storage system 400 comprises a memory 401 and a controller 402. The memory 401 can be any of the memories in the above embodiments. The controller 402 is electrically connected to the memory 401 and is configured to control the memory 401 to store data. The memory 401 can perform the operation of storing data based on the control of the controller 402.

[0091] In some embodiments, the storage system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro- MMC, a secure digital card in the form of SD, mini-SD and micro-SD, a storage device in the form of a personal computer memory card international association (PCMCIA) card, a storage device in the form of a peripheral component interconnect (PCI), a storage device in the form of a high-speed PCI (PCI-E), a compact flash (CF) card, a smart media card or a memory stick, etc.

[0092] The memory 401 comprises a substrate, a stack structure located on the substrate, and a plurality of channel structures. The stack structure comprises a first region extending along a first direction and a second region adjacent to the first region. The plurality of channel structures penetrate the stack structure of the second region.

[0093] The above description of the embodiments is only used to help understand the technical solutions of the present application and its core ideas; those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for producing a memory, characterized by, Comprising: providing a substrate; forming a stack layer on the substrate, the stack layer comprising a first region extending along a first direction and a second region adjacent to the first region; forming a hard mask layer on the stack layer, the hard mask layer having a first stop layer formed therein covering the first region; forming a patterned hard mask layer by etching the hard mask layer, the patterned hard mask layer comprising a first opening pattern on the first stop layer and a channel hole pattern on the stack layer corresponding to the second region, the first opening pattern and the channel hole pattern being formed in a same etching process, and a depth of the first opening pattern being less than a depth of the channel hole; etching the stack layer based on the patterned hard mask layer to form channel holes corresponding to the channel hole pattern in the second region.

2. The method of claim 1, wherein The first stop layer has an etching selectivity ratio relative to the patterned hard mask layer less than 1.

3. The method of claim 1, wherein the step of depositing the memory material is performed by atomic layer deposition. The first region is used to form a gate line slit.

4. The method of claim 1, wherein the step of depositing the memory material is performed by atomic layer deposition. The stack layer further comprises a third region located at a periphery of the second region; The patterned hard mask layer has a second stop layer formed therein covering the third region; the patterned hard mask layer further comprises: a second opening pattern on the second stop layer.

5. The method of claim 4, wherein the step of depositing the memory material is performed by atomic layer deposition. The first opening pattern and the second opening pattern are formed by using a same mask plate.

6. The method of claim 4, wherein the step of depositing the memory material is performed by atomic layer deposition. The third region surrounds a periphery of the second region.

7. The method of claim 1, wherein the method further comprises: A distance from the first stop layer to a bottom surface of the hard mask layer is less than a distance from the first stop layer to a top surface of the hard mask layer.

8. The method of claim 1, wherein the method further comprises: The step of forming the hard mask layer on the stack layer comprises: forming a first hard mask layer on the stack layer; etching the first hard mask layer to form an opening corresponding to the first region; filling the first stop layer in the opening; forming a second hard mask layer covering the first hard mask layer and the first stop layer.

9. The method of claim 8, wherein the step of depositing the memory material is performed by atomic layer deposition. A depth of the opening is less than a thickness of the first hard mask layer.

10. The method of claim 8, wherein the step of depositing the memory material is performed by atomic layer deposition. A width of the opening is greater than a width of the first region.

11. The method of claim 1, wherein After the step of etching the stack layer based on the patterned hard mask layer, the method for manufacturing the memory further comprises: removing the patterned hard mask layer.

12. The method of claim 1, wherein The first opening pattern comprises a plurality of virtual holes on the first stop layer.

13. The method of claim 1, wherein The first opening pattern is a groove extending along the first direction.

14. The method of claim 1, wherein A material of the first stop layer comprises one of tungsten, polysilicon, silicon nitride, silicon oxynitride, and aluminum oxide.

15. A memory, comprising: The memory is manufactured by the method for manufacturing the memory according to any one of claims 1-14, and the memory comprises: a substrate; a stack structure on the substrate, and comprising a first region extending along a first direction and a second region adjacent to the first region; a plurality of channel structures penetrating the stack structure of the second region.

16. A storage system, characterized by Comprising: the memory according to claim 15; a controller electrically connected with the memory, and configured to control the memory to store data.

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