A method of manufacturing a gate-all-around transistor

Abstract

The application discloses a manufacturing method of a ring gate transistor, and relates to the technical field of semiconductors, which is used for preventing the leakage of a parasitic channel in the ring gate transistor and improving the conductive performance of the ring gate transistor. The manufacturing method comprises the following steps: forming a germanium-containing semiconductor layer and a first fin on a substrate. The first fin comprises at least one layer along the thickness direction of the substrate. The content of germanium in the germanium-containing semiconductor layer is greater than the content of germanium in a channel layer and a sacrifice layer included in each layer. The germanium-containing semiconductor layer is subjected to at least a lateral thinning treatment, so that the width of the remaining part of the germanium-containing semiconductor layer is narrowed to a first preset width. The first preset width is greater than zero and smaller than the width of the first fin. The germanium-containing semiconductor layer subjected to the lateral thinning treatment is subjected to a first selective oxidation treatment, so that an isolation structure is formed between the substrate and the first fin. A shallow trench isolation is formed on the part of the substrate exposed outside the isolation structure. The top height of the shallow trench isolation is less than or equal to the top height of the isolation structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a manufacturing method of a ring gate transistor. BACKGROUND

[0002] Compared with a fin field effect transistor, the gate stack of the ring gate transistor is not only formed on the top and sidewall of the channel, but also formed on the bottom of the channel, so as to inhibit the short channel effect and enhance the gate control ability of the ring gate transistor.

[0003] However, in the case that the channel of the ring gate transistor includes at least one layer of nanosheet, it is difficult to prevent the leakage of the parasitic channel in the ring gate transistor by using the existing manufacturing method, thereby reducing the working performance of the ring gate transistor. SUMMARY

[0004] The present application aims to provide a manufacturing method of a ring gate transistor for preventing the leakage of the parasitic channel in the ring gate transistor and improving the conductive performance of the ring gate transistor.

[0005] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of a ring gate transistor, which comprises:

[0006] A germanium-containing semiconductor layer and a first fin portion located on the germanium-containing semiconductor layer are formed on a substrate. The first fin portion includes at least one layer of stack along the thickness direction of the substrate. Each layer of stack includes a sacrificial layer and a channel layer located on the sacrificial layer. The content of germanium in the germanium-containing semiconductor layer is greater than the content of germanium in the channel layer and the sacrificial layer, respectively.

[0007] The germanium-containing semiconductor layer is at least subjected to a lateral thinning process to narrow the width of the remaining part of the germanium-containing semiconductor layer to a first preset width. The first preset width is greater than zero and less than the width of the first fin portion.

[0008] The germanium-containing semiconductor layer at least after the lateral thinning process is subjected to a first selective oxidation process to form an isolation structure between the substrate and the first fin portion.

[0009] A shallow trench isolation is formed on the part of the substrate exposed outside the isolation structure. The top height of the shallow trench isolation is less than or equal to the top height of the isolation structure.

[0010] Compared with the prior art, the manufacturing method of the ring gate transistor provided by the application comprises the following steps: forming a germanium-containing semiconductor layer on a substrate, and forming a first fin on the germanium-containing semiconductor layer. The first fin comprises at least one layer stack, and each layer stack comprises a sacrificial layer and a channel layer on the sacrificial layer. The channel layer is a film layer for manufacturing nanosheets included in the ring gate transistor. Meanwhile, the content of germanium in the germanium-containing semiconductor layer is greater than the content of germanium in the channel layer and the sacrificial layer. Based on this, the processing technology and etchant which only have a corresponding lateral thinning effect on the germanium-containing semiconductor layer can be selected according to the different content of germanium in the germanium-containing semiconductor layer and the channel layer and the sacrificial layer, so that the lateral thinning processing is only performed on the germanium-containing semiconductor layer, without affecting the channel layer for manufacturing nanosheets and the sacrificial layer, thereby improving the yield of the ring gate transistor.

[0011] In addition, the manufacturing method provided by the application is to perform at least lateral thinning processing on the germanium-containing semiconductor layer to narrow the width of the germanium-containing semiconductor layer to a first preset width, and then perform first selective oxidation processing, so that the non-conductive isolation structure and the shallow trench isolation between the substrate and the first fin are filled to prevent the parasitic channel from leaking, and the manufacturing efficiency of the isolation structure is improved under the premise of improving the conductive performance of the ring gate transistor. In addition, it is also beneficial to solve the problem of affecting the channel layer for manufacturing nanosheets caused by the long processing time of the first selective oxidation processing and other factors, thereby further improving the yield of the ring gate transistor.

[0012] Furthermore, the channel layer in the first fin is a film layer for manufacturing nanosheets, and the channel layer is formed on the substrate before at least lateral thinning processing is performed on the germanium-containing semiconductor layer, so that the first fin comprising the sacrificial layer and the channel layer is not formed by replacing the fin in the process of forming the shallow trench isolation through the STI first process, thereby simplifying the manufacturing process of the ring gate transistor and improving the manufacturing efficiency of the ring gate transistor. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0014] Figure 1 Part (1) in FIG. 1 is a structure schematic diagram of a first fin structure and a barrier layer after being formed on a substrate; Figure 1 Part (2) in FIG. 1 is a structure sectional view of a fin field effect transistor after being formed on a substrate;

[0015] Figure 2 Part (1) in FIG. 2 is a structure sectional view after a second fin structure is processed by using a punch-through prevention implantation process; Figure 2Part (2) in FIG. 1 is a structure sectional view after forming a ring gate transistor based on the second fin structure;

[0016] Figure 3 A flow chart of a manufacturing method of a ring gate transistor provided by an embodiment of the present application;

[0017] Figure 4 A structure schematic diagram after sequentially forming a film layer for manufacturing a germanium-containing semiconductor layer and at least one layer stack on a substrate in an embodiment of the present application;

[0018] Figure 5 A first structure schematic diagram after forming a germanium-containing semiconductor layer and a first fin portion in an embodiment of the present application;

[0019] Figure 6 A second structure schematic diagram after forming a germanium-containing semiconductor layer and a first fin portion in an embodiment of the present application;

[0020] Figure 7 Part (1) in FIG. 2 is a structure sectional view along the B-B' direction after forming a germanium-containing semiconductor layer and a first fin portion; Figure 7 Parts (2) and (3) in FIG. 2 are two structure sectional views along the A-A' direction after forming a germanium-containing semiconductor layer and a first fin portion in an embodiment of the present application;

[0021] Figure 8 A third structure schematic diagram after forming a germanium-containing semiconductor layer and a first fin portion in an embodiment of the present application;

[0022] Figure 9 A structure sectional view along the A-A' direction after forming a protection structure in an embodiment of the present application;

[0023] Figure 10 Parts (1) and (2) in FIG. 4 are two structure sectional views along the A-A' direction after forming a second fin portion in an embodiment of the present application;

[0024] Figure 11 Parts (1) and (2) in FIG. 5 are two structure schematic diagrams after forming an oxide layer in an embodiment of the present application;

[0025] Figure 12 Parts (1) and (2) in FIG. 6 are two structure schematic diagrams after removing the oxide layer in an embodiment of the present application;

[0026] Figure 13 Parts (1) and (2) in FIG. 7 are two structure schematic diagrams after performing a lateral thinning process on the germanium-containing semiconductor layer in an embodiment of the present application;

[0027] Figure 14 A structure schematic diagram after forming an isolation structure in an embodiment of the present application;

[0028] Figure 15Fig. 1 is a schematic diagram of a structure after forming a shallow trench isolation in an embodiment of the present application;

[0029] Figure 16 Figs. 1 and 2 are cross-sectional views of a structure along the B-B' direction and the A-A' direction, respectively, after forming a sacrificial gate and a second sidewall in an embodiment of the present application;

[0030] Figure 17 Fig. 3 is a cross-sectional view of a structure along the B-B' direction after forming a source region and a drain region in an embodiment of the present application;

[0031] Figure 18 Fig. 4 is a cross-sectional view of a structure along the B-B' direction after forming a dielectric layer in an embodiment of the present application;

[0032] Figure 19 Fig. 5 is a schematic diagram of a structure after removing a sacrificial gate in an embodiment of the present application;

[0033] Figure 20 Figs. 5 and 6 are cross-sectional views of a structure along the B-B' direction and the A-A' direction, respectively, after forming a ring gate transistor in an embodiment of the present application;

[0034] Figure 21 Fig. 7 is a cross-sectional view of a structure along the A-A' direction after forming a ring gate transistor in an embodiment of the present application.

[0035] In the drawings: 11 is a substrate, 12 is a germanium-containing semiconductor layer, 13 is a first fin portion, 131 is a stack, 1311 is a sacrificial layer, 1312 is a channel layer, 14 is a source formation region, 15 is a drain formation region, 16 is a transition region, 17 is an oxide layer, 18 is a protection structure, 181 is a mask layer, 182 is a first sidewall, 19 is an isolation structure, 20 is a shallow trench isolation, 21 is a sacrificial gate, 22 is a second sidewall, 23 is a second fin portion, 24 is a source region, 25 is a drain region, 26 is a dielectric layer, 27 is a channel, 271 is a nanosheet, 28 is a gate stack, 281 is a gate dielectric layer, 282 is a gate electrode, 29 is a first fin structure, 30 is a barrier layer, 31 is a second fin structure, and 32 is a central region. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0037] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. These diagrams are not drawn to scale in that certain details are exaggerated for the purpose of clarity and that certain details can be omitted. The shapes and relative sizes of the various regions, layers, and the relative positions of the regions / layers shown in the drawings are merely exemplary and can deviate in actuality due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed according to actual needs by those skilled in the art.

[0038] In the context of the present disclosure, when one layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if one layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0039] In addition, the terms "first", "second", etc. are used only for the purpose of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0040] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0041] A fin field-effect transistor has a first fin structure and shallow trench isolation formed on a substrate. The portion of the first fin structure exposed outside the shallow trench isolation is called the fin. The portion of this fin surrounded by the gate stack structure corresponds to the channel of the fin field-effect transistor. In this case, when the fin field-effect transistor is in operation, the channel is controlled by the gate stack structure, thereby enabling conduction between the source and drain regions. However, the portion of the first fin structure surrounded by the shallow trench isolation is separated from the gate stack structure by the shallow trench isolation, making this portion far from the control of the gate stack structure, thus making it prone to channel punch-through effect, resulting in a parasitic channel.

[0042] like Figure 1 As shown, in order to solve the problem of parasitic channel leakage in fin field-effect transistors, during the fabrication of fin field-effect transistors, after forming a first fin structure 29 and a shallow trench isolation 20 on the substrate 11, at least one impurity ion with the opposite conductivity type to the impurities doped in the source and drain regions is injected into the first fin structure 29 through a punch-through injection process, so as to form a barrier layer 30 in the lower middle part of the first fin structure 29, thereby using the highly doped barrier layer 30 to suppress parasitic channels.

[0043] With the development of semiconductor technology, gate-around transistors (GOTMTs) have emerged. Compared to fin field-effect transistors (FETs), GOTMTs have a gate stacking structure formed not only on the top and sidewalls of the channel but also at the bottom, thereby enhancing the gate control capability, suppressing short-channel effects, and resulting in higher performance. However, when the channel width of a GOTMT is wide, it is difficult to solve the problem of parasitic channel leakage using the aforementioned anti-punch-through injection process. Specifically, for example... Figure 2 As shown, during the fabrication of the gate-around transistor, due to the wider channel width of the gate-around transistor, the second fin structure 31 formed on the substrate 11 also has a wider width. Therefore, when ionic impurities are implanted into the second fin structure 31 using a punch-through implantation process, the ionic impurities have difficulty entering the central region 32 along the width direction of the second fin structure 31; that is, the central region 32 along the width direction of the second fin structure 31 does not completely form a barrier layer 30. In this case, after applying an appropriate voltage to the gate stack 28 of the gate-around transistor, the source and drain regions can not only conduct through the channel, but the aforementioned central region 32 also suffers from parasitic channel leakage, thereby reducing the operating performance of the gate-around transistor.

[0044] To solve the above technical problems, the embodiment of the present application provides a manufacturing method of a ring gate transistor. In the manufacturing method of the ring gate transistor provided by the embodiment of the present application, the germanium-containing semiconductor layer is first subjected to at least a lateral thinning treatment to narrow its width to a first preset width, and then subjected to a first selective oxidation treatment, so as to fill the non-conductive isolation structure and the shallow trench isolation between the substrate and the first fin portion to prevent the parasitic channel from leaking, and improve the manufacturing efficiency of the isolation structure under the premise of improving the conductive performance of the ring gate transistor. In addition, it is also beneficial to solve the problem of affecting the channel layer for manufacturing nanosheets caused by the long processing time of the first selective oxidation treatment, and further improve the yield of the ring gate transistor.

[0045] As shown in Figure 3 , the embodiment of the present application provides a manufacturing method of a ring gate transistor. In the following, the manufacturing process will be described according to the perspective view and sectional view of the operation shown in Figures 4 to 21 . Specifically, the manufacturing method of the ring gate transistor comprises:

[0046] As shown in Figures 4 to 8 , a germanium-containing semiconductor layer 12 and a first fin portion 13 located on the germanium-containing semiconductor layer 12 are formed on a substrate 11. Along the thickness direction of the substrate 11, the first fin portion 13 comprises at least one layer of laminated layer 131. Each layer of laminated layer 131 comprises a sacrificial layer 1311 and a channel layer 1312 located on the sacrificial layer 1311. The content of germanium in the germanium-containing semiconductor layer 12 is greater than the content of germanium in the channel layer 1312 and the sacrificial layer 1311, respectively.

[0047] Specifically, the above-mentioned substrate can be any semiconductor substrate such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, etc.

[0048] For the above-mentioned germanium-containing semiconductor layer, the structure of the germanium-containing semiconductor layer can be set according to actual needs. For example, as shown in Figures 5 to 7 , the germanium-containing semiconductor layer 12 can be a fin-shaped structure formed on the substrate 11. At this time, the germanium-containing semiconductor layer 12 can be self-aligned with the first fin portion 13 above. For example, as shown in Figure 8 , the germanium-containing semiconductor layer 12 can be a film layer covering the surface of the substrate 11. At this time, the first fin portion 13 is formed on part of the germanium-containing semiconductor layer 12. In addition, the material of the germanium-containing semiconductor layer 12 can be any semiconductor material containing germanium, such as germanium-silicon or germanium. The specific content of germanium in the germanium-containing semiconductor layer 12 can be set according to the specific content of germanium in the channel layer 1312 and the sacrificial layer 1311, which is not limited here. Furthermore, the thickness of the germanium-containing semiconductor layer 12 can also be set according to actual needs.

[0049] In some cases, when the germanium-containing semiconductor layer is self-aligned with the first fin and the thickness of the subsequently formed shallow trench isolation is relatively large, in addition to forming the germanium-containing semiconductor layer and the first fin on the substrate, a third fin can also be formed on the substrate. This third fin is self-aligned with the germanium-containing semiconductor layer 12 and the first fin 13.

[0050] For the first fin described above, the channel layer in the stack included in the first fin is used to fabricate the nanosheets of the gate-around transistor. Therefore, the number of layers in the stack included in the first fin is equal to the number of nanosheet layers in the channel of the gate-around transistor. For example: Figures 5 to 8 ,as well as Figure 21 As shown, when the channel of the manufactured gate-around transistor includes two nanosheets 271, the first fin 13 includes two stacked layers 131. The height and width of the channel layer in the stack are the same as the height and width of the corresponding nanosheets in the channel. The height of the sacrificial layer determines the spacing between adjacent nanosheets or between the nanosheets and the substrate, so the height of the sacrificial layer can be set with reference to the specifications of the gate stack included in the gate-around transistor. As for the materials of the channel layer and the sacrificial layer, both can be semiconductor materials with a certain etching selectivity (for example, the material of the sacrificial layer can be silicon, and the material of the channel layer can be a group III-V semiconductor material), so as to facilitate the formation of the first fin by processes such as epitaxial growth, and to prevent the portion of the channel layer used to manufacture nanosheets from being affected during the subsequent removal of part of the sacrificial layer to form nanosheets, thereby improving the yield of the gate-around transistor. Furthermore, the germanium content in both the channel layer and the sacrificial layer is greater than or equal to zero and less than the germanium content in the germanium-containing semiconductor layer. The specific germanium content in both can be set according to actual needs, and is not specifically limited here. For example, the material of the germanium-containing semiconductor layer mentioned above is Si. 1-y Ge y When 0 < y ≤ 1, the channel layer material can be Si. 1-x Ge x The sacrificial layer can be made of Si. 1-z Ge z Where 0≤x≤1, 0≤z≤1, yx≥0.2, yz≥0.2, |xz|≥0.2. For example, the material of the germanium-containing semiconductor layer can be Si. 0.1 Ge 0.9 The channel layer can be made of Si 0.8 Ge 0.2 The sacrificial layer can be made of Si 0.5 Ge 0.5 For example, the material of the germanium-containing semiconductor layer can be Si. 0.5 Ge 0.5 The channel layer can be made of Si, and the sacrificial layer can also be made of Si. 0.7 Ge 0.3.

[0051] It is worth noting that, as described above, in the case of the material of the germanium-containing semiconductor layer, the channel layer and the sacrificial layer being Si 1- y Ge y , Si 1-x Ge x , Si 1-z Ge z , the film layer for manufacturing the germanium-containing semiconductor layer (or the germanium-containing semiconductor layer) located on the substrate can also serve as a strain buffer layer to provide stress to the film layer for manufacturing at least one stack formed thereon, so that the strain in the nanosheet formed based on the channel layer included in the above-mentioned stack is generated, the carrier mobility of the ring gate transistor is improved, and the driving performance of the ring gate transistor is improved.

[0052] In actual application, in the case of self-alignment of the germanium-containing semiconductor layer and the first fin, as shown in Figure 4 , the film layer for manufacturing the germanium-containing semiconductor layer and the film layer for manufacturing the first fin can be formed on the substrate 11 in sequence by using epitaxial growth and other processes. As shown in Figures 5 to 7 , the film layer for manufacturing the germanium-containing semiconductor layer 12 and the film layer for manufacturing the first fin 13 can be formed by using photolithography and etching processes from top to bottom. Specifically, as described above, refer to Figure 6 and Figure 7 Part (3), if the thickness of the shallow trench isolation formed subsequently is relatively small, only the film layer for manufacturing the germanium-containing semiconductor layer 12 and the film layer for manufacturing the first fin 13 need to be etched. Refer to Figure 5 and Figure 7 Parts (1) and (2), if the thickness of the shallow trench isolation is relatively large, in addition to the above-mentioned case, the substrate 11 also needs to be etched, and the etched part of the substrate 11 forms the third fin.

[0053] And in the case of the germanium-containing semiconductor layer covering the surface of the substrate, as shown in Figure 4 , the germanium-containing semiconductor layer and the film layer for manufacturing the first fin can be formed on the substrate 11 in sequence. As shown in Figure 8 , the film layer for manufacturing the first fin 13 can be obtained by etching from top to bottom using the above-mentioned process. After obtaining the first fin 13, the mask layer 181 located at the top of the first fin 13 can be retained.

[0054] As shown in Figures 9 to 13As shown, at least a lateral thinning process is performed on the germanium-containing semiconductor layer 12 to narrow the width of the remaining part of the germanium-containing semiconductor layer 12 to a first preset width W1. The first preset width W1 is greater than zero and less than the width of the first fin 13.

[0055] Specifically, as described above, in the case of self-alignment of the germanium-containing semiconductor layer and the first fin, the lateral thinning process can be directly performed on the germanium-containing semiconductor layer. In the case of the germanium-containing semiconductor layer covering the surface of the substrate, the lateral thinning process can be directly performed on the germanium-containing semiconductor layer, or the germanium-containing semiconductor layer can be selectively etched first to reduce the width of the germanium-containing semiconductor layer to a certain value, and then the lateral thinning process is performed on the germanium-containing semiconductor layer. Based on this, compared with directly performing the lateral thinning process on the germanium-containing semiconductor layer with a larger width, the thinning efficiency is higher when the lateral thinning process is performed on the germanium-containing semiconductor layer with a width equal to or slightly greater than the first fin, and at the same time, it can also prevent the first fin from being affected due to too long lateral thinning process time, thereby obtaining a high-quality channel based on the first fin and improving the yield of the ring gate transistor.

[0056] It can be understood that the above-mentioned germanium-containing semiconductor layer is located below the first fin. And after at least a lateral thinning process is performed on the germanium-containing semiconductor layer, the width of the remaining part of the germanium-containing semiconductor layer is smaller. Correspondingly, the support force provided by the remaining part of the germanium-containing semiconductor layer to the first fin is reduced. In addition, the more layers the first fin includes, the greater support force it needs, so the size of the above-mentioned first preset width can be determined according to the width of the first fin, the thickness of the layers included in the first fin, and the actual demand. For example: the above-mentioned first preset width can be 5nm to 15nm. Within the above-mentioned data range, the preferred value of the first preset width is 5nm to 8nm.

[0057] In addition, along the width direction of the first fin (parallel to the A-A' direction), the specific position of the remaining part of the germanium-containing semiconductor layer below the first fin after at least a lateral thinning process can be set according to the actual application scenario. For example: as shown in part (2) of Figure 13 , the remaining part of the germanium-containing semiconductor layer 12 can be located below the left side of the center of the first fin 13. For another example: as shown in part (1) of Figure 13 , the remaining part of the germanium-containing semiconductor layer 12 can be located directly below the first fin 13. At this time, as shown in part (2) of Figures 11 to 21As shown, compared to the remaining portion of the germanium-containing semiconductor layer 12 being offset from the bottom center of the first fin 13, the remaining portion of the germanium-containing semiconductor layer 12 being located directly below the first fin 13 corresponds to the equal processing rates on both sides of the germanium-containing semiconductor layer 12 during the aforementioned lateral thinning process. Therefore, the germanium-containing semiconductor layer 12 can provide equal support forces on both sides of the at least one stack 131 located thereon along the width direction during the aforementioned lateral thinning process, which helps to prevent the first fin 13, including the aforementioned at least one stack 131, from bending or collapsing during the lateral thinning process, thereby improving the yield of the gate ring transistor.

[0058] For example, such as Figure 8 As shown, when the germanium-containing semiconductor layer 12 covers the surface of the substrate 11, as Figures 9 to 13 As shown, the above-mentioned lateral thinning process of the germanium-containing semiconductor layer 12 to narrow the width of the remaining portion of the germanium-containing semiconductor layer 12 to a first preset width may include the following steps: Figure 9 As shown, a protective structure 18 is formed covering the outer periphery of the first fin 13. (As shown...) Figure 10 As shown, under the masking effect of the protective structure 18, at least the germanium-containing semiconductor layer 12 is patterned to obtain the second fin 23. Figures 11 to 13 As shown, the patterned germanium-containing semiconductor layer 12 is subjected to lateral thinning.

[0059] In practical applications, as mentioned above, if a mask layer is retained at the top of the first fin after its formation, sidewall material for manufacturing the first sidewall can be deposited on the formed structure using processes such as chemical vapor deposition. For example... Figure 9As shown, then a dry etching process or the like can be used to remove the part of the side wall material covering the substrate 11 and the mask layer 181, only leaving the part of the side wall material covering the sidewall of the first fin 13, to obtain the first side wall 182. The above-mentioned protection structure 18 includes the above-mentioned first side wall 182 and the above-mentioned mask layer 181. The material of the first side wall and the mask layer can be silicon nitride or the like. The specification of the protection structure can be set according to the actual application scenario. Then, under the masking effect of the protection structure, a dry etching process or the like can be used to at least pattern the germanium-containing semiconductor layer to obtain the second fin. Specifically, as described above, in the case that the thickness of the subsequently formed shallow trench isolation is different, the object of the above-mentioned patterning process is also different. If the thickness of the subsequently formed shallow trench isolation is relatively small, only the germanium-containing semiconductor layer needs to be etched. At this time, the second fin only includes the part of the germanium-containing semiconductor layer remaining after etching. If the thickness of the subsequently formed shallow trench isolation is relatively large, the substrate also needs to be etched additionally. The depth of the etched substrate can be set according to the thickness of the shallow trench isolation and the germanium-containing semiconductor layer. At this time, the second fin includes the part of the germanium-containing semiconductor layer remaining after etching, and the part of the substrate etched. Finally, the germanium-containing semiconductor layer after the patterning process can be subjected to a lateral thinning process under the protection of the protection structure. Because the protection structure can isolate the first fin from the external environment during the lateral thinning process, the protection structure can prevent the first fin from being affected during the lateral thinning process, thereby improving the yield of the ring gate transistor.

[0060] It can be understood that, as shown in FIG. 2, Figure 10 The width W2 of the above-mentioned second fin 23 is equal to the maximum width of the protection structure 18. In addition, as known from the above, the thickness of the above-mentioned germanium-containing semiconductor layer has a plurality of possible ranges, and the formation of the germanium-containing semiconductor layer, the first fin and the second fin also has a plurality of optional ways, thereby improving the applicability of the manufacturing method of the ring gate transistor provided by the embodiment of the present application in different application scenarios.

[0061] In actual application, taking the self-alignment of the germanium-containing semiconductor layer and the first fin as an example, the lateral thinning process of the germanium-containing semiconductor layer is described: after the formation of the germanium-containing semiconductor layer and the first fin on the substrate, according to the difference between the content of germanium in the germanium-containing semiconductor layer and the content of germanium in the channel layer and the sacrificial layer, an etchant having etching effect on the germanium-containing semiconductor layer is selected to directly perform lateral thinning process on the germanium-containing semiconductor layer. For example: the germanium-containing semiconductor layer can be etched by a dry etching process in a protective atmosphere of He gas using CF4 and O2 plasma. Alternatively, the germanium-containing semiconductor layer can also be subjected to a lateral thinning process by using a quasi-atomic layer etching process.

[0062] For example, Figures 11 to 13As shown, in the case of performing the above lateral thinning treatment by using a quasi-atomic layer etching process, the following steps can be included: as shown in Figure 11 As shown, the second selective oxidation treatment is performed on the germanium-containing semiconductor layer 12 with a width equal to the second preset width by using a wet etching solution with oxidizing property. After the second selective oxidation treatment, the sidewall of the germanium-containing semiconductor layer 12 along the width direction is inwardly recessed by a fixed thickness, and an oxidation layer 17 is formed on the sidewall of the germanium-containing semiconductor layer 12 along the width direction. The second preset width is greater than the first preset width and smaller than the width of the substrate 11. As shown in Figure 12 As shown, the oxidation layer is removed. As shown in Figure 13 As shown, the above operations are repeated until the width of the remaining portion of the germanium-containing semiconductor layer 12 is narrowed to the first preset width.

[0063] Specifically, the type and concentration of the above wet etching solution with oxidizing property can be set according to the actual application scenario. For example, the wet etching solution with oxidizing property can be a nitric acid solution or a hydrogen peroxide solution, etc. The mass fraction of the nitric acid can be 20% to 70%. The mass fraction of the hydrogen peroxide can be 20% to 40%. In addition, the size of the above second preset width is also different according to the structure of the germanium-containing semiconductor layer before the lateral thinning treatment and the number of times of performing the above two-step operation. Specifically, in the case of performing the second selective oxidation treatment for the first time, the above second preset width is equal to the width of the first fin or the maximum width of the protection structure. In the case of performing the number of times greater than or equal to 2, the above second preset width is equal to the width of the first fin minus the above fixed thickness multiplied by the above number of times. Or, the second preset width is equal to the maximum width of the protection structure minus the above fixed thickness multiplied by the above number of times. Furthermore, the size of the above fixed thickness is also different according to different specifications of the germanium-containing semiconductor layer and different conditions of the second selective oxidation treatment, etc. For example, as shown in Figure 12 As shown, the sidewall of the germanium-containing semiconductor layer 12 along the width direction can be inwardly recessed by 0.25 nm relative to the sidewall of the first fin 13 (in the case of forming the protection structure 18, relative to the sidewall of the protection structure 18) after each second selective oxidation treatment.

[0064] In the actual application process, as shown in Figure 11 As shown, since the above wet etching solution with oxidizing property only oxidizes the germanium-containing semiconductor layer 12, after performing the second selective oxidation treatment on the germanium-containing semiconductor layer 12 with a width equal to the second preset width by using the wet etching solution with oxidizing property along the width direction of the germanium-containing semiconductor layer 12 (the direction is parallel to the A-A' direction), the sidewall of the germanium-containing semiconductor layer 12 along the width direction is inwardly recessed by a fixed thickness relative to the sidewall of the first fin 13 (in the case of forming the protection structure 18, relative to the sidewall of the protection structure 18). As shown in Figure 12As shown, the oxide layer formed on the sidewall of the germanium-containing semiconductor layer 12 after the second selective oxidation treatment can be removed by etching agent such as hydrofluoric acid. It can be seen that the germanium-containing semiconductor layer 12 with a width equal to the second preset width can be laterally thinned by a certain thickness through the above two operations. As shown Figure 13 As shown, the number of repetitions of the above two operations can be determined according to the thickness of the germanium-containing semiconductor layer 12 with a width equal to the second preset width that is laterally thinned each time, and the difference between the second preset width and the first preset width.

[0065] It is worth noting that during the above-mentioned second selective oxidation treatment, the thickness of each oxidation will be saturated after a certain time. In other words, after the time of each second selective oxidation treatment is greater than or equal to the saturation time, the oxide layer formed can isolate the sidewall of the germanium-containing semiconductor layer with a width equal to the second preset width from the wet etching solution with oxidizing property, preventing the part from continuing to react, so as to accurately control the thickness of each lateral thinning without accurately controlling the etching time, ensuring that the width of the remaining part of the germanium-containing semiconductor layer after the lateral thinning treatment is equal to the first preset width, preventing the width of the germanium-containing semiconductor layer after the lateral thinning treatment from being too large to cause the time of the subsequent first selective oxidation treatment to be too long, thereby affecting the first fin, and preventing the width of the remaining part of the germanium-containing semiconductor layer after the lateral thinning treatment from being too small to provide sufficient support for the upper stack, thereby causing the first fin to bend or collapse, further improving the yield of the ring gate transistor.

[0066] It should be noted that along the width direction of the first fin, if the distance between any germanium-containing semiconductor layer and the structures located on both sides thereof is different, then after the lateral thinning treatment of the germanium-containing semiconductor layer, the thickness of the two sidewalls of the germanium-containing semiconductor layer along the width direction may be different, thereby causing the remaining part of the germanium-containing semiconductor layer after the lateral thinning treatment to deviate from the center of the bottom of the first fin. For example, if a plurality of groups of germanium-containing semiconductor layers and first fins are formed on the substrate, and along the width direction of the first fin, there is at least one germanium-containing semiconductor layer whose distance to the two adjacent germanium-containing semiconductor layers is different, the above phenomenon may occur.

[0067] As shown Figure 14 As shown, the first selective oxidation treatment is performed on at least the germanium-containing semiconductor layer after the lateral thinning treatment to form an isolation structure 19 between the substrate 11 and the first fin 13.

[0068] In practical applications, a first selective oxidation process can be performed on a germanium-containing semiconductor layer with a width equal to a first preset width, such as rapid annealing or low-temperature oxidation, to form an isolation structure from the remaining portion of the germanium-containing semiconductor layer after at least lateral thinning. Specifically, the oxidation conditions for the first selective oxidation process can be set according to the actual application scenario. For example, when using a rapid annealing process, the annealing temperature can be 600°C to 850°C, and the annealing time can be 10s to 60s. For example, when using a low-temperature oxidation process, the oxidation temperature can be 600°C to 850°C, and the oxidation atmosphere is an ozone gas. The ozone gas can be ozone, or a mixture of ozone and oxygen.

[0069] It should be noted that, as mentioned earlier, when the initially formed germanium-containing semiconductor layer covers the substrate surface, the germanium-containing semiconductor layer needs to be patterned under the masking effect of the protective structure. Therefore, if the protective structure is retained after the lateral thinning process, it can isolate the first fin from the external environment during the first selective oxidation process, preventing the first fin from being affected. This facilitates the subsequent formation of high-quality nanosheets based on a high-quality channel layer, thereby improving the conductivity of the gate-around transistor.

[0070] For example, as described above, when the above-mentioned protective structure is retained during the first selective oxidation process, the method for manufacturing the above-mentioned gate-ring transistor further includes the step of: […]. Figure 14 As shown, the protective structure needs to be removed. Specifically, this protective structure can be removed using processes such as dry etching or wet etching.

[0071] like Figure 15 As shown, a shallow trench isolation 20 is formed on the portion of the substrate 11 exposed outside the isolation structure 19. The top height of the shallow trench isolation 20 is less than or equal to the top height of the isolation structure 19.

[0072] In practical applications, processes such as chemical vapor deposition can be used to form an isolation material covering the substrate, followed by planarization. Then, the planarized isolation material is etched back until the top height of the remaining portion of the isolation material is less than or equal to the top height of the isolation structure, resulting in shallow trench isolation. The material for shallow trench isolation can be insulating materials such as SiN, Si3N4, SiO2, or SiCO.

[0073] In one example, such as Figure 15As shown, the first fin 13 can have a source formation region 14, a drain formation region 15, and a transition region 16 between the source formation region 14 and the drain formation region 15. In this case, after the shallow trench isolation 20 is formed on the substrate 11, the method for manufacturing the ring gate transistor further includes the steps of: Figures 16 to 21 As shown, the source formation region 14 and the drain formation region 15 are processed to form a source region 24 and a drain region 25 included in the ring gate transistor; and the portion of each layer of the at least one stack 131 in the transition region 16 is removed, so that the portion of the channel layer 1312 included in the at least one stack 131 in the transition region 16 forms a channel 27 included in the ring gate transistor.

[0074] Specifically, the formation of the source region, the drain region, and the channel is different according to the formation process adopted by the gate stack included in the manufactured ring gate transistor. The following takes the gate stack included in the ring gate transistor formed by the back gate process as an example to specifically describe the formation of the source region, the drain region, and the channel:

[0075] As shown, Figure 16 The sacrificial gate 21 and the second side wall 22 covering the outer periphery of the transition region 16 are formed.

[0076] Specifically, a chemical vapor deposition process or the like can be adopted to deposit a gate material for forming the sacrificial gate on the formed structure. Then, a dry etching process or the like can be adopted to etch the gate material, so as to retain the portion of the gate material covering the outer periphery of the transition region to obtain the sacrificial gate. The gate material can be amorphous silicon, polysilicon, or the like material that is easy to remove. As shown, Figure 16 After the formation of the sacrificial gate 21, the second side wall 22 can be formed at least on the sidewall of the sacrificial gate 21 in the above-mentioned manner. The material of the second side wall 22 can be silicon nitride or the like insulating material. The thickness of the second side wall 22 can be set according to actual requirements.

[0077] Then, a dry etching process or a wet etching process can be adopted to remove the portion of the fin in the source formation region and the drain formation region. As shown, Figure 17 An epitaxial growth process or the like can be adopted to epitaxially form the source region 24 at least in the source formation region, and to epitaxially form the drain region 25 at least in the drain formation region. Alternatively, ion implantation processing can be directly performed on the portion of the fin in the source formation region and the drain formation region, so that the source formation region corresponds to the formation of the source region, and so that the drain formation region corresponds to the formation of the drain region.

[0078] In some cases, as shown, Figure 18As shown, if the manufactured gate-ring transistor also includes a dielectric layer 26, then after forming the source region 24 and drain region 25, a dielectric layer 26 covering the substrate 11 needs to be formed using processes such as deposition and etching before subsequent operations. The top height of this dielectric layer 26 is equal to the top height of the sacrificial gate 21. It should be understood that, as Figures 19 to 20 As shown, the presence of dielectric layer 26 protects source region 24 and drain region 25 from etching and cleaning operations when the sacrificial gate 21 and the portion of the sacrificial layer located within the transition region 16 are subsequently etched. Specifically, the dielectric layer 26 can be made of insulating materials such as SiO2 or SiN.

[0079] like Figure 19 As shown, the sacrificial gate is removed to expose the channel layer and the portion of the sacrificial layer covered by the sacrificial gate. Exemplarily, the sacrificial gate can be removed using either dry etching or wet etching processes.

[0080] like Figure 20 As shown, wet etching or dry etching processes can be used to remove the portion of each sacrificial layer located in the transition region, so that the portion of each channel layer located in the transition layer forms the corresponding nanosheet 271 included in the channel 27.

[0081] like Figure 21 As shown, a gate stack 28 is formed around the outer periphery of the channel 27 to obtain a gate ring transistor.

[0082] For example, the gate stack 28 described above can be formed using processes such as atomic layer deposition. The gate stack 28 may include a gate dielectric layer 281 and a gate 282 formed on the gate dielectric layer 281. The gate dielectric layer 281 may only surround the outer periphery of each nanosheet 271. Alternatively, the gate dielectric layer 281 may also be additionally formed on portions of the shallow trench isolation 20 and the isolation structure 19 corresponding to the gate formation region. Specifically, the gate dielectric layer 281 may be made of an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The gate 282 may be made of a conductive material such as doped polycrystalline silicon, TiN, TaN, or TiSiN.

[0083] It should be noted that, besides the germanium-containing semiconductor layer and the isolation structure, the above-mentioned source region, drain region, channel, and gate stack structures can be formed in various ways. How these structures are formed is not the main feature of this invention; therefore, this specification only provides a brief description to enable those skilled in the art to easily implement the invention. Those skilled in the art can certainly conceive of other ways to fabricate the above structures.

[0084] From the above, the manufacturing method of the ring gate transistor provided by the embodiment of the present application forms a germanium-containing semiconductor layer on a substrate, and a first fin on the germanium-containing semiconductor layer. The first fin includes at least one layer stack, and each layer stack includes a sacrificial layer and a channel layer on the sacrificial layer. The channel layer is a film layer for manufacturing nanosheet included in the ring gate transistor. Meanwhile, the content of germanium in the germanium-containing semiconductor layer is greater than the content of germanium in the channel layer and the sacrificial layer. Based on this, it is convenient to select a processing technology and an etchant that only have a corresponding lateral thinning effect on the germanium-containing semiconductor layer according to the different content of germanium in the germanium-containing semiconductor layer and the channel layer and the sacrificial layer, so as to realize lateral thinning processing only on the germanium-containing semiconductor layer without affecting the sacrificial layer and the channel layer for manufacturing nanosheet, thereby improving the yield of the ring gate transistor.

[0085] In addition, the manufacturing method provided by the embodiment of the present application is to first perform lateral thinning processing on the germanium-containing semiconductor layer to narrow its width to a first preset width, and then perform first selective oxidation processing, so as to prevent the parasitic channel from leaking under the premise of ensuring that the substrate and the first fin are filled with non-conductive isolation structures and shallow trench isolation to prevent the parasitic channel from leaking, and improving the conductive performance of the ring gate transistor. In addition, it is also beneficial to solve the problem of affecting the channel layer for manufacturing nanosheet caused by the long processing time of the first selective oxidation processing and other factors, thereby further improving the yield of the ring gate transistor. Moreover, the germanium-containing semiconductor layer can only be subjected to lateral thinning processing and first selective oxidation processing, without the need to perform the above processing on the substrate and other structures to prevent the parasitic channel from leaking, thereby simplifying the manufacturing process of the ring gate transistor.

[0086] Furthermore, the channel layer in the first fin is a film layer for manufacturing nanosheet, and the channel layer is formed on the substrate before the germanium-containing semiconductor layer is subjected to lateral thinning processing, without the need to form the first fin including the sacrificial layer and the channel layer by replacing the fin and other processing methods in the process of forming the shallow trench isolation by using the STI first process, thereby simplifying the manufacturing process of the ring gate transistor and improving the manufacturing efficiency of the ring gate transistor.

[0087] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0088] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a gate-ring transistor, characterized in that, include: A germanium-containing semiconductor layer and a first fin located on the germanium-containing semiconductor layer are formed on the substrate; Along the thickness direction of the substrate, the first fin includes at least one stack; each of the stacks includes a sacrificial layer and a channel layer located on the sacrificial layer; The germanium content in the germanium-containing semiconductor layer is greater than the germanium content in the channel layer and the sacrificial layer, respectively; the germanium-containing semiconductor layer covers the surface of the substrate; The germanium-containing semiconductor layer is subjected to at least lateral thinning to narrow the width of the remaining portion of the germanium-containing semiconductor layer to a first preset width; The first preset width is greater than zero and less than the width of the first fin; The germanium-containing semiconductor layer, after at least the lateral thinning process, is subjected to a first selective oxidation process to form an isolation structure between the substrate and the first fin; Shallow trench isolation is formed on the portion of the substrate exposed outside the isolation structure; The top height of the shallow trench isolation is less than or equal to the top height of the isolation structure; The step of performing at least a lateral thinning process on the germanium-containing semiconductor layer to narrow the width of the remaining portion of the germanium-containing semiconductor layer to a first preset width includes: A protective structure is formed covering the outer periphery of the first fin. Under the masking effect of the protective structure, at least the germanium-containing semiconductor layer is patterned to obtain the second fin; The germanium-containing semiconductor layer after the patterning process is subjected to the lateral thinning process. After performing a first selective oxidation treatment on the germanium-containing semiconductor layer that has undergone at least the lateral thinning treatment, and before forming a shallow trench isolation on the portion of the substrate exposed outside the isolation structure, the method for manufacturing the gate ring transistor further includes: removing the protective structure.

2. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The lateral thinning process was performed using a quasi-atomic layer etching process.

3. The method for manufacturing a gate-ring transistor according to claim 2, characterized in that, The lateral thinning process performed using a quasi-atomic layer etching process includes: A second selective oxidation treatment is performed on a germanium-containing semiconductor layer with a width of a second preset width using an oxidizing wet etching solution; after the second selective oxidation treatment, the germanium-containing semiconductor layer is recessed inward by a fixed thickness along the width direction of the sidewall, and an oxide layer is formed on the sidewall along the width direction of the germanium-containing semiconductor layer after the second selective oxidation treatment; the second preset width is greater than the first preset width and less than the width of the substrate; Remove the oxide layer; Repeat the above operation until the width of the remaining portion of the germanium-containing semiconductor layer is narrowed to the first preset width.

4. The method for manufacturing a gate-ring transistor according to claim 3, characterized in that, The oxidizing wet etching solution is a nitric acid solution or a hydrogen peroxide solution; And / or, The oxide layer was removed using hydrofluoric acid.

5. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The first preset width is 5nm to 15nm; And / or, The germanium-containing semiconductor layer is made of Si. 1-y Ge y The channel layer is made of Si. 1-x Ge x The sacrificial layer is made of Si. 1-z Ge z ; Wherein, 0≤x≤1, 0<y≤1, 0≤z≤1, yx≥0.2, yz≥0.2, |xz|≥0.

2.

6. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The first selective oxidation treatment is performed on the germanium-containing semiconductor layer that has undergone at least the lateral thinning treatment using a rapid annealing process or a low-temperature oxidation process.

7. The method for manufacturing a gate-to-ring transistor according to claim 6, characterized in that, The rapid annealing process has an annealing temperature of 600°C to 850°C and an annealing time of 10s to 60s. or, The oxidation temperature of the low-temperature oxidation process is 600℃ to 850℃, and the oxidation atmosphere is ozone gas.

8. The method for manufacturing a gate-to-ring transistor according to any one of claims 1 to 7, characterized in that, The first fin has a source forming region, a drain forming region, and a transition region located between the source forming region and the drain forming region; After forming a shallow trench isolation on the portion of the substrate exposed outside the isolation structure, the method for manufacturing the gate-ring transistor further includes: The source formation region and drain formation region are processed to form the source region and drain region included in the gate ring transistor; And remove the portion of each of the sacrificial layers located within the transition region, such that the portion of the channel layer included in the at least one stack located within the transition region forms the channel included in the gate ring transistor.

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