Method for improving over-etching of contact holes in large-sized metal gates

Abstract

The present invention provides a method for improving over-etching of contact holes in large-sized metal gates. A substrate is provided, and a plurality of metal gate structures are formed on the substrate on low, medium, and high-voltage device regions. The size of the metal gate on the high-voltage device region is larger than that on the low and medium-voltage device regions. A first interlayer dielectric layer covering the metal gate structures is formed on the substrate; through photolithography and etching, the first interlayer dielectric layer on the metal gate structure in the high-voltage device region is opened, and then an etch stop layer covering the first interlayer dielectric layer and the metal gate structure is formed; the etch stop layer outside the high-voltage device region is removed through photolithography and etching; a second interlayer dielectric layer covering the etch stop layer and the first interlayer dielectric layer is formed, and then contact holes for communicating with the gate, source, and drain of the metal gate structure are formed through photolithography and etching. Even when the metal gate is thin, it will not be etched through by the contact hole etching in the present invention, improving the product reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving over-etching of contact holes in large-size metal gates. Background Art

[0002] In the 28nm HV HKMG (High-Voltage High-K Metal Gate) process platform, there are three working voltage regions in the chip: a low-voltage region (0.9V), a medium-voltage region (8V), and a high-voltage region (32V);

[0003] Among them, for the high-voltage region (32V devices), there are relatively large metal gates. After the chemical mechanical polishing process, compared with the low-voltage region and the medium-voltage region, the metal gates in the high-voltage region are worn more severely. Therefore, during subsequent contact hole etching, the contact hole etching in the low-voltage region and the medium-voltage region stops above the metal gates, but the metal gates in the high-voltage region are etched through by the contact hole etching due to their smaller worn thickness. The etched-through contact holes penetrate into the STI (Shallow Trench Isolation) by several hundred angstroms, which has serious side effects on the performance of the product, such as a decrease in the balance voltage and a decrease in reliability.

[0004] To solve the above problems, a method for improving over-etching of contact holes in large-size metal gates is needed. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving over-etching of contact holes in large-size metal gates, which is used to solve the problem that in the prior art, for the high-voltage region, there are relatively large metal gates. After the chemical mechanical polishing process, the metal gates are worn more severely. Therefore, during subsequent contact hole etching, the contact hole etching in the low-voltage region and the medium-voltage region stops above the metal gates, but the metal gates in the high-voltage region are etched through by the contact hole etching due to their smaller worn thickness.

[0006] To achieve the above purpose and other related purposes, the present invention provides a method for improving over-etching of contact holes in large-size metal gates, including:

[0007] Step 1: Provide a substrate, on which a plurality of metal gate structures are formed on the low-, medium-, and high-voltage device regions. The size of the metal gate on the high-voltage device region is larger than its size on the low- and medium-voltage device regions. A first interlayer dielectric layer covering the metal gate structures is formed on the substrate;

[0008] Step 2: Through photolithography and etching, open the first interlayer dielectric layer on the metal gate structure in the high-voltage device region, and then form an etch stop layer covering the first interlayer dielectric layer and the metal gate structure;

[0009] Step 3: Remove the etch stop layer outside the high-voltage device region through photolithography and etching;

[0010] Step 4: Form a second interlayer dielectric layer covering the etch stop layer and the first interlayer dielectric layer, and then form contact holes for communicating with the gate, source, and drain of the metal gate structure through photolithography and etching.

[0011] Preferably, the substrate in Step 1 is a silicon substrate.

[0012] Preferably, the material of the first interlayer dielectric layer in Step 1 is silicon dioxide.

[0013] Preferably, the etch stop layer in Step 2 is composed of a titanium nitride layer and a silicon nitride layer stacked in sequence from bottom to top.

[0014] Preferably, the metal gate structure in Step 1 includes: a stack, the stack is composed of an oxide layer, a high-k dielectric layer, and a first bottom isolation layer stacked from bottom to top, and sidewalls are formed on the sidewalls of the stack; a U-shaped second bottom isolation layer, a work function metal layer, and a top isolation layer are sequentially stacked on the upper surface of the first bottom isolation layer, and a metal gate layer is formed in the top isolation layer.

[0015] Preferably, the material of the metal gate layer in Step 1 is aluminum.

[0016] Preferably, the thickness of the first interlayer dielectric layer on the metal gate structure in Step 1 is 190 to 210 angstroms.

[0017] Preferably, the material of the second interlayer dielectric layer in Step 4 is silicon dioxide.

[0018] Preferably, silicon nitride layers are formed on the sidewalls of the metal gate structure and on the substrate between the metal gate structures in Step 1.

[0019] As described above, the method for improving over-etching of contact holes in large-size metal gates of the present invention has the following beneficial effects:

[0020] The present invention retains an etch stop layer on the large-size metal gate in the high-voltage region to ensure that even when the metal gate is thin, it will not be etched through by the contact hole etching, thereby improving product reliability. Description of the Drawings

[0021] Figure 1 It shows a schematic diagram of the substrate of the present invention;

[0022] Figure 2 It shows a schematic diagram of forming an etch stop layer of the present invention;

[0023] Figure 3 It shows a schematic diagram of etching to remove part of the etch stop layer of the present invention;

[0024] Figure 4 Schematic diagram showing the formation of contact holes according to the present invention;

[0025] Figure 5 Schematic diagram showing the process flow according to the present invention. Detailed implementation manners

[0026] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please refer to Figure 5 , the present invention provides a method for improving over-etching of contact holes in large-sized metal gates, including:

[0028] Step 1, please refer to Figure 1 , provide a substrate 01, on which a plurality of metal gate structures 02 are formed on low, medium, and high-voltage device regions. Active regions and drain regions are formed by ion implantation on the substrate 01 on both sides of the metal, corresponding to the source and drain electrodes in a transistor respectively. The size of the metal gate on the high-voltage device region is larger than that on the low and medium-voltage device regions. A first interlayer dielectric layer 03 covering the metal gate structure 02 is formed on the substrate 01;

[0029] In an embodiment of the present invention, the substrate 01 in Step 1 is a silicon substrate 01, and a plurality of metal gate structures 02 are formed on the silicon substrate 01 on low, medium, and high-voltage device regions.

[0030] In an embodiment of the present invention, the material of the first interlayer dielectric layer 03 in Step 1 is silicon dioxide, which can be formed by atomic vapor deposition.

[0031] In an embodiment of the present invention, the metal gate structure 02 in Step 1 includes: a stack, which is composed of an oxide layer, a high-K dielectric layer, and a first bottom isolation layer stacked from bottom to top. Sidewalls of the stack are formed with sidewalls; on the upper surface of the first bottom isolation layer, a U-shaped second bottom isolation layer, a work function metal layer, and a top isolation layer are sequentially stacked, and a metal gate layer is formed in the top isolation layer.

[0032] In an embodiment of the present invention, the material of the metal gate layer in Step 1 is aluminum.

[0033] In an embodiment of the present invention, a silicon nitride layer 05 is formed on the sidewalls of the metal gate structure 02 and on the substrate 01 between the metal gate structures 02.

[0034] In an embodiment of the present invention, in step one, the thickness of the first interlayer dielectric layer 03 on the metal gate structure 02 is 190 to 210 angstroms, and its preferred thickness is 200 angstroms. After the first interlayer dielectric layer 03 is deposited, the thickness of the first interlayer dielectric layer 03 can be controlled by polishing to the required thickness.

[0035] Step two, please refer to Figure 2 , through photolithography and etching, open the first interlayer dielectric layer 03 on the metal gate structure 02 in the high-voltage device region, and then form an etch stop layer 04 covering the first interlayer dielectric layer 03 and the metal gate structure 02;

[0036] Specifically, a photoresist layer is formed on the surface of the first interlayer dielectric layer 03. The position of the larger metal gate structure 02 in the high-voltage device region is defined by photolithography. Then, through steps such as exposure, development, standing film, and baking, the photoresist layer except on the larger metal gate structure 02 is opened. Then, the exposed first interlayer dielectric layer 03 is removed by etching, the photoresist layer is removed, and then an etch stop layer 04 covering the first interlayer dielectric layer 03 and the metal gate structure 02 is formed.

[0037] In an embodiment of the present invention, the etch stop layer 04 in step two is composed of a titanium nitride layer and a silicon nitride layer 05 stacked in sequence from bottom to top.

[0038] Step three, please refer to Figure 3 , through photolithography and etching, remove the etch stop layer 04 outside the high-voltage device region;

[0039] Specifically, a photoresist layer is formed on the surface of the etch stop layer 04. The position of the larger metal gate structure 02 in the high-voltage device region is defined by photolithography. Then, through steps such as exposure, development, standing film, and baking, the photoresist layer except on the larger metal gate structure 02 is opened. Then, the exposed etch stop layer 04 is removed by etching, and the photoresist layer is removed.

[0040] Step four, please refer to Figure 4 , form a second interlayer dielectric layer 06 covering the etch stop layer 04 and the first interlayer dielectric layer 03, and then form contact holes for communicating with the gate, source, and drain of the metal gate structure through photolithography and etching.

[0041] In an embodiment of the present invention, the material of the second interlayer dielectric layer 06 in step four is silicon dioxide, which can be formed by atomic vapor deposition.

[0042] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0043] In summary, the present invention retains an etch stop layer on the large-area metal gate in the high-voltage region to ensure that even when the metal gate is relatively thin, it will not be etched through by the contact hole etching, thereby improving the product reliability. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0044] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving over-etching of contact holes in large-sized metal gates, characterized in that, it at least includes: Step 1: Provide a substrate, on which multiple metal gate structures are formed on low, medium, and high-voltage device regions. The size of the metal gate on the high-voltage device region is larger than its size on the low and medium-voltage device regions. A first interlayer dielectric layer covering the metal gate structures is formed on the substrate; Step 2: Form a photoresist layer on the surface of the first interlayer dielectric layer. Define the position of the larger metal gate structure in the high-voltage device region through lithography, open the photoresist layer except on the larger metal gate structure, then remove the exposed first interlayer dielectric layer through etching, remove the photoresist layer, and then form an etch stop layer covering the first interlayer dielectric layer and the metal gate structures; Step 3: Remove the etch stop layer outside the high-voltage device region through lithography and etching; Step 4: Form a second interlayer dielectric layer covering the etch stop layer and the first interlayer dielectric layer, and then form contact holes for communicating with the gates, sources, and drains of the metal gate structures through lithography and etching.

2. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: The substrate in Step 1 is a silicon substrate.

3. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: The material of the first interlayer dielectric layer in Step 1 is silicon dioxide.

4. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: The etch stop layer in Step 2 is composed of a titanium nitride layer and a silicon nitride layer stacked from bottom to top in sequence.

5. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: The metal gate structure in Step 1 includes: a stack, which is composed of an oxide layer, a high-k dielectric layer, and a first bottom isolation layer stacked from bottom to top. Sidewalls are formed on the sidewalls of the stack; a U-shaped second bottom isolation layer, a work function metal layer, and a top isolation layer are sequentially stacked on the upper surface of the first bottom isolation layer, and a metal gate layer is formed inside the top isolation layer.

6. The method for improving over-etching of contact holes in large-sized metal gates according to claim 5, characterized in that: The material of the metal gate layer in Step 1 is aluminum.

7. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: The thickness of the first interlayer dielectric layer on the metal gate structure in Step 1 is 190 to 210 angstroms.

8. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: The material of the second interlayer dielectric layer in Step 4 is silicon dioxide.

9. The method for improving over-etching of contact holes in large-sized metal gates according to claim 1, characterized in that: Silicon nitride layers are formed on the sidewalls of the metal gate structure in Step 1 and on the substrate between the metal gate structures.

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