Method for forming a microelectronic device and related microelectronic device, memory device, and electronic system

Abstract

This application relates to methods of forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems. A microelectronic device includes a stacked structure that includes blocks separated from each other by dielectric trench structures. At least one of the blocks includes two peak regions, a stadium structure inserted between the two peak regions in a first horizontal direction, and two bridging regions adjacent opposite sides of the stadium structure in a second horizontal direction. A fill trench vertically overlies and is within a horizontal boundary of the stadium structure of at least one of the blocks. The fill trench includes dielectric liner material on the opposing stepped structures of the stadium structure and on inner sidewalls of the two bridging regions, and a dielectric structure on the dielectric liner material and having a material composition different from that of the dielectric liner material. The dielectric structure is substantially confined within the stepped horizontal regions of the stadium structure.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 249,552, "METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS," filed on March 4, 2021. Technical Field

[0003] In various embodiments, the present disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to methods of forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems. Background Art

[0004] Microelectronic device designers generally desire to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the separation distance between adjacent features. Additionally, microelectronic device designers generally desire to design architectures that are not only compact but also provide performance advantages and simplify the design.

[0005] One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits within a computer or other electronic device. There are many types of memory devices, including but not limited to non-volatile memory devices (e.g., NAND flash memory devices). One way to increase the memory density in a non-volatile memory device is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include memory cell strings that vertically extend through one or more stacked structures that include layers of conductive and insulating materials. Each memory cell string can include at least one select device coupled thereto. This configuration permits a greater number of switching devices (e.g., transistors) to be located within the cells of a die area (i.e., the length and width of the active surface consumed) by building the array upward (e.g., vertically) on the die as compared to a structure having a conventional planar (e.g., two-dimensional) transistor arrangement.

[0006] A vertical memory array architecture generally includes electrical connections between conductive materials of layers of a stacked structure of memory devices and control logic devices (e.g., string drivers) such that memory cells of the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such electrical connections includes forming a so-called "ladder" (or "rung") structure at an edge (e.g., a horizontal end) of a layer of the stacked structure of memory devices. The ladder structure includes respective "rungs" that define contact regions of the conductive material of the layer, on which conductive contact structures can be placed to provide an electrical path to the conductive material. A conductive wiring structure can also be employed to couple the conductive contact structures to the control logic devices. However, conventional ladder structure fabrication techniques can split the conductive material of a single layer in a way that results in a discontinuous conductive path through the layer, which may require multiple (e.g., more than one) switching devices (e.g., transistors) of at least one string driver to fully drive a voltage across the layer and / or drive a voltage in opposite directions across the layer. SUMMARY OF THE INVENTION

[0007] In some embodiments, a microelectronic device includes a stacked structure including blocks separated from each other by dielectric trench structures and each including a vertical alternating sequence of conductive and insulating structures arranged in a layered manner. At least one of the blocks includes: two peak regions; a stadium structure inserted between the two peak regions in a first horizontal direction and including opposing ladder structures, each ladder structure having rungs including the edges of the layers; and two bridging regions adjacent opposite sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with the upper surfaces of the two peak regions. A fill trench vertically overlies and is within the horizontal boundaries of the stadium structure of at least one of the blocks. The fill trench includes: a dielectric liner material on the opposing ladder structures of the stadium structure and on inner sidewalls of the two bridging regions; and a dielectric structure on the dielectric liner material and having a different material composition from the dielectric liner material. The dielectric structure is substantially confined within the horizontal regions of the rungs of the stadium structure.

[0008] In an additional embodiment, a method of forming a microelectronic device includes forming a preliminary stack structure that includes a vertical alternating sequence of sacrificial material and insulating material arranged in layers. The preliminary stack structure further includes multiple rows of stadium structures, each row of stadium structures including at least two of the stadium structures that are adjacent to each other in a first horizontal direction and each including opposing stepped structures having steps that include edges of the layers of the preliminary stack structure. Forming at least two fill trenches vertically above and within horizontal boundaries of the at least two stadium structures in each row of the multiple rows of stadium structures. Each of the at least two fill trenches includes: a dielectric liner material on a surface of the preliminary stack structure; and a dielectric structure on the dielectric liner material and substantially confined within a horizontal region of the steps of one of the opposing stepped structures of the at least two stadium structures. Dividing the preliminary stack structure into blocks separated from each other by slots. Each of the blocks includes: a row of the multiple rows of stadium structures; at least one peak region inserted between the at least two stadium structures of the row of the multiple rows of stadium structures in the first horizontal direction; and a bridging region integral and continuous with the at least one peak region and adjacent to the at least two stadium structures in a second horizontal direction orthogonal to the first horizontal direction. Replacing the sacrificial material of the preliminary stack structure with a conductive material by way of the slots.

[0009] In a further embodiment, a memory device includes a stack structure, fill trenches, and memory cell strings. The stack structure includes layers, each layer including a conductive material and an insulating material vertically adjacent to the conductive material. The stack structure is divided into blocks that extend parallel to each other in a first direction and are separated from each other by a dielectric trench structure in a second direction. Each of the blocks includes a stadium structure, a first raised region, and a second raised region. The stadium structure includes opposing stepped structures having steps, respectively, the steps including horizontal ends of at least some of the layers of the stack structure. The first raised region is adjacent to opposing ends of the stadium structure in the first direction. The second raised region is adjacent to opposing sides of the stadium structure in a second direction. The uppermost surface of the second raised region is substantially coplanar with the uppermost surface of the first raised region. The fill trenches are within the blocks of the stack structure. Each of the fill trenches is vertically located above and within a horizontal region of the stadium structure of one of the blocks of the stack structure. Each of the fill trenches includes: a dielectric liner material on surfaces of the stadium structure, the first raised region, and the second raised region; a dielectric structure on the dielectric liner material and substantially confined within horizontal boundaries of the steps of the stadium structure; and a dielectric fill material above the dielectric structure and the dielectric liner material. The memory cell strings extend vertically in the first direction through each of the blocks adjacent to a portion of the stadium structure.

[0010] In a further embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes at least one microelectronic device structure, and the microelectronic device structure includes a stacked structure, a filled trench, and a conductive contact structure. The stacked structure has a vertical alternating sequence of conductive materials and insulating materials arranged in layers. The stacked structure includes at least two blocks separated from each other by at least one dielectric structure. Each of the at least two blocks includes two raised regions, a stadium structure, and two additional raised regions. The stadium structure is inserted between the two raised regions in a first horizontal direction and includes stepped structures that are opposite to each other in the first horizontal direction. Each of the stepped structures has steps including edges of the layers of the stacked structure. The two additional raised regions are adjacent to opposite sides of the stadium structure in a second horizontal direction perpendicular to the first horizontal direction. The filled trench is above and within the horizontal boundaries of the at least two blocks of the stacked structure. Each of the filled trenches includes a dielectric liner material, a dielectric structure, and a dielectric filling material. The dielectric liner material is on the surfaces of the stadium structure, the two raised regions, and the two additional raised regions of one of the at least two blocks of the stacked structure. The dielectric structure is on a horizontally extending surface of the dielectric liner material and is omitted from a vertically extending surface of the dielectric liner material. The dielectric filling material is above the dielectric structure and the dielectric liner material. The conductive contact structure extends vertically through the filled trench completely. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a simplified partial perspective view of a microelectronic device structure in a processing stage of a method of forming a microelectronic device according to an embodiment of the present disclosure. Figure 1B is in Figure 1A a partial A ( Figure 1A identified by a dashed line in Figure 1C is a simplified longitudinal cross-sectional view of a microelectronic device structure in a processing stage. Figure 1A and 1B is a simplified partial longitudinal cross-sectional view of a portion of the microelectronic device structure around Figure 1B the dashed line B-B shown in

[0012] Figure 2A is in Figures 1A to 1C another processing stage of a method of forming a microelectronic device after a processing stage Figures 1A to 1C is a simplified longitudinal cross-sectional view of a portion A of the microelectronic device structure shown in Figure 2B is in Figure 2AThe microelectronic device structure in the processing stage surrounds Figure 2A A simplified partial longitudinal cross-sectional view of the portion of the microelectronic device structure shown by the dashed line B-B in FIG.

[0013] Figure 3A is in Figure 2A and 2B Another processing stage of the method for forming a microelectronic device after the processing stage Figures 1A to 1C A simplified longitudinal cross-sectional view of portion A of the microelectronic device structure shown in FIG. Figure 3B is in Figure 3A The microelectronic device structure in the processing stage surrounds Figure 3A A simplified partial longitudinal cross-sectional view of the portion of the microelectronic device structure shown by the dashed line B-B in FIG.

[0014] Figure 4A is in Figure 3A and 3B Another processing stage of the method for forming a microelectronic device after the processing stage Figures 1A to 1C A simplified partial perspective view of the microelectronic device structure shown in FIG. Figure 4B is Figure 4A A simplified longitudinal cross-sectional view of portion A of the microelectronic device structure shown in the processing stage in FIG. Figure 4C is in Figure 4A and 4B The microelectronic device structure in the processing stage surrounds Figure 4B A partial longitudinal cross-sectional view of the portion of the microelectronic device structure shown by the dashed line B-B in FIG.

[0015] Figure 5A is in Figures 4A to 4C Another processing stage of the method for forming a microelectronic device after the processing stage Figures 1A to 1C A simplified longitudinal cross-sectional view of portion A of the microelectronic device structure shown in FIG. Figure 5B is in Figure 5A The microelectronic device structure in the processing stage surrounds Figure 5A A simplified partial longitudinal cross-sectional view of the portion of the microelectronic device structure shown by the dashed line B-B in FIG.

[0016] Figure 6A is in Figure 5A and 5B Another processing stage of the method for forming a microelectronic device after the processing stage Figures 1A to 1C A simplified longitudinal cross-sectional view of portion A of the microelectronic device structure shown in FIG. Figure 6B is in Figure 6A The microelectronic device structure in the processing stage surrounds Figure 6A A simplified partial longitudinal cross-sectional view of the portion of the microelectronic device structure shown by the dashed line B-B in FIG.

[0017] Figure 7is a simplified partial cross-sectional perspective view of a microelectronic device in accordance with an embodiment of the present disclosure.

[0018] Figure 8 is a schematic block diagram showing an electronic system in accordance with an embodiment of the present disclosure. Detailed Description

[0019] The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a sufficient description of embodiments of the present disclosure. However, one of ordinary skill in the art will understand that embodiments of the present disclosure may be practiced without these specific details. In fact, embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. Additionally, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of the present disclosure are described in detail below. Additional actions for forming a complete microelectronic device from the described structures may be performed by conventional manufacturing techniques.

[0020] The figures presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. It is expected that the shapes depicted in the figures will vary due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments described herein should not be construed as limited to the specific shapes or regions as illustrated, but should include, for example, shape deviations resulting from manufacturing. For example, regions illustrated or described as box-shaped may have rough and / or non-linear features, and regions illustrated or described as circular may include some rough and / or linear features. Additionally, the sharp angles shown may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and do not limit the scope of the claims. The drawings are not necessarily to scale. Additionally, common elements between the figures may retain the same numerical designations.

[0021] As used herein, a "memory device" refers to and includes microelectronic devices that exhibit memory functionality but are not necessarily limited to memory functionality. In other words and by way of non-limiting example only, the term "memory device" includes not only conventional memories (e.g., conventional volatile memories such as conventional dynamic random access memories (DRAMs); conventional non-volatile memories such as conventional NAND memories), but also microelectronic devices that combine application specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoCs)), combinational logic, and memory, as well as graphics processing units (GPUs) incorporating memory.

[0022] As used herein, the term "configured to" refers to the size, shape, material composition, orientation, and arrangement of one or more of the structures and devices that facilitate the operation of one or more of at least one structure and at least one device in a predetermined manner.

[0023] As used herein, the terms "vertical", "longitudinal", "horizontal", and "lateral" are referenced to the principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction that is substantially parallel to the principal plane of the structure, while a "vertical" or "longitudinal" direction is a direction that is substantially perpendicular to the principal plane of the structure. The principal plane of a structure is defined by a surface of the structure that has a relatively large area compared to other surfaces of the structure. Referring to the various figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0024] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other refer to and include features of the disclosed identity (or identities) that are located closest (e.g., nearest) to each other. Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identity (or identities) of the "adjacent" features may be disposed between the "adjacent" features. In other words, "adjacent" features may be positioned directly adjacent to each other such that no other features intervene between the "adjacent" features; or "adjacent" features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one "adjacent" feature is located between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other refer to and include features of the disclosed identity (or identities) that are located vertically closest (e.g., vertically nearest) to each other. Additionally, features described as being "horizontally adjacent" to each other refer to and include features of the disclosed identity (or identities) that are located horizontally closest (e.g., horizontally nearest) to each other.

[0025] As used herein, spatial relative terms, such as “below”, “beneath”, “lower”, “bottom”, “above”, “upper”, “top”, “front”, “rear”, “left”, “right” and the like, are used for convenience to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, an element described as “below”, “beneath”, “under” or “on the bottom” of another element or feature will be oriented “above” or “on the top” of the other element or feature. Thus, the term “below” can cover both an upper and a lower orientation depending on the context in which the term is used, which will be apparent to those of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein are to be interpreted accordingly.

[0026] As used herein, the singular forms “a / an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0028] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, e.g., electrically connected by direct ohmic connection or by an indirect connection (e.g., by means of another structure).

[0029] As used herein, the term “substantially” with respect to a given parameter, property or condition means and includes the degree to which the given parameter, property or condition is met with a degree of deviation that would be understood by one of ordinary skill in the art (as within an acceptable tolerance). By way of example, depending on the particular parameter, property or condition that is substantially met, the parameter, property or condition may be met at least 90.0%, may be met at least 95.0%, may be met at least 99.0%, may be met at least 99.9%, or even met 100.0%.

[0030] As used herein, “about” or “substantially” with reference to a numerical value of a particular parameter includes the recited numerical value and the degree of deviation therefrom that would be understood by one of ordinary skill in the art within the acceptable tolerance of the particular parameter. For example, “about” or “substantially” with respect to a numerical value may include additional numerical values that are within the range of 90.0% to 110.0% of the recited numerical value, such as within the range of 95.0% to 105.0% of the recited numerical value, within the range of 97.5% to 102.5% of the recited numerical value, within the range of 99.0% to 101.0% of the recited numerical value, within the range of 99.5% to 100.5% of the recited numerical value, or within the range of 99.9% to 100.1% of the recited numerical value.

[0031] As used herein, "conductive material" refers to and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe- and Ni-based alloys, Co- and Ni-based alloys, Fe- and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steels, low-carbon steels, stainless steels); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). In addition, "conductive structure" refers to and includes a structure formed of and containing a conductive material.

[0032] As used herein, "insulating material" refers to and includes electrical insulating materials such as at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x )) and one or more of at least one dielectric nitride material (e.g., silicon nitride (SiN y )) and at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y )) and one or more of the chemical formulas containing one or more of "x", "y", and "z" (e.g., SiO x , AlO x , HfO x , NbO x , TiOx , SiN y , SiO x N y , SiO x C z N y ) represents a material having an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if present) per atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since chemical formulas represent relative atomic ratios and not a strict chemical structure, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values of “x”, “y”, and “z” (if present) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a compound having a composition of an element that cannot be represented by a ratio of well-defined natural numbers and that violates the law of definite proportions. Further, “insulating structure” means and includes a structure formed of and including an insulating material.

[0033] As used herein, the term “homogeneous” means that the relative amounts of the elements contained in a feature (e.g., a material, a structure) do not vary throughout the different portions of the feature (e.g., different horizontal portions, different vertical portions). Conversely, as used herein, the term “heterogeneous” means that the relative amounts of the elements contained in a feature (e.g., a material, a structure) vary throughout the different portions of the feature. If a feature is heterogeneous, the amount of one or more of the elements contained in the feature may vary stepwise (e.g., change abruptly), or may vary continuously throughout the different portions of the feature (e.g., change gradually, such as linearly, parabolically). A feature may be formed, for example, of a stack of at least two different materials and include a stack of at least two different materials.

[0034] Unless the context otherwise indicates, the materials described herein may be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the particular material to be formed, the technique used to deposit or grow the material may be selected by one of ordinary skill in the art. Further, unless the context otherwise indicates, the removal of the materials described herein may be accomplished by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, planarization by polishing (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0035] Figures 1A to 6BShows various views of a microelectronic device structure (described in further detail below) at different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) in accordance with embodiments of the present disclosure. In conjunction with the description provided below, it will be apparent to those of ordinary skill in the art that the methods described herein can be used to form a variety of devices. In other words, the methods of the present disclosure can be used whenever it is desired to form a microelectronic device.

[0036] Figure 1A Depicts a simplified partial perspective view of a microelectronic device structure 100. As Figure 1A shown, the microelectronic device structure 100 can be formed to include a preliminary stack structure 102 that includes a vertical alternating (e.g., in the Z direction) sequence of insulating material 104 and sacrificial material 106 arranged in layers 108. Each of the layers 108 of the preliminary stack structure 102 can include a sacrificial material 106 that is vertically adjacent (e.g., directly vertically adjacent) to the insulating material 104. Figure 1B Is of the microelectronic device structure 100 at Figure 1A the depicted processing stage, a simplified longitudinal cross-sectional view of part A ( Figure 1A identified by the dashed box in Figure 1C Is of the microelectronic device structure at Figure 1A and 1B the processing stage, a simplified partial longitudinal cross-sectional view of a portion of the microelectronic device structure around Figure 1B the dashed line B-B shown in

[0037] The insulating structure 104 of the layers 108 of the preliminary stack structure 102 can be formed of at least one dielectric material and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y)。In some embodiments, the insulating material 104 of each of the layers 108 of the preliminary stack structure 102 is formed of and comprises a dielectric oxide material, such as SiO x (e.g., SiO2). The insulating material 104 of each of the layers 108 may be substantially homogeneous, or the insulating material 104 of one or more (e.g., each) of the layers 108 may be inhomogeneous.

[0038] The sacrificial material 106 of each of the layers 108 of the preliminary stack structure 102 may be formed of and comprise at least one material (e.g., at least one insulating material) that is selectively removable relative to the insulating material 104. The sacrificial material 106 may be selectively etched relative to the insulating material 104 during common (e.g., collective, mutual) exposure to a first etchant; and the insulating material 104 may be selectively etched to the sacrificial material 106 during common exposure to a second, different etchant. As used herein, if the etch rate of one material is at least about five times (5x), e.g., about ten times (10x), about twenty times (20x), or about forty times (40x) greater than the etch rate of another material, then the material is "selectively etchable" relative to the other material. As a non-limiting example, depending on the material composition of the insulating material 104, the sacrificial material 106 may be formed of and comprise one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric carbon oxide material (e.g., SiO x C y ), at least one hydrogenated dielectric carbon oxide material (e.g., SiC x O y H z ), at least one dielectric carbon oxynitride material (e.g., SiO x C z N y), and at least one semiconductive material (e.g., polysilicon). In some embodiments, the sacrificial material 106 of each of the layers 108 of the preliminary stack structure 102 is formed of and includes a dielectric nitride material, such as SiN y (e.g., Si3N4). For example, the sacrificial material 106 may be selectively etchable relative to the insulating material 104 during co-exposure to a wet etchant including phosphoric acid (H3PO4).

[0039] The preliminary stack structure 102 may be formed to include any desired number of layers 108. As a non-limiting example, the preliminary stack structure 102 may be formed to include greater than or equal to sixteen (16) layers of the layers 108, such as greater than or equal to thirty-two (32) layers of the layers 108, greater than or equal to sixty-four (64) layers of the layers 108, greater than or equal to one hundred and twenty-eight (128) layers of the layers 108, or greater than or equal to two hundred and fifty-six (256) layers of the layers 108.

[0040] As Figure 1A shown, the preliminary stack structure 102 may include a stadium structure 110 formed therein. The stadium structure 110 may be distributed throughout the preliminary stack structure 102. As Figure 1A shown, the preliminary stack structure 102 may include multiple rows of stadium structures 110 extending parallel in the X direction, and multiple columns of stadium structures 110 extending in the Y direction orthogonal to the X direction. The multiple rows of stadium structures 110 may each include some stadium structures 110 that are at least partially (e.g., substantially) aligned with each other in the Y direction. The multiple columns of stadium structures 110 may each include other stadium structures 110 that are at least partially (e.g., substantially) aligned with each other in the X direction. Different rows of stadium structures 110 may be located in different horizontal regions of the preliminary stack structure 102 to form different blocks of the stack structure formed from the preliminary stack structure 102, as described in further detail below. In Figure 1A order to be clear and for ease of understanding the figures and the associated description, portions of the preliminary stack structure 102 are depicted as transparent to more clearly show some of the stadium structures 110 distributed within the preliminary stack structure 102.

[0041] Still referring to Figure 1A , at least some (e.g., each) of the stadium structures 110 within a single row of stadium structures 110 may be at different vertical heights from each other in the Z direction. For example, as Figure 1AAs shown, the single-row stadium structure 110 may include a first stadium structure 110A, a second stadium structure 110B at a relatively lower vertical position (e.g., in the Z direction) within the preliminary stacking structure 102 compared to the first stadium structure 110A, a third stadium structure 110C at a relatively lower vertical position within the preliminary stacking structure 102 compared to the second stadium structure 110B, and a fourth stadium structure 110D at a relatively lower vertical position within the block 130 compared to the third stadium structure 110C. Additionally, within the single-row stadium structure 110, horizontally adjacent (e.g., in the X direction) stadium structures 110 may be horizontally spaced apart from each other substantially uniformly (e.g., equally, evenly). In additional embodiments, one or more rows of stadium structures 110 may respectively include a different number of stadium structures 110 and / or a different distribution of stadium structures 110 than that depicted. For example, the single-row stadium structure 110 may include more than four (4) stadium structures 110 (e.g., greater than or equal to five (5) stadium structures 110, greater than or equal to ten (10) stadium structures 110, greater than or equal to twenty-five (25) stadium structures 110, greater than or equal to fifty (50) stadium structures 110), or less than four (4) stadium structures 110 (e.g., less than or equal to three (3) stadium structures 110, less than or equal to two (2) stadium structures 110, only one (1) stadium structure 110). As another example, within the single-row stadium structure 110, at least some horizontally adjacent stadium structures 110 may be horizontally spaced apart at least partially non-uniformly (e.g., non-equally, non-evenly) such that at least one stadium structure 110 of the row is separated from at least two other stadium structures 110 that are horizontally adjacent to the at least one stadium structure 110 of the row by different (e.g., unequal) distances. As an additional non-limiting example, within the single-row stadium structure 110, the vertical positions (e.g., in the Z direction) of the stadium structures 110 may vary in a different manner than that shown. Figure 1A depicted different numbers of stadium structures 110 and / or different distributions of stadium structures 110. For example, the single-row stadium structure 110 may include more than four (4) stadium structures 110 (e.g., greater than or equal to five (5) stadium structures 110, greater than or equal to ten (10) stadium structures 110, greater than or equal to twenty-five (25) stadium structures 110, greater than or equal to fifty (50) stadium structures 110), or less than four (4) stadium structures 110 (e.g., less than or equal to three (3) stadium structures 110, less than or equal to two (2) stadium structures 110, only one (1) stadium structure 110). As another example, within the single-row stadium structure 110, at least some horizontally adjacent stadium structures 110 may be horizontally spaced apart at least partially non-uniformly (e.g., non-equally, non-evenly) such that at least one stadium structure 110 of the row is separated from at least two other stadium structures 110 that are horizontally adjacent to the at least one stadium structure 110 of the row by different (e.g., unequal) distances. As an additional non-limiting example, within the single-row stadium structure 110, the vertical positions (e.g., in the Z direction) of the stadium structures 110 may vary in a different manner than that shown. Figure 1A depicted different. For example, the single-row stadium structure 110 may include more than four (4) stadium structures 110 (e.g., greater than or equal to five (5) stadium structures 110, greater than or equal to ten (10) stadium structures 110, greater than or equal to twenty-five (25) stadium structures 110, greater than or equal to fifty (50) stadium structures 110), or less than four (4) stadium structures 110 (e.g., less than or equal to three (3) stadium structures 110, less than or equal to two (2) stadium structures 110, only one (1) stadium structure 110). As another example, within the single-row stadium structure 110, at least some horizontally adjacent stadium structures 110 may be horizontally spaced apart at least partially non-uniformly (e.g., non-equally, non-evenly) such that at least one stadium structure 110 of the row is separated from at least two other stadium structures 110 that are horizontally adjacent to the at least one stadium structure 110 of the row by different (e.g., unequal) distances. As an additional non-limiting example, within the single-row stadium structure 110, the vertical positions (e.g., in the Z direction) of the stadium structures 110 may vary in a different manner than that shown (e.g., may alternate between relatively deeper and relatively shallower vertical positions).

[0042] Each stadium structure 110 may include opposing stepped structures 112 and a central region 114 horizontally inserted (e.g., in the X direction) between the opposing stepped structures 112. The opposing stepped structures 112 of each stadium structure 110 may include a forward stepped structure 112A and a reverse stepped structure 112B. A phantom line extending from the top to the bottom of the forward stepped structure 112A may have a positive slope, while another phantom line extending from the top to the bottom of the reverse stepped structure 112B may have a negative slope. In additional embodiments, one or more of the stadium structures 110 may respectively exhibit different fromFigure 1A Depicted are configurations that are different. As a non-limiting example, at least one stadium structure 110 can be modified to include the forward stepped structure 112A but not the reverse stepped structure 112B (e.g., the reverse stepped structure 112B may not exist), or, at least one stadium structure 110 can be modified to include the reverse stepped structure 112B but not the forward stepped structure 112A (e.g., the forward stepped structure 112A may not exist). In such embodiments, the central region 114 is horizontally adjacent to the bottom of the forward stepped structure 112A (e.g., if the reverse stepped structure 112B does not exist), or the central region 114 is horizontally adjacent to the bottom of the reverse stepped structure 112B (e.g., if the forward stepped structure 112A does not exist).

[0043] The opposing stepped structures 112 (e.g., the forward stepped structure 112A and the reverse stepped structure 112B) of a single stadium structure 110 each include steps 116 defined by the edges (e.g., horizontal ends) of the layers 108 of the preliminary stack structure 102. For the opposing stepped structures 112 of a single stadium structure 110, each step 116 of the forward stepped structure 112A can have a corresponding step 116 within the reverse stepped structure 112B having substantially the same geometric configuration (e.g., shape, dimensions), vertical position (e.g., in the Z direction), and horizontal distance (e.g., in the X direction) from the horizontal center of the central region 114 of the stadium structure 110 (e.g., in the X direction). In additional embodiments, at least one step 116 of the forward stepped structure 112A does not have a corresponding step 116 within the reverse stepped structure 112B having substantially the same geometric configuration (e.g., shape, dimensions), vertical position (e.g., in the Z direction), and / or horizontal distance (e.g., in the X direction) from the horizontal center of the central region 114 of the stadium structure 110 (e.g., in the X direction); and / or at least one step 116 of the reverse stepped structure 112B does not have a corresponding step 116 within the forward stepped structure 112A having substantially the same geometric configuration (e.g., shape, dimensions), vertical position (e.g., in the Z direction), and / or horizontal distance (e.g., in the X direction) from the horizontal center of the central region 114 of the stadium structure 110 (e.g., in the X direction).

[0044] Each of the stadium structures 110 of the initial stack structure 102 may respectively include a desired number of steps 116. Each of the stadium structures 110 may include substantially the same number of steps 116 as each other stadium structure in the stadium structure 110, or at least one of the stadium structures 110 may include a different number of steps 116 than at least one other stadium structure in the stadium structure 110. In some embodiments, at least one of the stadium structures 110 includes a different (e.g., greater, less) number of steps 116 than at least one other stadium structure in the stadium structure 110. As Figure 1A shown, in some embodiments, the steps 116 of each of the stadium structures 110 are arranged in an orderly manner such that steps 116 that are directly horizontally adjacent (e.g., in the X direction) to each other correspond to layers 108 of the initial stack structure 102 that are directly vertically adjacent (e.g., in the Z direction) to each other. In additional embodiments, the steps 116 of at least one of the stadium structures 110 are arranged disorderly such that at least some of the steps 116 of the stadium structure 110 that are directly horizontally adjacent (e.g., in the X direction) to each other do not correspond to layers 108 of the initial stack structure 102 that are directly vertically adjacent (e.g., in the Z direction) to each other.

[0045] Continuing to refer to Figure 1A , for a single stadium structure 110, its central region 114 may horizontally intervene (e.g., in the X direction) between the forward stepped structure 112A and the reverse stepped structure 112B and separate its forward stepped structure from the reverse stepped structure. The central region 114 may horizontally abut the vertically lowest step 116 of the forward stepped structure 112A and may also horizontally abut the vertically lowest step 116 of the reverse stepped structure 112B. The central region 114 of a single stadium structure 110 may have a desired horizontal dimension. Additionally, the central region 114 of each of the stadium structures 110 may have a substantially the same horizontal dimension as the central region 114 of each other stadium structure in the stadium structure 110, or the central region 114 of at least one of the stadium structures 110 may have a different horizontal dimension than the central region 114 of at least one other stadium structure in the stadium structure 110.

[0046] Still referring to Figure 1A, each stadium structure 110 (including the forward stepped structure 112A, the reverse stepped structure 112B, and its central region 114) within the preliminary stacked structure 102 can respectively partially define the boundaries (e.g., horizontal boundaries, vertical boundaries) of the trenches 118 that vertically extend (e.g., in the Z direction) through the preliminary stacked structure 102. The horizontally adjacent portions of the preliminary stacked structure 102 to a single stadium structure 110 can also partially define the boundaries of the trenches 118 associated with the stadium structure 110. The trenches 118 can vertically extend only through the layers 108 that define the forward stepped structure 112A and the reverse stepped structure 112B of the stadium structure 110 of the preliminary stacked structure 102; or they can also vertically extend through additional layers 108 of the preliminary stacked structure 102 that do not define the forward stepped structure 112A and the reverse stepped structure 112B of the stadium structure 110, such as additional layers 108 of the preliminary stacked structure 102 that are vertically overlying the stadium structure 110. For example, the edges of the additional layers 108 of the preliminary stacked structure 102 can define one or more additional stadium structures that are vertically overlying the stadium structure 110 and horizontally offset from the stadium structure. Subsequently, the trenches 118 can be filled with one or more dielectric materials, as described in further detail below.

[0047] As previously described, Figure 1B is part A ( Figure 1A identified by the dashed box in Figure 1A ) of the microelectronic device structure 100 at the depicted processing stage, a simplified longitudinal cross-sectional view. Part A encompasses the first stadium structure 110A of a single row of stadium structures 110 within the preliminary stacked structure 102 ( Figure 1A ). Part A also encompasses the regions of the preliminary stacked structure 102 that are horizontally adjacent to the first stadium structure 110A in the X direction and the Y direction. Although additional features (e.g., structures, materials) of the microelectronic device structure 100 are described below with reference to part A of the microelectronic device structure 100, such additional features can also be formed in and included in additional parts of the microelectronic device structure 100, including additional parts that encompass additional stadium structures 110 of the preliminary stacked structure 102 ( Figure 1A ), and additional regions of the preliminary stacked structure 102 whose boundaries are defined by the additional stadium structures 110.

[0048] In addition, as previously described, Figure 1C is a simplified partial longitudinal cross-sectional view of part of the microelectronic device structure 100 at the Figure 1A and 1B processing stages, around the dashed line B-B shown in Figure 1B . As Figure 1CAs shown, the insulating material 104 and the sacrificial material 106 of each layer 108 of the preliminary stack structure 102 have horizontal ends that define a single stadium structure 110 (e.g., the first stadium structure 110A) within the preliminary stack structure 102, and the insulating material and the sacrificial material can horizontally extend continuously in the X direction across the sides of the stadium structure 110 that are opposite to each other in the Y direction. Additionally, for a single stadium structure 110 within the preliminary stack structure 102, the inner horizontal boundary (e.g., the inner sidewall) of the preliminary stack structure 102 partially defines a trench 118 associated with the stadium structure 110 (e.g., vertically overlying within its horizontal boundary), and the inner horizontal boundary can be substantially perpendicular to the uppermost vertical boundary (e.g., the uppermost surface) of the preliminary stack structure 102, or can be substantially non-perpendicular to the uppermost vertical boundary (e.g., the uppermost surface) of the preliminary stack structure 102.

[0049] Next, refer to Figure 2A , which is a simplified longitudinal cross-sectional view of part A of the microelectronic device structure 100 after the Figures 1A to 1C processing stage. A dielectric liner material 120 can be formed on or above the portions of the preliminary stack structure 102 that define the stadium structure 110 and the trench 118. The dielectric liner material 120 can partially (e.g., less than completely) fill each of the trenches 118. For a single trench 118, the dielectric liner material 120 can be formed to extend substantially continuously on or above the surfaces (e.g., horizontally extending surfaces, vertically extending surfaces) of the stadium structure 110 and the boundaries (e.g., horizontal boundaries, vertical boundaries) of the preliminary stack structure 102 that define the trench 118. The dielectric liner material 120 can be formed to extend substantially continuously on or above the surfaces of the opposing stepped structures 112 (e.g., the forward stepped structure 112A and the reverse stepped structure 112B) in each of the stadium structures 110 and on or above the inner sidewalls of the preliminary stack structure 102 that are horizontally adjacent (e.g., in the Y direction) to each of the stadium structures 110. The dielectric liner material 120 can also be formed to extend beyond the boundaries (e.g., horizontal boundaries, vertical boundaries) of the trench 118. For example, the dielectric liner material 120 can also be formed to extend above the uppermost surface of the preliminary stack structure 102 that is outside the horizontal boundaries (e.g., in the X direction and the Y direction) of the trench 118. Figure 2B is a simplified partial longitudinal cross-sectional view of the microelectronic device structure 100 around the Figure 2A processing stage taken along the dashed line B-B shown in Figure 2A .

[0050] The dielectric liner material 120 can be used as (e.g., as) a barrier material to protect (e.g., shield) a subsequently formed structure (e.g., a subsequently formed dielectric structure) from being removed during subsequent processing operations (e.g., subsequent replacement gate processing operations, e.g., subsequent etching operations) described in further detail below. The dielectric liner material 120 can be formed to have a desired thickness capable of protecting the subsequently formed structure during subsequent processing operations. In some embodiments, the thickness of the dielectric liner material 120 ranges from about 5 nanometers (nm) to about 100 nm (e.g., from about 10 nm to about 50 nm, from about 10 nm to about 30 nm).

[0051] The dielectric liner material 120 can be formed of and include at least one dielectric material having an etch selectivity different from that of the sacrificial material 106 of the layer 108 of the initial stack structure 102. The dielectric liner material 120 can also have an etch selectivity different from that of at least one additional dielectric material subsequently formed within the remainder of the trench 118. For example, the etch selectivity of the dielectric liner material 120 can be substantially similar to that of the insulating material 104 of the layer 108 of the initial stack structure 102. As a non-limiting example, the dielectric liner material 120 can be formed of and include at least one oxygen-containing dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , and TiO x ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). In some embodiments, the dielectric liner material 120 is formed of SiO x (e.g., SiO2) and includes SiO x . The dielectric liner material 120 can be substantially homogeneous or heterogeneous.

[0052] Next, refer to Figure 3A , which is in the previous reference Figure 2A and 2BSimplified longitudinal cross-sectional view of part A of the microelectronic device structure 100 after the described processing stage. A dielectric structure 122 (e.g., a dielectric mesa structure) can be formed on or above a portion of the dielectric liner material 120 within the horizontal region of the step 116 of the stadium structure 110. Then, a dielectric fill material 124 can be formed on or above the dielectric structure 122 and the dielectric liner material 120. The dielectric structure 122 and the dielectric fill material 124 can together substantially fill a portion of the unfilled trench 118 remaining after the formation of the dielectric liner material 120 ( Figure 2A and 2B ). The dielectric liner material 120, the dielectric structure 122, and the dielectric fill material 124 can together form fill trenches 126 that extend vertically (e.g., in the Z direction) through the preliminary stack structure 102. Figure 3B is a simplified partial longitudinal cross-sectional view of the microelectronic device structure 100 at the Figure 3A processing stage around a portion of the dashed line B-B shown. Figure 3A

[0053] The dielectric structure 122 can be used as (e.g., serve as) an etch stop structure during subsequent processing operations (e.g., subsequent etch operations) to form openings (e.g., contact openings, contact vias) that extend vertically through the dielectric fill material 124, as described in further detail below. The dielectric structure 122 can be formed to discontinuously extend on or above a portion of the dielectric liner material 120 that is within the horizontal boundaries of the stadium structure 110. Each dielectric structure 122 can be located within the horizontal boundaries of each step 116 of each stadium structure 110 within the preliminary stack structure 102 (e.g., each step 116 of its respective stepped structure 112, e.g., each step 116 of the forward stepped structure 112A and / or each step 116 of the reverse stepped structure 112B). As Figure 3AAs shown, for each stadium structure 110, at least one dielectric structure 122 can also be located within the horizontal boundaries of the central region 114 of the stadium structure 110. Each dielectric structure 122 can be substantially confined within the horizontal region of the tier 116 or the associated central region 114. The horizontal region of each dielectric structure 122 within the horizontal boundaries of the respective tiers 116 of a single stadium structure 110 can be less than the horizontal region of the tier 116. Additionally, the horizontal region of each dielectric structure 122 within the horizontal boundaries of the single central region 114 of a single stadium structure 110 can be less than the horizontal region of the central region 114. Each dielectric structure 122 can be formed to have a desired thickness capable of protecting the underlying dielectric liner material 120 from openings that vertically extend through the dielectric fill material 124 during subsequent processing. In some embodiments, the thickness of each dielectric structure 122 is in the range of about 10 nm to about 100 nm (e.g., about 20 nm to about 80 nm).

[0054] As Figure 3A and 3B shown, the vertically extending (e.g., in the Z - direction) surface of the dielectric liner material 120 can be substantially free of dielectric structures 122 thereon. For example, in a portion of the vertically extending surface of the preliminary stack structure 102 that forms part of the boundary of the trench 118 (e.g., the vertically extending surface of the stadium structure 110 and the vertically extending surface of the portion of the preliminary stack structure 102 that is horizontally adjacent to the stadium structure 110 (and thus also horizontally adjacent to the trench 118) (e.g., the sidewalls)) or above it ( Figures 1A - 1C ), the dielectric structures 122 can be absent (e.g., omitted). Within the horizontal boundaries of a single stadium structure 110, each of the dielectric structures 122 can be horizontally offset in the X - direction from each other dielectric structure 122. Additionally, within the horizontal boundaries of a single stadium structure 110, the dielectric structures 122 can be at least partially (e.g., substantially) horizontally aligned in the Y - direction with each other dielectric structure 122.

[0055] The dielectric structures 122 can be formed of and include at least one dielectric material having an etch selectivity different from that of the dielectric liner material 120 and the dielectric fill material 124. For example, the etch selectivity of the dielectric structures 122 can be substantially similar to the etch selectivity of the sacrificial material 106 of the layer 108 of the preliminary stack structure 102. As a non - limiting example, the dielectric structures 122 can be formed of and include at least one nitrogen - containing dielectric material, such as at least one dielectric nitride material. In some embodiments, each of the dielectric structures 122 is formed of SiNy (e.g., Si3N4) is formed and contains SiN y . The dielectric structures 122 can be substantially homogeneous or heterogeneous, respectively.

[0056] The dielectric structure 122 can be formed by forming at least one dielectric material on or above the dielectric liner material 120 and then removing a portion of the dielectric material on or above the vertical extension (e.g., in the Z direction) surface of the dielectric liner material 120 within the trench 118 ( Figure 2A and 2B ). An additional portion of the dielectric material remaining after the material removal process on or above the horizontal extension surface of the dielectric liner material 120 within the trench 118 ( Figure 2A and 2B ) can form the dielectric structure 122. By doping a portion of the dielectric material on or above the vertical extension surface of the dielectric liner material 120 or an additional portion of the dielectric material on or above the horizontal extension surface of the dielectric liner material 120 with at least one chemical substance (e.g., at least one dopant), then modifying the etch selectivity of the portion relative to the additional portion, and then exposing the portion and the additional portion to at least one etchant, the portion can be selectively removed relative to the additional portion. In some embodiments, the additional horizontal extension portion of the dielectric material is doped with a relatively larger amount of at least one chemical substance than the vertical extension portion of the dielectric material, wherein the at least one chemical substance effectively reduces the etch rate of the additional horizontal extension portion of the dielectric material relative to the vertical extension portion during mutual exposure to a predetermined etchant (e.g., a predetermined wet etchant, e.g., a wet etchant containing hydrofluoric acid HF). As a non-limiting example, the additional horizontal extension portion of the dielectric material can be doped with a relatively larger amount of carbon (C) than the vertical extension portion of the dielectric material. In additional embodiments, the vertical extension portion of the dielectric material is doped with a relatively larger amount of at least one chemical substance than the additional horizontal extension portion of the dielectric material, wherein the at least one chemical substance effectively increases the etch rate of the vertical extension portion relative to the additional horizontal extension portion during mutual exposure to a predetermined etchant.

[0057] Still referring to Figure 3A and 3B , the dielectric fill material 124 can substantially fill the trench 118 not occupied by the dielectric liner material 120 and the dielectric structure 122 ( Figure 2A and 2B) portion. The dielectric fill material 124 can be formed to extend substantially continuously over or above the dielectric structure 122 and the dielectric liner material 120. The dielectric fill material 124 can be formed to exhibit a substantially flat upper vertical boundary and a substantially non-planar lower vertical boundary that is complementary to the underlying surface topography (e.g., substantially mirror-imaged).

[0058] As Figure 3A and 3B shown, within the horizontal boundaries of each of the stadium structures 110, the dielectric fill material 124 covers and surrounds the dielectric structure 122. For example, the dielectric fill material 124 can substantially cover and surround the horizontally extending upper surface and the vertically extending side surfaces of each of the dielectric structures 122. Additionally, within the horizontal boundaries of each of the stadium structures 110, the dielectric fill material 124 also covers portions of the dielectric liner material 120 that are not covered by the dielectric structures 122. For example, the dielectric fill material 124 can substantially cover the surfaces of the dielectric liner material 120 that are not covered by the dielectric structures 122 (e.g., horizontally extending surfaces, vertically extending surfaces). Portions of the dielectric fill material 124 can be horizontally inserted (e.g., in the X direction, in the Y direction) between the dielectric structure 122 and the dielectric liner material 120.

[0059] The dielectric fill material 124 can be formed of and include at least one dielectric material having an etch selectivity different from that of the dielectric structure 122. For example, the selective etching of the dielectric fill material 124 can be substantially similar to the etch selectivity of one or more of the dielectric liner material 120 and the insulating material 104 of the layer 108 of the preliminary stack structure 102. As a non-limiting example, the dielectric fill material 124 can be formed of and include at least one oxygen-containing dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , and TiO x ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). In some embodiments, the dielectric fill material 124 is formed of SiO x (e.g., SiO2) and includes SiO x .

[0060] As described below Figure 4C As will be described in further detail below, the microelectronic device structure 100 can be formed to further include support pillars that extend vertically through the initial stack structure 102. The support pillars can be configured and positioned to support the layer 108 of the initial stack structure 102 during subsequent processing (e.g., replacement gate processing) of the microelectronic device structure 100. For example, the support pillars can be configured and positioned to prevent (e.g., substantially prevent) portions of the insulating material 104 of the layer 108 from collapsing with the horizontal regions of the stadium structure 110 during subsequent replacement gate processing operations.

[0061] Next, referring to Figure 4A , which is a simplified partial perspective view of the microelectronic device structure 100 after the processing stages described in the previous references Figure 3A and 3B , the initial stack structure 102 ( Figure 3A and 3B ) can be partitioned (e.g., divided, segmented) and subjected to replacement gate processing to form a stack structure 128. The stack structure 128 can be divided into blocks 130 that are separated from each other by trench structures 132. The trench structures 132 can extend vertically (e.g., in the Z direction) completely through the stack structure 128. Additional features (e.g., materials, structures) of the stack structure 128 (including its blocks 130) are described in further detail below. In Figure 4A , for clarity and ease of understanding the figures and the associated description, the trench structures 132 are depicted as transparent to more clearly show the features of the blocks 130. Figure 4B is a simplified longitudinal cross-sectional view of portion A of the microelectronic device structure 100 at the processing stage depicted in Figure 4A . Figure 4C is a partial longitudinal cross-sectional view of the microelectronic device structure 100 around the portion along the dashed line B-B shown in Figure 4A and 4B at the processing stages. Figure 4B shown.

[0062] As Figure 4AAs shown, the blocks 130 of the stacked structure 128 can be formed to horizontally extend parallel to each other in the X direction. As used herein, the term "parallel" means substantially parallel. The horizontally adjacent blocks 130 of the stacked structure 128 can be separated from each other in the Y direction orthogonal to the X direction by the slot structure 132. The slot structure 132 can also horizontally extend parallel to each other in the X direction. Each of the blocks 130 of the stacked structure 128 can exhibit substantially the same geometric configuration (e.g., substantially the same size and substantially the same shape) as each of the other blocks 130, or one or more of the blocks 130 can exhibit a geometric configuration different from one or more of the other blocks 130 (e.g., one or more different sizes and / or different shapes). Additionally, each pair of horizontally adjacent blocks 130 of the stacked structure 128 can be horizontally separated from each other by substantially the same distance as each of the other pairs of horizontally adjacent blocks 130 of the stacked structure 128 (e.g., corresponding to the width of each of the slot structures 132 in the Y direction), or at least one pair of horizontally adjacent blocks 130 of the stacked structure 128 can be horizontally separated from each other by a different distance than at least one other pair of horizontally adjacent blocks 130 of the stacked structure 128. In some embodiments, the size, shape, and spacing relative to each other of the blocks 130 of the stacked structure 128 are substantially consistent (e.g., substantially immutable, substantially equal, substantially uniform).

[0063] Each of the blocks 130 of the stacked structure 128 can be formed to include a vertically alternating (e.g., in the Z direction) sequence of an insulating structure 134 and a conductive structure 136 arranged in layers 138. For each of the blocks 130 of the stacked structure 128, each of the layers 138 can respectively include one of the conductive structures 136 vertically adjacent to one of the insulating structures 134 (e.g., directly vertically adjacent). The insulating structure 134 of the blocks 130 of the stacked structure 128 can include a portion of the insulating material 104 ( Figure 3A and 3B ) of the initial stacked structure 102 ( Figure 3A and 3B ) remaining after the formation of the blocks 130. The conductive structure 136 of the blocks 130 of the stacked structure 128 can include a sacrificial material 106 ( Figure 3A and 3B ) of the initial stacked structure 102 ( Figure 3A and 3B ) formed (e.g., deposited) through a replacement gate process.) at least one conductive material, as described in further detail below. The conductive material may be formed from and include one or more of the following: at least one conductively doped semiconductor material, at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., at least one conductive metal nitride, at least one conductive metal silicide, at least one conductive metal carbide, at least one conductive metal oxide). In some embodiments, the conductive structure 136 is formed of W and contains W. Optionally, at least one liner material (e.g., at least one insulating liner material, at least one conductive liner material) may be formed around the conductive structure 136. For example, the liner material may be formed from and include one or more metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the liner material includes at least one conductive material that serves as a seed material for forming the conductive structure 136. In some embodiments, the liner material includes titanium nitride (TiN x , e.g., TiN). In further embodiments, the liner material further contains aluminum oxide (AlO x , e.g., Al2O3). As a non-limiting example, for each of the blocks 130 of the stack structure 128, AlO x (e.g., Al2O3) may be formed directly adjacent to the insulating structure 134, TiN x (e.g., TiN) may be formed directly adjacent to AlO x , and W may be formed directly adjacent to TiN x . For clarity and ease of description, the liner material is not shown in Figures 4A - 4C , but it should be understood that the liner material may be disposed around the conductive structure 136.

[0064] Within each block 130 of the stacked structure 128, one or more conductive structures 136 of one or more relatively vertically higher layers 138 (e.g., upper layers) may be employed to form an upper select gate structure (e.g., a drain side select gate (SGD) structure) of an upper select transistor (e.g., a drain side select transistor) of the block 130. The conductive structures 136 of the relatively vertically higher layer 138 may be segmented by one or more fill trenches (e.g., fill SGD trenches) to form the upper select gate structure of the block 130. In some embodiments, within each block 130 of the stacked structure 128, the conductive structures 136 of each of less than or equal to eight (8) relatively higher layers 138 (e.g., one (1) relatively vertically higher layer 138 to eight (8) relatively vertically higher layers 138) of the stacked structure 128 are employed to form the upper select gate structure (e.g., SGD structure) of the block 130. Additionally, within each block 130 of the stacked structure 128, the conductive structures 136 of at least some of the relatively vertically lower layers 138 that are vertically underlying the relatively vertically higher layer 138 may be employed to form an access line structure (e.g., a word line structure) of the block 130. Further, within each block 130 of the stacked structure 128, the conductive structures 136 of at least the vertically lowest layer 138 may be employed to form at least one lower select gate structure (e.g., at least one source side select gate (SGS) structure) of a lower select transistor (e.g., a source side select transistor) of the block 130.

[0065] To form the stacked structure 128, including its blocks 130, trenches (e.g., grooves, openings, apertures) having a geometric configuration (e.g., shape, dimensions) and position corresponding (e.g., substantially the same) to the geometric configuration (e.g., shape, dimensions) and position of the trench structure 132 may be formed in the preliminary stacked structure 102 ( Figure 3A and 3B ). Thereafter, the microelectronic device structure 100 may be processed using at least one wet etchant formulated to selectively remove portions of the sacrificial material 106 ( Figure 3A and 3B ) of the layer 108 ( Figure 3A and 3B ) of the preliminary stacked structure 102 ( Figure 3A and 3B ) through the trenches. The wet etchant may be selected to remove portions of the sacrificial material 106 ( Figure 3A and 3B ) while substantially not removing the insulating material 104 ( Figure 3A and 3B ) of the layer 108 ( Figure 3A and 3B ) of the preliminary stacked structure 102 ( Figure 3A and 3B) and substantially no portion of the dielectric liner material 120 is removed. During the material removal process, the dielectric liner material 120 may protect (eg, shield) the dielectric structure 122 from being removed. Figure 3A and 3B ) include dielectric nitride materials (e.g., SiN y , such as Si3N4) and the insulating material 104 and the dielectric liner material 120 include a dielectric oxide material (e.g., SiO x , such as SiO2), at least the preliminary stack structure 1202 ( Figure 3A and 3B ) of layer 108( Figure 3A and 3B ) of sacrificial material 106( Figure 3A and 3B ). In the selective removal of the sacrificial material 106 ( Figure 3A and 3B ), the resulting recess may be filled with a conductive material to form a conductive structure 136 of a block 130 of the stacked structure 128. In addition, after forming the block 130, at least one dielectric material (e.g., at least one dielectric oxide material, such as SiO x ; At least one dielectric nitride material, such as SiN y ) fills (eg, substantially fills) the grooves between the blocks 130 to form groove structures 132. In some embodiments, the groove structures 132 are formed of and include SiO2. The groove structures 132 may be formed to be substantially homogeneous, or may be formed to be non-homogeneous.

[0066] Reference again Figure 4A , each block 130 of the stacked structure 128 may be formed to include a row of stadium structures 110 (e.g., including the first stadium structure 110A, the second stadium structure 110B, the third stadium structure 110C, and the fourth stadium structure 110D of the row), a peak area 140 (e.g., an elevated area), and a bridge area 142 (e.g., an additional elevated area). The stadium structures 110 may be distributed over the entire horizontal area of ​​the block 130 and substantially confined within the horizontal area. The peak area 140 may be horizontally inserted between the stadium structures 110 that are horizontally adjacent to each other in the X direction. The bridge area 142 may be horizontally adjacent to opposite sides of each stadium structure 110 in the Y direction, and may extend horizontally from the peak areas 140 that are horizontally adjacent to each other in the X direction and extend horizontally between the peak areas. Figure 4AIn order to clearly and easily understand the drawings and the related descriptions, a portion of one of the blocks 130 of the stacked structure 128 (e.g., some in the bridging area 142 that is horizontally adjacent to the first side of the stadium structure 110 in the Y direction) is depicted as transparent to more clearly show the stadium structure 110 distributed within the block 130.

[0067] As Figure 4A shown, the peak region 140 of a single block 130 of the stacked structure 128 can be horizontally interposed between and separate the stadium structures 110 that are horizontally adjacent to each other in the X direction. For example, one of the peak regions 140 can be interposed between and separate the first stadium structure 110A and the second stadium structure 110B; an additional one of the peak regions 140 can be interposed between and separate the second stadium structure 110B and the third stadium structure 110C; and yet another one of the peak regions 140 can be interposed between and separate the third stadium structure 110C and the fourth stadium structure 110D. The vertical height of the peak region 140 in the Z direction can be substantially equal to the maximum vertical height of the block 130 in the Z direction; and the horizontal width of the peak region 140 in the Y direction can be substantially equal to the maximum horizontal width of the block 130 in the Y direction. Additionally, each of the peak regions 140 can respectively exhibit a desired horizontal length in the X direction. Each of the peak regions 140 of a single block 130 of the stacked structure 128 can exhibit a horizontal length that is substantially the same as each other peak region of the peak regions 140 of the block 130 in the X direction; or, at least one of the peak regions 140 of the block 130 can exhibit a horizontal length that is different from at least one other peak region of the peak regions 140 of the block 130 in the X direction.

[0068] Still referring to Figure 4A, the bridging region 142 of a single block 130 of the stacked structure 128 can be formed to be between and separate the stadium structure 110 of the block 130 and the trench structure 132 that is horizontally adjacent to the block 130 in the Y direction. For example, for each stadium structure 110 within a single block 130 of the stacked structure 128, a first bridging region 142A can be horizontally inserted in the Y direction between the first side of the stadium structure 110 and the first one of the trench structures 132 that is horizontally adjacent to the block 130; and a second bridging region 142B can be horizontally inserted in the Y direction between the second side of the stadium structure 110 and the second one of the trench structures 132 that is horizontally adjacent to the block 130. The first bridging region 142A and the second bridging region 142B can horizontally extend in parallel in the X direction. Additionally, the first bridging region 142A and the second bridging region 142B can each horizontally extend in the X direction from the peak region 140 of a block 130 that is horizontally adjacent to each other and horizontally extend between the peak regions. The bridging region 142 of the block 130 can be integral and continuous with the peak region 140 of the block 130. The upper boundary (e.g., upper surface) of the bridging region 142 can be substantially coplanar with the upper boundary of the peak region 140. The vertical height of the bridging region 142 in the Z direction can be substantially equal to the maximum vertical height of the block 130 in the Z direction. Additionally, each of the bridging regions 142 (including each first bridging region 142A and each second bridging region 142B) can respectively exhibit a desired horizontal width in the Y direction and a desired horizontal length in the X direction. Each of the bridging regions 142 of the block 130 can exhibit a horizontal length that is substantially the same as each other bridging region of the bridging regions 142 of the block 130 in the X direction; or, at least one of the bridging regions 142 of the block 130 can exhibit a horizontal length that is different from at least one other bridging region of the bridging regions 142 of the block 130 in the X direction. Additionally, each of the bridging regions 142 of the block 130 can exhibit a horizontal width that is substantially the same as each other bridging region of the bridging regions 142 of the block 130 in the Y direction; or, at least one of the bridging regions 142 of the block 130 can exhibit a horizontal width that is different from at least one other bridging region of the bridging regions 142 of the block 130 in the Y direction.

[0069] For each block 130 of the stacked structure 128, its bridging region 142 horizontally extends around the fill trench 126 of the block 130. Some of the bridging regions 142 of the block 130 can be employed to form a continuous conductive path that extends from and between the horizontally adjacent peak regions 140 of the block 130. As Figure 4CAs shown, the dielectric liner material 120 filling the trench 126 can be positioned (e.g., in the Y direction) directly horizontally adjacent to the inner surface (e.g., inner wall) of the bridging region 142, and the slot structure 132 can be positioned (e.g., in the Y direction) directly horizontally adjacent to the outer surface (e.g., outer wall) of the bridging region 142. The vertical extension of the dielectric liner material 120 that is directly horizontally adjacent to the inner surface of the bridging region 142 is substantially free of dielectric structures 122 thereon. In contrast, the dielectric fill material 124 filling the trench 126 can be positioned (e.g., in the Y direction) directly horizontally adjacent to the inner surface (e.g., inner wall) of the vertical extension of the dielectric liner material 120 and can substantially cover the inner surface. Additionally, for each trench 126, the dielectric liner material 120 is vertically inserted between the upper boundary of the step 116 of the stadium structure 110 associated with the trench 126 and the lower boundary of the dielectric structure 122 within the horizontal boundary of the step 116.

[0070] Reference Figure 4C, during and after the replacement gate process for forming the stacked structure 128, the configuration of the filled trenches 126 (including the configuration of its dielectric liner material 120, dielectric structure 122, and dielectric fill material 124) provides several advantages. For example, the configuration of the dielectric liner material 120 of each filled trench 126 protects the dielectric structure 122 of the filled trench 126 from being removed and replaced with a conductive material during the replacement gate process, thereby preventing the formation of unwanted void spaces that might otherwise occur due to replacing the dielectric structure 122 with a conductive material. For example, at the steps 116 of the stadium structure 110, such void spaces might otherwise form at the interface of the conductive materials of the dielectric structure 122 and the conductive structure 136 of the respective blocks 130 of the stacked structure 128. Retaining the dielectric structure 122 also aids in the subsequent use of the dielectric structure 122 as a so-called "etch stop" structure to mitigate (e.g., prevent) unwanted damage (e.g., over-etch damage, via damage) to the layers 138 of the respective blocks 130 of the stacked structure 128 during subsequent processing to form contact openings within the boundaries of the blocks 130, as described in further detail below. As another example, the configuration of the dielectric structure 122 of each filled trench 126 prevents unwanted damage, defects, and / or processing difficulties that might otherwise occur in the case where the dielectric structure 122 vertically extends across and substantially covers (e.g., substantially lines) the vertical extension of the dielectric liner material 120. For example, omitting the dielectric structure 122 from the vertical extension of the dielectric liner material 120 can prevent unwanted shorts between the conductive structures 136 of different layers 138 of a single block 130, which might otherwise result due to defects within the dielectric liner material 120. For example, such defects might otherwise provide access points for unwanted replacement of the vertical extensions of such dielectric structure configurations with a conductive material during the replacement gate process.

[0071] Still referring to Figure 4C , each block 130 of the stacked structure 128 can be separately formed to have a desired distribution of support structures 141 (e.g., support contacts, support pillars) extending vertically therethrough (depicted by the dashed lines in Figure 4C ). For example, the support structures 141 can be formed in the preliminary stacked structure 102 ( Figure 3A and 3B ) before the replacement gate process to form the conductive structure 136 of the blocks 130 of the stacked structure 128. The support structures 141 can be configured and positioned to assist in supporting the preliminary stacked structure 102 ( Figure 3A and 3B ) during the replacement of the sacrificial material 106 ( Figure 3A and 3B ) of the layer 108 ( Figure 3A and3B )'s layer 108( Figure 3A and 3B )'s insulating material 104( Figure 3A and 3B ). In some embodiments, each block 130 of the stacked structure 128 includes at least one array of support structures 141 that extend vertically therethrough, which includes multiple rows of support structures 141 extending in the X direction and multiple columns of support structures 141 extending into the Y direction. For each block 130, portions of at least one array of support structures 141 may be located within the horizontal region of the stadium structure 110 within the block 130.

[0072] The support structures 141 may each be formed to exhibit a desired horizontal cross-sectional shape. In some embodiments, each of the support structures 141 is formed to exhibit a substantially circular horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the support structures 141 exhibit a non-circular cross-sectional shape, such as one or more of a square cross-sectional shape, a rectangular cross-sectional shape, a rectangular cross-sectional shape, an oval cross-sectional shape, a teardrop cross-sectional shape, a semi-circular cross-sectional shape, a tombstone cross-sectional shape, a crescent cross-sectional shape, a triangular cross-sectional shape, a kite cross-sectional shape, and an irregular cross-sectional shape. Additionally, each of the support structures 141 may be formed to exhibit substantially the same horizontal cross-sectional size (e.g., substantially the same horizontal diameter), or at least one of the support structures 141 may be formed to exhibit one or more different horizontal cross-sectional sizes (e.g., different horizontal diameters) from at least one other support structure among the support structures 141. In some embodiments, all of the support structures 141 are formed to exhibit substantially the same horizontal cross-sectional size.

[0073] The support structures 141 may each be formed of and include at least one electrically conductive material, such as one or more of the following: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe- and Ni-based alloy, Co- and Ni-based alloy, Fe- and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low-carbon steel, stainless steel), at least one material containing an electrically conductive metal (e.g., electrically conductive metal nitride, electrically conductive metal silicide, electrically conductive metal carbide, electrically conductive metal oxide), and at least one doped electrically conductive semiconductor material (e.g., doped conductive Si, doped conductive Ge, doped conductive SiGe). Additionally, at least one insulating liner material may be formed to substantially surround (e.g., substantially horizontally and vertically cover) the side surfaces (e.g., sidewalls) of each of the support structures 141. The insulating liner material may be horizontally inserted between the support structures 141 and the layer 138 of the block 130 of the stack structure 128. The insulating liner material may be formed of and include one or more of the following: at least one dielectric oxide material (e.g., one or more of SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ) and amorphous carbon. In some embodiments, the insulating liner material includes SiO2.

[0074] Next, refer to Figure 5A , which is a previous reference Figures 4A to 4CSimplified longitudinal cross-sectional view of part A of the microelectronic device structure 100 after the described processing stage. For each block 130 of the stacked structure 128, portions of at least the dielectric fill material 124, the dielectric structure 122, and the dielectric liner material 120 are removed (e.g., etched) to form contact openings 144 (e.g., apertures, vias) that extend vertically (e.g., in the Z direction) therethrough. The contact openings 144 may also vertically extend through the insulating structures 134 of the layers 138 of the block 130, respectively. The contact openings 144 may vertically extend to or into one or more (e.g., each) of the steps 116 of the stadium structure 110, such as the steps 116 of the forward step structure 112A and / or the steps 116 of the reverse step structure 112B of one or more of the stadium structures 110. At a single step 116 of a single stadium structure 110 of a single block 130 of the stacked structure 128, the bottom (e.g., lower vertical end) of each contact opening 144 may be exposed and defined by the upper surface of the conductive structure 136 of a single layer 138 of the stacked structure 128. Figure 5B is a simplified partial longitudinal cross-sectional view of the portion of the microelectronic device structure 100 around Figure 5A the dashed line B-B shown. Figure 5A shown in the dashed line B-B.

[0075] Within each block 130 of the stacked structure 128, each contact opening 144 may be formed at a desired horizontal position (e.g., in the X and Y directions) on or above one of the steps 116 of one of the stadium structures 110. In some embodiments, within the horizontal regions of one or more of the stadium structures 110, at least some of the contact openings 144 are horizontally offset in the Y direction from at least some of the other contact openings 144. In Figure 5A this figure, such horizontal offsets are depicted by dashed lines at the boundaries (e.g., horizontal boundaries, vertical boundaries) of the contact openings 144. Additionally, the individual steps 116 of a single stadium structure 110 (e.g., the individual steps 116 of its forward step structure 112A, the individual steps 116 of its reverse step structure 112B) may have a single (e.g., only one) contact opening 144 extending vertically thereto, may have multiple (e.g., more than one) contact openings 144 extending vertically thereto, or may have no contact openings 144 extending vertically thereto.

[0076] The contact openings 144 can each be formed to exhibit a desired horizontal cross-sectional shape. In some embodiments, each of the contact openings 144 is formed to exhibit a substantially circular horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the contact openings 144 exhibit a non-circular cross-sectional shape, such as one or more of a rectangular cross-sectional shape, an oval cross-sectional shape, a square cross-sectional shape, a rectangular cross-sectional shape, a teardrop cross-sectional shape, a semi-circular cross-sectional shape, a tombstone cross-sectional shape, a crescent cross-sectional shape, a triangular cross-sectional shape, a kite cross-sectional shape, and an irregular cross-sectional shape. Additionally, each of the contact openings 144 can be formed to exhibit a substantially same horizontal cross-sectional dimension (e.g., substantially the same horizontal diameter), or at least one of the contact openings 144 can be formed to exhibit a horizontal cross-sectional dimension (e.g., a different horizontal diameter) different from one or more of at least one other contact opening of the contact openings 144. In some embodiments, all of the contact openings 144 are formed to exhibit a substantially same horizontal cross-sectional dimension.

[0077] Multiple material removal operations can be used to form the contact openings 144. For example, a first material removal operation (e.g., a first etching process) can be used to remove portions of the dielectric fill material 124 to form a preliminary contact opening that vertically extends to and exposes a portion of the dielectric structure 122; then, a second material removal operation (e.g., a second etching process) can be used to remove portions of at least the dielectric structure 122 and the dielectric liner material 120 within the horizontal boundaries of the preliminary contact opening to vertically extend the preliminary contact opening to the step 116 of the stadium structure 110 and form the contact openings 144. As Figure 5A shown, depending on the sequence of the conductive structure 136 and the insulating structure 134 of the block 130 of the stack structure 128, the second material removal operation extends the preliminary contact opening through the insulating structure 134 of the layer 139 of the block 130 that defines the step 116 of the stadium structure 110. As a non-limiting example, the first material removal operation can include a first etching process (e.g., anisotropic dry etching, such as one or more of RIE, deep RIE, plasma etching, reactive ion beam etching, and chemically assisted ion beam etching); and the second material removal act can include a second different etching process (e.g., a so-called "via" etching). In the first etching process, the dielectric structure 122 can be used as a so-called "etch stop" structure to protect the dielectric liner material 120 and the underlying portions of the stack structure 128 from being removed.

[0078] Next refer to Figure 6A which is in the previous reference Figure 5A and 5BSimplified longitudinal cross-sectional view of part A of the microelectronic device structure 100 after the described processing stage, where a contact structure 146 can be formed within contact openings 144( Figure 5A and 5B ). The contact structure 146 can be substantially confined within the boundaries (e.g., horizontal boundaries, vertical boundaries) of the contact openings 144( Figure 5A and 5B ), and can substantially fill the contact openings 144( Figure 5A and 5B ). Each contact structure 146 can have a geometric configuration (e.g., shape, size) corresponding to (e.g., substantially the same as) the geometric configuration of the contact openings 144( Figure 5A and 5B ) filled with the contact structure 146. As Figure 6A shown, each contact structure 146 can have an uppermost vertical boundary (e.g., uppermost surface) that is substantially coplanar with the uppermost vertical boundary (e.g., uppermost surface) of the dielectric fill material 124, and a lowermost vertical boundary (e.g., lowermost surface) that is vertically adjacent to the uppermost vertical boundary (e.g., uppermost surface) of the conductive structure 136 of a single layer 138 of a single block 130 of the stacked structure 128. In additional embodiments, one or more (e.g., each) of the contact structures 146 can have an uppermost vertical boundary that is offset from the uppermost vertical boundary (e.g., uppermost surface) of the dielectric fill material 124 (e.g., vertically above, vertically below). Each contact structure 146 can contact (e.g., physically contact, electrically contact) the conductive structure 136 of a single layer 138 of the stacked structure 128 at a single rung 116 of a single stadium structure 110 of a single block 130 of the stacked structure 128, respectively.

[0079] The contact structure 146 can be formed of and include a conductive material. As a non-limiting example, the contact structure 146 can be formed of and include one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The material composition of the contact structure 146 can be substantially the same as the material composition of the conductive structure 136 of the layer 138 of the block 130 of the stacked structure 128, or the material composition of the contact structure 146 can be different from the material composition of the conductive structure 136 of the layer 138 of the block 130 of the stacked structure 128. In some embodiments, the contact structures 146 are formed of and include W, respectively. The contact structures 146 can be homogeneous, respectively, or the contact structures 146 can be heterogeneous, respectively.

[0080] By forming in the contact openings 144( Figure 5A and 5B) form conductive material inside and outside (e.g., deposited non-uniformly, e.g., by one or more of a PVD process and a non-uniform CVD process), and then remove (e.g., by a planarization process such as chemical mechanical polishing (CMP)) a portion of the conductive material covering the uppermost vertical boundary (e.g., the uppermost surface) of the dielectric fill material 124 to form the contact structure 146.

[0081] Thus, according to an embodiment of the present disclosure, a microelectronic device includes a stacked structure including blocks separated from each other by dielectric trench structures and each including a vertical alternating sequence of conductive structures and insulating structures arranged in layers. At least one of the blocks includes: two peak regions; a stadium structure inserted between the two peak regions in a first horizontal direction and including opposing stepped structures, each stepped structure having a step including an edge of the layer; and two bridging regions adjacent to opposite sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having an upper surface substantially coplanar with the upper surfaces of the two peak regions. A fill trench is vertically over the horizontal boundary of the stadium structure of at least one of the blocks and within the horizontal boundary. The fill trench includes: a dielectric liner material on the opposing stepped structures of the stadium structure and on the inner sidewalls of the two bridging regions; and a dielectric structure on the dielectric liner material and having a material composition different from that of the dielectric liner material. The dielectric structure is substantially confined within the horizontal region of the steps of the stadium structure.

[0082] In addition, according to an embodiment of the present disclosure, a method of forming a microelectronic device includes forming a preliminary stacked structure including a vertical alternating sequence of sacrificial material and insulating material arranged in layers. The preliminary stacked structure further includes multiple rows of stadium structures, each row of stadium structures including at least two of the stadium structures that are adjacent to each other in a first horizontal direction and each including opposing stepped structures having steps including edges of the layers of the preliminary stacked structure. Forming at least two fill trenches vertically above and within the horizontal boundaries of the at least two stadium structures in each row of the multiple rows of stadium structures. Each of the at least two fill trenches includes: a dielectric liner material on the surface of the preliminary stacked structure; and a dielectric structure on the dielectric liner material and substantially confined within a horizontal region of the steps of the opposing stepped structures of one of the at least two stadium structures. Dividing the preliminary stacked structure into blocks separated from each other by slots. Each of the blocks includes: a row of the multiple rows of stadium structures; at least one peak region inserted between the at least two stadium structures of the row of the multiple rows of stadium structures in the first horizontal direction; and a bridging region integral and continuous with the at least one peak region and adjacent to the at least two stadium structures in a second horizontal direction orthogonal to the first horizontal direction. Replacing the sacrificial material of the preliminary stacked structure with a conductive material by means of the slots.

[0083] The microelectronic device structures of the present disclosure (e.g., the microelectronic device structure 100 previously referenced Figure 6A and 6B described) may be included in the microelectronic devices of the present disclosure. For example, Figure 7 FIG. shows a partial cross-sectional perspective view of a portion of a microelectronic device 201 (e.g., a memory device, such as a 3D NAND flash memory device) including a microelectronic device structure 200. The microelectronic device structure 200 may be substantially similar to the microelectronic device structure 100 previously referenced Figure 6A and 6B described. In Figure 7 and the related description, like reference numerals incremented by 100 are used to reference functionally similar features (e.g., structures, materials). To avoid repetition, not all features shown in Figure 7 are described in detail herein. Instead, unless otherwise specified below, features designated by reference numerals incremented by 100 from the reference numerals of the previously described features will be understood to be substantially similar to the previously described features. As a non-limiting example, unless otherwise specified below, the feature designated by reference numeral 226 in Figure 7 will be understood to be substantially similar to the feature previously referenced herein in Figure 6A and6B The described filled trench 126 (including its dielectric liner material 120, dielectric structure 122, and dielectric fill material 124). Additionally, for clarity and ease of understanding the drawings and the associated description, Figure 7 some features (e.g., structures, materials) of the microelectronic device structure 100 previously described herein are not shown. However, it should be understood that any features of the microelectronic device structure 100 described in one or more of the previous references Figure 6A and 6B may be included in the microelectronic device structure 200 of the microelectronic device 201 described herein with reference to Figure 7 as described.

[0084] As Figure 7 shown, in addition to the features of the microelectronic device structure 200 previously described herein with respect to the microelectronic device structure 100 ( Figure 6A and 6B ), the microelectronic device 201 may further include unit column structures 248 that vertically extend through each block 230 of the stacked structure 228. The unit column structures 248 may be located within a region (e.g., a memory array region) of the block 230 that is horizontally offset (e.g., in the X direction) from the stadium structure 210 (e.g., the first stadium structure 210A) within the block 230 (and thus the bridging region 242). The intersection of the unit column structures 248 and the conductive structures 236 of the layer 238 of the block 230 of the stacked structure 228 forms a string of memory cells 250 that vertically extends through each block 230 of the stacked structure 202. For each string of memory cells 250, its memory cells 250 may be coupled in series with each other. Within each block 230, the conductive structures 236 in some of its layers 238 may serve as access line structures (e.g., word line structures) for the strings of memory cells 250 within the horizontal region of the block 230. In some embodiments, within each block 230, the memory cells 250 formed at the intersection of the conductive structures 236 and the unit column structures 248 in some layers 238 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 250 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of the MONOS memory cells. In further embodiments, the memory cells 250 include so-called "floating gate" memory cells that include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally interposed between the central structure of the unit column structure 248 and the conductive structures 236 of different layers 238 of the stacked structure 228.

[0085] The microelectronic device 201 may further include at least one source structure 252, an access line wiring structure 254, a first select gate 256 (e.g., an upper select gate, a source / drain select gate (SGD)), a select line wiring structure 258, one or more second select gates 260 (e.g., a lower select gate, a source select gate (SGS)), and a digital line structure 262. The digital line structure 262 may be vertically overlying and coupled to the cell column structure 248 (and thus the memory cell 250 string). The source structure 252 may be vertically underlying and coupled to the cell column structure 248 (and thus the memory cell 250 string). Additionally, as shown, the contact structure 244 may couple various features of the microelectronic device 201 to each other (e.g., coupling the select line wiring structure 258 to the first select gate 256; coupling the access line wiring structure 254 to the conductive structure 236 of layer 238 of block 230 of the stack structure 228).

[0086] The microelectronic device 201 may further include an infrastructure 264 vertically located below the cell column structure 248 (and thus the memory cell 250 string). The infrastructure 264 may include at least one control logic region that includes control logic devices configured to control various operations of other features of the microelectronic device 201 (e.g., the memory cell 250 string). As a non-limiting example, the control logic region of the infrastructure 264 may further include one or more (e.g., each) of the following: charge pumps (e.g., V CCP charge pump, V NEGWL charge pump, DVC2 charge pump), a delay locked loop (DLL) circuit (e.g., a ring oscillator), V dd regulator, driver (e.g., a string driver), page buffer, decoder (e.g., a local bank decoder, column decoder, row decoder), sense amplifier (e.g., an equalization (EQ) amplifier, isolation (ISO) amplifier, NMOS sense amplifier (NSA), PMOS sense amplifier (PSA)), repair circuit (e.g., a column repair circuit, row repair circuit), I / O device (e.g., a local I / O device), memory test device, MUX, error checking and correction (ECC) device, self-refresh / wear leveling device, and other chip / bank control circuits. The control logic region of the infrastructure 264 may be coupled to the source structure 252, the access line wiring structure 254, the select line wiring structure 258, and the digital line structure 262. In some embodiments, the control logic region of the infrastructure 264 includes CMOS (complementary metal oxide semiconductor) circuitry. In such embodiments, the control logic region of the infrastructure 264 may be characterized as having an “array control CMOS” (“CuA”) configuration.

[0087] Thus, according to an embodiment of the present disclosure, a memory device includes a stacked structure, fill trenches, and memory cell strings. The stacked structure includes layers, each layer including a conductive material and an insulating material vertically adjacent to the conductive material. The stacked structure is divided into blocks that extend parallel to each other in a first direction and are separated from each other by a dielectric trench structure in a second direction. Each of the blocks includes a stadium structure, a first raised region, and a second raised region. The stadium structure includes opposing step structures, each of the step structures having steps that include horizontal ends of at least some of the layers of the stacked structure. The first raised region is adjacent to opposing ends of the stadium structure in the first direction. The second raised region is adjacent to opposing sides of the stadium structure in a second direction. A topmost surface of the second raised region is substantially coplanar with a topmost surface of the first raised region. The fill trenches are within the blocks of the stacked structure. Each of the fill trenches is vertically located above and within a horizontal region of the stadium structure of one of the blocks of the stacked structure. Each of the fill trenches includes: a dielectric liner material on surfaces of the stadium structure, the first raised region, and the second raised region; a dielectric structure on the dielectric liner material and substantially confined within horizontal boundaries of the steps of the stadium structure; and a dielectric fill material above the dielectric structure and the dielectric liner material. The memory cell strings extend vertically in the first direction through each of the blocks adjacent to a portion of the stadium structure.

[0088] A microelectronic device structure (e.g., the microelectronic device structure 100 previously referenced Figure 6A and 6B described) and a microelectronic device (e.g., the microelectronic device 201( Figure 7 )) according to an embodiment of the present disclosure can be used in embodiments of the electronic systems of the present disclosure. For example, Figure 8 is a block diagram of a schematic electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 can include, for example, a computer or computer hardware components, a server or other networked hardware components, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., or tablet computer), an e-book, a navigation device, etc. The electronic system 303 includes at least one memory device 305. The memory device 305 can include, for example, the microelectronic device structures (e.g., the microelectronic device structures previously referenced Figure 6A and 6B described) and microelectronic devices (e.g., the microelectronic device 201( Figure 7one or more of those in ( )). The electronic system 303 may further include at least one electronic signal processor device 307 (commonly referred to as a "microprocessor"). The electronic signal processor device 307 may optionally include the microelectronic device structures described previously herein (e.g., the microelectronic device structure 100 previously referenced Figure 6A and 6B ), and one or more of the microelectronic devices (e.g., the microelectronic device 201( Figure 7 ))). Although Figure 8 depicts the memory device 305 and the electronic signal processor device 307 as two (2) separate devices, in additional embodiments, a single (e.g., only one) memory / processor device having the functions of the memory device 305 and the electronic signal processor device 307 is included in the electronic system 303. In such embodiments, the memory / processor device may include the microelectronic device structures described previously herein (e.g., the microelectronic device structure 100 previously referenced Figure 6A and 6B ), and one or more of the microelectronic devices (e.g., the microelectronic device 201( Figure 7 ))). The electronic system 303 may further include one or more input devices 309 used by a user to input information into the electronic system 303, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, speakers, etc. In some embodiments, the input device 309 and the output device 311 include a single touchscreen device that can be used both to input information into the electronic system 303 and to output visual information to the user. The input device 309 and the output device 311 may be in electrical communication with one or more of the memory device 305 and the electronic signal processor device 307.

[0089] Accordingly, in accordance with an embodiment of the present disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes at least one microelectronic device structure that includes a stack structure, a filled trench, and a conductive contact structure. The stack structure has a vertical alternating sequence of conductive and insulating materials arranged in layers. The stack structure includes at least two blocks separated from each other by at least one dielectric structure. Each of the at least two blocks includes two raised regions, a stadium structure, and two additional raised regions. The stadium structure is inserted between the two raised regions in a first horizontal direction and includes stepped structures that face each other in the first horizontal direction. Each of the stepped structures has steps that include edges of the layers of the stack structure. The two additional raised regions are adjacent to opposite sides of the stadium structure in a second horizontal direction perpendicular to the first horizontal direction. The filled trench is above and within the horizontal boundaries of the at least two blocks of the stack structure. Each of the filled trenches includes a dielectric liner material, a dielectric structure, and a dielectric fill material. The dielectric liner material is on the surfaces of the stadium structure, the two raised regions, and the two additional raised regions of one of the at least two blocks of the stack structure. The dielectric structure is on the horizontally extending surface of the dielectric liner material and omitted from the vertically extending surface of the dielectric liner material. The dielectric fill material is above the dielectric structure and the dielectric liner material. The conductive contact structure extends vertically through the filled trench completely.

[0090] Compared to conventional structures, conventional devices, conventional systems, and conventional methods, the structures, devices, systems, and methods of the present disclosure advantageously facilitate improved performance of microelectronic devices, reduced cost (e.g., manufacturing cost, material cost), increased miniaturization of components, and increased packaging density. Compared to conventional structures, conventional devices, conventional systems, and conventional methods, the structures, devices, systems, and methods of the present disclosure can also improve scalability, efficiency, and simplicity.

[0091] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0092] Example 1: A microelectronic device includes: a stacked structure including blocks separated from each other by dielectric trench structures and each containing a vertical alternating sequence of conductive and insulating structures arranged in layers, at least one of the blocks including: two peak regions; a stadium structure inserted between the two peak regions in a first horizontal direction and including opposing stepped structures, each stepped structure having steps including edges of the layers; and two bridging regions adjacent to opposite sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with the upper surfaces of the two peak regions; and a fill trench vertically overlying and within the horizontal boundaries of the stadium structure of at least one of the blocks, the fill trench including: a dielectric liner material on the opposing stepped structures of the stadium structure and on inner sidewalls of the two bridging regions; and a dielectric structure on the dielectric liner material and having a material composition different from that of the dielectric liner material, the dielectric structure being substantially confined within the horizontal regions of the steps of the stadium structure.

[0093] Example 2: The microelectronic device according to Example 1, wherein the fill trench further includes a dielectric fill material on the surfaces of the dielectric structure and the dielectric liner material, and the dielectric fill material has at least a different material composition from that of the dielectric structure, the dielectric fill material being horizontally inserted in a second horizontal direction between portions of the dielectric liner material and the dielectric structure.

[0094] Example 3: The microelectronic device according to Example 2, wherein the dielectric fill material is horizontally inserted in a first horizontal direction between each pair of the dielectric structures horizontally adjacent to each other.

[0095] Example 4: The microelectronic device according to one of Examples 2 and 3, wherein the dielectric fill material directly physically contacts and substantially covers the vertically extending surfaces of the portions of the dielectric liner material on the inner sidewalls of the two bridging regions.

[0096] Example 5: The microelectronic device according to any one of Examples 2 to 4, further including conductive contact structures vertically extending through the dielectric fill material, the dielectric structure, and the dielectric liner material of the fill trench and extending into at least some of the steps of the stadium structure.

[0097] Example 6: The microelectronic device according to any one of Examples 1 to 5, wherein: the dielectric liner material includes a dielectric oxide material; and the dielectric structure includes a dielectric nitride material.

[0098] Example 7: The microelectronic device according to any one of Examples 1 to 6, wherein the vertical extension portions of the dielectric liner material on the inner sidewalls of the two bridging regions are substantially free of the dielectric structures thereon.

[0099] Example 8: The microelectronic device according to any one of Examples 1 to 7, wherein the two bridging regions of at least one of the blocks are horizontally inserted in the second horizontal direction between the dielectric liner material of the filling trench and two dielectric trench structures on opposite sides adjacent to at least one of the blocks.

[0100] Example 9: The microelectronic device according to Example 8, wherein a portion of the dielectric liner material is inserted horizontally in the first horizontal direction between pairs of the dielectric structures adjacent to each other horizontally.

[0101] Example 10: The microelectronic device according to any one of Examples 1 to 9, wherein the stadium structure further includes a central region horizontally inserted in the first horizontal direction between the vertically lowest steps of the opposing stepped structures, a portion of the dielectric liner material of the filling trench substantially covers and extends across the central region of the stadium structure, and one of the dielectric structures of the filling trench is on the portion of the dielectric liner material and is restricted within the horizontal region of the central region.

[0102] Example 11: The microelectronic device according to any one of Examples 1 to 10, further comprising a conductive support structure that vertically extends completely through the filling trench and the portion of at least one of the blocks within the horizontal boundary of the stadium structure.

[0103] Example 12: A method of forming a microelectronic device, comprising: forming a preliminary stack structure, the preliminary stack structure including a vertical alternating sequence of sacrificial material and insulating material arranged in layers, the preliminary stack structure further including multiple rows of stadium structures, each row of stadium structures including: at least two of the stadium structures, which are adjacent to each other in a first horizontal direction and each include opposing stepped structures, the opposing stepped structures having steps including edges of the layers of the preliminary stack structure; forming at least two fill trenches vertically above and within the horizontal boundaries of the at least two stadium structures in each row of the multiple rows of stadium structures, each of the at least two fill trenches including: a dielectric liner material on the surface of the preliminary stack structure; and a dielectric structure on the dielectric liner material and substantially confined within a horizontal region of the steps of the opposing stepped structures of one of the at least two stadium structures; dividing the preliminary stack structure into blocks separated from each other by slots, each of the blocks including: a row of the multiple rows of stadium structures; at least one peak region inserted between the at least two stadium structures of the row of the multiple rows of stadium structures in the first horizontal direction; and a bridging region integral and continuous with the at least one peak region and adjacent to the at least two stadium structures in a second horizontal direction orthogonal to the first horizontal direction; and replacing the sacrificial material of the preliminary stack structure with a conductive material by means of the slots.

[0104] Example 13: The method according to Example 12, wherein forming at least two fill trenches further includes forming each of the at least two fill trenches to further include a dielectric fill material on the surfaces of the dielectric structure and the dielectric liner material.

[0105] Example 14: The method according to Example 13, further including forming a portion of the dielectric fill material to horizontally intervene between and separate the vertically extending surfaces of the dielectric structure and the dielectric liner material.

[0106] Example 15: The method according to one of Examples 13 and 14, further including forming a conductive contact structure extending vertically through each of the at least two fill trenches, and the conductive contact structure extending to a portion of the conductive material at the steps of the opposing stepped structures of each of the at least two stadium structures.

[0107] Example 16: The method according to Example 15, wherein forming the conductive contact structure includes: removing a portion of the dielectric fill material overlying the dielectric structure to form a contact opening extending vertically into the dielectric structure; extending the contact opening through the dielectric structure and the dielectric liner material and into the portion of the conductive material; and forming a conductive material within the extended contact opening.

[0108] Example 17: The method according to any one of Examples 13 to 16, further comprising: forming the dielectric liner material to include silicon dioxide; forming the dielectric structure to include silicon nitride; and forming the dielectric fill material to include additional silicon dioxide.

[0109] Example 18: The method according to any one of Examples 12 to 17, further comprising forming the dielectric liner material of each of the at least two fill trenches to be horizontally interposed between pairs of the dielectric structures adjacent to each other in the first horizontal direction.

[0110] Example 19: The method according to any one of Examples 12 to 18, wherein forming at least two fill trenches includes: forming additional dielectric liner material on the dielectric liner material; and substantially removing a portion of the additional dielectric liner material on the vertically extending surface of the dielectric liner material to form the dielectric structure of each of the at least two fill trenches.

[0111] Example 20: The method according to any one of Examples 12 to 19, further comprising forming the upper surfaces of the at least one peak region and the bridging region of each of the blocks to be substantially coplanar with the upper surfaces of the at least two fill trenches vertically above the at least two stadium structures in each row of the multi-row stadium structure.

[0112] Embodiment 21: A memory device includes: a stack structure including layers, each layer including a conductive material and an insulating material vertically adjacent to the conductive material, the stack structure being divided into blocks extending parallel to each other in a first direction and separated from each other in a second direction by a dielectric trench structure, each of the blocks including: a stadium structure including opposing stepped structures, the stepped structures each having steps, the steps including horizontal ends of at least some of the layers of the stack structure; a first raised region adjacent to opposing ends of the stadium structure in the first direction; and a second raised region adjacent to opposing sides of the stadium structure in the second direction, an uppermost surface of the second raised region being substantially coplanar with an uppermost surface of the first raised region; filling trenches within the blocks of the stack structure, each of the filling trenches being vertically located above and within a horizontal region of the stadium structure of one of the blocks of the stack structure and including: a dielectric liner material on surfaces of the stadium structure, the first raised region, and the second raised region; a dielectric structure on the dielectric liner material and substantially confined within horizontal boundaries of the steps of the stadium structure; and a dielectric fill material above the dielectric structure and the dielectric liner material; and memory cell strings vertically extending through each of the blocks in the first direction adjacent to a portion of the stadium structure.

[0113] Embodiment 22: The memory device according to Embodiment 21, wherein: the dielectric liner material includes a silicon oxide material; the dielectric structure includes a silicon nitride material; and the dielectric fill material includes additional silicon oxide material.

[0114] Embodiment 23: The memory device according to one of Embodiments 21 and 22, further including conductive contact structures on at least some of the steps of the opposing stepped structures of the stadium structure within each of the blocks of the stack structure.

[0115] Embodiment 24: The memory device according to Embodiment 23, further including: a digital line overlying the stack structure and electrically coupled to the memory cell strings; a source structure underlying the stack structure and electrically coupled to the memory cell strings; a conductive wiring structure coupled to the conductive contact structures; and control logic circuitry underlying the stack structure and coupled to the source structure, the digital line, and the conductive wiring structure.

[0116] Embodiment 25: An electronic system, comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the microelectronic device structure including: a stacked structure having a vertical alternating sequence of conductive and insulating materials arranged in layers, the stacked structure including at least two blocks separated from each other by at least one dielectric structure, each of the at least two blocks including: two raised regions; a stadium structure inserted between the two raised regions in a first horizontal direction and including stepped structures opposite each other in the first horizontal direction, the stepped structures each having steps including edges of the layers of the stacked structure; and two additional raised regions adjacent opposite sides of the stadium structure in a second horizontal direction perpendicular to the first horizontal direction; filled trenches above and within the horizontal boundaries of the at least two blocks of the stacked structure, each of the filled trenches including: a dielectric liner material on the surfaces of the stadium structure, the two raised regions, and the two additional raised regions of one of the at least two blocks of the stacked structure; a dielectric structure on the horizontally extending surface of the dielectric liner material and omitted from the vertically extending surface of the dielectric liner material; and a dielectric fill material above the dielectric structure and the dielectric liner material; and conductive contact structures vertically extending completely through the filled trenches.

[0117] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the figures and have been described in detail herein. However, the present disclosure is not limited to the particular forms disclosed. Indeed, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment of the present disclosure may be combined with elements and features disclosed with respect to other embodiments of the present disclosure.

Claims

1. A microelectronic device, comprising: A stacked structure, comprising blocks separated from each other by dielectric trench structures and each containing a vertical alternating sequence of conductive and insulating structures arranged in layers, at least one of the blocks comprising: Two peak regions; A stadium structure inserted between the two peak regions in a first horizontal direction and comprising opposing stepped structures, each stepped structure having steps including edges of the layers; and Two bridging regions adjacent opposite sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with the upper surfaces of the two peak regions; and A filled trench vertically overlying and within the horizontal boundaries of the stadium structure of at least one of the blocks, the filled trench comprising: A dielectric liner material on the opposing stepped structures of the stadium structure and on the inner sidewalls of the two bridging regions; A dielectric structure on the dielectric liner material and having a material composition different from that of the dielectric liner material, the dielectric structure being substantially confined within the horizontal regions of the steps of the stadium structure; and A dielectric fill material on the surfaces of the dielectric structure and the dielectric liner material, and the dielectric fill material having at least a different material composition from that of the dielectric structure, the dielectric fill material being horizontally inserted in the second horizontal direction between portions of the dielectric liner material and the dielectric structure.

2. The microelectronic device according to claim 1, wherein the dielectric fill material is horizontally inserted in the first horizontal direction between each pair of the dielectric structures horizontally adjacent to each other.

3. The microelectronic device according to claim 1, wherein the dielectric fill material directly physically contacts and substantially covers the vertically extending surfaces of the portions of the dielectric liner material on the inner sidewalls of the two bridging regions.

4. The microelectronic device according to claim 1, further comprising conductive contact structures vertically extending through the dielectric fill material, the dielectric structure, and the dielectric liner material of the filled trench and extending into at least some of the steps of the stadium structure.

5. The microelectronic device according to any one of claims 1 to 4, wherein: The dielectric liner material comprises a dielectric oxide material; and The dielectric structure comprises a dielectric nitride material.

6. The microelectronic device according to any one of claims 1 to 4, wherein the vertically extending portions of the dielectric liner material on the inner sidewalls of the two bridging regions are substantially free of the dielectric structure thereon.

7. The microelectronic device according to any one of claims 1 to 4, wherein the two bridging regions of at least one of the blocks are horizontally inserted in the second horizontal direction between the dielectric liner material of the filled trench and two of the dielectric trench structures adjacent to opposite sides of at least one of the blocks.

8. The microelectronic device according to claim 7, wherein a portion of the dielectric liner material is inserted in the first horizontal direction between pairs of the dielectric structures that are horizontally adjacent to each other.

9. The microelectronic device according to any one of claims 1 to 4, wherein the stadium structure further includes a central region that is horizontally inserted in the first horizontal direction between the vertically lowest steps of the opposing stepped structures, a portion of the dielectric liner material filling the trench substantially covers and extends across the central region of the stadium structure, and one of the dielectric structures filling the trench is on the portion of the dielectric liner material and is restricted within a horizontal region of the central region.

10. The microelectronic device according to any one of claims 1 to 4, further comprising a conductive support structure that vertically extends completely through the filling trench and the portion of the at least one of the blocks within the horizontal boundary of the stadium structure.

11. A method of forming a microelectronic device, comprising: forming a preliminary stacked structure that includes a vertical alternating sequence of sacrificial material and insulating material arranged in layers, the preliminary stacked structure further including multiple rows of stadium structures, each row of stadium structures including: at least two of the stadium structures that are adjacent to each other in a first horizontal direction and each include opposing stepped structures having steps that include edges of the layers of the preliminary stacked structure; forming at least two filling trenches that are vertically above and within the horizontal boundaries of the at least two of the stadium structures in each row of the multiple rows of stadium structures, each of the at least two filling trenches including: dielectric liner material on a surface of the preliminary stacked structure; a dielectric structure on the dielectric liner material and substantially restricted within a horizontal region of a step of the opposing stepped structure of at least one of the at least two stadium structures; and dielectric filling material on surfaces of the dielectric structure and the dielectric liner material, and the dielectric filling material has at least a different material composition from the dielectric structure, and the dielectric filling material is horizontally inserted in a second horizontal direction between a portion of the dielectric liner material and the dielectric structure; dividing the preliminary stacked structure into blocks separated from each other by slots, each of the blocks including: one row of the multiple rows of stadium structures; at least one peak region that is inserted in the first horizontal direction between the at least two of the stadium structures in the one row of the multiple rows of stadium structures; and a bridging region that is integral and continuous with the at least one peak region and is adjacent to the at least two stadium structures in a second horizontal direction orthogonal to the first horizontal direction; and replacing the sacrificial material of the preliminary stacked structure with a conductive material by means of the slots.

12. The method according to claim 11, further comprising forming a portion of the dielectric fill material to horizontally intervene between and separate the dielectric structure and a vertically extending surface of the dielectric liner material.

13. The method according to claim 11, further comprising forming conductive contact structures vertically extending through each of the at least two fill trenches, and the conductive contact structures extending to portions of the conductive material at the steps of the opposing stepped structures of each of the at least two of the stadium structures.

14. The method according to claim 13, wherein forming the conductive contact structures comprises: removing portions of the dielectric fill material overlying the dielectric structure to form contact openings vertically extending into the dielectric structure; extending the contact openings through the dielectric structure and the dielectric liner material and into the portions of the conductive material; and forming conductive material within the extended contact openings.

15. The method according to claim 11, further comprising: forming the dielectric liner material to comprise silicon dioxide; forming the dielectric structure to comprise silicon nitride; and forming the dielectric fill material to comprise additional silicon dioxide.

16. The method according to any one of claims 11 to 15, further comprising forming the dielectric liner material of each of the at least two fill trenches to horizontally intervene between pairs of the dielectric structures adjacent to each other in the first horizontal direction.

17. The method according to any one of claims 11 to 15, wherein forming the at least two fill trenches comprises: forming additional dielectric liner material on the dielectric liner material; and substantially removing portions of the additional dielectric liner material on vertically extending surfaces of the dielectric liner material to form the dielectric structures of each of the at least two fill trenches.

18. The method according to any one of claims 11 to 15, further comprising forming upper surfaces of the at least one peak region and the bridging region of each of the blocks to be substantially coplanar with upper surfaces of the at least two fill trenches vertically located above the at least two of the stadium structures in each row of the multiple rows of stadium structures.

19. A memory device, comprising: a stacked structure including layers, each layer including conductive material and insulating material vertically adjacent to the conductive material, the stacked structure being divided into blocks extending parallel to each other in a first direction and separated from each other by dielectric trench structures in a second direction, each of the blocks including: a stadium structure including opposing stepped structures, the stepped structures respectively having steps, the steps including horizontal ends of at least some of the layers of the stacked structure; a first raised region adjacent to opposing ends of the stadium structure in the first direction; and a second raised region adjacent to opposing sides of the stadium structure in the second direction, an uppermost surface of the second raised region being substantially coplanar with an uppermost surface of the first raised region; The fill trenches within the block of the stack structure, each of the fill trenches vertically located above and within a horizontal region of the stadium structure of one of the blocks of the stack structure and including: A dielectric liner material on the surfaces of the stadium structure, the first raised region, and the second raised region; A dielectric structure on the dielectric liner material and substantially confined within the horizontal boundaries of the steps of the stadium structure; and A dielectric fill material above the dielectric structure and the dielectric liner material and having at least a different material composition from the dielectric structure, the dielectric fill material horizontally inserted in a second direction between a portion of the dielectric liner material and the dielectric structure; and Memory cell strings vertically extending in a first direction through each of the blocks adjacent a portion of the stadium structure.

20. The memory device according to claim 19, wherein: The dielectric liner material comprises a silicon oxide material; The dielectric structure comprises a silicon nitride material; and The dielectric fill material comprises an additional silicon oxide material.

21. The memory device according to any one of claims 19 and 20, further comprising conductive contact structures on at least some of the steps of the opposing stepped structures of the stadium structure within each of the blocks of the stack structure.

22. The memory device according to claim 21, further comprising: A digital line overlying the stack structure and electrically coupled to the memory cell strings; A source structure underlying the stack structure and electrically coupled to the memory cell strings; A conductive wiring structure coupled to the conductive contact structures; And Control logic circuitry underlying the stack structure and coupled to the source structure, the digital line, and the conductive wiring structure.

23. An electronic system, comprising: An input device; An output device; A processor device operatively coupled to the input device and the output device; And A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the microelectronic device structure including: A stack structure having a vertical alternating sequence of conductive and insulating materials arranged in a layered manner, the stack structure including at least two blocks separated from each other by at least one dielectric structure, each of the at least two blocks including: Two raised regions; A stadium structure inserted between the two raised regions in a first horizontal direction and including stepped structures opposite each other in the first horizontal direction, each of the stepped structures having steps including edges of the layers of the stack structure; and Two additional raised regions adjacent opposite sides of the stadium structure in a second horizontal direction perpendicular to the first horizontal direction; Fill trenches above and within the horizontal boundaries of the at least two blocks of the stack structure, each of the fill trenches including: A dielectric liner material on a surface of the stadium structure, the two raised regions, and the two additional raised regions of one of the at least two blocks of the stacked structure; A dielectric structure on a horizontally extending surface of the dielectric liner material and omitted from a vertically extending surface of the dielectric liner material; and A dielectric fill material above the dielectric structure and the dielectric liner material and having at least a different material composition from the dielectric structure, the dielectric fill material being horizontally inserted in a portion of the dielectric liner material and the dielectric structure in the second horizontal direction; and A conductive contact structure vertically extending completely through the filled trench.

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