An arrayed chip structure and a preparation method thereof

Abstract

The present invention provides an arrayed chip structure and a preparation method thereof. The arrayed chip structure includes: a first chip, channels, bonding pads, ground vias, a second chip, and micro-bumps; at least two channels are sequentially arranged between one end and the opposite end of the upper surface of the first chip; a bonding pad is arranged at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the channel; a plurality of ground vias penetrating the upper and lower surfaces of the first chip are arranged between adjacent two channels and outside the head and tail channels; the upper surface of the first chip and the upper surface of the second chip are connected by a plurality of micro-bumps, and the plurality of micro-bumps are respectively arranged between adjacent two channels and outside the head and tail channels, and / or at corresponding positions between adjacent two channels and outside the head and tail channels on the upper surface of the second chip. The present invention can effectively improve the isolation degree between channels in the arrayed chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and particularly to an arrayed chip structure and a preparation method thereof. Background Art

[0002] Arrayed chips are widely used in multi-channel integrated environments to achieve the goals of small size, high performance, and multi-channel parallelism, and are an indispensable part of systems such as radar, electronic warfare, test and measurement, communication, and sensing. As the main indicator of electromagnetic interference between channels of an arrayed chip, isolation determines the purity and mutual interference characteristics of signals between channels, and has an important impact on the realization of system performance indicators. Therefore, improving the isolation between channels has become an important part of improving the performance of arrayed chips.

[0003] The existing methods for achieving isolation between channels in the spatial dimension mainly involve adding metal isolation cavities or shielding covers in the spatial dimension. However, due to the limitations of the size and structural strength of the arrayed chip, it is impossible to add metal isolation cavities, and it is also very difficult to ensure the positioning accuracy and manufacturing tolerance of the shielding cover. Therefore, in the prior art, it is impossible to effectively improve the isolation between channels in the arrayed chip. Summary of the Invention

[0004] Embodiments of the present invention provide an arrayed chip structure and a preparation method thereof to solve the problem in the prior art that it is impossible to effectively improve the isolation between channels in the arrayed chip.

[0005] In a first aspect, embodiments of the present invention provide an arrayed chip structure, including: a first chip, channels, bonding pads, ground vias, a second chip, and micro-bumps;

[0006] At least two channels are sequentially arranged between one end and the opposite end of the upper surface of the first chip;

[0007] A bonding pad is arranged at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the channel;

[0008] A plurality of ground vias penetrating the upper and lower surfaces of the first chip are provided between adjacent two channels and outside the head and tail channels;

[0009] The upper surface of the first chip and the upper surface of the second chip are connected by a plurality of micro-bumps, and the plurality of micro-bumps are respectively arranged between adjacent two channels and outside the head and tail channels, and / or at corresponding positions between adjacent two channels and outside the head and tail channels on the upper surface of the second chip.

[0010] In a possible implementation manner, the radius of the micro-bump is any value from 40 microns to 50 microns; the interval between adjacent micro-bumps is less than one-quarter of the signal wavelength.

[0011] In a possible implementation, the plurality of micro bumps are respectively and uniformly arranged between two adjacent channels and on the outer sides of the head and tail channels;

[0012] The plurality of micro bumps between every two adjacent channels are all arranged in at least one straight line, and the plurality of micro bumps on the outer side of the head channel are all arranged in at least one straight line, and the plurality of micro bumps on the outer side of the tail channel are all arranged in at least one straight line.

[0013] In a possible implementation, the micro bumps on two adjacent straight lines between every two adjacent channels are arranged in a staggered manner, and the micro bumps on two adjacent straight lines on the outer side of the head channel are arranged in a staggered manner, and the micro bumps on two adjacent straight lines on the outer side of the tail channel are arranged in a staggered manner.

[0014] In a possible implementation, the plurality of ground vias are a plurality of metallized ground vias;

[0015] The interval between adjacent ground vias is less than one quarter of the signal wavelength.

[0016] In a possible implementation, the plurality of ground vias are respectively and uniformly arranged between two adjacent channels and on the outer sides of the head and tail channels;

[0017] The plurality of ground vias between every two adjacent channels are all arranged in at least one straight line, and the plurality of ground vias on the outer side of the head channel are all arranged in at least one straight line, and the plurality of ground vias on the outer side of the tail channel are all arranged in at least one straight line;

[0018] The ground vias on two adjacent straight lines between every two adjacent channels are arranged in a staggered manner, and the ground vias on two adjacent straight lines on the outer side of the head channel are arranged in a staggered manner, and the ground vias on two adjacent straight lines on the outer side of the tail channel are arranged in a staggered manner.

[0019] In a possible implementation, the second chip is disposed within the range of the first chip, and the bonding pads are exposed outside the edge of the second chip.

[0020] In a possible implementation, the at least two channels are at least two first coplanar waveguide structures;

[0021] The bonding pads are respectively connected to the input end and the output end of the signal transmission line in the first coplanar waveguide structure.

[0022] In a possible implementation, it further includes:

[0023] A metal conductor layer disposed on the upper surface of the second chip;

[0024] The upper surface of the first chip and the metal conductor layer on the upper surface of the second chip are connected by a plurality of micro-bumps, and the plurality of micro-bumps are respectively arranged between two adjacent channels and outside the head and tail channels, and / or at corresponding positions between two adjacent channels and outside the head and tail channels of the metal conductor layer on the upper surface of the second chip.

[0025] In a second aspect, an embodiment of the present invention provides a method for manufacturing an arrayed chip structure, including:

[0026] At least two channels are sequentially fabricated from one end to the opposite end on the upper surface of the first chip;

[0027] A bonding pad is fabricated at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the corresponding channel;

[0028] A plurality of ground vias penetrating the upper and lower surfaces of the first chip are fabricated between two adjacent channels and outside the head and tail channels;

[0029] A plurality of micro-bumps are respectively fabricated between two adjacent channels and outside the head and tail channels, and / or at corresponding positions between two adjacent channels and outside the head and tail channels on the upper surface of the second chip;

[0030] The upper surface of the second chip is flip-chip arranged on the upper surface of the first chip, and the upper surface of the first chip and the upper surface of the second chip are connected by the plurality of micro-bumps to obtain an arrayed chip structure.

[0031] An embodiment of the present invention provides an arrayed chip structure and a method for manufacturing the same. The arrayed chip structure includes: a first chip, channels, bonding pads, ground vias, a second chip, and micro-bumps; at least two channels are sequentially arranged between one end and the opposite end on the upper surface of the first chip; a bonding pad is arranged at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the corresponding channel; a plurality of ground vias penetrating the upper and lower surfaces of the first chip are provided between two adjacent channels and outside the head and tail channels; the upper surface of the first chip and the upper surface of the second chip are connected by a plurality of micro-bumps, and the plurality of micro-bumps are respectively arranged between two adjacent channels and outside the head and tail channels, and / or at corresponding positions between two adjacent channels and outside the head and tail channels on the upper surface of the second chip. The plurality of micro-bumps arranged between two adjacent channels and outside the head and tail channels, and / or at corresponding positions between two adjacent channels and outside the head and tail channels on the upper surface adjacent to the second chip, due to having a certain height, can form a shielding network in the space above the first chip, thereby effectively improving the inter-channel isolation degree of the space above the arrayed chip. Description of the Drawings

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0033] Figure 1 is a front view schematic diagram of the arrayed chip structure provided by an embodiment of the present invention;

[0034] Figure 2 is a top view schematic diagram of the arrayed chip structure provided by an embodiment of the present invention;

[0035] Figure 3 is a top view schematic diagram of the first chip provided by an embodiment of the present invention;

[0036] Figure 4 is a top view schematic diagram of the first chip provided by another embodiment of the present invention;

[0037] Figure 5 is a top view schematic diagram of the first chip provided by another embodiment of the present invention;

[0038] Figure 6 is a top view schematic diagram of the first chip provided by another embodiment of the present invention;

[0039] Figure 7 is a top view schematic diagram of the first chip provided by another embodiment of the present invention;

[0040] Figure 8 is a top view schematic diagram of the second chip provided by another embodiment of the present invention;

[0041] Figure 9 is a flowchart for implementing the preparation method of the arrayed chip structure provided by an embodiment of the present invention. Detailed implementation manners

[0042] To enable those skilled in the art to better understand this solution, the following will clearly describe the technical solutions in the embodiments of this solution in conjunction with the accompanying drawings in the embodiments of this solution. Obviously, the described embodiments are some, rather than all, of the embodiments of this solution. Based on the embodiments in this solution, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this solution.

[0043] In the specification, claims and above-mentioned drawings of this solution, the term "comprising" and any other variations thereof mean "including but not limited to", intending to cover non-exclusive inclusion and not limited only to the examples listed in the text. In addition, terms such as "first" and "second" are used to distinguish different objects rather than to describe a specific order.

[0044] The implementation of the present invention will be described in detail with reference to the specific drawings as follows:

[0045] Please refer to Figure 1 and Figure 2 , the arrayed chip structure includes: a first chip 11, a channel 12, a bonding pad 13, a ground via 14, a second chip 15 and a micro-bump 16;

[0046] At least two channels 12 are sequentially arranged between one end and the opposite end of the upper surface of the first chip 11;

[0047] A bonding pad 13 is respectively arranged at both ends of each channel 12, and each bonding pad 13 is respectively connected to the input end and the output end of the channel 12;

[0048] A plurality of ground vias 14 penetrating the upper and lower surfaces of the first chip 11 are arranged between adjacent two channels and outside the head and tail channels;

[0049] The upper surface of the first chip 11 and the upper surface of the second chip 15 are connected by a plurality of micro-bumps 16, and the plurality of micro-bumps 16 are respectively arranged between adjacent two channels and outside the head and tail channels, and / or at the corresponding positions between adjacent two channels and outside the head and tail channels on the upper surface of the second chip 15.

[0050] As a preferred implementation manner, the plurality of micro-bumps 16 are respectively arranged between adjacent two channels and outside the head and tail channels on the upper surface of the first chip 11, and at the corresponding positions of the micro-bumps between adjacent two channels and outside the head and tail channels on the upper surface of the second chip 15.

[0051] Figure 1 and Figure 2 are only exemplary drawings and do not limit the number of channels, the number of micro-bumps and the number of ground vias.

[0052] Refer to Figure 3 , in a possible implementation manner, at least two channels 12 are at least two first coplanar waveguide structures;

[0053] The first coplanar waveguide structure includes: a signal transmission line 121, ground lines 122 located on both sides of the signal transmission line, and traveling wave electrodes 123 between the signal transmission line and the ground lines.

[0054] The bonding pads 13 are respectively connected to the input end and the output end of the signal transmission line 121 in the first coplanar waveguide structure.

[0055] In a possible implementation, the radius of the microbump is any value from 40 microns to 50 microns.

[0056] The radius of the microbump is determined by the manufacturing process and is usually any value from 40 microns to 50 microns, such as: 40 microns, 45 microns or 50 microns.

[0057] In a possible implementation, the spacing between adjacent microbumps is less than one quarter of the signal wavelength.

[0058] Substantially, as long as the spacing between adjacent microbumps is less than the signal wavelength (i.e., λ), it can ensure that the signals between channels will not interfere with each other. However, in practical applications, when the spacing between adjacent microbumps is greater than one quarter of the signal wavelength (i.e., λ / 4), problems affecting signal quality will occur. Therefore, in the embodiments of the present invention, the spacing between adjacent microbumps is limited to be less than λ / 4.

[0059] In addition, it should be noted that: when the signal wavelengths between two adjacent channels are different, the spacing between adjacent microbumps is determined according to the smaller signal wavelength.

[0060] Since the radius of the microbump is any value from 40 microns to 50 microns, which is significantly smaller than the wavelength corresponding to the common arrayed channel frequency, the crosstalk signal between channels will not break through the shielding network constructed by the microbumps at a distance less than λ / 4 above the first chip, thus achieving the technical effect of improving the spatial isolation between channels.

[0061] In a possible implementation, multiple microbumps are respectively and evenly arranged between two adjacent channels and on the outer sides of the head and tail channels.

[0062] The multiple microbumps between every two adjacent channels are arranged in at least one straight line, and the multiple microbumps on the outer side of the head channel are arranged in at least one straight line, and the multiple microbumps on the outer side of the tail channel are arranged in at least one straight line.

[0063] Since the coplanar waveguide structure in the channel on the upper surface of the first chip has an antenna effect, it will emit electromagnetic waves into the space to form crosstalk, resulting in a reduction in the spatial isolation between channels. The straight lines formed by the arrangement of the microbumps between two adjacent channels and on the outer sides of the head and tail channels are substantially equivalent to spatial shielding lines, which are used to shield the signal crosstalk between channels in the space above the chip and improve the spatial isolation between channels. Correspondingly, the more the number of spatial shielding lines, the better the spatial isolation between channels. However, due to the limited size between two adjacent channels and on the outer sides of the head and tail channels, the number of spatial shielding lines needs to be set by the user according to the actual situation. Figure 3These are only exemplary drawings and do not specifically limit the number of microbumps and the number of spatial shielding lines.

[0064] See Figure 4 , in a possible implementation, the microbumps on two adjacent straight lines between every two adjacent channels are staggered, and the microbumps on two adjacent straight lines outside the first channel are staggered, and the microbumps on two adjacent straight lines outside the last channel are staggered.

[0065] Among them, the first channel and the last channel can be defined by the user according to the channel arrangement order. For example, Figure 4 shown in

[0066] channel 1201 is defined as the first channel, channel 1202 and channel 1203 are defined as the second channel and the third channel in sequence, and channel 1204 is defined as the last channel;

[0067] Or, channel 1204 is defined as the first channel, channel 1203 and channel 1202 are defined as the second channel and the third channel in sequence, and channel 1201 is defined as the last channel.

[0067] Meanwhile, referring to Figure 4 and Figure 5 together, the microbumps on two adjacent straight lines on both sides of each channel can be staggered or parallel, and the embodiments of the present invention do not specifically limit this.

[0068] To further improve the isolation effect between channels, when the number of straight lines formed by the arrangement of microbumps between every two adjacent channels is greater than or equal to 2, the microbumps on two adjacent straight lines between every two adjacent channels are staggered; correspondingly, when the number of straight lines formed by the arrangement of microbumps outside the first channel is greater than or equal to 2, the microbumps on two adjacent straight lines outside the first channel are staggered; when the number of straight lines formed by the arrangement of microbumps outside the last channel is greater than or equal to 2, the microbumps on two adjacent straight lines outside the last channel are staggered.

[0069] Correspondingly, as a preferred implementation, a plurality of microbumps are also arranged at the corresponding positions of the microbumps between every two adjacent channels on the upper surface of the second chip 15 and outside the first and last channels. That is, microbumps are also arranged on the upper surface of the second chip 15 and correspond one-to-one to the positions of the microbumps on the upper surface of the first chip 11.

[0070] In a possible implementation, the plurality of ground vias are a plurality of metallized ground vias.

[0071] In a possible implementation, the interval between adjacent ground vias is less than one-quarter of the signal wavelength.

[0072] Similarly to the setting rule of micro bumps, the interval between adjacent ground vias only needs to be less than the signal wavelength (i.e., λ) to ensure that signals between channels do not interfere with each other. However, in practical applications, when the interval between adjacent ground vias is greater than one-fourth of the signal wavelength (i.e., λ / 4), problems affecting signal quality will occur. Therefore, in the embodiments of the present invention, the distance between adjacent ground vias is limited to be less than λ / 4.

[0073] In addition, it should be noted that: when the signal wavelengths between two adjacent channels are different, the distance between adjacent ground vias is determined according to the smaller signal wavelength.

[0074] See Figure 3 , in a possible implementation, multiple ground vias are respectively and evenly arranged between two adjacent channels and outside the head and tail channels;

[0075] Multiple ground vias between each two adjacent channels are arranged in at least one straight line, and multiple ground vias outside the head channel are arranged in at least one straight line, and multiple ground vias outside the tail channel are arranged in at least one straight line;

[0076] Signal crosstalk also occurs between different channels inside the first chip. The straight lines formed by the arrangement of ground vias between two adjacent channels and outside the head and tail channels are substantially equivalent to shielded wires located inside the first chip, which are used to shield signal crosstalk between different channels inside the chip and improve the isolation degree between channels. Correspondingly, the more the number of shielded wires, the better the isolation degree between channels. However, due to the limited size between two adjacent channels and outside the head and tail channels, and too many ground vias will reduce the structural strength of the first chip. Therefore, the number of shielded wires needs to be set by the user according to the actual situation.

[0077] It should be noted that multiple ground vias do not coincide with multiple micro bumps. At the same time, between each two adjacent channels, the straight line formed by the arrangement of multiple ground vias and the straight line formed by the arrangement of micro bumps can be in a parallel state or a coincident state, which is not specifically limited in the embodiments of the present invention. Correspondingly, outside the head channel, the straight line formed by the arrangement of multiple ground vias and the straight line formed by the arrangement of micro bumps can be in a parallel state or a coincident state; outside the tail channel, the straight line formed by the arrangement of multiple ground vias and the straight line formed by the arrangement of micro bumps can be in a parallel state or a coincident state.

[0078] See Figure 6 , in a possible implementation, the ground vias on two adjacent straight lines between each two adjacent channels are arranged staggeredly, and the ground vias on two adjacent straight lines outside the head channel are arranged staggeredly, and the ground vias on two adjacent straight lines outside the tail channel are arranged staggeredly.

[0079] Correspondingly, referring together to Figure 6and Figure 7 , similar to the setting rule of the microbumps, the ground vias on two adjacent straight lines on both sides of each channel can be arranged staggeredly or in parallel. The embodiments of the present invention do not make specific limitations on this.

[0080] To further improve the isolation effect between channels, when the number of straight lines formed by the arrangement of the ground vias between two adjacent channels is greater than or equal to 2, the ground vias on two adjacent straight lines between each adjacent two channels are arranged staggeredly; correspondingly, when the number of straight lines formed by the arrangement of the ground vias outside the first channel is greater than or equal to 2, the ground vias on two adjacent straight lines outside the first channel are arranged staggeredly; when the number of straight lines formed by the arrangement of the ground vias outside the last channel is greater than or equal to 2, the ground vias on two adjacent straight lines outside the last channel are arranged staggeredly.

[0081] Substantially, the ground vias are used to construct the shielding network inside the first chip, and the microbumps are used to construct the shielding network in the space above the first chip. By combining the shielding networks constructed by the two, the signal crosstalk inside the first chip and in the space above the first chip can be effectively shielded, thereby effectively improving the isolation degree between channels.

[0082] Refer to Figure 1 and Figure 2 , in a possible implementation, the second chip 15 is disposed within the range of the first chip 11, and the bonding pads 13 are exposed outside the edge of the second chip 15.

[0083] The second chip 15 is disposed within the range of the first chip 11 such that the bonding pads 13 are exposed outside the edge of the second chip 15 to ensure that while improving the isolation degree between channels, the test function of the first chip is not affected.

[0084] Meanwhile, the thickness of the second chip 15 is generally set to any value between 100 microns and 200 microns to ensure the basic structural strength of the chip.

[0085] See Figure 8 , in a possible implementation, the arrayed chip structure further includes: a metal conductor layer 51 disposed on the upper surface of the second chip 15;

[0086] Correspondingly, the upper surface of the first chip 11 and the metal conductor layer 51 on the upper surface of the second chip 15 are connected by a plurality of microbumps 16, and the plurality of microbumps 16 are respectively disposed between two adjacent channels and outside the first and last channels, and / or at corresponding positions between two adjacent channels and outside the first and last channels on the metal conductor layer 51 on the upper surface of the second chip.

[0087] The metal conductor layer here can be prepared using gold or copper. The metal conductor layer prepared from gold or copper is laid on the upper surface of the second chip 15 and connected to the upper surface of the first chip 11 through micro-bumps 16. At this time, the metal conductor layer also has the same ground signal as the first chip, which is essentially equivalent to a metal ground layer. The metal ground layer and the micro-bumps jointly form a metal shielding network above the first chip, which can further improve the spatial shielding effect.

[0088] The beneficial effects of the arrayed chip structure provided by the embodiments of the present invention are as follows:

[0089] 1. High spatial isolation. Traditional arrayed chips can only ensure the isolation between the upper surface of the first chip and the channels inside the first chip, but cannot ensure the spatial isolation of the space above the first chip. Due to the antenna effect of the first coplanar waveguide structure on the upper surface of the first chip, electromagnetic waves will be emitted into the space above the first chip to form signal crosstalk between channels, resulting in a decrease in the spatial isolation between channels; while the embodiments of the present invention can significantly improve the spatial isolation between channels;

[0090] 2. Small size. Compared with traditional arrayed chips, the embodiments of the present invention only increase the height of the micro-bumps and the thickness of the second chip in the height direction. The radius of the micro-bumps and the thickness of the second chip are both in the micron range, so the size does not increase much;

[0091] 3. Easy to test. Since the size of the second chip used is set within the range of the first chip, and the bonding pads of the first chip are set on the four edges of the first chip (in line with the design rules of common chips), exposed outside the edge of the second chip, thus ensuring that the spatial isolation between channels is improved without affecting the testing of the first chip;

[0092] 4. Avoid contamination of the upper surface of the first chip by foreign objects. Since the radius of the micro-bumps is in the micron range, it is extremely difficult for foreign objects to contaminate the first chip through the gap between the second chip and the first chip, which also protects the first chip to a certain extent and can reduce the phenomenon of shortened lifespan of the first chip caused by foreign objects.

[0093] On the other hand, referring to Figure 9 , the embodiments of the present invention also provide a preparation method for an arrayed chip structure, including:

[0094] Step 901, prepare at least two channels in sequence from one end to the opposite end on the upper surface of the first chip;

[0095] Step 902, prepare a bonding pad at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the channel;

[0096] Step 903: Prepare a plurality of ground vias penetrating the upper and lower surfaces of the first chip between adjacent two channels and outside the head and tail channels;

[0097] Step 904: Prepare a plurality of micro-bumps between adjacent two channels and outside the head and tail channels, and / or at corresponding positions between adjacent two channels and outside the head and tail channels on the upper surface of the second chip;

[0098] Step 905: Flip-chip the upper surface of the second chip onto the upper surface of the first chip, and connect the upper surface of the first chip and the upper surface of the second chip through a plurality of micro-bumps to obtain an arrayed chip structure.

[0099] In the embodiment of the present invention, at least two channels are sequentially prepared from one end to the opposite end of the upper surface of the first chip; a bonding pad is prepared at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the corresponding channel; a plurality of ground vias penetrating the upper and lower surfaces of the first chip are prepared between adjacent two channels and outside the head and tail channels; a plurality of micro-bumps are prepared between adjacent two channels and outside the head and tail channels, and / or at corresponding positions between adjacent two channels and outside the head and tail channels on the upper surface of the second chip; the upper surface of the second chip is flip-chip arranged on the upper surface of the first chip, and the upper surface of the first chip and the upper surface of the second chip are connected through a plurality of micro-bumps to obtain an arrayed chip structure. By constructing a shielding network through a plurality of micro-bumps and the second chip in the space above the first chip, the channel isolation degree of the space above the first chip can be effectively improved.

[0100] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An arrayed chip structure, characterized in that, it includes: a first chip, channels, bonding pads, ground vias, a second chip, and micro-bumps; at least two channels are sequentially arranged between one end and the opposite end of the upper surface of the first chip; a bonding pad is respectively arranged at both ends of each channel, and each bonding pad is respectively connected to the input end and the output end of the corresponding channel; a plurality of ground vias penetrating the upper and lower surfaces of the first chip are arranged between adjacent two channels and outside the head and tail channels; the upper surface of the first chip and the upper surface of the second chip are connected by a plurality of micro-bumps, and the plurality of micro-bumps are respectively arranged between adjacent two channels and outside the head and tail channels, and / or at corresponding positions between adjacent two channels and outside the head and tail channels on the upper surface of the second chip; the radius of the micro-bump is any value from 40 microns to 50 microns; the interval between adjacent micro-bumps is less than one-fourth of the signal wavelength.

2. The arrayed chip structure according to claim 1, characterized in that, the plurality of micro-bumps are respectively uniformly arranged between adjacent two channels and outside the head and tail channels; the plurality of micro-bumps between every two adjacent channels are arranged in at least one straight line, and the plurality of micro-bumps outside the head channel are arranged in at least one straight line, and the plurality of micro-bumps outside the tail channel are arranged in at least one straight line.

3. The arrayed chip structure according to claim 2, characterized in that, the micro-bumps on adjacent two straight lines between every two adjacent channels are staggered, and the micro-bumps on adjacent two straight lines outside the head channel are staggered, and the micro-bumps on adjacent two straight lines outside the tail channel are staggered.

4. The arrayed chip structure according to claim 1, characterized in that, the plurality of ground vias are a plurality of metallized ground vias; the interval between adjacent ground vias is less than one-fourth of the signal wavelength.

5. The arrayed chip structure according to claim 4, characterized in that, the plurality of ground vias are respectively uniformly arranged between adjacent two channels and outside the head and tail channels; the plurality of ground vias between every two adjacent channels are arranged in at least one straight line, and the plurality of ground vias outside the head channel are arranged in at least one straight line, and the plurality of ground vias outside the tail channel are arranged in at least one straight line; the ground vias on adjacent two straight lines between every two adjacent channels are staggered, and the ground vias on adjacent two straight lines outside the head channel are staggered, and the ground vias on adjacent two straight lines outside the tail channel are staggered.

6. The arrayed chip structure according to claim 1, characterized in that, the second chip is arranged within the range of the first chip, and the bonding pads are exposed outside the edge of the second chip.

7. The arrayed chip structure according to claim 1, characterized in that, the at least two channels are at least two first coplanar waveguide structures; the bonding pads are respectively connected to the input end and the output end of the signal transmission line in the first coplanar waveguide structure.

8. The arrayed chip structure according to claim 1, characterized in that, it further includes: a metal conductor layer arranged on the upper surface of the second chip; The upper surface of the first chip is connected to the metal conductor layer on the upper surface of the second chip through a plurality of micro-bumps, and the plurality of micro-bumps are respectively arranged between the adjacent two channels and outside the head and tail channels, and / or at the corresponding positions between the adjacent two channels on the metal conductor layer on the upper surface of the second chip and outside the head and tail channels.

9. A method for preparing an arrayed chip structure, characterized in that, at least two channels are sequentially prepared from one end to the opposite end on the upper surface of the first chip; a bonding pad is prepared at each end of each channel, and each bonding pad is respectively connected to the input end and the output end of the corresponding channel; a plurality of ground vias penetrating the upper and lower surfaces of the first chip are prepared between the adjacent two channels and outside the head and tail channels; a plurality of micro-bumps are respectively prepared between the adjacent two channels and outside the head and tail channels, and / or at the corresponding positions between the adjacent two channels on the upper surface of the second chip and outside the head and tail channels; the upper surface of the second chip is flip-chip arranged on the upper surface of the first chip, and the upper surface of the first chip and the upper surface of the second chip are connected through the plurality of micro-bumps to obtain an arrayed chip structure; the radius of the micro-bump is any value from 40 microns to 50 microns; the interval between adjacent micro-bumps is less than one-fourth of the signal wavelength.

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