Ring-shaped barrel capacitor and its preparation method
By forming grooves on the substrate and filling epitaxial materials, annular barrel-type capacitors are prepared, which solves the problem of insufficient capacitance in the prior art and achieves a significant increase in capacitance.
Patent Information
- Application Number
- CN202210590714.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-27
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2042-05-27
AI Technical Summary
In the prior art, the capacitance of the capacitor is less affected by the process and cannot meet the demand.
By forming grooves on the substrate and filling the epitaxial material in the grooves, a capacitance layer of the dielectric layer and the conductive layer is formed, and the area of the dielectric layer and the conductive layer is increased, thereby increasing the capacitance.
The capacitance is greatly increased and the capacity needs are met.
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Figure CN115020384B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to an annular barrel-shaped capacitor and a manufacturing method thereof. Background Art
[0002] The larger the capacitance of a capacitor is, the better. However, in the prior art, the capacitance of a capacitor is affected by the process and is relatively small, which cannot well meet the requirements.
[0003] Therefore, it is necessary to provide a new type of annular barrel-shaped capacitor and a manufacturing method thereof to solve the above problems existing in the prior art. Summary of the Invention
[0004] The purpose of the present invention is to provide an annular barrel-shaped capacitor and a manufacturing method thereof to increase the capacitance.
[0005] To achieve the above purpose, the manufacturing method of the annular barrel-shaped capacitor of the present invention includes:
[0006] Provide a substrate;
[0007] Successively form a first silicon nitride layer and a hard mask layer on the substrate;
[0008] Successively etch the hard mask layer, the first silicon nitride layer and the substrate to form at least one groove;
[0009] Form at least one groove-shaped second silicon nitride layer in the groove, and fill epitaxial material in a part of the space between the second silicon nitride layer and the groove and in a part of the space inside the groove of the second silicon nitride layer;
[0010] Form at least one capacitor layer to cover the inner wall of the groove, the surface of the second silicon nitride layer and the top surface of the hard mask layer, and the capacitor layer includes a dielectric layer and a conductive layer in contact;
[0011] Remove the capacitor layer on the top surface of the hard mask layer;
[0012] Form an interlayer dielectric layer on the top surface of the hard mask layer and the exposed top surface of the capacitor layer;
[0013] Form a first metal conductive column with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer to form an annular barrel-shaped capacitor.
[0014] The beneficial effects of the method for preparing the ring-barrel capacitor are as follows: etching the hard barrier layer, the first silicon nitride layer, and the substrate in sequence to form at least one groove, forming at least one groove-shaped second silicon nitride layer in the groove, and filling epitaxial materials in partial spaces between the second silicon nitride layer and the groove and in partial spaces inside the groove of the second silicon nitride layer to form at least one capacitor layer covering the inner wall of the groove, the surface of the second silicon nitride layer, and the top surface of the hard barrier layer. The capacitor layer includes a dielectric layer and a conductive layer in contact with each other. The capacitor layer is arranged along the surface of the groove-shaped second silicon nitride layer and the inner wall of the groove, greatly increasing the areas of the dielectric layer and the conductive layer, and thus increasing the capacitance.
[0015] Optionally, forming at least one groove-shaped second silicon nitride layer in the groove, and filling epitaxial materials in partial spaces between the second silicon nitride layer and the groove and in partial spaces inside the groove of the second silicon nitride layer includes:
[0016] forming a first layer of epitaxial material on the inner surface of the groove and the top surface of the hard barrier layer;
[0017] alternately forming at least one second silicon nitride layer and at least one second layer of epitaxial material on the first layer of epitaxial material;
[0018] removing the first layer of epitaxial material, the second layer of epitaxial material, and the second silicon nitride layer located outside the groove to form at least one groove-shaped second silicon nitride layer;
[0019] etching partial first layer of epitaxial material and second layer of epitaxial material located inside the groove.
[0020] Optionally, after performing the removing the first layer of epitaxial material, the second layer of epitaxial material, and the second silicon nitride layer located outside the groove, it further includes:
[0021] etching the first layer of epitaxial material, the second layer of epitaxial material, and the second silicon nitride layer located inside the groove to make the top surface of the second silicon nitride layer lower than the top surface of the hard barrier layer.
[0022] Optionally, the etching partial first layer of epitaxial material and second layer of epitaxial material located inside the groove includes:
[0023] etching the first layer of epitaxial material and the second layer of epitaxial material located inside the groove until the top surfaces of the first layer of epitaxial material and the second layer of epitaxial material are at 1 / 5 to 1 / 4 of the depth of the groove.
[0024] Optionally, at least one capacitive layer is formed to cover the inner wall of the groove, the surface of the second silicon nitride layer, and the top surface of the hard barrier layer. The capacitive layer includes a dielectric layer and a conductive layer in contact with each other, including:
[0025] At least one dielectric layer and at least one conductive layer are alternately formed on the inner wall of the groove, the surface of the second silicon nitride layer, and the top surface of the hard barrier layer to form at least one capacitive layer.
[0026] Optionally, the formation of the first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer includes:
[0027] A first photoresist is formed on the interlayer dielectric layer;
[0028] The first photoresist is exposed to form a first photoresist pattern;
[0029] Using the first photoresist pattern as a mask, the interlayer dielectric layer is etched until the conductive layer is exposed to form a first conductive pillar through-channel;
[0030] The first conductive pillar through-channel is filled with metal to form a first metal conductive pillar.
[0031] Optionally, after successively etching the hard barrier layer, the first silicon nitride layer, and the substrate to form at least one groove, it further includes:
[0032] The first silicon nitride layer located under the hard barrier layer is etched to form side ear grooves in the groove.
[0033] Optionally, the formation of the first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer includes:
[0034] A first photoresist is formed on the interlayer dielectric layer;
[0035] The first photoresist is exposed to form a first photoresist pattern;
[0036] Using the first photoresist pattern as a mask, the interlayer dielectric layer is etched until the conductive layer is exposed to form a first conductive pillar through-channel;
[0037] Using the first photoresist pattern as a mask, the interlayer dielectric layer, the hard barrier layer, and the dielectric layer are successively etched until the conductive layer is exposed to form a second conductive pillar through-channel;
[0038] The first conductive pillar through-channel and the second conductive pillar through-channel are filled with metal to form a first metal conductive pillar.
[0039] Optionally, the method for manufacturing the ring barrel-shaped capacitor further includes:
[0040] Forming a second metal conductive pillar connected to the substrate and having one end extending to the top surface of the interlayer dielectric layer.
[0041] The present invention also provides a ring barrel-shaped capacitor, including:
[0042] A capacitor substrate, including a substrate, a first silicon nitride layer, a hard barrier layer, and at least one groove sequentially arranged from bottom to top, the groove penetrating through the hard barrier layer and the first silicon nitride layer and extending into the substrate;
[0043] At least one groove-shaped second silicon nitride layer disposed in the groove, and a part of the space between the second silicon nitride layer and the groove and a part of the space inside the groove of the second silicon nitride layer are filled with an epitaxial material;
[0044] A capacitor layer covering the inner wall of the groove and the surface of the second silicon nitride layer, the capacitor layer including a dielectric layer and a conductive layer in contact with each other;
[0045] An interlayer dielectric layer covering the top surface of the hard barrier layer and the exposed top surface of the capacitor layer;
[0046] A first metal conductive pillar having one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer.
[0047] The beneficial effect of the ring barrel-shaped capacitor is that at least one groove-shaped second silicon nitride layer is disposed in the groove, and a part of the space between the second silicon nitride layer and the groove and a part of the space inside the groove of the second silicon nitride layer are filled with an epitaxial material, the capacitor layer covers the inner wall of the groove and the surface of the second silicon nitride layer, the capacitor layer includes a dielectric layer and a conductive layer in contact with each other, and the capacitor layer is disposed along the surface of the groove-shaped second silicon nitride layer and the inner wall of the groove, greatly increasing the area of the dielectric layer and the conductive layer, and thus increasing the capacitance.
[0048] Optionally, the part of the space between the second silicon nitride layer and the groove and the part of the space inside the groove of the second silicon nitride layer are filled with an epitaxial material to a depth of 1 / 5 to 1 / 4 of the groove depth.
[0049] Optionally, a side ear groove is provided on the groove, and the side ear groove is disposed between the hard barrier layer and the substrate.
[0050] Optionally, the ring barrel-shaped capacitor further includes a second metal conductive pillar, one end of the second metal conductive pillar is connected to the substrate, and the other end extends to the top surface of the interlayer dielectric layer. Description of the Drawings
[0051] Figure 1It is a flowchart of the preparation method of the barrel-shaped capacitor of the present invention;
[0052] Figure 2 It is a schematic diagram of the first intermediate structure in some embodiments of the present invention;
[0053] Figure 3 It is a schematic diagram of the second intermediate structure in some embodiments of the present invention;
[0054] Figure 4 It is a schematic diagram of the third intermediate structure in some embodiments of the present invention;
[0055] Figure 5 It is a schematic diagram of the fourth intermediate structure in some embodiments of the present invention;
[0056] Figure 6 It is a schematic diagram of the fifth intermediate structure in some embodiments of the present invention;
[0057] Figure 7 It is a schematic diagram of the sixth intermediate structure in some embodiments of the present invention;
[0058] Figure 8 It is a schematic diagram of the seventh intermediate structure in some embodiments of the present invention;
[0059] Figure 9 It is a schematic diagram of the structure of the annular barrel-shaped capacitor in some embodiments of the present invention. Detailed implementation manners
[0060] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.
[0061] In view of the problems existing in the prior art, embodiments of the present invention provide a method for preparing an annular barrel-shaped capacitor. Referring to Figure 1 , the method for preparing the annular barrel-shaped capacitor includes the following steps:
[0062] S0: Provide a substrate;
[0063] S1: Sequentially form a first silicon nitride layer and a hard barrier layer on the substrate;
[0064] S2: Etch the hard barrier layer, the first silicon nitride layer, and the substrate in sequence to form at least one groove.
[0065] S3: Form at least one groove-shaped second silicon nitride layer in the groove, and fill epitaxial material in a partial space between the second silicon nitride layer and the groove and in a partial space inside the groove of the second silicon nitride layer.
[0066] S4: Form at least one layer of capacitor layer to cover the inner wall of the groove, the surface of the second silicon nitride layer, and the top surface of the hard barrier layer. The capacitor layer includes a dielectric layer and a conductive layer in contact with each other.
[0067] S5: Remove the capacitor layer on the top surface of the hard barrier layer.
[0068] S6: Form an interlayer dielectric layer on the top surface of the hard barrier layer and the exposed top surface of the capacitor layer.
[0069] S7: Form a first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer to form a ring-shaped barrel capacitor.
[0070] In some embodiments, forming at least one groove-shaped second silicon nitride layer in the groove, and filling epitaxial material in a partial space between the second silicon nitride layer and the groove and in a partial space inside the groove of the second silicon nitride layer includes:
[0071] Form a first layer of epitaxial material on the inner surface of the groove and the top surface of the hard barrier layer.
[0072] Alternately form at least one layer of second silicon nitride layer and at least one layer of second layer of epitaxial material on the first layer of epitaxial material.
[0073] Remove the first layer of epitaxial material, the second layer of epitaxial material, and the second silicon nitride layer located outside the groove to form at least one groove-shaped second silicon nitride layer.
[0074] Etch a part of the first layer of epitaxial material and the second layer of epitaxial material located inside the groove.
[0075] In some embodiments, after performing the removal of the first layer of epitaxial material, the second layer of epitaxial material, and the second silicon nitride layer located outside the groove, it further includes:
[0076] Etch the first layer of epitaxial material, the second layer of epitaxial material, and the second silicon nitride layer located inside the groove so that the top surface of the second silicon nitride layer is lower than the top surface of the hard barrier layer.
[0077] In some embodiments, the etching of a part of the first layer of epitaxial material and the second layer of epitaxial material located inside the groove includes:
[0078] Etch the first epitaxial material and the second epitaxial material located in the groove until the top surfaces of the first epitaxial material and the second epitaxial material are at 1 / 5 to 1 / 4 of the depth of the groove.
[0079] In some embodiments, forming at least one capacitor layer to cover the inner wall of the groove, the surface of the second silicon nitride layer, and the top surface of the hard barrier layer, the capacitor layer includes a dielectric layer and a conductive layer in contact with each other, including:
[0080] Alternately form at least one dielectric layer and at least one conductive layer on the inner wall of the groove, the surface of the second silicon nitride layer, and the top surface of the hard barrier layer to form at least one capacitor layer.
[0081] In some embodiments, forming a first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer, including:
[0082] Form a first photoresist on the interlayer dielectric layer;
[0083] Expose the first photoresist to form a first photoresist pattern;
[0084] Etch the interlayer dielectric layer using the first photoresist pattern as a mask until the conductive layer is exposed to form a first conductive pillar through-channel;
[0085] Fill the first conductive pillar through-channel with metal to form a first metal conductive pillar.
[0086] In some embodiments, after performing the sequential etching of the hard barrier layer, the first silicon nitride layer, and the substrate to form at least one groove, further including:
[0087] Etch the first silicon nitride layer under the hard barrier layer to form side ear grooves in the groove.
[0088] In some embodiments, forming a first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer, including:
[0089] Form a first photoresist on the interlayer dielectric layer;
[0090] Expose the first photoresist to form a first photoresist pattern;
[0091] Etch the interlayer dielectric layer using the first photoresist pattern as a mask until the conductive layer is exposed to form a first conductive pillar through-channel;
[0092] Using the first photoresist pattern as a mask, etch the interlayer dielectric layer, the hard barrier layer, and the dielectric layer in sequence until the conductive layer is exposed, so as to form a second conductive column through-channel;
[0093] Fill the first conductive column through-channel and the second conductive column through-channel with metal to form a first metal conductive column.
[0094] In some embodiments, the method for manufacturing the annular barrel-shaped capacitor further includes:
[0095] Form a second metal conductive column connected to the substrate and extending to the top surface of the interlayer dielectric layer at one end.
[0096] In some embodiments, the epitaxial material is tetraethyl orthosilicate, the material of the dielectric layer is an oxide or a nitride, the material of the conductive layer is a doped polymer, titanium nitride, tungsten, or cobalt silicide, and the material of the interlayer dielectric layer is tetraethoxysilane or borophosphosilicate glass.
[0097] In some embodiments, the material of the dielectric layer is an olefin composed of carbon, hydrogen, and fluorine, titanium monoxide, zirconium oxide, or trimethylaluminum.
[0098] Figure 2 This is a schematic diagram of the first intermediate structure in some embodiments of the present invention. Refer to Figure 2 , deposit a first silicon nitride layer 200 on the substrate 100, then deposit a hard barrier layer 300 on the first silicon nitride layer, coat a photoresist 400 on the hard barrier layer, and then expose the photoresist to form a photoresist pattern. Using the photoresist pattern as a mask, etch the hard barrier layer 300, the first silicon nitride layer 200, and the substrate 100 in sequence to form three grooves 101, and further etch the first silicon nitride layer 200 to form side ear grooves 102 on the grooves, thereby obtaining the first intermediate structure.
[0099] Figure 3 This is a schematic diagram of the second intermediate structure in some embodiments of the present invention. Refer to Figure 2 and Figure 3 , based on the first intermediate structure, deposit a first layer of epitaxial material 103 on the inner surfaces of the three grooves 101 and the top surface of the hard barrier layer 300, deposit a second silicon nitride layer 104 on the first layer of epitaxial material 103, and deposit a second layer of epitaxial material 105 on the second silicon nitride layer 104 to obtain the second intermediate structure.
[0100] Figure 4 This is a schematic diagram of the third intermediate structure in some embodiments of the present invention. Refer to Figure 3 and Figure 4, based on the second intermediate structure, remove the first epitaxial material 103, the second epitaxial material 105, and the second silicon nitride layer 104 outside the three grooves, and then remove the first epitaxial material 103, the second epitaxial material 105, and the second silicon nitride layer 104 inside the three grooves to respectively form a groove-shaped second silicon nitride layer 104 in the three grooves, thereby obtaining a third intermediate structure.
[0101] Figure 5 Schematic diagram of the fourth intermediate structure in some embodiments of the present invention. Refer to Figure 4 and Figure 5 , based on the third intermediate structure, etch the first epitaxial material 103 and the second epitaxial material 105 in the groove until the top surfaces of the first epitaxial material 103 and the second epitaxial material 105 are at 1 / 3 of the groove depth to obtain a fourth intermediate structure.
[0102] Figure 6 Schematic diagram of the fifth intermediate structure in some embodiments of the present invention. Refer to Figure 5 and Figure 6 , based on the fourth intermediate structure, deposit a first dielectric layer 106, deposit a first conductive layer 107 on the first dielectric layer 106, deposit a second dielectric layer 108 on the first conductive layer 107, and deposit a second conductive layer 109 on the second dielectric layer 108 to obtain a fifth intermediate structure. Among them, the first dielectric layer 106 and the first conductive layer 107 constitute a capacitance layer, and the second dielectric layer 108 and the second conductive layer 109 constitute a capacitance layer.
[0103] Figure 7 Schematic diagram of the sixth intermediate structure in some embodiments of the present invention. Refer to Figure 6 and Figure 7 , based on the fifth intermediate structure, remove the first dielectric layer 106, the first conductive layer 107, the second dielectric layer 108, and the second conductive layer 109 on the top surface of the hard barrier layer 300, that is, remove the capacitance layer on the top surface of the hard barrier layer, to obtain a sixth intermediate structure.
[0104] Figure 8 Schematic diagram of the seventh intermediate structure in some embodiments of the present invention. Refer to Figure 7 and Figure 8 , based on the sixth intermediate structure, deposit an interlayer dielectric layer 500 to obtain a seventh intermediate structure.
[0105] Figure 9 Schematic diagram of the structure of the ring-shaped barrel capacitor in some embodiments of the present invention. Refer to Figure 8 and Figure 9, based on the seventh intermediate structure, a photoresist is coated on the interlayer dielectric layer, and the photoresist is exposed to obtain a photoresist pattern. Using the photoresist pattern as a mask, the interlayer dielectric layer 500 is etched until the second conductive layer 109 is exposed to form a first conductive pillar through-channel; using the photoresist pattern as a mask, the interlayer dielectric layer 500, the hard barrier layer 300, and the first dielectric layer 106 are etched in sequence until the first conductive layer 107 is exposed to form a second conductive pillar through-channel; using the photoresist pattern as a mask, the interlayer dielectric layer 500, the hard barrier layer 300, and the first silicon nitride layer 200 are etched in sequence until the substrate 100 is exposed to form a third conductive pillar through-channel; then the photoresist is removed; a metal is deposited, and then a photoresist is coated on the metal. The newly coated photoresist is exposed to form a new photoresist pattern. Using the new photoresist pattern as a mask, the metal is etched to form a first metal conductive pillar 501 and a second metal conductive pillar 502, and then the photoresist is removed to form a ring-shaped barrel capacitor.
[0106] In some embodiments, the same first metal conductive pillar can be connected to the first conductive layer in adjacent grooves.
[0107] The present invention also provides a ring-shaped barrel capacitor, comprising:
[0108] A capacitor substrate, including a substrate, a first silicon nitride layer, a hard barrier layer, and at least one groove arranged from bottom to top in sequence. The groove penetrates the hard barrier layer and the first silicon nitride layer and extends into the substrate;
[0109] At least one groove-shaped second silicon nitride layer is arranged in the groove, and a part of the space between the second silicon nitride layer and the groove and a part of the space inside the groove of the second silicon nitride layer are filled with an epitaxial material;
[0110] A capacitor layer covers the inner wall of the groove and the surface of the second silicon nitride layer. The capacitor layer includes a dielectric layer and a conductive layer in contact with each other;
[0111] An interlayer dielectric layer covers the top surface of the hard barrier layer and the exposed top surface of the capacitor layer;
[0112] A first metal conductive pillar has one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer.
[0113] In some embodiments, a part of the space between the second silicon nitride layer and the groove and a part of the space inside the groove of the second silicon nitride layer are filled with an epitaxial material to 1 / 5 to 1 / 4 of the depth of the groove.
[0114] In some embodiments, a side ear groove is provided on the groove, and the side ear groove is arranged between the hard barrier layer and the substrate.
[0115] In some embodiments, the annular barrel-shaped capacitor further includes a second metal conductive column, one end of the second metal conductive column is connected to the substrate, and the other end extends to the top surface of the interlayer dielectric layer.
[0116] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.
Claims
1. A method for preparing a ring-barrel-shaped capacitor, characterized in that, Comprising: Providing a substrate; Successively forming a first silicon nitride layer and a hard mask layer on the substrate; Successively etching the hard mask layer, the first silicon nitride layer and the substrate to form at least one groove; Forming at least one groove-shaped second silicon nitride layer in the groove, and filling epitaxial material in a partial space between the second silicon nitride layer and the groove and in a partial space within the groove of the second silicon nitride layer; Forming at least one capacitor layer to cover the inner wall of the groove, the surface of the second silicon nitride layer and the top surface of the hard mask layer, the capacitor layer including a dielectric layer and a conductive layer in contact with each other; Removing the capacitor layer on the top surface of the hard mask layer; Forming an interlayer dielectric layer on the top surface of the hard mask layer and the exposed top surface of the capacitor layer; Forming a first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer to form an annular barrel-shaped capacitor; The forming at least one groove-shaped second silicon nitride layer in the groove, and filling epitaxial material in a partial space between the second silicon nitride layer and the groove and in a partial space within the groove of the second silicon nitride layer, includes: Forming a first layer of epitaxial material on the inner surface of the groove and the top surface of the hard mask layer; Successively forming at least one second silicon nitride layer and at least one second layer of epitaxial material on the first layer of epitaxial material; Removing the first layer of epitaxial material, the second layer of epitaxial material and the second silicon nitride layer located outside the groove to form at least one groove-shaped second silicon nitride layer; Etching a part of the first layer of epitaxial material and the second layer of epitaxial material located within the groove.
2. The method for preparing a ring-barrel capacitor according to claim 1, wherein After performing the removing of the first layer of epitaxial material, the second layer of epitaxial material and the second silicon nitride layer located outside the groove, further comprising: Etching the first layer of epitaxial material, the second layer of epitaxial material and the second silicon nitride layer located within the groove so that the top surface of the second silicon nitride layer is lower than the top surface of the hard mask layer.
3. The method for preparing a ring-barrel capacitor according to claim 1 or 2, wherein The etching a part of the first layer of epitaxial material and the second layer of epitaxial material located within the groove, includes: Etching the first layer of epitaxial material and the second layer of epitaxial material located within the groove until the top surfaces of the first layer of epitaxial material and the second layer of epitaxial material are at 1 / 5 to 1 / 4 of the depth of the groove.
4. The method for preparing a ring-barrel capacitor according to claim 1, wherein The forming at least one capacitor layer to cover the inner wall of the groove, the surface of the second silicon nitride layer and the top surface of the hard mask layer, the capacitor layer including a dielectric layer and a conductive layer in contact with each other, includes: Successively forming at least one dielectric layer and at least one conductive layer on the inner wall of the groove, the surface of the second silicon nitride layer and the top surface of the hard mask layer to form at least one capacitor layer.
5. The method for preparing a ring-barrel capacitor according to claim 1, wherein The forming a first metal conductive pillar with one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer, includes: Forming a first photoresist on the interlayer dielectric layer; Exposing the first photoresist to form a first photoresist pattern; Etching the interlayer dielectric layer using the first photoresist pattern as a mask until the conductive layer is exposed to form a first conductive pillar through-channel; Filling metal in the first conductive pillar through-channel to form a first metal conductive pillar.
6. The method for preparing a ring-barrel capacitor according to claim 1, wherein After performing the sequential etching of the hard mask layer, the first silicon nitride layer, and the substrate to form at least one groove, the method further includes: Etching the first silicon nitride layer under the hard mask layer to form side ear grooves within the groove.
7. The method for preparing a ring-barrel capacitor according to claim 6, characterized in that, The forming of the first metal conductive pillar having one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer includes: Forming a first photoresist on the interlayer dielectric layer; Exposing the first photoresist to form a first photoresist pattern; Etching the interlayer dielectric layer using the first photoresist pattern as a mask until the conductive layer is exposed to form a first conductive pillar through-channel; Sequentially etching the interlayer dielectric layer, the hard mask layer, and the dielectric layer using the first photoresist pattern as a mask until the conductive layer is exposed to form a second conductive pillar through-channel; Filling the first conductive pillar through-channel and the second conductive pillar through-channel with metal to form a first metal conductive pillar.
8. The method for preparing a ring-barrel-shaped capacitor according to claim 1, wherein The method further includes: Forming a second metal conductive pillar connected to the substrate and having one end extending to the top surface of the interlayer dielectric layer.
9. A ring-shaped barrel capacitor, characterized in that, The method includes: A capacitor substrate including a substrate, a first silicon nitride layer, a hard mask layer, and at least one groove sequentially arranged from bottom to top, where the groove penetrates the hard mask layer and the first silicon nitride layer and extends into the substrate; At least one groove-shaped second silicon nitride layer disposed within the groove, and a portion of the space between the second silicon nitride layer and the groove and a portion of the space within the groove of the second silicon nitride layer are filled with an epitaxial material; A capacitor layer covering the inner wall of the groove and the surface of the second silicon nitride layer, the capacitor layer including a dielectric layer and a conductive layer in contact with each other; An interlayer dielectric layer covering the top surface of the hard mask layer and the exposed top surface of the capacitor layer; A first metal conductive pillar having one end connected to the conductive layer and the other end extending to the top surface of the interlayer dielectric layer.
10. The annular barrel-shaped capacitor according to claim 9, wherein, The portion of the space between the second silicon nitride layer and the groove and the portion of the space within the groove of the second silicon nitride layer are filled with an epitaxial material to a depth of 1 / 5 to 1 / 4 of the groove depth.
11. The annular barrel-shaped capacitor according to claim 9, characterized in that, Side ear grooves are provided on the groove, and the side ear grooves are disposed between the hard mask layer and the substrate.
12. The annular barrel-shaped capacitor according to claim 9, wherein, The method further includes a second metal conductive pillar having one end connected to the substrate and the other end extending to the top surface of the interlayer dielectric layer.
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