Method for die-to-wafer device layer transfer with precise control of device layer vertical position

Abstract

The present disclosure relates to methods for die-to-wafer device layer transfer with precise control of the device layer's vertical position. Methods and structures are described for facilitating the transfer of device layer coupons with controlled vertical positions. In one embodiment, a plurality of device layer coupons are bonded to a receiving substrate with an adhesive layer, wherein the distance between the front surfaces of the plurality of device layer coupons and the bulk layer of the receiving substrate is controlled by a plurality of rigid mechanical spacers.

Description

[0001] Related patent applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 156,140, filed on March 3, 2021, which is incorporated herein by reference. Technical Field

[0003] The embodiments described herein relate to die-to-wafer transfer, and more particularly to layer transfer of epitaxial device layers. Background Art

[0004] Wafer-to-wafer (W2W) and die-to-wafer (D2W) are well-established microelectronics manufacturing techniques that often use SiO2-SiO2 fusion bonding between wafers or chips on a wafer. This can additionally be combined with metal-to-metal bonding for hybrid bonding techniques. Hybrid bonding is a suitable technique that has been adopted in the mass production of high-density input / output (I / O) chips with ultra-small pad pitches. Generally speaking, the hybrid bonding process flow may include initial oxide-to-oxide bonding at room temperature, followed by heating to close the recessed gap, and then further heating to compress the metal.

[0005] Typically, when using hybrid bonding for heterogeneous integration of dissimilar materials, the two bonded substrates should have similar coefficients of thermal expansion (CTE). For substrates with different CTEs, the bond can be damaged between the heating and cooling processes due to strain between the substrates, leading to delamination or other damage. Hybrid bonding processes also require a rigorous pre-bonding cleaning regimen to avoid the presence of particles at the bonding interface. Summary of the Invention

[0006] Methods and structures for controlling the vertical position of device layer coupons during device layer transfer are described. Specifically, the manufacturing sequence can be used to manufacture micro light emitting diode (LED) display panels. In one embodiment, the manufacturing sequence includes forming a reconstructed structure of multiple device layer coupons and then bonding the reconstructed structure to a receiving substrate to transfer the multiple device layer coupons to the receiving substrate. More specifically, the method of forming the reconstructed structure may include bonding multiple device layer coupons on a carrier substrate with an adhesive layer. The multiple device layer coupons can be cut from multiple different processing (e.g., growth) substrates. In such a process, the multiple rigid mechanical spacers can be used to control the distance between the front surface of the multiple device layer coupons and the body layer of the carrier substrate. The multiple rigid mechanical spacers can be used to control the vertical position while also allowing the presence of potential particles at the bonding interface without affecting the vertical position of the device layer coupons. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a schematic perspective view illustration of a baseline micro-LED microdisplay fabrication sequence according to an embodiment, including epitaxial reconstruction, micro-LED frontplane fabrication, and wafer-to-wafer hybrid integration.

[0008] Figure 2A is a schematic cross-sectional side view illustration of a reconstructed structure including multiple device layer coupons fusion-bonded to a carrier substrate.

[0009] Figure 2B yes Figure 2A Schematic cross-sectional side view illustration of the plurality of device layer coupons after removal of the handle substrate.

[0010] Figure 3A is a schematic cross-sectional side view illustration of a reconstructed structure including multiple device layer coupons adhesively bonded to a carrier substrate.

[0011] Figure 3B yes Figure 3A Schematic cross-sectional side view illustration of the multiple device layer coupons after handle substrate removal and planarization.

[0012] Figure 4A is a schematic cross-sectional side view illustration of a reconstructed structure including a plurality of device layer coupons adhesively bonded to a carrier substrate including a plurality of hard stop protrusion structures, according to one embodiment.

[0013] Figure 4B According to an embodiment Figure 4A Schematic cross-sectional side view illustration of the plurality of device layer coupons after removal of the handle substrate.

[0014] Figure 4C is a close up schematic cross-sectional side view illustration of an epitaxial device layer coupon adhesively bonded to a carrier substrate including a plurality of hard stop protrusion structures according to one embodiment.

[0015] Figure 4D According to an embodiment Figure 4A 2 is a schematic, cross-sectional side view illustration of a close-up of a plurality of micro-LEDs formed in an epitaxial device layer coupon after removal of a handle substrate.

[0016] 5A to 5D Is formed according to the implementation plan Figure 4B Schematic cross-sectional side view illustration of a sequence of reconstructed structures.

[0017] Figure 6 is a schematic cross-sectional side view illustration of a bonding operation including a colloidal adhesive layer according to an embodiment.

[0018] Figure 7is a schematic cross-sectional side view illustration of a bonding operation including a patterned adhesive layer on a carrier substrate according to an embodiment.

[0019] Figure 8 is a schematic cross-sectional side view illustration of a bonding operation including a patterned adhesive layer on a device layer coupon, according to an embodiment.

[0020] Figure 9 is a schematic cross-sectional side view illustration of a bonding operation including patterned adhesive layers on both a carrier substrate and a device layer coupon, according to an embodiment.

[0021] Figures 10A to 10E According to one embodiment, Figure 4B Schematic cross-sectional side view illustration of a reconstructed structured device layer coupon fusion-bonded to a receiving substrate.

[0022] Figure 10F According to an embodiment Figure 10E A close-up schematic cross-sectional side view illustration of multiple micro-LEDs formed in an epitaxial device layer coupon.

[0023] Figure 11 According to one embodiment, Figure 4D or Figure 10F Close-up schematic cross-sectional side view illustration of a reconstructed micro-LED device layer coupon hybrid-bonded to a receiving substrate. DETAILED DESCRIPTION

[0024] The embodiment describes a method for die-to-wafer transfer of a device layer for controlling the vertical position of the transferred device layer. More specifically, an embodiment for forming a reconstructed structure is described, comprising bonding a plurality of device layer coupons to a carrier substrate with an adhesive layer, wherein a plurality of rigid mechanical spacers control the distance between the front surfaces of the plurality of device layer coupons and the body layer of the carrier substrate, and the adhesive layer at least partially fills the space between the plurality of rigid mechanical spacers. Thereafter, the reconstructed structure can be bonded to a receiving substrate, and the carrier substrate removed. In such a sequence, the plurality of protrusions can help control the vertical position of the device layer coupons and mitigate the effects of potential particle contamination when forming the reconstructed structure. In one embodiment, the plurality of rigid mechanical spacers are a plurality of hard stop protrusion structures extending from the body layer. In one embodiment, the plurality of rigid mechanical spacers are a plurality of microspheres dispersed in the adhesive layer.

[0025] After transferring the device layer coupon to the carrier substrate, the device layer coupon can then optionally be further processed, or even transferred to an intermediate carrier substrate for further processing. For example, where the device layer coupon includes a pn diode layer, a specific transfer or flip can be performed so that the preferred side (e.g., the p-side or the n-side) is facing up for processing. In one embodiment, the device layer coupon is further processed to form a plurality of micro light emitting diodes (LEDs) or at least a micro LED mesa structure of partially fabricated micro LEDs. The reconstructed structure can then be bonded to a receiving substrate such as a carrier substrate to transfer the plurality of device layer coupons again.

[0026] The device layer specimen block according to the embodiment may be any device layer for heterogeneous integration and may include an epitaxial layer, such as but not limited to a grown light emitting diode (LED) epitaxial layer, a laser diode (LD) epitaxial layer, a photodiode (PD) epitaxial layer, a vertical cavity surface emitting laser (VCSEL) epitaxial layer, a microelectromechanical system (MEMS) epitaxial layer, an InGaN / GaN-based blue / green / red LED epitaxial layer, an AlInGaP / GaAs-based red / orange / yellow LED epitaxial layer, or an organic LED layer.

[0027] The device layer may additionally include a conductive layer on top, such as an indium tin oxide (ITO) or other transparent conductive oxide layer or a metal layer. In addition, a dielectric layer may be formed over the conductive layer. For example, the dielectric layer may be a SiO2 layer, an AlO x layer, SiN x In some embodiments, the device layer may include functional devices formed by patterning the epitaxial device layer and forming electrical connections.

[0028] According to an embodiment, the manufacturing sequence described herein can be used to form a display panel, or more specifically, a micro-LED-based display panel for a micro-display. The manufacture of a micro-display panel based on a micro-LED array according to an embodiment may include hybrid integration of a micro-LED array front plane (e.g., a wafer or device layer sample block) into a complementary metal oxide semiconductor (CMOS) driver backplane. Typically, the complex design of a high pixel density driver backplane requires a CMOS technology node that is only available on a 12-inch silicon platform. In addition, a 12-inch silicon CMOS backplane is preferred from cost and throughput considerations. However, LED epitaxial structures for efficient blue / green / red emission can be grown on substrate wafers that are 8 inches or smaller in size. In addition, the direct growth of epitaxial LED layers on 12-inch silicon substrate wafers is still in the early stages of development and may take considerable time to mature. According to an embodiment, epitaxial device layer reconstruction provides an alternative method to generate an artificial 12-inch silicon epitaxial wafer from a commercially available smaller-sized epitaxial wafer. In the epitaxial layer reconstruction process described herein, the smaller-sized epitaxial wafer can be cut into individual sample block stacks and then bonded face-down to a 12-inch silicon carrier wafer. Once the growth (eg, handle) substrate of the epitaxial coupon is removed, an artificial 12-inch epitaxial-on-silicon wafer is generated for subsequent micro-LED front-plane processing and 12-inch wafer-to-wafer hybrid integration.

[0029] Among the various available bonding technologies, fusion bonding and adhesive bonding are two widely used wafer bonding techniques. It has been observed that for fusion bonding where the bonding layer on both the epitaxial coupon and the receiving 12-inch silicon substrate is a rigid material such as SiO2, the presence of particles on the bonding surface can cause detrimental effects. To avoid bonding failure due to the presence of particles or debris on the bonding surface, an alternative approach is to use an adhesive polymer in a liquid or soft-cured form as a bonding agent. However, it has been observed that because the epitaxial coupons filling the 12-inch silicon wafer are derived from multiple epitaxial wafers, the thickness of the epitaxial coupons can vary due to variations in the thickness of the growth substrate and variations in the thickness of the epitaxial layers. Consequently, it has been observed that such thickness variations, together with the soft bonding layer, lead to poor vertical position control and tilt of the transferred epitaxial coupons, which makes subsequent micro-LED array processing very challenging and degrades the performance and uniformity of the micro-LED arrays. To address this issue, embodiments implement structural hard stop mechanisms that press the transferred epitaxial coupons against these hard stop features, thereby mitigating the uncertainty in the vertical position and tilt of the transferred epitaxial coupons.

[0030] It should be understood that although 6-inch, 8-inch, 12-inch, and 450 mm wafers, etc. are specifically described herein, these are industry standard representations that may vary. Therefore, the embodiments are not limited to the specific wafer or substrate sizes described in the exemplary description.

[0031] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and constructions. In the following description, many specific details such as specific configurations, dimensions, and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. References to "one embodiment" throughout the specification refer to specific features, structures, constructions, or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, constructions, or characteristics may be combined in one or more embodiments in any appropriate manner.

[0032] As used herein, the terms "over," "to," "between," "span," and "on" may refer to the relative position of one layer relative to other layers. A layer that is "over," "spanning," or "on," or coupled "to," or "in contact with," relative to another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0033] Now refer to Figure 1 , provides an illustration of a baseline reconstruction structure 131 and a fusion bonding sequence according to an embodiment. As shown, the sequence can begin with a plurality of device layer coupons 106 on a processing substrate 104. For example, the device layer coupon 106 can be a patterned epitaxial device layer, or an area that will be subsequently cut (as shown by the dotted line). The processing substrate 104 can optionally be a growth substrate, such as silicon, sapphire, GaN, GaAs, etc., depending on the composition of the device layer coupon 106. Thus, the device layer coupon 106 can be a uniform device layer, wherein the growth substrate and the device layer will subsequently be cut to form a coupon stack including the device layer coupon 106. Alternatively, the processing substrate can be a support substrate to which the device layer has been transferred, for example, from a growth substrate. In this configuration, the support substrate and the device layer can subsequently be cut to form a coupon stack including the device layer coupon 106. Either sequence is possible, depending on which side of the device layer is to be processed.

[0034] The device layer coupons may additionally include a conductive layer on top, such as an indium tin oxide (ITO) or other transparent conductive oxide layer or a metal layer. In addition, a dielectric layer may optionally be formed over the conductive layer. For example, the dielectric layer may be a SiO2 layer, an AlO x layer, SiN x In some embodiments, the device layer may include functional devices formed by patterning the epitaxial device layer and forming electrical connections.

[0035] The plurality of device layer coupons 106 may then be transferred to a carrier substrate 130 at operation 1010 to form a reconstructed structure 131. For example, such transfer may include individual device layer coupons 106 (or coupon stacks) or D2W bonding of W2W. Any such technique may use techniques such as fusion bonding, hybrid bonding, adhesive bonding, etc. As will be described in further detail herein, the plurality of device layer coupons 106 (or coupon stacks) may be adhesively bonded on top of a plurality of rigid mechanical spacers. For example, these may be a plurality of hard stop protrusion structures extending from a bulk layer of a carrier substrate, or a plurality of microspheres dispersed in an adhesive layer.

[0036] The carrier substrate 130 can be made of various materials, such as a silicon wafer, a glass substrate, a sapphire wafer, or a substrate having a coefficient of thermal expansion (CTE) in the range of, for example, 1-20×10 -6 The carrier substrate may be any flat wafer made of a material within the Å / K range. For example, the carrier substrate may be 6 inches, 8 inches, 12 inches, or 450 mm in size. In one embodiment, the semiconductor device layer coupons have a nominal size range of 100 μm to 10 cm in maximum lateral dimension, or more specifically, 500 μm to 10 cm in maximum lateral dimension.

[0037] At this stage, reconstructing the structure 131 may involve several different processing sequences. Figure 1In the embodiment of the first processing sequence shown, the reconstructed structure 131 can then be further processed at operation 1020A, for example, to form an array of micro-LEDs 150, or at least micro-LED mesas 155 of partially fabricated micro-LEDs 150 in the device layer coupon 106. For example, each micro-LED mesa 155 can have a maximum lateral dimension of 1-100 μm, such as 1-10 μm, or possibly even less than 1 μm. A receiving substrate 202 can then be provided, including circuitry 210, such as driver circuitry. According to an embodiment, the receiving substrate 202 can be, for example, a silicon substrate to support CMOS driver circuitry. The reconstructed structure 131 can then be bonded to the receiving substrate 202 at operation 1030A. Specifically, the array of micro-LED mesas 155 of the device layer coupon 106 can be bonded to driver pads, as well as any other pad connections of the circuitry 210. This can include W2W bonding, including fusion bonding or hybrid bonding. In this manner, hybrid bonding can include both metal-metal bonding for the micro LED 150 pads to the driver pads, and oxide-oxide bonding of the planarized insulating layer (e.g., SiO 2 ). The carrier substrate 130 can then be removed, leaving the plurality of device layer coupons 106 on the receiving substrate 202. Further wafer-level processing can then be performed, including chemical mechanical polishing (CMP), redistribution layer (RDL), and / or optical structure formation, such as a color filter array, a microlens array, and the like.

[0038] In an alternative second processing sequence, the resulting reconstructed structure 131 of operation 1010 can then be bonded to a second carrier substrate 130A. For example, this can include a fusion bonding process (e.g., a SiO2-SiO2 bonding interface). The carrier substrate 130 can then be removed, leaving the device layer coupon 106 on the second carrier substrate 130A. As a result, the orientation of the device layer coupon 106 is now flipped. The resulting reconstructed structure 131 can then be further processed at operation 1020B, similar to that previously described at operation 1020A, to form an array of micro-LEDs 150, or at least micro-LED mesa structures 155 of partially fabricated micro-LEDs 150 in the device layer coupon 106. The reconstructed structure 131 can then be bonded to a receiving substrate 202 at operation 1030B, similar to that previously described with respect to operation 1030A.

[0039] As will become more apparent in the following description, there are two significant differences in the two process flows. First, the orientation of the device layer coupon 106 can be flipped in an additional W2W operation. Second, processing the device layer coupon 106 to form an array of micro-LEDs 150 or micro-LED mesas 155 can be formed on different carrier substrates. For example, the device layer coupon 106 can be bonded to the carrier substrate 130 using adhesive bonding material and rigid mechanical spacers, while the device layer coupon 106 can be fusion bonded to the second carrier substrate 130A. In addition, the fusion bonded reconstruction structure 131 including the second carrier substrate 130A can potentially be exposed to higher processing temperature conditions without including the adhesive bonding material used to initially transfer the device layer coupon 106 to the carrier substrate 130 and initially control the vertical position.

[0040] Now refer to Figures 2A to 2B , Figure 2A is a schematic cross-sectional side view illustration of a plurality of device layer coupons 106 fusion-bonded to a carrier substrate 130, Figure 2B yes Figure 2A 1. A schematic cross-sectional side view of the plurality of device layer coupons 106 after removal of the processing (eg, growth) substrate 104 is shown. In particular, Figures 2A to 2B The potential impact of particles on fusion bonding, and therefore on hybrid bonding techniques, is shown. For fusion bonding where the bonding layers on both the epitaxial device layer coupons and the carrier substrate 130 (e.g., 12-inch silicon) are of a rigid material such as SiO2, the presence of particles 135 on the bonding surface may cause adverse effects. In addition, since the epitaxial device layer coupons 106 that populate the 12-inch silicon wafer are from multiple handle substrates 104, variations in the bonding layer thickness may determine variations in the vertical position of the epitaxial device layer coupons 106 that are transferred to the larger carrier substrate 130. The vertical position variation (Δz) of the front surface 108 of the device layer coupons 106 across the exemplary 12-inch carrier substrate 130 can be as large as approximately 500 nm, which can make the subsequent micro LED array manufacturing process challenging and degrade the performance and uniformity of the micro LED array.

[0041] Reference again Figure 2A, shows an exemplary processing sequence in which one or more dielectric layers 120 (e.g., SiO2) are deposited on top of the plurality of device layer coupons 106 on a handling substrate 104, which are then cut into a plurality of coupon stacks 110. It has been observed that the cutting of the coupon stacks 110 may produce particles 135. The particles may affect the bonding interface when bonding to the corresponding dielectric layer 132 on the carrier substrate 130. Furthermore, in case the coupon stacks 110 are transferred from different handling substrates 104 or from different areas of the same handling substrate 104, there may be process variations in the layer thickness, in particular the dielectric layer 120, which may also contribute to vertical position variations (Δz). This may occur after removing portions of the handling substrate 104, for example using known techniques such as grinding, laser lift-off, etc. Figure 2B . The presence of particles 135 may additionally result in delamination of the device layer coupon 106. Furthermore, vertical position variation (Δz) may also contribute to irregular thickness of the device layer coupon 106, or incomplete removal of the handle substrate 104, further resulting in variations in final product performance.

[0042] Now refer to Figures 3A to 3B , Figure 3A is a schematic cross-sectional side view illustration of a plurality of device layer coupons 106 adhesively bonded to a carrier substrate 130, Figure 3B yes Figure 3A 1. A schematic cross-sectional side view of the plurality of device layer coupons 106 after removal of the processing (eg, growth) substrate 104 is shown. In particular, Figures 3A to 3B The potential influence of particles on adhesive bonding, and therefore on hybrid bonding techniques, is shown.

[0043] To avoid bonding failures due to the presence of particles or debris on the bonding surface, an alternative approach is to use an adhesive polymer in liquid or soft cured form as a bonding agent. However, since the device layer coupons 106 that populate the exemplary 12-inch carrier substrate 130 may come from multiple handle substrates 104, the thickness of the coupon stack 110 may vary due to variations in the thickness of the handle (growth) substrate 104 and variations in the thickness of the epitaxial device layer coupons 106. Such thickness variations, together with the soft bonding layer, can result in poor vertical position control and tilting of the transferred device layer coupons 106. Reference Figure 3B The vertical position variation (Δz) may also contribute to the result of irregular thickness of the device layer coupon 106, or incomplete removal of the handle substrate 104, further leading to variations in final product performance.

[0044] Now refer to Figures 4A to 4B , Figure 4Ais a schematic cross-sectional side view illustration of a reconstructed structure 131 including a plurality of device layer coupons 106 adhesively bonded to a carrier substrate 130 including a plurality of hard stop protrusion structures 134, according to one embodiment, Figure 4B According to an embodiment Figure 4A FIG. 1 is a schematic cross-sectional side view illustration of the plurality of device layer coupons 106 after the handle (eg, growth) substrate 104 is removed.

[0045] In one aspect, the hard stop protrusion structure 134 according to an embodiment is implemented to address Figures 2A to 2B Fusion or hybrid bonding technology and Figures 3A to 3B Specifically, to achieve greater particle tolerance, better vertical position control, and better parallelism control of the transferred device layer coupons 106 onto the exemplary 12-inch carrier substrate 130, separate hard stop protrusion structures 134 are formed on or from the carrier substrate 130 using suitable techniques, such as (1) photolithographic patterning and etching of the exposed bulk layer 138 (e.g., silicon); (2) nanoimprint lithography followed by dry / wet etching methods; (3) forming a hard stop protrusion on the bulk layer 138. (4) forming a uniform layer of a photosensitive polymer (e.g., polyimide, benzocyclobutene (BCB), photoresist, or SU-8) on top of the bulk layer 138 and then patterning the layer using photolithography or embossing / imprinting methods; or (5) attaching a pre-patterned protrusion structure layer to the bulk layer 138. As shown, the hard stop protrusion structure 134 can extend from the bulk layer 138 of the carrier substrate 130 and can be formed integrally with the bulk layer 138 or as a separate layer on top of the bulk layer 138.

[0046] Forming the hard stop protrusion structure 134 on top of the carrier substrate 130 may further include chemically mechanically polishing the hard stop protrusion structure 134 to flatten the top surface 136 of the protrusion structure across the entire carrier substrate 130. For example, the plane defined by the top surface 136 can be substantially flat, with an unevenness of less than 200 nm. When viewed from the top surface 136, the hard stop protrusion structure 134 can have various shapes, such as circular, square, rectangular, triangular, hexagonal, star-shaped, a mesh network pattern, and other arbitrary shapes. The arrangement of the hard stop protrusion structure 134 can be a uniform array pattern or a non-uniform array pattern, for example, less densely arranged in areas with higher particle density. The sidewalls of the hard stop protrusion structure 134 can be vertical or inclined. In various embodiments, the horizontal dimension (e.g., width) of the hard stop protrusion structure nominally ranges from 1 μm to 100 μm, and the height of the hard stop protrusion structure nominally ranges from 200 nm to 10 μm. The average spacing between adjacent hard stop protrusion structures may be nominally 2 to 10 times the horizontal dimension of the hard stop protrusion structures and may be substantially smaller than the dimension of the device layer coupon 106 , such as half or less.

[0047] like Figure 4A As shown, an adhesive layer 140 may be dispensed on top of a carrier substrate 130 having hard stop protrusion structures 134. The adhesive layer may cover the top surface 136 of the hard stop protrusion structures and fill the space (S) therebetween. Forming the adhesive layer 140 according to one embodiment may include (1) forming a continuous adhesive layer 140 covering the entire surface of the carrier substrate 130; (2) forming a patterned adhesive layer having periodically present gaps or voids to facilitate lateral expansion of the adhesive when pressed during the adhesive hardening process, and (3) forming a patterned adhesive layer covering the surface of the carrier substrate 130 except near the hard stop protrusion structures, so that the hard stop protrusion structures are isolated from the adhesive layer. The adhesive layer may also be formed on the front surface 108 of the device layer coupon 106. The adhesive layer may be a continuous layer or a patterned layer having recessed areas, wherein the positions of the recessed areas match the hard stop protrusion structures 134 on the carrier substrate 130. The adhesive layer 140 may be a benzocyclobutene (BCB) layer, a polyimide layer, a SU-8 layer, an acrylic layer, a silicone layer, or a combination thereof.

[0048] In other embodiments, the adhesive layer 140 can be a colloidal adhesive layer that provides rigid mechanical spacer control and can be applied without the hard stop protrusion structure 134. For example, as described with respect to Figure 6 As further described in detail, the adhesive layer 140 may also be a colloidal adhesive layer having rigid microspheres suspended in the adhesive, wherein the diameters (d) of the microspheres are substantially the same, preferably Δd<100 nm.

[0049] The sample block stack 110 can be transferred to a carrier substrate 130 that is securely attached to a rigid mechanical spacer, such as a Figure 4A The hard stop projection structure 134 is shown, or alternatively may be Figure 6 of rigid microspheres. The adhesive layer 140 can additionally be cured and hardened by heating to a high temperature or by irradiation (laser, UV, electron beam, etc.) while the force firmly abuts the device layer coupon 106 against the hard stop protrusion structure. In this way, the front surface 108 of the device layer coupon 106 will be well aligned with the plane defined by the top surface 136 of the hard stop protrusion structure 134, thereby achieving precise control of the vertical position and parallelism of the device layer coupon 106 transferred to the exemplary 12-inch carrier substrate. The handle substrate 104 portion can then be removed, for example, using known techniques such as grinding, laser stripping, etc., without affecting the position of the device layer coupon 106. In one embodiment, the resulting reconstructed structure 121 includes a vertical position change (Δz) of the front surface 108 of less than 50 nm.

[0050] Now refer to Figures 4C to 4D , Figure 4C is a close-up schematic cross-sectional side view illustration of an epitaxial device layer coupon 106 adhesively bonded to a carrier substrate 130 including a plurality of hard stop protrusion structures 134 according to one embodiment, Figure 4D is formed in Figure 4A The plurality of micro LEDs 150 in the epitaxial device layer coupon 106 are removed and processed (eg, grown) on the substrate 104 according to one embodiment. Figure 1 Schematic cross-sectional side view illustration of the subsequent processing operation 1020A after. In particular, Figures 4C to 4D A reconfiguration structure 131 is shown that can be used in the manufacture of a microdisplay based on a microLED array. Although a specific process is illustrated with respect to a hard stop protrusion structure 134, alternatively a hard stop protrusion structure 134 may be used. Figure 6 Rigid microspheres.

[0051] exist Figure 4CIn the structure shown, the sample block stack has been transferred and bonded to a carrier substrate 130. Similar to the previous description, the sample block stack includes a handle substrate 104 and a portion of a device layer sample block 106. The device layer sample block 106 may have been previously transferred to the handle substrate 104, or grown directly on the handle substrate. In such a configuration, the device layer sample block 106 may include a buffer layer 117 for lattice matching and absorbing growth defects, a first doped layer 116 (e.g., n-doped or p-doped), an active layer 114 that may include one or more quantum well layers separated by barrier layers, and a second doped layer 112 (e.g., p-doped or n-doped) doped opposite to the first doped layer. As is known, additional layers such as electron or hole blocking layers may be included. Before removing the handle substrate 104, Figure 4C The structure shown in Figure 1 The structure completed at operation 1010.

[0052] Now refer to Figure 4D , as previously described with respect to the processing sequence including operation 1020A, the reconstructed structure 131 can then be further processed at operation 1020A to form an array of micro-LEDs 150, or at least partially fabricated micro-LEDs, including micro-LED mesas 155 in the device layer coupon 106. Such a processing sequence can optionally be performed to condition the reconstructed structure 131 for use in Figure 1 It should be understood that the micro-LEDs 150 and micro-LED mesas 155 can take on various configurations and Figure 4D The specific configuration of the embodiment is not limited to Figure 4D In an exemplary process flow, the handle substrate 104 is first removed, and then the device layer coupons 106 are patterned into one or more micro-LED mesas 155 .

[0053] A suitable etching technique (eg, dry process) and a hard mask (such as SiO2 or HfO2) may be used. x ) to form the micro-LED mesa structure 155. An optional sidewall passivation layer 107 can then be formed on the mesa sidewalls and underlying topography (e.g., doped layer 112). For example, the sidewall passivation layer 107 can be formed by atomic layer deposition. An exemplary material is Al2O3 or other suitable dielectric material. The sidewall passivation layer 107 can then be patterned to form openings that will expose the micro-LED mesa structure 155 (e.g., doped layer 116).

[0054] In one embodiment, a well structure 173 is then formed around the micro-LED mesa structure 155. In one embodiment, the well structure 173 is formed of one or more insulating materials. In one embodiment, the well structure material is a polymer or glass material. The well structure 173 material may additionally include scattering particles dispersed in a matrix (e.g., a polymer or glass) to act as a diffuser. In such a structure, the propagation length of light between scattering events may be very small, giving light emitted from the micro-LED an opportunity to be extracted. An exemplary diffuser may include a transparent well structure 173 material filled with scattering particles. The transparent well structure 173 material may also be a low refractive index material, a high refractive index material, or have the same refractive index as the overlying layer. In one embodiment, the well structure 173 material is deposited and patterned to form a well structure. Suitable techniques include, but are not limited to, spin coating, spray coating, ink jetting, slit coating, and the like.

[0055] After forming the well structure 173, a reflective layer may be optionally deposited and patterned to form a reflective layer 175 around the well structure. The reflective layer 175 may be a continuous layer that spans within the opening in the well structure 173 material around and below the corresponding micro-LED mesa structure 155 and above the doped layer 116. It should be understood that terms such as below, bottom, and above may refer to other features at a particular stage of manufacturing. For example, the reflective layer 175 may be Figure 4D 150 is above the micro LED mesa structure 155 during the manufacturing stage and below the bottom surface of the micro LED mesa structure 155 of the micro LED microdisplay in the downstream manufacturing stages. As shown, the reflective layer 175 spans along the sidewalls of the well structure 173. In some embodiments, the reflective layer 175 can be formed directly on the bottom surface of the micro LED mesa structure 155. In other embodiments, a contact layer (e.g., ITO) is pre-formed above the doped layer 116. In this way, the reflective layer 175 can be formed directly on the contact layer on the bottom surface of the micro LED mesa structure 155. The reflective layer 175 can be formed of various reflective materials and can be different depending on the composition of the micro LEDs 150. Therefore, different reflective layers 175 can be formed over different LED coupons. Exemplary materials include, but are not limited to, aluminum, silver, gold, etc.

[0056] The bottom contact 180 (i.e., bond post) can then be formed. In one embodiment, the bottom contact 180 is formed using a suitable technique (such as electroplating). The fill layer 174 (e.g., a planarization layer) can then be blanket deposited, such as using spin coating techniques, spray coating, etc. An oxide bonding layer 178, such as a high-quality oxide (e.g., silicon oxide) for promoting hybrid bonding, can optionally be formed over the fill layer 174. The fill layer 174 and / or the oxide bonding layer 178 can then be planarized to produce a flat surface 186, including the flat surface 172 of the fill layer 174 or the oxide bonding layer 178, and the flat surface 182 of the bottom contact 180. The fill layer 174 can be formed of a suitable insulating material (such as a polymer or glass). In embodiments in which the reflective layer 175 is not formed, the well structure 173 material is selected to have a refractive index higher than the refractive index of the fill layer 174 to take advantage of reflection by total internal reflection. The order of forming bottom contact 180 and fill layer 174 and oxide bonding layer 178 may also be reversed, wherein fill layer 174 and oxide bonding layer 178 are formed, followed by patterning, forming bottom contact 180 (e.g., by electroplating), and planarization to create flat surface 186.

[0057] Now refer to 5A to 5D , providing a formation according to an embodiment Figure 4B A schematic cross-sectional side view of a sequence of reconstructed structures 131 is shown. As shown, the sequence may begin with a plurality of starting process (growth) substrates 104 and an epitaxially grown device layer 105. In one embodiment, the epitaxially grown device layer 105 is a pn diode layer. As shown, the device layer in this specific embodiment may include a buffer layer 117 on the process (growth) substrate 104 for arranging the lattice constant between the heterogeneous materials and absorbing the resulting defects, as well as a doping layer 116 (e.g., n-doped), an active layer 114, and a doping layer 112 (e.g., p-doped) as previously described. The thickness of the epitaxially grown device layer 105 may vary depending on the application. In one embodiment, the buffer layer 117 has a thickness of approximately 5 μm, the doping layer 116 has a thickness of approximately 0.1 μm-6 μm, or more specifically 0.1 μm-3 μm, the active layer 114 has a thickness of less than approximately 0.3 μm, and the doping layer 112 has a thickness of approximately 0.1 μm-1 μm. In one embodiment, the total thickness of the pn diode minus the buffer layer 117 is less than 5 μm or more specifically less than 3 μm. In one embodiment, as previously described, a contact layer such as ITO is formed over the doped layer 112. The stack shown is exemplary, and embodiments are not limited to this particular layer sequence. Figure 5A Also shown is a carrier substrate 130 that includes a plurality of hard stop protrusion structures 134 as previously described.

[0058] The handle (growth) substrate 104 and the epitaxially grown device layer 105 can then be cut into separate coupon stacks 110 using a suitable technique such as blade sawing, laser cutting, plasma cutting, etc. Figure 5B As shown, such techniques can potentially result in residual particles 135 on the front surface 108 of the sample block stack 110. The adhesive layer 140 can then be applied to the carrier substrate 130 according to any of the methods previously described. Figure 5C In the particular embodiment shown, the adhesive layer may completely cover the top surface 136 of the hard stop protrusion structure 134, although other configurations are also contemplated.

[0059] Now refer to Figure 5D , the plurality of coupon stacks 110 and the carrier substrate 130 can be brought together by pressing the front surface 108 directly against the top surface 136 of the hard stop protrusion structure 134 with pressure applied from a top platen 164 and a bottom platen 162. The bottom platen may also include or be connected to a heater to provide heat to the adhesive layer 140. As shown, the applied pressure can cause excess adhesive layer 140 material to be squeezed out from under the coupon stacks 110 into the area between the coupon stacks 110. The top squeeze platen 164 may include a flexible surface for the coupon stacks 110 to ensure that uniform pressure is applied to each coupon stack placed on top of the carrier substrate 130 with the protrusion structure. In one embodiment, the vertical position of the front surface 108 of the device layer coupons 106 varies by less than 50 nm.

[0060] The adhesive layer 140 can additionally be cured and hardened by heating to a high temperature with a heater (e.g., connected to the bottom platen 162) or by irradiation (laser, UV, electron beam, etc.), while the device layer coupon 106 is firmly pressed against the hard stop protrusion structure 134. The handle substrate 104 portion can then be removed, for example, using known techniques such as grinding, laser lift-off, etc. This can be accompanied by a back grinding or polishing operation to obtain Figure 4B The structure shown in .

[0061] The adhesive layer 140 according to the embodiment may be formed of various compositions and applied in various forms. Figure 61 is a schematic cross-sectional side view illustration of a bonding operation including a colloidal adhesive layer 140 according to an embodiment. As shown, the adhesive layer 140 may include microspheres 142 distributed within a matrix of the adhesive layer 140. For example, the microspheres may be rigid spheres that are not relatively ductile, although certain metals may be used. In one embodiment, the diameters (d) of the microspheres 142 are substantially the same, preferably Δd < 100 nm. In the illustrated embodiment, the uniform diameter microspheres 142 can provide the same function as the hard stop protrusion structure 134. Thus, the adhesive layer 140 film can be used in place of the hard stop protrusion structure 134, but they can be combined.

[0062] Figure 7 14 is a schematic cross-sectional side view diagram of a bonding operation including a patterned adhesive layer 144 on a carrier substrate according to an embodiment. The patterned adhesive layer 144 can be identical in composition to the adhesive layer 140 described previously. As shown, the patterned adhesive layer 144 can be a single preformed pattern or multiple separate pieces. In other embodiments, a uniform patterned adhesive layer 144 can be deposited and then subsequently patterned. In each case, the patterned arrangement can be used to accommodate the expansion of the patterned adhesive layer 144 after compression due to pressure applied from the top platen 164 and the bottom platen 162.

[0063] Figure 8 1 is a schematic cross-sectional side view illustration of a bonding operation including a patterned adhesive layer 144 on a device layer coupon 106, according to an embodiment. As shown, the patterned adhesive layer 144 can be a single preformed pattern or multiple separate pieces. In other embodiments, a uniformly patterned adhesive layer 144 can be deposited and then subsequently patterned. In an embodiment, the hard stop protrusion structures 134 can have different sizes. For example, some of the hard stop protrusion structures 134 can have a smaller width in the area that will receive the device layer coupon 106 (below it), while a larger width can be formed between the device layer coupons 106, where it may be less necessary to provide adhesion. The spacing between the hard stop protrusion structures 134 can also vary. The pitch between the hard stop protrusion structures 134 in a regular pattern can vary. The hard stop protrusion structures 134 can have a regularly spaced structure. The hard stop protrusion structures 134 can include one or more groups of protrusions of varying sizes or pitches deployed in the same area. The hard stop protrusion structures 134 can have random or pseudo-random spacing. The hard stop protrusion structures 134 may not be present in some areas on the carrier substrate 130. Thus, embodiments contemplate various orientations.

[0064] Figure 9is a schematic cross-sectional side view illustration of a bonding operation according to an embodiment including patterned adhesive layer 144 on both carrier substrate 130 and device layer coupon 106. Such a configuration can provide additional clearance between rigid surfaces prior to high temperature reflow and curing operations.

[0065] All reconstructed structures 131 described above up to this point may then be bonded to a receiving substrate 202 to transfer the device layer coupons 106, which may be, for example, epitaxial films or patterned epitaxial films. Alternatively, the reconstructed structures may be bonded to a second carrier substrate 130A. 10A to 10F According to one embodiment, Figure 4B A schematic cross-sectional side view of a reconstructed device layer coupon 106 fusion-bonded to a second carrier substrate 130A is shown. 10A to 10F The processing sequence shown in corresponds to Figure 1 An alternative processing sequence including operations 1015, 1020B, 1030B is shown in FIG. It should be understood that the fusion bonding sequence is exemplary and that embodiments contemplate various modifications.

[0066] Now refer to Figure 10A , in the exemplary Figure 4B A dielectric layer 176 (e.g., a fusion bonding layer) is optionally formed over the reconstructed structure 131. Thus, the dielectric layer 176 (e.g., SiO2) can be a global layer formed over the carrier substrate 130. It is not required to form such a dielectric layer 176, but rather, the dielectric layer 176 can be formed as part of the device layer sample block 106. Similarly, a dielectric layer 204 (e.g., a fusion bonding layer) can be formed over the second carrier substrate 130A. For example, the dielectric layer 204 (e.g., SiO2) can be planarized in preparation for W2W bonding. It should be understood that the carrier substrate 130 including the hard stop protrusion structure 134 is exemplary and other rigid mechanical spacers, such as those dispersed throughout, can be implemented. Figure 6 The reconstructed structure 131 can then be bonded to a second carrier substrate 130A, such as Figure 10B In an exemplary embodiment, the illustrated dielectric layers 176, 204 are fusion bonded together. In one embodiment, Figure 10B The bonding operation is a W2W bonding operation between two wafers.

[0067] refer to Figure 10C , the carrier substrate 130, and optionally at least a portion of the adhesive layer 140, may be removed. At this stage, the relative orientation of the doped layers 112, 116 is reversed. As shown, the front surface 108 of the device layer coupon 106 is now facing upward. Figure 10DAs shown in FIG, a gap filling layer 214 is formed on the dielectric layer 176 and between the plurality of device layer coupons 106. The gap filling layer 214 can be any suitable insulating material formed by various deposition methods to provide a gap filling function between adjacent device layer coupons 106. The gap filling layer 214 can also be used for subsequent fusion / hybrid bonding. For example, the gap filling layer 214 can be SiO2. Then, the reconstructed structure 131 can be planarized or the thickness can be reduced in other ways, such as Figure 10E As shown, the front surface 108 of the device layer coupons 106 is exposed. As shown, a flat surface 186 can be formed across the gap-fill layer 214 and the plurality of device layer coupons 106.

[0068] Now see Figure 10F , according to one embodiment, Figure 10E FIG. 1 is a close-up schematic cross-sectional side view illustration of a plurality of micro-LEDs 150 formed in an epitaxial device layer coupon. Figure 10F The specific structure shown in Figure 4D shown and previously relative to Figure 4D The structures described above are similar to those described above. Therefore, for the sake of clarity and brevity, similarities are not repeated. There are significant differences in the formation of micro-LEDs 150 over the fusion-bonded second carrier substrate 130A. Additionally, the adhesive layer material has been removed during previous processing. Furthermore, the orientation of the LED mesas 155 is reversed, with bottom contacts 180 formed on doped layer 112 opposite to doped layer 116.

[0069] Figure 11 According to one embodiment, Figure 4D or Figure 10F A close-up schematic cross-sectional side view illustration of a micro LED device layer coupon 106 of a reconstructed structure 131 hybrid bonded to a receiving substrate 202, including metal-to-metal bonding. In particular, Figure 11 The structure shown in Figure 1 As shown, the bottom contact 180 is bonded to a contact pad 211 (e.g., an electrode pad, a driver pad) on a receiving (e.g., display) substrate 202. The bonding can be achieved using various methods, including W2W.

[0070] In a particular embodiment, a hybrid bonding technique is utilized in which the bottom surface 182 of the bottom contact 180 is bonded to the top surface 212 of the contact pad 211 with metal-metal bonding, and the bottom surface 172 of the fill layer 174 or oxide bonding layer 178 is bonded to the top surface 205 of the receiving (display) substrate 202 with oxide-oxide bonding. For example, the top surface 205 can also be the top surface of the oxide bonding layer 204 of the receiving substrate, such as a high-quality oxide (e.g., silicon oxide). Depending on the embodiment, hybrid bonding can be facilitated by bonding of planarized surfaces. The receiving substrate 202 can be a variety of substrates including polymers, glass, silicon, etc., and can be rigid or flexible. In one embodiment, the receiving substrate 202 includes a silicon substrate. For example, the receiving substrate 202 can be a complementary metal oxide semiconductor (CMOS) wafer that includes circuitry 210 for addressing the micro-LEDs 150 bonded to the contact pad 211.

[0071] exist Figure 11 In the embodiment shown, the carrier substrate 130 or the second carrier substrate 130A has been removed along with the corresponding adhesive layer 140 or fusion bonding dielectric layer 176, 204, which may be followed by thinning of the device layer coupons 106, or more specifically, the doping layer 112 or the doping layer 116 to form separate, isolated micro-LEDs 150. Various contacts (e.g., n-contacts, although p-contacts may be used) may optionally be formed on the micro-LED mesas 155 of the micro-LEDs 150. A top electrode layer 190 is then formed over the micro-LEDs 150. The top electrode layer 190 may be a common layer shared by multiple micro-LEDs 150, and in some embodiments, across multiple pixels. The top electrode layer 190 may additionally be formed on contact terminals 220. For example, the contact terminals may be connected to a ground or low voltage (Vss) line. As shown, the contact terminals 220 may be in the form of plugs or through-holes extending through the fill layer 174. In one embodiment, the contact terminals 220 are located on corresponding contact pads 211 of the receiving substrate 202. The contact terminals 220 can be formed at various stages. For example, the contact terminals 220 can be formed together with the bottom contact pads 211. In such an embodiment, the contact terminals 220 can be bonded to the contact pads 211 by metal-metal bonding during a hybrid bonding technique. The contact terminals 220 can optionally be formed after the carrier substrate is removed. Further wafer-level processing can follow, including CMP, RDL and / or optical structure formation, such as color filter arrays, microlens arrays, etc. Figure 11 In the exemplary embodiment shown in FIG, a microlens 192 may be formed above each micro LED 150. For example, the microlens 192 may be formed of a transparent high refractive index material (eg, n=1.3-2.4) and may be formed in various shapes including a hemisphere.

[0072] When utilizing various aspects of the embodiments, it will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming micro-LED arrays using wafer reconfiguration and die-to-wafer transfer of device layers with controlled vertical positions. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as exemplary embodiments of the claims.

Claims

1. A method for forming a reconstructed structure, comprising: bonding a plurality of device layer coupons on a carrier substrate with an adhesive layer, wherein each of the plurality of device layer coupons is connected to a corresponding handle substrate, wherein a plurality of rigid mechanical spacers control distances between front surfaces of the plurality of device layer coupons and a bulk layer of the carrier substrate, wherein the adhesive layer at least partially fills spaces between the plurality of rigid mechanical spacers and the adhesive layer at least partially fills spaces between the plurality of device layer coupons; hardening the adhesive layer; removing each processed substrate; as well as Back grinding is performed to form a surface having the plurality of device layer coupons and the adhesive layer. 2 . The method of claim 1 , further comprising forming the adhesive layer over the body layer of the carrier substrate, wherein the plurality of rigid mechanical spacers are a plurality of hard stop protrusion structures extending from the body layer.

3. The method of claim 2 , wherein forming the adhesive layer comprises forming a patterned adhesive layer covering the body layer of the carrier substrate except in the vicinity of the plurality of hard stop protrusion structures, such that the plurality of hard stop protrusion structures are isolated from the adhesive layer. 4 . The method of claim 1 , further comprising forming the adhesive layer over the bulk layer of the carrier substrate, wherein the plurality of rigid mechanical spacers are a plurality of microspheres dispersed in the adhesive layer. The method of claim 1 , wherein forming the adhesive layer comprises forming a continuous adhesive layer over the carrier substrate. 6 . The method of claim 1 , wherein an average spacing between adjacent hard stop protrusion structures is half or less of an average width of the device layer coupons.

7. The method of claim 1, wherein top surfaces of the plurality of rigid mechanical spacers form a plane with a non-flatness less than 200 nm.

8. The method of claim 1, further comprising patterning a plurality of micro light emitting diode mesas into each device layer coupon when the plurality of device layer coupons are bonded to the carrier substrate.

9. The method according to claim 8, further comprising: hybrid bonding the plurality of device layer coupons to a receiving substrate; wherein the receiving substrate includes a complementary metal oxide semiconductor (CMOS) driver circuit, and the plurality of micro light emitting diode mesas are bonded to contact pads connected to the CMOS driver circuit; The maximum lateral dimension of each micro-LED mesa structure is 1-100 μm; or wherein the maximum lateral dimension of each micro-LED mesa structure is 1-10 μm; or wherein the maximum lateral dimension of each micro-LED mesa structure is less than 1 μm; or wherein the carrier substrate is a 6-inch, 8-inch, 12-inch or 450 mm substrate; or wherein the receiving substrate and the carrier substrate are of the same size; or wherein the maximum lateral dimension of each device layer specimen is 100 μm to 10 cm; or wherein bonding the plurality of device layer coupons on the carrier substrate comprises transferring the plurality of device layer coupons from a same handle substrate to a carrier substrate, wherein the handle substrate is smaller than the carrier substrate; or wherein bonding the plurality of device layer coupons on the carrier substrate comprises transferring the plurality of device layer coupons from a different handle substrate to the carrier substrate, wherein the different handle substrate is smaller than the carrier substrate; or Also included are a plurality of reflective layers surrounding the plurality of micro-LED mesa structures; Also included is forming a plurality of bottom contacts over the plurality of micro light emitting diode mesas, and wherein hybrid bonding the plurality of device layer coupons to the receiving substrate comprises bonding the plurality of bottom contacts to the contact pads with metal-metal bonding.

10. The method according to claim 1, further comprising: bonding the plurality of device layer coupons to a second carrier substrate; as well as The carrier substrate is removed. 11 . The method of claim 10 , further comprising patterning a plurality of micro light emitting diode mesas into each device layer coupon after removing the carrier substrate.

12. The method according to claim 11, further comprising: bonding the plurality of device layer coupons to a receiving substrate; The receiving substrate includes a complementary metal oxide semiconductor (CMOS) driver circuit, and the plurality of micro light emitting diode mesas are bonded to contact pads connected to the CMOS driver circuit.

13. The method of claim 12, wherein bonding the plurality of device layer coupons to the second carrier substrate comprises fusion bonding, and bonding the plurality of device layer coupons to the receiving substrate comprises hybrid bonding; wherein the maximum lateral dimension of each micro-LED mesa structure is 1-100 μm; or wherein the maximum lateral dimension of each micro-LED mesa structure is 1-10 μm; or wherein the maximum lateral dimension of each micro-LED mesa structure is less than 1 μm; or wherein the carrier substrate is a 6-inch, 8-inch, 12-inch or 450 mm substrate; or wherein the receiving substrate and the carrier substrate are of the same size; or wherein the maximum lateral dimension of each device layer specimen is 100 μm to 10 cm; or wherein bonding the plurality of device layer coupons on the carrier substrate comprises transferring the plurality of device layer coupons from a same handle substrate to a carrier substrate, wherein the handle substrate is smaller than the carrier substrate; or wherein bonding the plurality of device layer coupons on the carrier substrate comprises transferring the plurality of device layer coupons from a different handle substrate to the carrier substrate, wherein the different handle substrate is smaller than the carrier substrate; or Also included are a plurality of reflective layers surrounding the plurality of micro-LED mesa structures; Also included is forming a plurality of bottom contacts over the plurality of micro light emitting diode mesas, and wherein hybrid bonding the plurality of device layer coupons to the receiving substrate comprises bonding the plurality of bottom contacts to the contact pads with metal-metal bonding.

14. A reconstruction structure, comprising: a carrier substrate including a body layer; a plurality of device layer coupons bonded to the carrier substrate with an adhesive layer; as well as a plurality of rigid mechanical spacers extending between the front surfaces of the plurality of device layer coupons and the bulk layer of the carrier substrate, wherein the plurality of rigid mechanical spacers control the distance between the front surfaces of the plurality of device layer coupons and the bulk layer of the carrier substrate, wherein the adhesive layer at least partially fills the spaces between the plurality of rigid mechanical spacers and the adhesive layer at least partially fills the spaces between the plurality of device layer coupons; and The adhesive layer spans between the plurality of device layer coupons and the back ground surfaces of the plurality of device layer coupons.

15. The reconstruction structure of claim 14, wherein the plurality of rigid mechanical spacers are a plurality of hard stop protrusion structures extending from the bulk layer of the carrier substrate.

16. The reconstitution structure of claim 14, wherein the plurality of rigid mechanical spacers are a plurality of microspheres dispersed in the adhesive layer.

17. The reconstructed structure of claim 14, further comprising a plurality of micro-LED mesas patterned into each device layer coupon.

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