Array substrate and display panel

Abstract

The present invention provides an array substrate and display panel. The array substrate comprises: a substrate; a thin-film transistor circuit layer disposed on the substrate and including thin-film transistors; a planarization layer disposed on the thin-film transistor circuit layer; and a first electrode disposed on the planarization layer and electrically connected to the thin-film transistors via vias penetrating the planarization layer. The first electrode comprises a stacked structure of a first film layer, a second film layer, and a third film layer, wherein the first film layer is disposed in contact with the planarization layer, and the second film layer is spaced apart from the planarization layer. Under high-temperature conditions, the first film layer is inert relative to the planarization layer. By adding a first film layer structure within the first electrode, the present invention prevents the first electrode from reacting with water vapor in the planarization layer during high-temperature processes, thereby preventing the generation of hydrogen ions. This, in turn, prevents the reduction of the active layer of the thin-film transistor by hydrogen ions, which typically causes negative drift in the thin-film transistor.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] In top-emitting organic light-emitting diode (OLED) display panels, the anode generally adopts a laminated structure of aluminum-nickel-copper-lanthanum alloy / tungsten oxide (ANCL / WO x ), the preparation process is as follows: first, an aluminum-nickel-copper-lanthanum alloy is deposited on the pixel definition layer by a physical vapor deposition process, and then a dense aluminum oxide layer is formed on the surface of the aluminum-nickel-copper-lanthanum alloy by vacuum oxidation. Then, a tungsten single film is prepared by a physical vapor deposition process again, and finally, the entire surface is subjected to high-temperature annealing treatment to convert the tungsten single film into tungsten oxide.

[0003] However, the aforementioned aluminum-nickel-copper-lanthanum alloy / tungsten oxide structure has a series of defects: First, because the aluminum-nickel-copper-lanthanum alloy is in direct contact with the planarization layer, the high-temperature annealing process and subsequent curing process will cause the aluminum in the aluminum-nickel-copper-lanthanum alloy to react with the water vapor in the planarization layer, generating hydrogen ions. The hydrogen ions will diffuse downward, causing the active layer of the thin-film transistor to be reduced, thereby causing the electrical properties of the thin-film transistor to drift negatively. Second, tungsten oxide is easily reduced by water washing and corroded by developer, making it impossible to use conventional water washing and development processes in the later stages, resulting in process instability, yield loss, and difficulty in mass production. Summary of the Invention

[0004] The present invention provides an array substrate and a display panel to solve the problem of hydrogen ions generated by the reaction between the anode and the water vapor in the planarization layer.

[0005] To solve the above problems, the technical solutions provided by the present invention are as follows:

[0006] The present invention provides an array substrate, comprising:

[0007] substrate;

[0008] a thin film transistor circuit layer, provided on the substrate, comprising thin film transistors;

[0009] a planarization layer, disposed on the thin film transistor circuit layer;

[0010] The first electrode is provided on the planarization layer and is electrically connected to the thin film transistor through a via hole penetrating the planarization layer; wherein,

[0011] The first electrode is a stacked structure of a first film layer / a second film layer / a third film layer. The first film layer is arranged in contact with the planarization layer, and the second film layer is arranged in intervals with the planarization layer. Under high temperature conditions, the first film layer is inert relative to the planarization layer.

[0012] Optionally, in some embodiments of the present invention, the material of the first film layer includes indium tin oxide, indium zinc oxide, metal molybdenum, titanium, nickel, niobium, and an alloy of molybdenum, titanium, nickel, and niobium.

[0013] Optionally, in some embodiments of the present invention, the material of the first film layer is molybdenum-titanium-nickel alloy.

[0014] Optionally, in some embodiments of the present invention, the material of the third film layer is indium tin oxide or indium zinc oxide.

[0015] Optionally, in some embodiments of the present invention, the third film layer covers the second film layer.

[0016] Optionally, in some embodiments of the present invention, the surface of the third film layer facing away from the second film layer is a passivation surface.

[0017] Optionally, in some embodiments of the present invention, the material of the second film layer is aluminum alloy.

[0018] Optionally, in some embodiments of the present invention, the material of the second film layer is aluminum-nickel-copper-lanthanum alloy.

[0019] Optionally, in some embodiments of the present invention, the thickness of the first film layer is 200 angstroms to 1000 angstroms, the thickness of the second film layer is 1000 angstroms to 3000 angstroms, and the thickness of the third film layer is 50 angstroms to 200 angstroms.

[0020] Meanwhile, the present invention provides a display panel, which includes the array substrate described in any one embodiment of the present invention.

[0021] The present invention provides an array substrate and a display panel. The array substrate has a first film layer structure added within a first electrode. The first film layer is arranged in contact with the planarization layer, so that the second film layer is arranged spaced apart from the planarization layer. Under high temperature conditions, the first film layer is inert relative to the planarization layer. In this way, during a high-temperature annealing process or a curing process, the first electrode will not react with water vapor in the planarization layer, thereby avoiding the generation of hydrogen ions, and further avoiding the active layer of the thin film transistor being reduced by hydrogen ions, which causes the typical negative drift problem of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0023] Figure 1 A schematic structural diagram of an array substrate provided in an embodiment of the present invention;

[0024] Figure 2 A flow chart of a method for preparing an array substrate provided in an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the fabrication structure of an array substrate provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the specific embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments and / or examples of the present invention. Obviously, the embodiments and / or examples described below are only part of the embodiments and / or examples of the present invention, rather than all the embodiments and / or examples. Based on the embodiments and / or examples in the present invention, all other embodiments and / or examples obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0027] Directional terms used in this disclosure, such as [upper], [lower], [left], [right], [front], [back], [inner], [outer], and [side], are used solely to refer to directions in the accompanying drawings. Therefore, the directional terms used are intended to illustrate and understand the present disclosure, not to limit it. Terms such as "first," "second," and the like are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referenced. Therefore, a feature designated as "first," "second," and the like may explicitly or implicitly include one or more of such features.

[0028] The anode of the existing OLED display panel adopts a laminated structure of aluminum-nickel-copper-lanthanum alloy / tungsten oxide. There are problems such as the aluminum in the aluminum-nickel-copper-lanthanum alloy reacting with water vapor in the planarization layer under high temperature conditions, and the tungsten oxide is easily reduced by water washing and corroded by developer penetration. The present invention provides an array substrate that can solve these problems.

[0029] In one embodiment, see Figure 1 , Figure 1 FIG. 1 shows a schematic structural diagram of an array substrate provided by an embodiment of the present invention. Figure 1 As shown, the array substrate provided by the embodiment of the present invention includes:

[0030] substrate 10;

[0031] The thin film transistor circuit layer 20 is provided on the substrate 10 and includes a thin film transistor 201;

[0032] a planarization layer 30 , disposed on the thin film transistor circuit layer 20 ;

[0033] The first electrode 40 is provided on the planarization layer 30 and is electrically connected to the thin film transistor 201 through a via hole penetrating the planarization layer 30; wherein,

[0034] The first electrode 40 is a stacked structure of a first film layer 41 / a second film layer 42 / a third film layer 43. The first film layer 41 is arranged in contact with the planarization layer 30, and the second film layer 42 is arranged in a spaced relationship from the planarization layer 30. Under high temperature conditions, the first film layer 41 is inert relative to the planarization layer 30.

[0035] In an embodiment of the present invention, a first film layer structure is added within the first electrode. The first film layer is arranged in contact with the planarization layer, so that the second film layer and the planarization layer are spaced apart, and under high temperature conditions, the first film layer is inert relative to the planarization layer. In this way, during a high-temperature annealing process or a curing process, the first electrode will not react with water vapor in the planarization layer, thereby avoiding the generation of hydrogen ions, and further avoiding the active layer of the thin film transistor being reduced by hydrogen ions, which would cause the typical negative drift problem of the thin film transistor.

[0036] When the array substrate is used in a top-emitting OLED display panel, the second film layer 42 is generally made of a metal or alloy with high reflectivity to reflect light emitted by the OLED display panel's luminescent material, thereby improving the luminous efficiency of the OLED display panel. Therefore, in one embodiment, the material of the second film layer 42 is an aluminum alloy, preferably an aluminum-nickel-copper-lanthanum alloy.

[0037] In one embodiment, the thickness of the second film layer 42 is in the range of 1000 angstroms to 3000 angstroms, preferably 1500 angstroms to 2000 angstroms.

[0038] Due to the instability of aluminum alloys, when the aluminum alloy is in direct contact with organic matter and is under high temperature conditions, the aluminum element in the aluminum alloy is very easy to react with the water molecules in the organic matter to produce hydrogen ions. The hydrogen ions diffuse to the thin film transistor circuit layer, causing the active layer of the thin film transistor to be reduced, thereby causing the electrical properties of the thin film transistor to drift negatively. In the array substrate, the planarization layer is usually an organic material. Therefore, the second film layer is not suitable for direct contact with the planarization layer. The embodiment of the present invention provides the first film layer 41 between the second film layer 42 and the planarization layer 30, and the first film layer 41 does not react with the planarization layer 30 under high temperature conditions, thereby isolating the second film layer 42 and the planarization layer 30, avoiding the generation of hydrogen ions and improving the electrical properties of the array substrate.

[0039] In one embodiment, the material of the first film layer 41 includes, but is not limited to, indium tin oxide, indium zinc oxide, metal molybdenum, titanium, nickel, niobium, and alloys of molybdenum, titanium, nickel, and niobium. Any material selection method that satisfies the requirements that the first film layer 41 does not react with the planarization layer 30 under high temperature conditions and simultaneously meets the conductive properties of the first electrode 40 is within the scope of protection of the embodiments of the present invention. Preferably, the material of the first film layer 41 is a molybdenum-titanium-nickel alloy.

[0040] In one embodiment, the thickness of the first film layer 41 is in the range of 200 angstroms to 1000 angstroms, preferably 300 angstroms to 500 angstroms.

[0041] When the array substrate is applied to a top-emitting OLED display panel, and the first electrode 40 serves as the anode of the OLED display panel, the third film layer 43 and the light-emitting material layer of the OLED display panel are connected. During the light-emitting process of the OLED display panel, holes enter the light-emitting material layer from the side of the third film layer 43. The third film layer 43 needs to have a higher work function to achieve a better hole injection effect. Therefore, in one embodiment, the material of the third film layer 43 is indium tin oxide or indium zinc oxide. Furthermore, the third film layer 43 covers the second film layer 42, and the surface of the third film layer 43 facing away from the second film layer 42 is a passivation surface; in this way, in the subsequent development process, the third film layer 43 can protect the second film layer 42 from corrosion by the developer.

[0042] In one embodiment, the thickness of the third film layer 43 is in the range of 50 angstroms to 200 angstroms, preferably 75 angstroms to 150 angstroms.

[0043] Accordingly, the embodiment of the present invention further provides a method for preparing an array substrate, which is used to prepare the array substrate described in the embodiment of the present invention. Figure 2 and Figure 3 , Figure 2FIG2 shows a flow chart of a method for preparing an array substrate provided by an embodiment of the present invention. Figure 3 The schematic diagram of the manufacturing structure of the array substrate provided by the embodiment of the present invention is shown. The manufacturing method includes:

[0044] Step B1: Provide a substrate and prepare a thin film transistor circuit layer on the substrate; for details, please refer to Figure 3 Middle (a).

[0045] Specifically, step B1 includes:

[0046] Providing a substrate 10 and cleaning the substrate 10; the substrate may be an organic substrate or an inorganic substrate, preferably a glass substrate;

[0047] A layer of metal is deposited on the substrate 10 and patterned to serve as a light shielding layer 21 . The material of the light shielding layer 21 includes but is not limited to metals such as molybdenum, titanium, copper, manganese, etc., or alloys thereof.

[0048] Depositing a buffer layer 22 on the substrate 10 and the light shielding layer 21; the buffer layer 22 includes but is not limited to a single layer of silicon oxide, a single layer of silicon nitride, or a multilayer structure of silicon oxide and silicon nitride;

[0049] A layer of metal oxide semiconductor material is deposited on the buffer layer 22 and patterned to form a semiconductor layer 23; the semiconductor material includes but is not limited to metal oxides, such as indium gallium tin oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), etc.;

[0050] Depositing an insulating film on the semiconductor layer 23; the insulating film includes but is not limited to a single layer of silicon oxide, a single layer of silicon nitride, or a multilayer structure of silicon oxide and silicon nitride;

[0051] A layer of metal is deposited on the insulating film and patterned to form a gate layer 25; the material of the gate layer includes but is not limited to metals such as molybdenum, titanium, copper, etc. or alloys thereof;

[0052] Using the gate layer 25 as a self-mask, the insulating film is etched to form a gate insulating layer 24;

[0053] performing plasma treatment on the semiconductor layer 23;

[0054] An interlayer insulating layer 26 is deposited on the gate layer 25, the semiconductor layer 23, and the buffer layer 22, and a first via hole penetrating the interlayer insulating layer 26 and a second via hole penetrating the interlayer insulating layer 26 and the buffer layer 22 are etched by a yellow light process; the interlayer insulating layer 26 includes but is not limited to a single layer of silicon oxide, a single layer of silicon nitride, or a multilayer structure of silicon oxide and silicon nitride;

[0055] A layer of metal is deposited on the interlayer insulating layer 26 and patterned to form a first source-drain electrode layer 27. The first source-drain electrode layer 27 is connected to the semiconductor layer 23 through the first via hole and is connected to the light shielding layer 21 through the second via hole. The material of the first source-drain electrode layer 27 includes but is not limited to metals such as molybdenum, titanium, copper, manganese, etc., or alloys thereof, preferably copper or a copper alloy.

[0056] A passivation layer 28 is deposited on the first source / drain electrode layer 27 and the interlayer insulating layer 26, and a third via hole penetrating the passivation layer 28 is etched by a yellow light process; the passivation layer 28 includes but is not limited to a single layer of silicon oxide, a single layer of silicon nitride, or a multilayer structure of silicon oxide and silicon nitride;

[0057] A layer of metal is deposited on the passivation layer 28 and patterned to form a second source-drain layer 29 , which is connected to the first source-drain layer 27 through the third via. The material of the second source-drain layer 29 includes but is not limited to metal molybdenum, titanium, etc. or alloys thereof.

[0058] Step B2: prepare a planarization layer on the thin film transistor circuit layer; for details, please refer to Figure 3 Middle (b).

[0059] Specifically, the step B2 includes: depositing a planarization layer 30 on the second source and drain electrode layer 29 and the passivation layer 28, and etching a fourth via hole penetrating the planarization layer 30 by a yellow light process; the planarization layer 30 may be a single-layer structure or a two-layer or multi-layer structure;

[0060] Step B3, preparing a first electrode on the planarization layer; the first electrode is a stacked structure of a first film layer / a second film layer / a third film layer, wherein the first film layer is in contact with the planarization layer, and the second film layer is spaced apart from the planarization layer. Under high temperature conditions, the first film layer is inert relative to the planarization layer; for details, please refer to Figure 3 Middle (c).

[0061] Specifically, step B3 includes:

[0062] A first film layer material 41 and a second film layer material 42 are sequentially deposited on the planarization layer 30 using a physical vapor deposition process; the first film layer material 41 includes but is not limited to indium tin oxide, indium zinc oxide, metal molybdenum, titanium, nickel, niobium, an alloy of molybdenum, titanium, nickel, and niobium, preferably an aluminum-nickel-copper-lanthanum alloy; and the second film layer material 42 is an aluminum alloy, preferably an aluminum-nickel-copper-lanthanum alloy;

[0063] oxidizing the second film layer material 42 to form a dense aluminum oxide film on a side of the second film layer material 42 facing away from the first film layer material;

[0064] Depositing a third film layer material 43 on the second film layer material 42, the third film layer material 43 including but not limited to indium tin oxide or indium zinc oxide, preferably indium tin oxide;

[0065] Etching the first film layer material 41, the second film layer material 42, and the third film layer material 43 by a yellow light process;

[0066] A high-temperature process is performed on the surface of the third film layer material 43 to form a dense passivation surface, thereby forming the first electrode 40 .

[0067] Furthermore, embodiments of the present invention further provide a display panel, comprising the array substrate described in any embodiment of the present invention. Because the display panel comprises the array substrate described in any embodiment of the present invention, it possesses the technical features and beneficial effects of the array substrate described in the embodiments of the present invention. For details, please refer to the above embodiments and will not be further described here. The display panel is preferably an OLED display panel.

[0068] In summary, an embodiment of the present invention provides an array substrate and a display panel, wherein a first film layer structure is added within the first electrode, the first film layer is arranged in contact with the planarization layer, so that the second film layer and the planarization layer are spaced apart, and under high temperature conditions, the first film layer is inert relative to the planarization layer. In this way, during a high-temperature annealing process or a curing process, the first electrode will not react with water vapor in the planarization layer, thereby avoiding the generation of hydrogen ions, and further avoiding the active layer of the thin film transistor being reduced by hydrogen ions, which causes the typical negative drift problem of the thin film transistor; by arranging a third film layer on the side of the second film layer away from the first film layer, the third film layer covers the second film layer, and the surface of the third film layer facing away from the second film layer is a passivation surface, so that in a subsequent development process, the third film layer can protect the second film layer from corrosion by the developer.

[0069] The above is a detailed introduction to the array substrate and display panel provided in the embodiments of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, based on the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; a thin film transistor circuit layer, provided on the substrate, comprising thin film transistors; a planarization layer, disposed on the thin film transistor circuit layer; A first electrode is provided on the planarization layer and is electrically connected to the thin film transistor through a via hole penetrating the planarization layer, and the first electrode extends into the via hole of the planarization layer; wherein, The first electrode is a stacked structure of a first film layer / a second film layer / a third film layer, wherein the first film layer is disposed in contact with the planarization layer, and the second film layer is disposed spaced apart from the planarization layer. Under high temperature conditions, the first film layer is inert relative to the planarization layer, so that the first electrode does not react with water vapor in the planarization layer to generate hydrogen ions. The material of the first film layer is a molybdenum-titanium-nickel alloy; the material of the second film layer is an aluminum-nickel-copper-lanthanum alloy; the surface of the third film layer facing away from the second film layer is a passivated surface; The thickness of the second film layer is 1000 angstroms to 3000 angstroms, and the thickness of the third film layer is 50 angstroms to 200 angstroms.

2. The array substrate according to claim 1, wherein: The material of the third film layer is indium tin oxide or indium zinc oxide.

3. The array substrate according to claim 1, wherein: The third film layer covers the second film layer.

4. The array substrate according to claim 1, wherein: The thickness of the first film layer is 200 angstroms to 1000 angstroms.

5. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 4.

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