A layout of a transmission gate circuit and a design method thereof

Abstract

An embodiment of the present application provides a layout and design method for a transmission gate circuit, wherein the method includes: placing multiple PMOS transistors side by side along a first direction, and multiple NMOS transistors corresponding to the multiple PMOS transistors one-to-one and arranged side by side below the multiple PMOS transistors. The source of each PMOS transistor is connected to the source of the corresponding NMOS transistor disposed below it, and the drain of each PMOS transistor is connected to the drain of the corresponding NMOS transistor disposed below it. The gate of each PMOS transistor and the gate of the corresponding NMOS transistor disposed below it are each connected to a different control signal line. The source of each PMOS transistor is connected and a first signal line is arranged along the first direction, and the drain of each NMOS transistor is connected and a second signal line is arranged along the first direction. The P-type substrates of the multiple NMOS transistors are connected to a ground line, and the ground lines are arranged in a closed and symmetrical manner. The layout design method provided in the present application achieves matching of the parasitic capacitances generated by the first signal line and the second signal line on the ground line, thereby reducing the impact of the parasitic capacitances on circuit performance.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of layout design, and specifically to a layout of a transmission gate circuit and a design method thereof. Background Art

[0002] In analog integrated circuit design, in addition to circuit design and simulation, layout design is also crucial. Layout design establishes the connection between circuit design and chip design. The layout embodies the circuit design, allowing factories to create masks based on the layout. The mask's shape, combined with the process flow, enables chip manufacturing.

[0003] When drawing the layout of the transmission gate circuit in the prior art, Figure 1 As shown, multiple PMOS transistors 21 are placed side by side, and multiple NMOS transistors 22 are placed correspondingly and side by side below the multiple PMOS transistors 21. A power line 23 is arranged above the multiple PMOS transistors 21, and a ground line 24 is arranged below the multiple NMOS transistors 22. A first signal line 25 and a second signal line 26 are arranged in parallel between the multiple PMOS transistors 21 and the multiple NMOS transistors 22.

[0004] The drawback of the prior art is that the first signal line 25 and the second signal line 26 cannot match the parasitic capacitance generated by the ground line 24 , thereby affecting circuit performance indicators, such as common mode rejection ratio. Summary of the Invention

[0005] In view of the above problems, an embodiment of the present application provides a layout of a transmission gate circuit and a design method thereof, which overcomes or at least partially solves the problem that the first signal line and the second signal line cannot match the parasitic capacitance generated by the ground line.

[0006] According to one aspect of an embodiment of the present application, a layout design method for a transmission gate circuit is provided, comprising: placing a plurality of PMOS tubes side by side along a first direction, and a plurality of NMOS tubes corresponding to the plurality of PMOS tubes one by one and arranged side by side below the plurality of PMOS tubes. The source of each PMOS tube is connected to the source of the corresponding NMOS tube arranged below it, and the drain of each PMOS tube is connected to the drain of the corresponding NMOS tube arranged below it. The gate of each PMOS tube and the gate of the corresponding NMOS tube arranged below it are both connected to different control signal lines. The source of each PMOS tube is connected and a first signal line is arranged along the first direction, and the drain of each NMOS tube is connected and a second signal line is arranged along the first direction. The P-type substrates of the plurality of NMOS tubes are connected to a ground line, and the ground lines are arranged in a closed and symmetrical manner.

[0007] An embodiment of the present application provides a layout design method for a transmission gate circuit. By arranging the ground line in a closed, symmetrical pattern, the first and second signal lines are equidistant from the ground line. Furthermore, the first and second signal lines are symmetrically distributed relative to the ground line. This ensures that the parasitic capacitances generated by the first and second signal lines on the ground line are matched, minimizing the impact of the parasitic capacitances on circuit performance.

[0008] In an optional manner, the method further includes: connecting the N-type substrates of the plurality of PMOS tubes to a power line, wherein the power line is arranged along a second direction, and the second direction is perpendicular to the first direction.

[0009] By arranging the power line perpendicular to the first signal line and the second signal line, the first signal line and the second signal line are symmetrically distributed relative to the power line. Therefore, the parasitic capacitance generated by the first signal line and the second signal line to the power line is matched, further reducing the impact of the parasitic capacitance on the circuit performance.

[0010] In an optional manner, connecting the N-type substrates of the plurality of PMOS tubes to the power line includes: distributing the N-type substrates of the plurality of PMOS tubes in a centralized manner and connecting the N-type substrates to the power line.

[0011] By centrally distributing the N-type substrates of the plurality of PMOS tubes, a straight line perpendicular to the first direction can be formed after the power line is connected to the N-type substrates of all the PMOS tubes.

[0012] In an optional manner, connecting the P-type substrates of the plurality of NMOS transistors to the ground line includes: distributing the P-type substrates of the plurality of NMOS transistors at the edge and connecting them to the ground line.

[0013] By distributing the P-type substrates of the plurality of NMOS transistors at the edge, the ground wire can be connected to the P-type substrates of all the NMOS transistors to form a closed and symmetrical arrangement.

[0014] In an optional manner, multiple PMOS tubes are placed side by side along a first direction, and multiple NMOS tubes correspond one-to-one to the multiple PMOS tubes and are placed side by side below the multiple PMOS tubes, including: two adjacent PMOS tubes share a source, and two adjacent NMOS tubes share a source; or, two adjacent PMOS tubes share a drain, and two adjacent NMOS tubes share a drain.

[0015] By sharing the source or drain, the chip area can be reduced, the cost can be lowered, and the impact of parasitic capacitance on the circuit can be reduced.

[0016] In an optional manner, the source of each PMOS tube and the source of the corresponding NMOS tube arranged thereunder are connected on the first metal layer, the drain of each PMOS tube and the drain of the corresponding NMOS tube arranged thereunder are connected on the first metal layer, and the first signal line and the second signal line are arranged on the second metal layer.

[0017] By arranging the first signal line and the second signal line on the second metal layer, the first signal line and the second signal line can avoid intersecting with wiring on the first metal layer, thereby reducing interference between wirings.

[0018] In an optional manner, the ground line is arranged in the first metal layer, and the power line is arranged in the first metal layer and the third metal layer, wherein the second metal layer is higher than the third metal layer, and the third metal layer is higher than the first metal layer.

[0019] By placing the ground line on the first metal layer, it can share a metal layer with the wiring connecting the PMOS and NMOS transistor sources and drains, thereby reducing the size of the chip. By placing the power line on the first and third metal layers, the power line can be led out on the third metal layer, avoiding intersection with the first and second signal lines on the second metal layer.

[0020] According to another aspect of an embodiment of the present application, a layout for a transmission gate circuit is provided, comprising: a plurality of PMOS transistors arranged side by side along a first direction; a plurality of NMOS transistors corresponding one-to-one to the plurality of PMOS transistors and arranged side by side below the plurality of PMOS transistors. The source of each PMOS transistor is connected to the source of the corresponding NMOS transistor arranged below it, the drain of each PMOS transistor is connected to the drain of the corresponding NMOS transistor arranged below it, and the gate of each PMOS transistor is connected to a different control signal line as is the gate of the corresponding NMOS transistor arranged below it. The source of each PMOS transistor is connected to a first signal line arranged along the first direction, and the drain of each NMOS transistor is connected to a second signal line arranged along the first direction. The N-type substrates of the plurality of PMOS transistors are connected to a power line, which is arranged along a second direction perpendicular to the first direction. The P-type substrates of the plurality of NMOS transistors are connected to a ground line, and the ground lines are arranged in a closed, symmetrical manner.

[0021] By arranging the ground lines in a closed, symmetrical pattern, the parasitic capacitances generated by the first and second signal lines on the ground lines are matched. By arranging the power lines in a second direction perpendicular to the first, the parasitic capacitances generated by the first and second signal lines on the power lines are matched. This significantly reduces the impact of parasitic capacitance on circuit performance.

[0022] In an optional manner, the N-type substrates of the plurality of PMOS tubes are connected to the power line, specifically including: the N-type substrates of the plurality of PMOS tubes are concentratedly distributed and connected to the power line.

[0023] In an optional manner, the P-type substrates of the plurality of NMOS transistors are connected to the ground line, specifically including: the P-type substrates of the plurality of NMOS transistors are distributed at the edge and connected to the ground line.

[0024] By distributing the N-type substrates of multiple PMOS tubes in a concentrated manner, a straight line perpendicular to the first direction can be formed after the power line is connected to the N-type substrates of all PMOS tubes; and by distributing the P-type substrates of multiple NMOS tubes at the edge, a closed and symmetrical arrangement can be formed after the ground line is connected to the P-type substrates of all NMOS tubes.

[0025] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 The diagram is a layout of a transmission gate circuit in the prior art.

[0028] Figure 2 A flow chart of a method for layout design of a transmission gate circuit provided in an embodiment of the present application.

[0029] Figure 3 A layout of a transmission gate circuit provided in an embodiment of the present application.

[0030] Figure 4 In the embodiment of this application Figure 3 A simplified schematic diagram of the provided layout. DETAILED DESCRIPTION

[0031] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] The terms "comprises", "comprising" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover but not exclude other contents. The word "a" or "an" does not exclude the presence of a plurality.

[0034] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it necessarily refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] The directional words appearing in the following description are all directions shown in the drawings, and do not limit the specific structure of the layout of a transmission gate circuit and its design method of the present application. For example, in the description of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., which indicate directions or positional relationships, are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be understood as limiting the present application.

[0036] Furthermore, the expressions indicating directions such as the X direction, the Y direction, and the Z direction used to illustrate the operation and construction of the components of the layout of a transmission gate circuit and the design method thereof of this embodiment are not absolute but relative, and although these indications are appropriate when the components of the layout of a transmission gate circuit and the design method thereof are in the positions shown in the figures, when these positions are changed, these directions should be interpreted differently to correspond to the changes.

[0037] In addition, the terms "first", "second", etc. in the description and claims of this application or the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0038] In the description of this application, unless otherwise specified, "plurality" means more than two (including two), and similarly, "multiple groups" means more than two (including two).

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, "connected" or "connected" in a mechanical structure can refer to a physical connection. For example, a physical connection can be a fixed connection, such as a fixed connection via a fixing member, such as a screw, bolt, or other fixing member. A physical connection can also be a detachable connection, such as a mutual snap-fit ​​connection. A physical connection can also be an integral connection, such as a connection formed by welding, bonding, or integral molding. "Connected" or "connected" in a circuit structure can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate element, as long as the circuit is interconnected. It can also refer to internal communication between two elements. A signal connection can refer to a signal connection through a circuit or a signal connection through a media medium, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application.

[0040] The present invention provides a method for designing a layout of a transmission gate circuit. Figure 2 , Figure 2 A flow chart of a method for layout design of a transmission gate circuit provided in an embodiment of the present application.

[0041] like Figure 2 As shown, a layout design method for a transmission gate circuit provided in an embodiment of the present application includes the following steps 101 to 105:

[0042] Step 101 : placing a plurality of PMOS transistors side by side along a first direction, with a plurality of NMOS transistors corresponding to the plurality of PMOS transistors one by one and being placed side by side below the plurality of PMOS transistors.

[0043] For example, there can be 3 PMOS transistors and 3 NMOS transistors. Figure 3 The three PMOS transistors are the first PMOS transistor 01, the second PMOS transistor 02, and the third PMOS transistor 03. The three NMOS transistors are the first NMOS transistor 04, the second NMOS transistor 05, and the third NMOS transistor 06. The first PMOS transistor 01, the second PMOS transistor 02, and the third PMOS transistor 03 are placed side by side along a first direction. The first NMOS transistor 04, the second NMOS transistor 05, and the third NMOS transistor 06 correspond to the first PMOS transistor 01, the second PMOS transistor 02, and the third PMOS transistor 03, respectively, and are placed side by side below the multiple PMOS transistors.

[0044] In step 102, the source of each PMOS transistor is connected to the source of the corresponding NMOS transistor disposed thereunder, the drain of each PMOS transistor is connected to the drain of the corresponding NMOS transistor disposed thereunder, and the gate of each PMOS transistor and the gate of the corresponding NMOS transistor disposed thereunder are both connected to different control signal lines.

[0045] For example, the different control signal lines can be clock signal lines, and an NMOS transistor and a PMOS transistor located above and below can be connected to opposite clock signal lines. The source of each PMOS transistor is connected to the source of the corresponding NMOS transistor located below it, and the drain of each PMOS transistor is connected to the drain of the corresponding NMOS transistor located below it, so that the NMOS transistor and the PMOS transistor located above and below form a transmission gate switch.

[0046] For example, Figure 3 The number of PMOS tubes and NMOS tubes shown is 3.

[0047] The source of the first PMOS transistor 01 is connected to the source of the first NMOS transistor 04 , the source of the second PMOS transistor 02 is connected to the source of the second NMOS transistor 05 , and the source of the third PMOS transistor 03 is connected to the source of the third NMOS transistor 06 .

[0048] The drain of the first PMOS transistor 01 is connected to the drain of the first NMOS transistor 04 , the drain of the second PMOS transistor 02 is connected to the drain of the second NMOS transistor 05 , and the drain of the third PMOS transistor 03 is connected to the drain of the third NMOS transistor 06 .

[0049] The gate of the first PMOS transistor 01 and the gate of the first NMOS transistor 04 are respectively connected to the opposite first pair of clock signal lines, the gate of the second PMOS transistor 02 and the gate of the second NMOS transistor 05 are respectively connected to the opposite second pair of clock signal lines, and the gate of the third PMOS transistor 03 and the gate of the third NMOS transistor 06 are respectively connected to the opposite third pair of clock signal lines.

[0050] The first PMOS transistor 01 and the first NMOS transistor 04 constitute a first transmission gate switch, the second PMOS transistor 02 and the second NMOS transistor 05 constitute a second transmission gate switch, and the third PMOS transistor 03 and the third NMOS transistor 06 constitute a third transmission gate switch.

[0051] Step 103: Connect the source of each PMOS transistor and arrange a first signal line along a first direction.

[0052] Step 104 : Connect the drains of each NMOS transistor and arrange a second signal line along the first direction.

[0053] The first signal line may be an input signal line of a transmission gate circuit provided in an embodiment of the present application, and correspondingly, the second signal line may be an output signal line of a transmission gate circuit provided in an embodiment of the present application. Alternatively, the second signal line may be an input signal line of a transmission gate circuit provided in an embodiment of the present application, and correspondingly, the first signal line may be an output signal line of a transmission gate circuit provided in an embodiment of the present application.

[0054] Exemplary, reference Figure 3 The sources of the first PMOS transistor 01, the second PMOS transistor 02, and the third PMOS transistor 03 are connected, and a first signal line 07 is arranged along the first direction. The first signal line 07 is an input signal line. The drains of the first NMOS transistor 04, the second NMOS transistor 05, and the third NMOS transistor 06 are connected, and a second signal line 08 is arranged along the first direction. The second signal line 08 is an output signal line.

[0055] In one possible embodiment, signal lines can also be grouped into multiple groups. For example, the sources of the first PMOS transistor 01 and the first NMOS transistor 04 are connected, and a first signal line is arranged along a first direction. The drains of the first PMOS transistor 01 and the first NMOS transistor 04 are connected, and a second signal line is arranged along the first direction. The first signal line and the second signal line form a group of input / output signal lines. The sources of the second PMOS transistor 02 and the second NMOS transistor 05 are connected, and a third signal line is arranged along the first direction. The drains of the second PMOS transistor 02 and the second NMOS transistor 05 are connected, and a fourth signal line is arranged along the first direction. The third signal line and the fourth signal line form a group of input / output signal lines. The sources of the third PMOS transistor 03 and the third NMOS transistor 06 are connected, and a fifth signal line is arranged along the first direction. The drains of the third PMOS transistor 03 and the third NMOS transistor 06 are connected, and a sixth signal line is arranged along the first direction. The fifth signal line and the sixth signal line form a group of input / output signal lines.

[0056] Step 105 : Connect the P-type substrates of the multiple NMOS transistors to ground wires, with the ground wires being arranged in a closed and symmetrical manner.

[0057] For example, Figure 3 As shown, the P-type substrate of the first NMOS transistor 04 , the P-type substrate of the second NMOS transistor 05 , and the P-type substrate of the third NMOS transistor 06 are connected to the ground line 09 , and the ground line 09 is arranged in a square shape.

[0058] In actual use, the P-type substrates of the plurality of NMOS transistors are connected to the ground line, which includes: distributing the P-type substrates of the plurality of NMOS transistors at the edge and connecting them to the ground line.

[0059] Figure 4 In the embodiment of this application Figure 3 A simplified schematic diagram of the provided layout is provided. Figure 4 The P-type substrates 10 of the three NMOS tubes are distributed at the edge and connected to the ground line 09.

[0060] exist Figure 4 In the embodiment, the P-type substrates 10 of the three NMOS transistors are distributed at the edge, so that after the ground line 09 is connected to the P-type substrates 10 of all the NMOS transistors, a closed symmetrical arrangement can be formed.

[0061] An embodiment of the present application provides a layout design method for a transmission gate circuit. By arranging the ground line in a closed, symmetrical pattern, the first and second signal lines are equidistant from the ground line. Furthermore, the first and second signal lines are symmetrically distributed relative to the ground line. This ensures that the parasitic capacitances generated by the first and second signal lines on the ground line are matched, minimizing the impact of the parasitic capacitances on circuit performance.

[0062] In one possible embodiment, based on the above embodiment, Figure 3 A metal layer 11 may be arranged around the first signal line 07 and the second signal line 08 to reduce interference with the first signal line 07 and the second signal line 08 caused by other signal lines in the circuit.

[0063] In one embodiment, considering that the parasitic capacitances generated by the first signal line and the second signal line on the power line cannot be matched, the performance of the circuit will be affected. Based on the above embodiment, the layout design method of a transmission gate circuit provided in this embodiment may further include:

[0064] The N-type substrates of the plurality of PMOS tubes are connected to a power line, and the power line is arranged along a second direction, which is perpendicular to the first direction.

[0065] For example, Figure 3 As shown, the N-type substrates of the first PMOS transistor 01 , the second PMOS transistor 02 and the third PMOS transistor 03 are connected to the power line 12 . The power line 12 is arranged along a second direction perpendicular to the first direction.

[0066] By arranging the power line 12 perpendicular to the first signal line 07 and the second signal line 08, the first signal line 07 and the second signal line 08 are symmetrically distributed relative to the power line 12. Therefore, the parasitic capacitances generated by the first signal line 07 and the second signal line 08 on the power line 12 are matched, further reducing the impact of the parasitic capacitance on the circuit performance.

[0067] In practical applications, connecting the N-type substrates of the plurality of PMOS tubes to the power line includes: distributing the N-type substrates of the plurality of PMOS tubes in a centralized manner and connecting the N-type substrates to the power line.

[0068] refer to Figure 4 The N-type substrates 13 of the three PMOS tubes are centrally distributed and connected to the power line 12.

[0069] exist Figure 4 In the embodiment, the N-type substrates 13 of the three PMOS transistors are centrally distributed so that the power line 12 is connected to the N-type substrates 13 of all the PMOS transistors to form a straight line perpendicular to the first direction.

[0070] In one embodiment, considering issues such as chip volume and chip manufacturing cost, based on the above embodiment, multiple PMOS transistors are placed side by side along a first direction, and multiple NMOS transistors correspond to the multiple PMOS transistors one by one and are placed side by side below the multiple PMOS transistors, including: two adjacent PMOS transistors share a source electrode, and two adjacent NMOS transistors share a source electrode; or two adjacent PMOS transistors share a drain electrode, and two adjacent NMOS transistors share a drain electrode.

[0071] For example, the present application embodiment takes two MOS tubes sharing a drain as an example for explanation. Figure 4 The source of the first PMOS transistor 01 is S1, the source of the second PMOS transistor 02 is S2, and the source of the third PMOS transistor 03 is S3. The drain of the third PMOS transistor 03 is D1, and the drain shared by the first and second PMOS transistors 01 and 02 is D2.

[0072] The source of the first NMOS transistor 04 is S4, the source of the second NMOS transistor 05 is S5, and the source of the third NMOS transistor 06 is S6. The drain of the third NMOS transistor 06 is D3, and the drain shared by the first NMOS transistor 04 and the second NMOS transistor 05 is D4.

[0073] By sharing the source or drain, the chip area can be reduced, the cost can be lowered, and the impact of parasitic capacitance on the circuit can be reduced.

[0074] In one embodiment, considering that interference between wirings can be reduced, based on the above embodiment, a layout design method for a transmission gate circuit provided in this embodiment may further include:

[0075] The source of each PMOS tube is connected to the source of the corresponding NMOS tube arranged below it on the first metal layer, the drain of each PMOS tube is connected to the drain of the corresponding NMOS tube arranged below it on the first metal layer, and the first signal line and the second signal line are arranged on the second metal layer.

[0076] The ground line is arranged in the first metal layer, and the power line is arranged in the first metal layer and the third metal layer, wherein the second metal layer is higher than the third metal layer, and the third metal layer is higher than the first metal layer.

[0077] Specifically, the source of each PMOS transistor and the source of the corresponding NMOS transistor disposed thereunder can be connected in the first metal layer via a first contact hole, and the drain of each PMOS transistor and the drain of the corresponding NMOS transistor disposed thereunder can be connected in the first metal layer via a second contact hole. The first metal layer and the second metal layer can be connected via a first through hole, and the second metal layer and the third metal layer can be connected via a second through hole. Multiple first contact holes, multiple second contact holes, multiple first through holes, and multiple second through holes can be provided.

[0078] By arranging the first and second signal lines on the second metal layer, they can avoid intersecting with wiring on the first metal layer, reducing interference between wiring. By arranging the ground line on the first metal layer, it can share a metal layer with the wiring connecting the PMOS tube source and NMOS tube source, as well as the wiring connecting the PMOS tube drain and NMOS tube drain, reducing the size of the chip. By arranging the power line on the first metal layer and the third metal layer, the power line can be led out of the third metal layer, avoiding intersection with the first and second signal lines on the second metal layer.

[0079] In another embodiment of the present application, a layout of a transmission gate circuit is provided, as described above. Figure 3 As shown, the above-mentioned layout design method of a transmission gate circuit is applied to Figure 3 The layout shown.

[0080] refer to Figure 3 、 Figure 4 The layout of a transmission gate circuit provided in an embodiment of the present application includes: multiple PMOS tubes are placed side by side along a first direction, and multiple NMOS tubes correspond one-to-one to the multiple PMOS tubes and are placed side by side below the multiple PMOS tubes. The source of each PMOS tube is connected to the source of the corresponding NMOS tube arranged below it, the drain of each PMOS tube is connected to the drain of the corresponding NMOS tube arranged below it, and the gate of each PMOS tube and the gate of the corresponding NMOS tube arranged below it are both connected to different control signal lines. The source of each PMOS tube is connected and a first signal line 07 is arranged along the first direction, and the drain of each NMOS tube is connected and a second signal line 08 is arranged along the first direction. The N-type substrates 13 of the multiple PMOS tubes are connected to a power line 12, which is arranged along a second direction, the second direction being perpendicular to the first direction. The P-type substrates 10 of the multiple NMOS tubes are connected to a ground line 09, and the ground line 09 is arranged in a closed and symmetrical manner.

[0081] By arranging the ground line 09 in a closed, symmetrical pattern, the parasitic capacitances generated by the first signal line 07 and the second signal line 08 on the ground line 09 are matched. The power line 12 is arranged in a second direction perpendicular to the first direction, thereby matching the parasitic capacitances generated by the first signal line 07 and the second signal line 08 on the power line 12. This significantly reduces the impact of parasitic capacitance on circuit performance.

[0082] In practical applications, reference Figure 4 , the N-type substrates 13 of the multiple PMOS tubes are connected to the power line 12 , specifically including: the N-type substrates 13 of the multiple PMOS tubes are concentratedly distributed and connected to the power line 12 .

[0083] In practical applications, reference Figure 4, the P-type substrates 10 of the multiple NMOS tubes are connected to the ground line 09 , specifically including: the P-type substrates 10 of the multiple NMOS tubes are distributed at the edge and connected to the ground line 09 .

[0084] By distributing the N-type substrates 13 of multiple PMOS tubes in a concentrated manner, the power line 12 can be connected to the N-type substrates 13 of all PMOS tubes to form a straight line perpendicular to the first direction; by distributing the P-type substrates 10 of multiple NMOS tubes at the edge, the ground line 09 can be connected to the P-type substrates 10 of all NMOS tubes to form a closed and symmetrical arrangement.

[0085] This embodiment is an embodiment corresponding to a layout design method for a transmission gate circuit in any of the above embodiments. The details described in the layout design method for a transmission gate circuit in any of the above embodiments are still applicable to this embodiment and will not be repeated here.

[0086] Those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0087] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A layout design method for a transmission gate circuit, characterized in that: The method comprises: Placing a plurality of PMOS tubes side by side along a first direction, and a plurality of NMOS tubes corresponding to the plurality of PMOS tubes one by one and arranged side by side below the plurality of PMOS tubes; The source of each PMOS transistor is connected to the source of the corresponding NMOS transistor disposed thereunder, the drain of each PMOS transistor is connected to the drain of the corresponding NMOS transistor disposed thereunder, and the gate of each PMOS transistor and the gate of the corresponding NMOS transistor disposed thereunder are both connected to different control signal lines; Connecting the source electrodes of each of the PMOS transistors and arranging a first signal line along a first direction; Connecting the drain of each of the NMOS transistors and arranging a second signal line along the first direction; The P-type substrates of the multiple NMOS transistors are connected to a ground line, the ground line is arranged in a closed symmetrical manner, and the first signal line and the second signal line are symmetrically distributed relative to the ground line, so that the first signal line and the second signal line are at equal distances from the ground line.

2. The method according to claim 1, characterized in that The method further includes: connecting the N-type substrates of the plurality of PMOS transistors to a power line, wherein the power line is arranged along a second direction, and the second direction is perpendicular to the first direction.

3. The method according to claim 2, characterized in that The step of connecting the N-type substrates of the plurality of PMOS tubes to a power line includes: The N-type substrates of the plurality of PMOS tubes are distributed centrally and connected to the power line.

4. The method according to claim 1, wherein Connecting the P-type substrates of the plurality of NMOS transistors to a ground line includes: The P-type substrates of the plurality of NMOS transistors are distributed at the edges and connected to the ground line.

5. The method according to claim 1, characterized in that The method of placing the plurality of PMOS transistors side by side along a first direction, and the plurality of NMOS transistors corresponding to the plurality of PMOS transistors one by one and placed side by side below the plurality of PMOS transistors, comprises: The two adjacent PMOS transistors share the source electrode, and the two adjacent NMOS transistors share the source electrode; Alternatively, two adjacent PMOS transistors share the drain, and two adjacent NMOS transistors share the drain.

6. The method according to claim 2 or 3, characterized in that The method also includes: the source of each PMOS tube and the source of the corresponding NMOS tube arranged thereunder are connected on a first metal layer, the drain of each PMOS tube and the drain of the corresponding NMOS tube arranged thereunder are connected on the first metal layer, and the first signal line and the second signal line are arranged on a second metal layer.

7. The method according to claim 6, characterized in that The method further includes: arranging the ground line in the first metal layer, and arranging the power line in the first metal layer and a third metal layer, wherein the second metal layer is higher than the third metal layer, and the third metal layer is higher than the first metal layer.

8. A layout of a transmission gate circuit, characterized in that: The layout includes: A plurality of PMOS transistors are arranged side by side along a first direction, and a plurality of NMOS transistors correspond one-to-one to the plurality of PMOS transistors and are arranged side by side below the plurality of PMOS transistors. The source of each PMOS transistor is connected to the source of the corresponding NMOS transistor arranged below it, the drain of each PMOS transistor is connected to the drain of the corresponding NMOS transistor arranged below it, and the gate of each PMOS transistor and the gate of the corresponding NMOS transistor arranged below it are connected to different control signal lines. The source electrodes of each of the PMOS transistors are connected and a first signal line is arranged along a first direction; The drain electrodes of each of the NMOS transistors are connected and a second signal line is arranged along the first direction; The N-type substrates of the plurality of PMOS transistors are connected to a power line, and the power line is arranged along a second direction, and the second direction is perpendicular to the first direction; The P-type substrates of the multiple NMOS transistors are connected to a ground line, which is arranged in a closed and symmetrical manner. The first signal line and the second signal line are symmetrically distributed relative to the ground line, so that the first signal line and the second signal line are at equal distances from the ground line.

9. The layout according to claim 8, characterized in that The N-type substrates of the plurality of PMOS tubes are connected to the power line, specifically comprising: The N-type substrates of the plurality of PMOS tubes are distributed centrally and connected to the power line.

10. The layout according to claim 8, wherein: The P-type substrates of the plurality of NMOS transistors are connected to the ground line, specifically comprising: The P-type substrates of the plurality of NMOS transistors are distributed at the edge and connected to the ground line.

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