Semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device that can be manufactured well. The semiconductor memory device according to an embodiment of the present invention includes a substrate having a first region and a second region arranged in a first direction. The first region includes: a plurality of first word line layers stacked in a second direction; a first semiconductor layer extending in the second direction and having an outer peripheral surface facing the plurality of first word line layers; and a first charge storage film provided between the plurality of first word line layers and the first semiconductor layer. The second region includes: a part of the plurality of first word line layers stacked in the second direction; a plurality of first insulating layers separated from the plurality of first word line layers in a third direction and stacked in the second direction; a first contact extending in the second direction and having an outer peripheral surface facing the plurality of first insulating layers; a second semiconductor layer provided between the plurality of first word line layers and the plurality of first insulating layers and extending in the first direction and the second direction; and a second charge storage film provided between the plurality of first insulating layers and the second semiconductor layer.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2021-36035 (filing date: March 8, 2021). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device is known to include: a semiconductor substrate; a plurality of conductive layers laminated in a direction intersecting the surface of the semiconductor substrate; a semiconductor layer extending in a direction intersecting the surface of the semiconductor substrate and facing the plurality of conductive layers; and a gate insulating film provided between the conductive layer and the semiconductor layer. Summary of the Invention

[0005] The embodiment provides a high-quality semiconductor memory device.

[0006] A semiconductor memory device according to an embodiment includes a substrate having a first region and a second region arranged in a first direction. The first region includes: a plurality of first word line layers laminated in a second direction intersecting the surface of the substrate; a first semiconductor layer extending in the second direction and having an outer peripheral surface facing the plurality of first word line layers; and a first charge storage film provided between the plurality of first word line layers and the first semiconductor layer. The second region includes: a part of the plurality of first word line layers laminated in the second direction; a plurality of first insulating layers separated from the plurality of first word line layers in a third direction intersecting the first direction and the second direction and laminated in the second direction; a first contact extending in the second direction and having an outer peripheral surface facing the plurality of first insulating layers; a second semiconductor layer provided between the plurality of first word line layers and the plurality of first insulating layers and extending in the first direction and the second direction; and a second charge storage film provided between the plurality of first insulating layers and the second semiconductor layer.

[0007] In addition, a plurality of second word line layers farther from the substrate than the plurality of first word line layers may also be provided. The first semiconductor layer includes: a first portion extending in the second direction and facing the plurality of first word line layers; a second portion extending in the second direction and facing the plurality of second word line layers; and a third portion connecting the first portion and the second portion. The width of the third portion in the third direction is greater than the widths of the first portion and the second portion in the third direction. The second semiconductor layer includes: a fourth portion extending in the second direction and facing the plurality of first word line layers; a fifth portion extending in the second direction and facing the plurality of second word line layers; and a sixth portion connecting the fourth portion and the fifth portion. The width of the sixth portion in the third direction is greater than the widths of the fourth portion and the fifth portion in the third direction.

[0008] In addition, if the position in the second direction of one of the plurality of first word line layers is set as the first position, the width in the third direction of the first position of the first semiconductor layer is set as the first width, and the width in the third direction of the first position of the second semiconductor layer is set as the second width, it is desirable that the second width is greater than 0.5 times the first width and less than 2.0 times the first width.

[0009] In addition, a first wiring electrically connected to the second semiconductor layer may also be provided.

[0010] A semiconductor memory device according to an embodiment includes a substrate having a first region and a second region arranged in a first direction. The first region includes: a plurality of first word line layers stacked in a second direction intersecting the surface of the substrate; a first semiconductor layer extending in the second direction and having an outer peripheral surface facing the plurality of first word line layers; and a first charge storage film provided between the plurality of first word line layers and the first semiconductor layer. The second region includes: a part of the plurality of first word line layers stacked in the second direction; a plurality of first insulating layers stacked in the second direction separated from the plurality of first word line layers in a third direction intersecting the first direction and the second direction; a first contact extending in the second direction and having an outer peripheral surface facing the plurality of first insulating layers; a first conductive layer provided between the plurality of first word line layers and the plurality of first insulating layers and extending in the first direction and the second direction; a second insulating layer provided between the first conductive layer and the plurality of first word line layers; and a third insulating layer provided between the first conductive layer and the plurality of first insulating layers.

[0011] According to the embodiment, a high-quality semiconductor memory device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic top view of a semiconductor memory device according to a first embodiment.

[0013] Figure 2 is Figure 1 a schematic enlarged cross-sectional view of the portion shown by A in

[0014] Figure 3 is a schematic cross-sectional view taken along line B-B' of the structure shown in Figure 2 and viewed in the direction of the arrow.

[0015] Figure 4 is Figure 3 a schematic enlarged view of the portion shown by C in

[0016] Figure 5 is a schematic cross-sectional view taken along line D-D' of the structure shown in Figure 2 and viewed in the direction of the arrow.

[0017] Figure 6 is Figure 5 a schematic enlarged view of the portion shown as E in

[0018] Figure 7 is a schematic cross-sectional view taken along the line F-F' Figure 2 of the structure shown, and viewed in the direction of the arrow.

[0019] Figures 8 to 24 is a schematic Y-Z cross-sectional view showing a method of manufacturing a semiconductor memory device according to the first embodiment.

[0020] Figure 25 is a Y-Z cross-sectional view of a portion including the insulating layer 200' and the inter-block structure 140 of the comparative example.

[0021] Figure 26 is a cross-sectional view showing the structure 200a of the second embodiment, and is a schematic cross-sectional view of a portion of the second embodiment corresponding to the portion Figure 5 shown in the first embodiment.

[0022] Figure 27 is a cross-sectional view showing the support member 400a of the second embodiment, and is a schematic cross-sectional view of a portion of the second embodiment corresponding to the portion Figure 7 shown in the first embodiment.

[0023] Figures 28 to 40 is a schematic Y-Z cross-sectional view showing a method of manufacturing a semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0024] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. In addition, the following embodiments are merely examples and are not intended to limit the present invention.

[0025] In addition, in the present specification, a specific direction parallel to the surface of the semiconductor substrate is referred to as the X direction, a direction parallel to the surface of the semiconductor substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the surface of the semiconductor substrate is referred to as the Z direction.

[0026] In addition, in the present specification, a direction along a specific plane is sometimes referred to as the first direction, a direction intersecting the first direction along the specific plane is referred to as the second direction, and a direction intersecting the specific plane is referred to as the third direction. The first direction, the second direction, and the third direction may or may not correspond to any of the X direction, the Y direction, and the Z direction.

[0027] In addition, in this specification, expressions such as "upper" or "lower" are based on the semiconductor substrate. For example, the direction away from the semiconductor substrate along the Z direction is called upper, and the direction approaching the semiconductor substrate along the Z direction is called lower. In addition, when referring to the lower surface or lower end portion of a certain component, it means the surface or end portion on the semiconductor substrate side of the component, and when referring to the upper surface or upper end portion, it means the surface or end portion on the side opposite to the semiconductor substrate of the component. In addition, a surface intersecting the X direction or Y direction may also be called a side surface or the like.

[0028] In addition, in this specification, when it is expressed that the first component is "electrically connected" to the second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wirings, semiconductor components, transistors, or the like. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is "electrically connected" to the third transistor.

[0029] In addition, in this specification, when it is expressed that the first component is "connected between" the second component and the third component, it means that the first component, the second component, and the third component are connected in series, and the first component is provided in the current path of the second component and the third component.

[0030] In addition, in this specification, when it is expressed that a circuit or the like "conducts" two wirings or the like, for example, it sometimes means that the circuit or the like includes transistors or the like, the transistors or the like are provided in the current path between the two wirings, and the transistors or the like are in the on state.

[0031] [First Embodiment]

[0032] Hereinafter, with reference to the drawings, the configuration of the semiconductor memory device according to the first embodiment will be described. In addition, the following drawings are schematic, and some components may be omitted for convenience of explanation.

[0033] [Structure]

[0034] Figure 1 is a schematic top view of the semiconductor memory device according to the first embodiment. Figure 2 is Figure 1 A schematic enlarged cross-sectional view of the portion shown in A, showing the configuration in the memory cell array layer. Figure 3 is a cross-section taken along line B-B' Figure 2 The structure shown, and a schematic cross-sectional view observed in the direction of the arrow. Figure 4 is Figure 3 A schematic enlarged view of the portion shown in C. Figure 5 is a cross-section taken along line D-D' Figure 2 The structure shown, and a schematic cross-sectional view observed in the direction of the arrow.Figure 6 yes Figure 5 E is a schematic enlarged view of the portion shown. Figure 7 Cut along the FF′ line Figure 2 The structure shown is a schematic cross-sectional view viewed along the direction of the arrow.

[0035] The semiconductor memory device of the first embodiment is, for example, Figure 1 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 is, for example, a semiconductor substrate including P-type silicon (Si) containing P-type impurities such as boron (B). In the example shown in the figure, four memory cell array regions R arranged in the X direction and the Y direction are provided on the semiconductor substrate 100. MCA In addition, the memory cell array region R MCA A plurality of memory hole regions R arranged in the X direction are provided. MH ( Figure 2 ), and arranged in the memory hole area R MH Multiple contacts between the connection area R 300 ( Figure 2 ). In addition, a peripheral region R is provided at the end of the semiconductor substrate 100 in the Y direction. P . Surrounding area R P An end portion of the semiconductor substrate 100 along the Y direction extends in the X direction.

[0036] The semiconductor memory device of the first embodiment includes a semiconductor substrate 100, a transistor layer provided on the semiconductor substrate 100, a wiring layer provided above the transistor layer and on the lower side, and a memory cell array layer L provided above the wiring layer on the lower side. MCA1 ( Figure 3 ), set in the memory cell array layer L MCA1 The memory cell array layer L above MCA2 ( Figure 3 ), and disposed in the memory cell array layer L MCA2 The wiring layer on the upper side above.

[0037] [Memory cell array layer L MCA1 , L MCA2 The memory hole area R MH Structure of

[0038] For example Figure 1 and Figure 2 As shown, in the memory cell array region R MCA , a plurality of memory blocks BLK arranged in the Y direction are provided. The memory blocks BLK are as follows. Figure 2As shown, there are a plurality of string units SU arranged in the Y direction. Between two memory blocks BLK adjacent in the Y direction, an inter-block structure 140 such as silicon oxide (SiO2) is provided.

[0039] The memory block BLK, for example Figure 3 is provided with: a plurality of conductive layers 110 arranged in the Z direction; a plurality of semiconductor layers 120 extending in the Z direction; and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0040] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), etc. In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Between the plurality of conductive layers 110 arranged in the Z direction, an insulating layer 101 such as silicon oxide (SiO2) is provided.

[0041] Below the conductive layer 110, a conductive layer 111 is provided. The conductive layer 111 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). In addition, between the conductive layer 111 and the conductive layer 110, an insulating layer 101 such as silicon oxide (SiO2) is provided. The conductive layer 111 functions as a gate electrode of a source-side select transistor, etc.

[0042] Below the conductive layer 111, a semiconductor layer 112 is provided. The semiconductor layer 112 functions as a source line, etc.

[0043] One or more of the conductive layers 110 located at the lowermost layer among the plurality of conductive layers 110 function as a gate electrode of a source-side select transistor, etc. The plurality of conductive layers 110 are electrically independent in each memory block BLK.

[0044] In addition, the plurality of conductive layers 110 located above it function as word lines and gate electrodes of memory transistors, etc. The plurality of conductive layers 110 are electrically independent in each memory block BLK respectively.

[0045] In addition, one or more of the conductive layers 110 located above it function as a gate electrode of a drain-side select transistor, etc. The plurality of conductive layers 110 have a smaller width in the Y direction than other conductive layers 110. In addition, between two conductive layers 110 adjacent in the Y direction, an inter-string-unit insulating layer 126 is provided. The plurality of conductive layers 110 are electrically independent in each string unit SU respectively.

[0046] The semiconductor layer 120 is arranged in a specific pattern in the X direction and the Y direction. The semiconductor layer 120 functions as a channel region of a plurality of memory transistors, a source-side selection transistor, and a drain-side selection transistor arranged in the Z direction. The semiconductor layer 120 is a semiconductor layer such as polysilicon (Si), for example. The semiconductor layer 120, for example Figure 3 as shown, has a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide (SiO2) is provided in the central portion.

[0047] The semiconductor layer 120 includes a semiconductor region 120 MCA1 included in the memory cell array layer L L and a semiconductor region 120 MCA2 included in the memory cell array layer L U . In addition, the semiconductor layer 120 includes a semiconductor region 120 provided between the semiconductor region 120 L and the semiconductor region 120 U , an impurity region 122 provided below the semiconductor region 120 J , and an impurity region 121 provided above the semiconductor region 120 L . U is a substantially cylindrical region whose radial width (width in the X direction and width in the Y direction) gradually decreases as it extends downward along the Z direction. The outer peripheral surfaces of the semiconductor regions 120

[0048] are respectively surrounded by a plurality of conductive layers 110 included in the memory cell array layer L L and face the plurality of conductive layers 110. L is a substantially cylindrical region whose radial width (width in the X direction and width in the Y direction) gradually decreases as it extends downward along the Z direction. The outer peripheral surfaces of the semiconductor regions 120 MCA1 are respectively surrounded by a plurality of conductive layers 110 included in the memory cell array layer L

[0049] and face the plurality of conductive layers 110. U is a substantially cylindrical region whose radial width (width in the X direction and width in the Y direction) gradually decreases as it extends downward along the Z direction. The outer peripheral surfaces of the semiconductor regions 120 U are respectively surrounded by a plurality of conductive layers 110 included in the memory cell array layer L MCA2 and face the plurality of conductive layers 110.

[0050] In addition, the radial width W L of the upper end portion of the semiconductor region 120 120LU is of the same degree as the radial width W U of the upper end portion of the semiconductor region 120 120UU . In addition, the radial width W L of the lower end portion of the semiconductor region 120 120LL is of the same degree as the radial width W UThe radial width W of the lower end portion 120UL is of the same degree.

[0051] In addition, the "upper end portion of the semiconductor region 120" L in the semiconductor region 120 L includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and a portion located above it. Additionally, the "upper end portion of the semiconductor region 120" U in the semiconductor region 120 U includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and a portion located above it. Additionally, the "lower end portion of the semiconductor region 120" L in the semiconductor region 120 L includes a position facing the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and a portion located below it. Additionally, the "lower end portion of the semiconductor region 120" U in the semiconductor region 120 U includes a position facing the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and a portion located below it.

[0052] The semiconductor regions 120 J are respectively provided above the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and are provided below the plurality of conductive layers 110 included in the memory cell array layer L MCA2 . The radial width W of the semiconductor region 120 J is greater than the radial width W of the upper end portion of the semiconductor region 120 120J or the radial width W of the upper end portion of the semiconductor region 120 L . 120LU U or the radial width W of the upper end portion of the semiconductor region 120 120UU .

[0053] The impurity region 122 is joined to the semiconductor layer 112. The impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0054] The impurity region 121 contains, for example, N-type impurities such as phosphorus (P). The impurity region 121 is connected to a bit line (not shown) via a contact (not shown).

[0055] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130, for example Figure 4 As shown, it includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2) for example. The charge storage film 132 is a film capable of storing charges such as silicon nitride (Si3N4) for example. The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0056] [Structure of the inter-block structure 140]

[0057] The inter-block structure 140 extends in the X direction as Figure 2 shown, and extends in the Z direction as Figure 3 shown, and is arranged in a segmented manner in the Y direction for a plurality of conductive layers 110 and a plurality of insulating layers 101 in the Z direction. The inter-block structure 140 as Figure 3 shown includes: a pair of insulating layers 142, 142, which extend in the Z direction and the X direction and are separated in the Y direction; and a conductive layer 141, which is disposed between the pair of insulating layers 142, 142 and extends in the Z direction and the X direction. The conductive layer 141 is connected to the semiconductor layer 112 at the lower end.

[0058] The pair of insulating layers 142, 142 are arranged to be inclined with respect to the Z direction when observed in a Y-Z cross section as Figure 3 shown. However, when observed in a Y-Z cross section, the insulating layers 142, 142 are arranged such that as the insulating layers 142, 142 extend downward along the Z direction, the widths (Y-direction widths) of the two insulating layers 142 gradually become smaller. As a result, the width W in the Y direction of the upper end portion of the inter-block structure 140 140U is greater than the width W in the Y direction of the lower end portion of the inter-block structure 140 140L .

[0059] In addition, the "upper end portion of the inter-block structure 140" in the inter-block structure 140 includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and a portion located above it. Further, the "lower end portion of the inter-block structure 140" in the inter-block structure 140 includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and a portion located below it.

[0060] In addition, for example, the width W 140U of the inter-block structure 140 and the width W140L Greater than the semiconductor region 120 of the semiconductor layer 120 L width W 120LU 、W 120LL 、the semiconductor region 120 U width W 120UU 、W 120UL 、or the semiconductor region 120 J width W 120J 。

[0061] [Memory cell array layer L MCA1 、L MCA2 contact connection region R 300 structure]

[0062] For example Figure 2 as shown, between the two block structures 140 arranged in the Y direction in the contact connection region R 300 , two structures 200 arranged in the Y direction are provided. In addition, between the two structures 200, a contact connection small region r 300 is provided. In addition, between the block structure 140 and the structure 200, a conductive layer connection small region r 110 is provided. The region extends in the X direction along the block structure 140.

[0063] The structure 200, for example Figure 2 as shown, extends in the X direction and, as Figure 5 shown, extends in the Z direction and is in contact with the semiconductor layer 112 at the lower end. The structure 200, as Figure 5 shown, is arranged at a position between the contact connection small region r 300 and the conductive layer connection small region r 110 . In this way, the structure 200 divides the insulating layer 101 and the insulating layer 110A to be described later in the contact connection small region r 300 in the Y direction, and the insulating layer 101 and the conductive layer 110 in the conductive layer connection small region r 110 .

[0064] The structure 200, as Figure 5 shown, is formed of, for example, a semiconductor layer 220 such as polysilicon (Si), an insulating layer 225 such as silicon oxide (SiO2), and a gate insulating film 230.

[0065] The semiconductor layer 220, as Figure 5 shown, has a substantially U-shaped shape when observed in the Y-Z cross section and extends in the X direction. In addition, the Y-Z cross-sectional shape of the semiconductor layer 220 is substantially the same as the Y-Z cross-sectional shape of the semiconductor layer 120 ( Figure 3 )

[0066] The semiconductor layer 220 includes a memory cell array layer L MCA1 semiconductor regions 220 separated in the Y direction included therein La and semiconductor regions 220 Lb and, with the memory cell array layer L MCA2 semiconductor regions 220 separated in the Y direction included therein Ua and semiconductor regions 220 Ub . Further, the semiconductor layer 220 includes semiconductor regions 220 separated in the Y direction in the region between the memory cell array layer L MCA1 and the memory cell array layer L MCA2 and semiconductor regions 220 Ja and semiconductor regions 220 Jb and, with semiconductor regions 220 disposed below the semiconductor regions 220 La and semiconductor regions 220 Lb . B .

[0067] The upper end of the semiconductor region 220 La is connected to the lower end of the semiconductor region 220 Ja , the upper end of the semiconductor region 220 Ja is connected to the lower end of the semiconductor region 220 Ua . The upper end of the semiconductor region 220 Lb is connected to the lower end of the semiconductor region 220 Jb , the upper end of the semiconductor region 220 Jb is connected to the lower end of the semiconductor region 220 Ub . The semiconductor region 220 B connects the lower end portion of the semiconductor region 220 La to the lower end portion of the semiconductor region 220 Lb .

[0068] The semiconductor regions 220 La , 220 Lb are disposed to be inclined with respect to the Z direction when observed in a Y-Z cross section as shown in Figure 5 . However, when observed in a Y-Z cross section, the semiconductor regions 220 La , 220 Lb are arranged such that as they extend downward along the Z direction, the widths (Y-direction widths) of the semiconductor regions 220 La , 220 Lb gradually become smaller La , 220 Lb .

[0069] The semiconductor regions 220 Ua , 220Ub When observed in the Y-Z cross section as shown in Figure 5 , it is disposed obliquely with respect to the Z direction. However, when observed in the Y-Z cross section, as the semiconductor regions 220 Ua , 220 Ub extend downward along the Z direction, the semiconductor regions 220 Ua , 220 Ub are arranged in such a way that the width (width in the Y direction) gradually decreases. Ua , 220 Ub .

[0070] In addition, the width W in the Y direction of the upper end portions of the semiconductor regions 220 La , 220 Lb is of the same degree as the width W in the Y direction of the upper end portions of the semiconductor regions 220 220LU , 220 Ua , 220 Ub . Also, the width W in the Y direction of the lower end portions of the semiconductor regions 220 220UU , 220 La , 220 Lb is of the same degree as the width W in the Y direction of the lower end portions of the semiconductor regions 220 220LL , 220 Ua , 220 Ub . 220UL

[0071] In addition, the "upper end portions of the semiconductor regions 220 La , 220 Lb " refer to the portions in the semiconductor regions 220 La , 220 Lb that include the positions facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and are located above it. Also, the "upper end portions of the semiconductor regions 220 Ua , 220 Ub " refer to the portions in the semiconductor regions 220 Ua , 220 Ub that include the positions facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and are located above it. Also, the "lower end portions of the semiconductor regions 220 La , 220 Lb " refer to the portions in the semiconductor regions 220 La , 220 Lb that include the positions facing the memory cell array layer L MCA1The portion located below and opposite to the lowermost conductive layer 110 among the plurality of conductive layers 110 included. Additionally, "the lower end portion of the semiconductor region 220 Ua 、220 Ub " is, in the semiconductor region 220 Ua 、220 Ub , the portion that includes the position opposite to the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and is located below it.

[0072] The semiconductor regions 220 Ja 、220 Jb are respectively disposed above the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and below the plurality of conductive layers 110 included in the memory cell array layer L MCA2 . The Y-direction width W Ja 、220 Jb of the semiconductor regions 220 220J 、220 La 、220 Lb is greater than the Y-direction width W 220LU of the upper end portion of the semiconductor regions 220 Ua 、220 Ub 、220 220UU .

[0073] In addition, the width W 220LU 、W 220UU ( Figure 5 ) of the semiconductor layer 220 can be made greater than 0.5 times and less than 2.0 times the width W 120LU 、W 120UU ( Figure 3 ) of the semiconductor layer 120. Additionally, the width W 220LL 、W 220UL ( Figure 5 ) of the semiconductor layer 220 can be made greater than 0.5 times and less than 2.0 times the width W 120LL 、W 120UL ( Figure 3 ) of the semiconductor layer 120. Additionally, the width W 220J ( Figure 5 ) of the semiconductor layer 220 can be made greater than 0.5 times and less than 2.0 times the width W 120J ( Figure 3 ) of the semiconductor layer 120.

[0074] In the semiconductor regions 220 of the semiconductor layer 220 La 、220 Ja 、220Ua and the semiconductor region 220 Lb 220 Jb 220 Ub there is an insulating layer 225 such as silicon oxide provided between them. The insulating layer 225 extends in the Z direction and in the X direction.

[0075] The gate insulating film 230 covers the outer side surface of the semiconductor layer 220 (the surface opposite to the surface where the insulating layer 225 is provided), has a substantially U-shaped shape when observed in the Y-Z cross section, and extends in the X direction.

[0076] The gate insulating film 230, for example Figure 6 as shown, includes a tunnel insulating film 231, a charge storage film 232, and a block insulating film 233 laminated between the semiconductor layer 220 and the conductive layer 110. The tunnel insulating film 231 and the block insulating film 233 are insulating films such as silicon oxide (SiO2) for example. The charge storage film 232 is a film capable of storing charges such as silicon nitride (Si3N4) for example. The tunnel insulating film 231, the charge storage film 232, and the block insulating film 233 extend in the X direction along the outer side surface of the semiconductor layer 220 (the surface opposite to the surface where the insulating layer 225 is provided).

[0077] In addition Figure 5 the Y-Z cross-sectional shape of the structure 200 including the semiconductor layer 220, the insulating layer 225, and the gate insulating film 230 shown in Figure 3 is substantially the same as the Y-Z cross-sectional shape of the structure including the semiconductor layer 120, the insulating layer 125, and the gate insulating film 130 shown in Figure 5 In addition, the width in the Y direction at each height position of the structure 200 shown in Figure 3 can be made greater than 0.5 times and less than 2.0 times the width in the radial direction at each height position of the structure including the semiconductor layer 120, the insulating layer 125, and the gate insulating film 130 shown in

[0078] The contact connection small region r 300 As Figure 5 shown, it includes a plurality of insulating layers 110A arranged in the Z direction and a through contact 300 extending in the Z direction.

[0079] The insulating layer 110A is a substantially plate-shaped insulating layer extending in the X direction. The insulating layer 110A may also include an insulating layer such as silicon nitride (SiN). Between the plurality of insulating layers 110A arranged in the Z direction, an insulating layer 101 such as silicon oxide (SiO2) is provided.

[0080] The through contact 300, for example Figure 2As shown, a plurality are arranged in the X direction. The via contact 300 may also include a stacked film such as a barrier conductive film of titanium nitride (TiN) or the like and a metal film such as tungsten (W). For example Figure 5 As shown, the outer peripheral surfaces of the via contacts 300 are respectively surrounded by the insulating layer 110A and the insulating layer 101, and face the insulating layer 110A and the insulating layer 101.

[0081] In this way, since the outer peripheral surfaces of the via contacts 300 are surrounded by the insulating layer 110A and the insulating layer 101, the dielectric breakdown voltage between the via contacts 300 and the conductive layer 110 functioning as a word line or the like can be ensured. In addition, the via contact 300 extends in the Z direction, and its upper end is connected to the wiring in the upper-layer side wiring layer. Further, the via contact 300 connects its lower end to the wiring in the lower-layer side wiring layer, and is electrically connected to the transistor layer provided below the wiring via the lower-layer side wiring.

[0082] Conductive layer connection small area r 110 For example Figure 2 As shown, there is provided a narrow portion 110 of a plurality of conductive layers 110 arranged in the Z direction 300 . In the X direction, two adjacent memory hole regions R MH The plurality of conductive layers 110 included are mutually connected through the narrow portion 110 300 .

[0083] As Figure 2 shown, in the end region in the X direction of the contact connection small area r 300 and the conductive layer connection small area r 110 , there is provided a substantially cylindrical support member 400 that functions to support the insulating layer 101 in the manufacturing process. The support member 400, as Figure 7 shown, extends in the Z direction and is connected to the semiconductor layer 112 at its lower end. The support member 400 includes, for example, silicon oxide (SiO2) or the like. For example Figure 7 shown, the outer peripheral surfaces of the support member 400 are respectively surrounded by a plurality of conductive layers 110 and the insulating layer 101 included in the memory cell array layers L MCA1 , L MCA2 , and face the conductive layer 110 and the insulating layer 101.

[0084] The support member 400 includes a support member region 400 MCA1 included in the memory cell array layer L L , and a support member region 400 MCA2 included in the memory cell array layer L U . Further, the support member 400 includes a support member region 400 provided in L and the support member region 400 UThe support component region 400 therebetween J The support component region 400 J is disposed above the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and is disposed below the plurality of conductive layers 110 included in the memory cell array layer L MCA2

[0085] In addition Figure 7 the Y-Z cross-sectional shape of the support component 400 shown becomes substantially the same shape as Figure 3 the Y-Z cross-sectional shape of the structure including the semiconductor layer 120, the insulating layer 125, and the gate insulating film 130 shown

[0086] In addition, the support component region 400 L the radial width W of the upper end portion 400LU is of the same degree as the radial width W of the upper end portion of the support component region 400 U the radial width W of the upper end portion 400UU is of the same degree as the radial width W of the upper end portion of the support component region 400 L the radial width W of the lower end portion 400LL is of the same degree as the radial width W of the lower end portion of the support component region 400 U the radial width W of the lower end portion 400UL is of the same degree as the radial width W of the lower end portion of the support component region 400 J the radial width W 400J is greater than the radial width W of the upper end portion of the support component region 400 L the radial width W of the upper end portion 400LU or the radial width W of the upper end portion of the support component region 400 U the radial width W of the upper end portion 400UU

[0087] In addition, the "upper end portion of the support component region 400 L in the support component region 400 L includes the position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and the portion located above it. In addition, the "upper end portion of the support component region 400 U in the support component region 400 U includes the position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and the portion located above it. In addition, the "lower end portion of the support component region 400 L in the support component region 400 L includes the position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 ​​The portion that faces the lowermost conductive layer 110 among the plurality of conductive layers 110 and is located below it. In addition, "the lower end portion of the support member region 400" U is in the support member region 400 U and includes the position that faces the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and is located below it.

[0088] In addition, Figure 7 the width in the Y direction of the support member 400 shown Figure 3 is slightly longer than, or approximately the same size as, the radial width of the structure including the semiconductor layer 120, the insulating layer 125, and the gate insulating film 130 shown Figure 3 and is shorter than the width in the Y direction of the inter-block structure 140 shown.

[0089] More specifically, the width W in the Y direction of the upper end portion of the support member region 400 of the support member 400 L is slightly longer than, or approximately the same size as, the width W in the Y direction of the upper end portion of the support member region 400U 400LU and is slightly longer than, or approximately the same size as, the width W of the upper end portion of the semiconductor region 120 of the semiconductor layer 120 400UU or the width W of the upper end portion of the semiconductor region 120 L or the width W of the upper end portion of the semiconductor region 120 120LU or the width W of the upper end portion of the semiconductor region 120 U or the width W of the upper end portion of the semiconductor region 120 120UU or the width W of the upper end portion of the semiconductor region 120 L In addition, the width W in the Y direction of the lower end portion of the support member region 400 of the support member 400 400LL is slightly longer than, or approximately the same size as, the width W in the Y direction of the lower end portion of the support member region 400 U and is slightly longer than, or approximately the same size as, the width W of the lower end portion of the semiconductor region 120 of the semiconductor layer 120 400UL or the width W of the lower end portion of the semiconductor region 120 L or the width W of the lower end portion of the semiconductor region 120 120LL or the width W of the lower end portion of the semiconductor region 120 U or the width W of the lower end portion of the semiconductor region 120 120UL or the width W of the lower end portion of the semiconductor region 120 J In addition, the width W in the Y direction of the support member region 400 of the support member 400 400J is slightly longer than, or approximately the same size as, the width W of the semiconductor region 120 of the semiconductor layer 120 J or the width W of the semiconductor region 120 120J or the width W of the semiconductor region 120

[0090] [Power-on Structure]

[0091] As Figure 2 and Figure 5As shown, the semiconductor layers 220 of the respective structures 200 are electrically connected to the wiring m included in the wiring layer on the upper layer side via the contacts C1 and C2, respectively.

[0092] [Manufacturing Method]

[0093] Next, with reference to Figures 8 to 24 , the manufacturing method of the semiconductor memory device according to the first embodiment will be described. Figure 8 , Figure 9 , Figures 11 to 15 , Figures 17 to 22 , Figure 24 are schematic cross-sectional views for explaining the manufacturing method, showing the cross-section corresponding to Figure 3 . Figure 10 , Figure 16 , Figure 23 are schematic cross-sectional views for explaining the manufacturing method, showing the cross-section corresponding to Figure 5 .

[0094] When manufacturing the semiconductor memory device of the first embodiment, first, a transistor layer and a wiring layer on the lower layer side are formed on a semiconductor substrate 100 ( Figure 1 ). In addition, an insulating layer is formed on the upper surface of the wiring layer on the lower layer side.

[0095] Next, on the insulating layer, for example, as shown in Figure 8 , a semiconductor layer 112A, a sacrificial layer 112B, a semiconductor layer 112C, an insulating layer 101, and a conductive layer 111 are formed. In addition, a plurality of insulating layers 101 and a plurality of insulating layers 110A are alternately formed on the conductive layer 111. Furthermore, an insulating layer 101 is formed on the upper surface of the structure including the alternately formed plurality of insulating layers 101 and plurality of insulating layers 110A. The above steps are performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0096] Next, for example, as shown in Figure 9 , a plurality of memory holes MH L are formed at positions corresponding to the semiconductor layer 120. L The memory holes MH

[0097] are through holes that extend in the Z direction, penetrate through the plurality of insulating layers 101, the plurality of insulating layers 110A, the conductive layer 111, the semiconductor layer 112C, and the sacrificial layer 112B, and reach the semiconductor layer 112A. The above steps are performed, for example, by a method such as RIE (Reactive Ion Etching). Figure 9 shown, and at the same time as forming the memory holes MH L shown, for example, as shown in Figure 10As shown, a groove G is formed at a position corresponding to the structure 200. 200L Groove G 200L The trench extends along the Z direction and the X direction, penetrates the plurality of insulating layers 101 and 110A, the conductive layer 111, the semiconductor layer 112C, and the sacrificial layer 112B, and reaches the semiconductor layer 112A. The steps are performed, for example, by RIE or other methods.

[0098] Next, for example Figure 11 As shown, in the memory hole MH L In addition, although the figure is omitted, at the same time as the above step, an amorphous silicon film 120A is formed inside. Figure 10 Groove G shown 200L The amorphous silicon film 120A is also formed inside. The above step is performed by, for example, a CVD method. In addition, in the above step, an insulating film such as silicon oxide (SiO2) or silicon nitride (SiN) may be formed before forming the amorphous silicon film 120A.

[0099] Next, the upper end portion of the amorphous silicon film 120A is removed by wet etching or the like. In addition, a portion of the uppermost insulating layer 101 is removed by wet etching or the like to enlarge the memory hole MH. L The radius of the upper end and the groove G 200L In addition, the memory hole MH L and groove G 200L An amorphous silicon film 120A is also formed inside the upper end.

[0100] Next, although illustration is omitted, for example, Figure 7 The support member 400 shown in the figure corresponds to the position of the hole H. 400L ( Figure 7 ). Hole H 400L With memory hole MH L Similarly, the through hole extends along the Z direction, penetrates the plurality of insulating layers 101 and 110A, the conductive layer 111, the semiconductor layer 112C, and the sacrificial layer 112B, and reaches the semiconductor layer 112A. The steps are performed by, for example, RIE or the like.

[0101] Next, although not shown in the figure, in the hole H 400L The amorphous silicon film 120A is formed inside the hole H 400L The radius of the upper end of the hole H 400L The interior of the upper end is filled with silicon oxide (SiO2) or the like. The steps are performed, for example, by a method such as CVD.

[0102] Next, for example Figure 12 As shown in reference Figure 11On the upper surface of the described structure, a plurality of insulating layers 101 and a plurality of insulating layers 110A are alternately formed. For example, the above steps are performed by methods such as CVD. At this time, in the trench G including the amorphous silicon film 120A formed therein 200L ( Figure 10 ) on the upper surface of the structure, and in the hole H filled with silicon oxide (SiO2) etc. 400L ( Figure 7 ) on the upper surface of the structure, a plurality of insulating layers 101 and a plurality of insulating layers 110A are also alternately formed.

[0103] Next, for example Figure 13 as shown, at positions corresponding to the semiconductor layer 120, a plurality of memory holes MH U are formed. The memory holes MH U extend in the Z direction, penetrate the insulating layer 101 and the insulating layer 110A, and expose the upper surface of the amorphous silicon film 120A in the memory holes MH L . For example, the above steps are performed by methods such as RIE.

[0104] In addition, simultaneously with the formation of Figure 13 the memory holes MH shown U , for example, at positions corresponding to the structure 200 shown Figure 5 , a trench G 200U ( Figure 16 ) is formed. The trench G 200U extends in the Z direction and the X direction, and segments the plurality of insulating layers 101 and the plurality of insulating layers 110A in the Y direction. Its lower end surface (bottom surface) exposes the upper surface of the amorphous silicon film 120A in the trench G 200L . For example, the above steps are performed by methods such as RIE.

[0105] Next, for example Figure 14 as shown, the amorphous silicon film 120A in the memory holes MH L is removed. For example, the above steps are performed by wet etching etc.

[0106] In addition, the amorphous silicon film 120A in the trench G 200L is removed. For example, the above steps are performed by wet etching etc.

[0107] Next, for example, at positions corresponding to the support member 400 shown Figure 7 , a hole H 400U ( Figure 7 ) is formed. The hole H 400U extends in the Z direction, penetrates the insulating layer 101 and the insulating layer 110A, and exposes the upper surface of the silicon oxide (SiO2) etc. in the hole H 400L . In the hole H 400U (Figure 7 ) inner peripheral surface is filled with silicon oxide (SiO2), etc. For example, the above step is performed by methods such as CVD. Thus, by filling the holes H 400L and H 400U with silicon oxide (SiO2), etc., the support member 400 ( Figure 2 , Figure 7 ) is formed.

[0108] Next, for example, Figure 15 as shown, on the inner peripheral surface of the memory holes MH L and MH U , the gate insulating film 130, the semiconductor layer 120, and the insulating layer 125 are formed. In the above step, for example, film formation is performed by CVD, etc. Inside the memory holes MH L and MH U , an amorphous silicon film is formed. Additionally, for example, by annealing treatment, etc., the crystal structure of the amorphous silicon film is modified.

[0109] In addition, for example, Figure 16 as shown, on the inner surface (side surface and bottom surface) of the trenches G 200L and G 200U , a structure 200 including the gate insulating film 230, the semiconductor layer 220, and the insulating layer 225 is formed. In the above step, for example, film formation is performed by CVD, etc. Inside the trenches G 200L and G 200U , an amorphous silicon film is formed. Additionally, for example, by annealing treatment, etc., the crystal structure of the amorphous silicon film is modified. The above step is performed simultaneously with the formation of, for example, Figure 15 the gate insulating film 130, the semiconductor layer 120, and the insulating layer 125 as shown.

[0110] Next, for example, Figure 17 as shown, trenches G 140 are formed at positions corresponding to the inter-block structure 140. The trenches G 140 are trenches that extend in the Z direction and the X direction and divide the insulating layer 101, the insulating layer 110A, the conductive layer 111, etc. in the Y direction. The above step is performed by methods such as RIE, for example.

[0111] Next, for example, Figure 18 as shown, a protective film P 140 such as silicon nitride is formed on the side surface in the Y direction of the trench G 140 . In the above step, for example, an insulating film such as silicon nitride is formed on the side surface and the bottom surface in the Y direction of the trench G 140 by CVD, etc. Additionally, by methods such as RIE, the portion of the insulating film that covers the bottom surface of the trench G 140 is removed.

[0112] Next, for exampleFigure 19 As shown, the sacrificial layer 112B and a part of the gate insulating film 130 are removed to expose a part of the semiconductor layer 120. The above step is performed by a method such as wet etching, for example.

[0113] Next, for example Figure 20 As shown, the semiconductor layer 112 is formed by epitaxial growth or the like.

[0114] Next, for example Figure 21 As shown, the protective film P is removed 140 . The above step is performed by a method such as wet etching, for example.

[0115] Next, for example Figure 22 As shown, the insulating layer 110A is removed via the trench G 140 . The above step is performed by a method such as wet etching, for example. By removing the insulating layer 110A in this way, a hollow is formed between the plurality of insulating layers 101 disposed in the Z direction. The plurality of insulating layers 101 having such a hollow structure are supported by Figure 22 the structure including the semiconductor layer 120, the gate insulating film 130, and the insulating layer 125 shown, Figure 5 the structure body 200 (semiconductor layer 220, gate insulating film 230, and insulating layer 225) shown, and Figure 7 the support member 400 shown.

[0116] In addition, as Figure 23 shown, in the above step, in the contact connection small region r 300 , that is, in the region between a pair of structure bodies 200, 200 extending in the X direction and separated in the Y direction, the insulating layer 110A remains.

[0117] Next, for example Figure 24 As shown, the conductive layer 110 is formed. The above step is performed by a method such as CVD, for example.

[0118] Next, an inter-block structure 140 ( 140 ) is formed in the trench G. The above step is performed by methods such as CVD and RIE, for example. Figure 7 )

[0119] After that, for example, a through contact 300 as described in the reference Figure 5 is formed. The step of forming the through contact 300 is performed by methods such as CVD and RIE, for example. In addition, an upper-layer wiring layer including an inter-string unit insulating layer 126 ( Figure 3 ), contacts C1, C2 ( Figure 5 ), or wirings m ( Figure 2 , Figure 5 ) is formed. In this way, a semiconductor memory device is manufactured.

[0120] [Comparative Example]

[0121] In the semiconductor memory device of the first embodiment, although the structure 200 is formed using the gate insulating film 230, the semiconductor layer 220, and the insulating layer 225 as shown, in the comparative example, as shown, the insulating layer 200' corresponding to the structure 200 is formed by filling an oxide such as silicon oxide (SiO2) in the trench. When an oxide such as silicon oxide (SiO2) is filled in the trench, "twisting" may occur in the semiconductor memory device due to the thermal shrinkage of the oxide such as silicon oxide (SiO2). Figure 5 For example, when manufacturing the semiconductor memory device of the comparative example, in the steps corresponding to and, the insulating layer 110A is removed to form a hollow structure including a plurality of insulating layers 101. At this time, the insulating layer 200' thermally shrinks in the Z direction. Here, there is a case where the shrinkage stress of the insulating layer 200' in the Z direction is greater than the shrinkage stress in the Z direction of the support member 400' (), which is provided in the small conductive layer connection area r (,). In this case, when manufacturing the semiconductor memory device of the comparative example, in the steps corresponding to and, the central portion in the Z direction of the hollow structure protrudes in a state of being laterally bent from the contact connection small area r (,,) to the lateral trench G (). Figure 25 When an oxide such as silicon oxide (SiO2) is filled in the trench, "twisting" may occur in the semiconductor memory device due to the thermal shrinkage of the oxide such as silicon oxide (SiO2).

[0122] For example, when manufacturing the semiconductor memory device of the comparative example, in the steps corresponding to and, the insulating layer 110A is removed to form a hollow structure including a plurality of insulating layers 101. At this time, the insulating layer 200' thermally shrinks in the Z direction. Here, there is a case where the shrinkage stress of the insulating layer 200' in the Z direction is greater than the shrinkage stress in the Z direction of the support member 400' (), which is provided in the small conductive layer connection area r (,). In this case, when manufacturing the semiconductor memory device of the comparative example, in the steps corresponding to and, the central portion in the Z direction of the hollow structure protrudes in a state of being laterally bent from the contact connection small area r (,,) to the lateral trench G (). Figure 22 and Figure 23 When an oxide such as silicon oxide (SiO2) is filled in the trench, "twisting" may occur in the semiconductor memory device due to the thermal shrinkage of the oxide such as silicon oxide (SiO2). 110 ( Figure 2 、 Figure 5 、 Figure 25 ) of the support member 400' ( Figure 25 ). In this case, when manufacturing the semiconductor memory device of the comparative example, in the steps corresponding to and, the central portion in the Z direction of the hollow structure protrudes in a state of being laterally bent from the contact connection small area r ( Figure 22 and Figure 23 ) to the lateral trench G ( 300 ( Figure 2 、 Figure 5 、 Figure 25 ). 140 When an oxide such as silicon oxide (SiO2) is filled in the trench, "twisting" may occur in the semiconductor memory device due to the thermal shrinkage of the oxide such as silicon oxide (SiO2).

[0123] If the conductive layer 110 is formed in the steps corresponding to in this state, then as shown, there is a concern that the width in the Y direction of the central portion in the Z direction of the trench G ( Figure 24 ) becomes narrow, and it is impossible to connect the conductive layer 141 in the block structure 140 to the semiconductor layer 112. In addition, there is a concern that two adjacent conductive layers 110 in the Y direction are electrically connected. Figure 25 When an oxide such as silicon oxide (SiO2) is filled in the trench, "twisting" may occur in the semiconductor memory device due to the thermal shrinkage of the oxide such as silicon oxide (SiO2). 140 When an oxide such as silicon oxide (SiO2) is filled in the trench, "twisting" may occur in the semiconductor memory device due to the thermal shrinkage of the oxide such as silicon oxide (SiO2).

[0124] In addition, as described above, in the comparative example, since the insulating layer 200' corresponding to the structure 200 is formed by filling an oxide such as silicon oxide (SiO2) in the trench, it must be formed by a step different from the step of forming the semiconductor layer 120, and the number of manufacturing steps increases.

[0125] [Effects of the First Embodiment]

[0126] As Figure 5 shown, the structure 200 of the first embodiment is composed of, for example, a gate insulating film 230, a semiconductor layer 220 such as polysilicon (Si), and an insulating layer 225 such as silicon oxide (SiO2). The shrinkage stress in the Z direction of such a structure 200 is smaller than the shrinkage stress in the Z direction of the insulating layer 200' described above. Therefore, in the semiconductor memory device of the first embodiment, it is possible to suppress the generation of the "twist" described above. As a result, the semiconductor memory device of the first embodiment can be manufactured well.

[0127] In addition, in the first embodiment, since it is possible to form, for example, Figure 16 the structure 200 composed of the gate insulating film 230, the semiconductor layer 220, and the insulating layer 225 shown, and, for example, Figure 15 the gate insulating film 130, the semiconductor layer 120, and the insulating layer 125 shown simultaneously, it is possible to reduce the number of manufacturing steps.

[0128] Furthermore, in the semiconductor memory device of the first embodiment, after the product is completed, it is possible to check whether there is a short-circuit defect between the semiconductor layer 220 and the conductive layer 110 by applying a voltage to the semiconductor layer 220 of the structure 200 via Figure 5 the wiring m and the contacts C1 and C2 shown. As a result of the inspection, if a short-circuit defect is detected, the memory block BLK including the portion where the short-circuit defect occurred is prohibited from being used. Since such an inspection can be performed, the semiconductor memory device of the first embodiment can maintain a high quality.

[0129] [Second Embodiment]

[0130] Next, the second embodiment will be described. The semiconductor memory device of the second embodiment includes a structure 200a ( Figure 26 ) and a support member 400a ( Figure 27 ), replacing the structure 200 ( Figure 5 ) and the support member 400 ( Figure 7 ) of the first embodiment, but the structure of other parts is the same as that of the first embodiment. Therefore, hereinafter, the structure 200a ( Figure 26 ) and the support member 400a ( Figure 27 ) will be described in detail, and the description of other parts will be omitted or simplified.

[0131] [Structure]

[0132] Figure 26 is a cross-sectional view showing the structure 200a of the second embodiment and is the same as that of the first embodiment Figure 5Schematic cross-sectional view of a part corresponding to the part of the second embodiment shown. Figure 27 It is a cross-sectional view showing the support member 400a of the second embodiment, and is the same as that of the first embodiment Figure 7 Schematic cross-sectional view of a part corresponding to the part of the second embodiment shown.

[0133] [Structure of the structure 200a]

[0134] As Figure 26 shown, between the conductive layer connection small area r 110 and the contact connection small area r 300 , a groove G 200a extending in the Z direction and the X direction is formed. In the groove G 200a , a structure 200a extending in the Z direction and the X direction is formed. The structure 200a is formed by an oxide film 200a such as silicon oxide (SiO2) 200a disposed on the side surface, bottom surface, and upper surface of the groove G and extending in the Z direction and the X direction, I and a metal layer 200a containing tungsten (W) I disposed in the oxide film 200a and extending in the Z direction and the X direction. W In addition, the metal layer 200a W is grounded by a conductive wire (not shown) or the like.

[0135] The oxide film 200a disposed on one side surface of the groove G (the side surface on the conductive layer connection small area r 200a side) is disposed between the plurality of insulating layers 101 and the plurality of conductive layers 110 of the conductive layer connection small area r 110 and the metal layer 200a. The oxide film 200a disposed on the other side surface of the groove G (the side surface on the contact connection small area r I side) is disposed between the plurality of insulating layers 101 and the plurality of insulating layers 110A of the contact connection small area r 110 and the metal layer 200a. W 200a 300 I 300 W I 300 300 W W between.

[0136] When observed in the Y-Z cross-section as Figure 26 shown, the structure 200a is configured such that the width in the Y direction gradually decreases as it extends downward in the Z direction. Therefore, the width W 200aU in the Y direction at the upper end of the structure 200a is greater than the width w 200aL at the lower end of the structure 200a.

[0137] In addition, the "upper end portion of the structure 200a" in the structure 200a includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and a portion located above it. Further, the "lower end portion of the structure 200a" in the structure 200a includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and a portion located below it.

[0138] [Structure of the support member 400a]

[0139] In a conductive layer connection small region r 110 ( Figure 27 ) formed by alternately laminating a plurality of insulating layers 101 and a plurality of conductive layers 110, or in a contact connection small region r 300 ( Figure 26 ) formed by alternately laminating a plurality of insulating layers 101 and a plurality of insulating layers 110A, holes H Figure 27 extending in the Z direction as shown are formed 400aL 、H 400aU . The holes H 400aL 、H 400aU communicate with each other along the Z direction. The hole H 400aL is formed in the memory cell array layer L MCA1 , and the hole H 400aU is formed in the memory cell array layer L MCA2 . In the holes H 400aL 、H 400aU , a support member 400a extending in the Z direction is formed. The support member 400a is composed of an oxide film 400a 400aL such as silicon oxide (SiO2) that is provided on the inner peripheral surface, bottom surface, and upper surface of the holes H 400aU and extends in the Z direction, and a metal layer 400a I containing tungsten (W) that is provided in the oxide film 400a I and extends in the Z direction. W

[0140] The support member 400a includes a support member region 400 MCA1 included in the memory cell array layer L aL , and a support member region 400 MCA2 included in the memory cell array layer L aU . Further, the support member 400a includes a support member region 400 aL provided between the support member region 400 aU and the support member region 400 aJ . The support member region 400​aJ is disposed above the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and is disposed below the plurality of conductive layers 110 included in the memory cell array layer L MCA2

[0141] In addition, Figure 27 the Y-Z cross-sectional shape and the radial width of the support member 400a shown become substantially the same as Figure 7 the Y-Z cross-sectional shape and the radial width of the support member 400 shown

[0142] In addition, the support member region 400 aL has a radial width W at the upper end 400aLU which is of the same degree as the radial width W at the upper end of the support member region 400 aU 400aUU aL has a radial width W at the lower end 400aLL which is of the same degree as the radial width W at the lower end of the support member region 400 aU 400aUL aJ The radial width W of the support member region 400 400aJ is greater than the radial width W at the upper end of the support member region 400 aL 400aLU or the radial width W at the upper end of the support member region 400 aU 400aUU

[0143] In addition, the "upper end of the support member region 400 aL " refers to a portion in the support member region 400 aL that includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L and is located above it. In addition, the "upper end of the support member region 400 MCA1 " refers to a portion in the support member region 400 aU that includes a position facing the uppermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L and is located above it. In addition, the "lower end of the support member region 400 aU " refers to a portion in the support member region 400 MCA2 that includes a position facing the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L and is located below it. In addition, the "lower end of the support member region 400 aL " refers to a portion in the support member region 400 aL that includes a position facing the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L and is located below it. In addition, the "lower end of the support member region 400 MCA1 " refers to a portion in the support member region 400 aU ​​​​​​​​The lower end portion is in the support member region 400 aU which includes a position facing the lowermost conductive layer 110 among the plurality of conductive layers 110 included in the memory cell array layer L MCA2 and is located at a position below it.

[0144] [Manufacturing method]

[0145] Next, with reference to Figures 28 to 40 , the manufacturing method of the semiconductor memory device of the second embodiment will be described. Figure 28 and Figure 35 are schematic cross-sectional views for explaining the manufacturing method, showing the cross-section of the portion of the second embodiment corresponding to the portion shown in the first embodiment Figure 3 . Figures 29 to 33 is a schematic cross-sectional view for explaining the manufacturing method, showing the cross-section corresponding to Figure 27 . Figure 34 , Figures 36 to 40 are schematic cross-sectional views for explaining the manufacturing method, showing the cross-sections corresponding to Figure 26 . In addition, steps that are the same as those of the manufacturing method of the semiconductor memory device of the first embodiment in the steps of the manufacturing method of the semiconductor memory device of the second embodiment are omitted from the description.

[0146] In the manufacturing method of the semiconductor memory device of the second embodiment, the steps included in the manufacturing method of the semiconductor memory device of the first embodiment are executed until the steps described with reference to Figure 14 . However, an amorphous silicon film 120A is formed instead of an insulating film such as silicon oxide (SiO2) in the hole H 400L corresponding to the support member 400. In addition, when forming the memory holes MH L , MH U , the trenches G 200L , G 200U are not formed.

[0147] Next, as Figure 28 shown, an insulating layer 500 such as silicon oxide (SiO2) is formed on the upper surface of the uppermost insulating layer 101 to block the memory holes MH U . For example, the above step is performed by a method such as CVD.

[0148] Next, for example Figure 29 shown, a hole H400 aU is formed at a position corresponding to the support member 400, the amorphous silicon film 120A inside the hole H400 aL is removed, and an insulating layer 500 such as silicon oxide (SiO2) is formed on the upper surface of the uppermost insulating layer 101 to block the memory holes MHU Occlusion. For example, perform the above steps by means such as CVD.

[0149] Next, as Figure 30 shown, remove the portions in the insulating layer 500 corresponding to the holes H 400aL , H 400aU . For example, perform the above steps by wet etching or the like.

[0150] Next, as Figure 31 shown, form an oxide film 400a such as silicon oxide (SiO2) on the inner peripheral surface and bottom surface of the holes H 400aL , H 400aU , and on the upper surface of the insulating layer 500. I . In addition, form a metal layer 400a containing tungsten (W) on the inner peripheral surface and upper surface of the oxide film 400a I . For example, perform the above steps by means such as CVD. W W

[0151] Next, as Figure 32 shown, remove the oxide film 400a 400aU formed on the upper surface of the insulating layer 500 and the upper end opening portion of the hole H I and the metal layer 400a W . As a result, the upper surface of the metal layer 400a W is exposed. For example, perform the above steps by means such as RIE.

[0152] Next, as Figure 33 shown, form an oxide film 400a on the upper surface of the metal layer 400a W . In this way, the support member 400a is formed. I I

[0153] Next, remove the insulating layer 500 as shown by means such as RIE Figure 28 and Figure 33 .

[0154] Next, perform the steps described with reference to Figure 15 in the steps included in the manufacturing method of the semiconductor storage device of the first embodiment.

[0155] Next, perform the steps described with reference to Figure 17 in the steps included in the manufacturing method of the semiconductor storage device of the first embodiment. At this time, as Figure 34 shown, at a position corresponding to the structure 200a, form a groove G 200a extending in the Z direction and the X direction and penetrating the insulating layer 101 and the insulating layer 110A.

[0156] Next, as Figure 35 andFigure 36 As shown, an insulating layer 510 such as silicon oxide (SiO2) is formed on the upper surface of the uppermost insulating layer 101 to close the trench G 200a and the trench G 140 For example, the above step is performed by a method such as CVD.

[0157] Next, as Figure 37 shown, the part corresponding to the trench G in the insulating layer 510 is removed. For example, the above step is performed by RIE or the like. 200a

[0158] Next, as Figure 38 shown, an oxide film 200a such as silicon oxide (SiO2) is formed on the side and bottom surfaces of the trench G 200a and on the upper surface of the insulating layer 510 I . In addition, a metal layer 200a containing tungsten (W) is formed on the side and upper surfaces of the oxide film 200a I . For example, the above step is performed by a method such as CVD. W

[0159] Next, as Figure 39 shown, the oxide film 200a formed on the upper surface of the insulating layer 510 and on the upper end opening part of the trench G 200a and the metal layer 200a I are removed. Thus, the upper surface of the metal layer 200a W is exposed. For example, the above step is performed by a method such as RIE. W

[0160] Next, as Figure 40 shown, an oxide film 200a is formed on the upper surface of the metal layer 200a W . In this way, the structure 200a is formed. I

[0161] Next, the insulating layer 510 is removed. For example, the above step is performed by wet etching or the like.

[0162] After that, by performing the steps described in the steps included in the manufacturing method of the semiconductor memory device of the first embodiment Figures 18 to 24 , the semiconductor memory device of the second embodiment is manufactured.

[0163] [Effect of the Second Embodiment]

[0164] In the second embodiment, as described above, the structure 200a has a metal layer 200a containing tungsten (W) w , and the support member 400a has a metal layer 400a containing tungsten (W) w . The metal layer 200a is constituted w ​​​​and the metal layer 400a w The tungsten (W) of w has the characteristics of high rigidity with a large Young's modulus and high heat resistance with a high melting point.

[0165] In this way, the structure 200a and the support member 400a have the characteristic of high rigidity. Therefore, in the semiconductor memory device of the second embodiment, the generation of the above-mentioned "twist" can be suppressed. As a result, the semiconductor memory device of the second embodiment can be manufactured well.

[0166] In addition, because the structure 200a and the support member 400a have the characteristic of high heat resistance, for example Figure 24 As shown, the structure 200a and the support member 400a can sufficiently withstand the heat when forming the conductive layer 110 by methods such as CVD. Thus, the semiconductor memory device of the second embodiment can be manufactured well.

[0167] [Variation example]

[0168] In addition, for example, as described with reference to Figure 2 etc., in the first embodiment, a pair of structures 200 arranged in the Y direction are separated from each other when viewed in the XY plane. Similarly, in the second embodiment, a pair of structures 200a arranged in the Y direction are separated from each other when viewed in the XY plane. However, such a configuration is only an example, and the specific configuration can be appropriately changed. For example, when viewed in the XY plane, a pair of structures 200 arranged in the Y direction can be connected to each other at one end and the other end. Similarly, a pair of structures 200a arranged in the Y direction can also be connected to each other at one end and the other end. In this case, the through contact 300 can be electromagnetic shielded with respect to, for example, the semiconductor layer 120, and the electrical characteristics can be improved.

[0169] [Others]

[0170] Although several embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The embodiments or their variations are included in the scope or gist of the invention and are included in the scope equivalent to the invention described in the claims.

[0171] [Description of symbols]

[0172] 100: Semiconductor substrate

[0173] 110: Conductive layer

[0174] 120: Semiconductor layer

[0175] 130: Gate insulating film

[0176] 140: Inter-block structure

[0177] 200: Structure

[0178] 400: Support component.

Claims

1. A semiconductor memory device comprising: a substrate having a first region and a second region arranged in a first direction; and the first region includes: a plurality of first word line layers stacked in a second direction intersecting the surface of the substrate; a plurality of second insulating layers provided between the plurality of first word line layers; a first semiconductor layer extending in the second direction and having an outer peripheral surface facing the plurality of first word line layers; and a first charge storage film, disposed between the plurality of first word line layers and the first semiconductor layer; and the second region includes: a first plate, extending along the first direction and the second direction; a second plate, extending along the first direction and the second direction, separated from the first plate in a third direction perpendicular to the first direction and the second direction from the first plate; a third plate, disposed between the first plate and the second plate, extending along the first direction and the second direction, and having a length shorter than that of the first plate in the first direction; a fourth plate, disposed between the second plate and the third plate, extending along the first direction and the second direction, and having a length shorter than that of the first plate in the first direction; the plurality of second insulating layers, disposed between the third plate and the fourth plate; a plurality of first insulating layers, disposed between the plurality of second insulating layers disposed between the third plate and the fourth plate; and a first contact, extending along the second direction, and having an outer peripheral surface facing the plurality of first insulating layers and the plurality of second insulating layers; and wherein, the plurality of first word line layers and the plurality of second insulating layers are disposed between the first plate and the third plate, and between the second plate and the fourth plate; the third plate has: a second semiconductor layer, disposed between the plurality of first word line layers and the plurality of first insulating layers, and extending along the first direction and the second direction; and a second charge storage film, disposed between the plurality of first insulating layers and the second semiconductor layer; the first insulating layer and the first word line layer are directly connected in the second region; there is no plate member connecting the third plate and the fourth plate and extending along the second direction and the third direction.

2. The semiconductor memory device according to claim 1, further comprising: a plurality of second word line layers farther from the substrate than the plurality of first word line layers; and the first semiconductor layer includes: a first portion extending in the second direction and facing the plurality of first word line layers; a second portion extending in the second direction and facing the plurality of second word line layers; and a third part, connected to the first part and the second part; and the width of the third part in the third direction is greater than the width of the first part and the second part in the third direction; and the second semiconductor layer includes: a fourth part, extending along the second direction, and facing the plurality of first word line layers; a fifth part, extending along the second direction, and facing the plurality of second word line layers; and a sixth part, connected to the fourth part and the fifth part; and the width of the sixth part in the third direction is greater than the width of the fourth part and the fifth part in the third direction.

3. The semiconductor memory device according to claim 1 or 2, wherein If the position of one of the plurality of first word line layers in the second direction is set as a first position, the width of the first semiconductor layer in the third direction at the first position is set as a first width, the width of the second semiconductor layer in the third direction at the first position is set as a second width, then the second width is greater than 0.5 times the first width and less than 2.0 times the first width.

4. The semiconductor memory device according to claim 1 or 2, comprising: a first wiring electrically connected to the second semiconductor layer.

5. A semiconductor memory device, comprising: a substrate having a first region and a second region arranged in a first direction; and the first region includes: a plurality of first word line layers stacked in a second direction intersecting with the surface of the substrate; a plurality of second insulating layers provided between the plurality of first word line layers; a first semiconductor layer, extending along the second direction, and having an outer peripheral surface facing the plurality of first word line layers; a first charge storage film, disposed between the plurality of first word line layers and the first semiconductor layer; and the second region includes: a first plate, extending along the first direction and the second direction; a second plate, extending along the first direction and the second direction, separated from the first plate in a third direction perpendicular to the first direction and the second direction from the first plate; a third plate, disposed between the first plate and the second plate, extending along the first direction and the second direction, and having a length shorter than that of the first plate in the first direction; The fourth plate is disposed between the second plate and the third plate, extends along the first direction and the second direction, and has a length shorter than that of the first plate in the first direction; The plurality of second insulating layers are disposed between the third plate and the fourth plate; A plurality of first insulating layers are disposed between the plurality of second insulating layers disposed between the third plate and the fourth plate; and The first contact extends along the second direction and has an outer peripheral surface facing the plurality of first insulating layers and the plurality of second insulating layers; and Among them, the plurality of first word line layers and the plurality of second insulating layers are disposed between the first plate and the third plate, and between the second plate and the fourth plate; The third plate has: a first conductive layer disposed between the plurality of first word line layers and the plurality of first insulating layers and extending along the first direction and the second direction; a second insulating layer disposed between the first conductive layer and the plurality of first word line layers; And a third insulating layer disposed between the first conductive layer and the plurality of first insulating layers; The first insulating layer and the first word line layer are directly connected in the second region; There is no plate member that connects the third plate and the fourth plate and extends along the second direction and the third direction.

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