An epitaxial wafer, a method for fabricating the epitaxial wafer, and a high electron mobility transistor.

Abstract

This invention provides an epitaxial wafer, a method for fabricating the epitaxial wafer, and a high electron mobility transistor. The epitaxial wafer includes a capping layer, which comprises a first sublayer, a second sublayer, and a third sublayer stacked sequentially. The first and third sublayers are both GaN layers, and the second sublayer is an InGaN layer. The growth thickness of the first and third sublayers is less than or equal to the growth thickness of the second sublayer, and the growth temperature of the first and third sublayers is higher than or equal to the growth temperature of the second sublayer. This invention solves the problem of low current carrying capacity due to high ohmic contact resistance in existing epitaxial wafers.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an epitaxial wafer, an epitaxial wafer fabrication method, and a high electron mobility transistor. Background Technology

[0002] As a third-generation semiconductor material, GaN-based materials have advantages such as large bandgap, high electron saturation drift velocity, good chemical stability, radiation resistance, high temperature resistance, and easy formation of heterojunctions, making them the preferred material for manufacturing high-temperature, high-frequency, high-power, radiation-resistant high electron mobility transistor (HEMT) structures.

[0003] The performance of HTME devices largely depends on the quality of their epitaxial layer crystal and the mobility of their two-dimensional electron gas. The mobility of the two-dimensional electron gas has a significant impact on the device's on-resistance, power consumption, current carrying capacity, switching speed, and cutoff frequency. Therefore, how to fabricate high electron mobility transistors with superior performance has become a key research challenge for major manufacturers.

[0004] In existing technologies, most capping layers are made of GaN because GaN capping layers can isolate the AlGaN barrier layer from air, preventing the Al components in the AlGaN barrier layer from being oxidized. This increases the effective barrier height of the AlGaN barrier layer and thus reduces gate leakage current. However, GaN has a relatively high work function and high ohmic contact resistance with the electrodes, resulting in high on-resistance and power consumption of the device, which in turn affects the current carrying capacity of the transistor. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide an epitaxial wafer, an epitaxial wafer preparation method, and a high electron mobility transistor, aiming to solve the problem of low current carrying capacity caused by high ohmic contact resistance of epitaxial wafers in the prior art.

[0006] The embodiments of the present invention are implemented as follows:

[0007] An epitaxial wafer includes a capping layer, the capping layer comprising a first sublayer, a second sublayer, and a third sublayer stacked sequentially, wherein the first sublayer and the third sublayer are both GaN layers, and the second sublayer is an InGaN layer;

[0008] Wherein, the growth thickness of the first sublayer and the growth thickness of the third sublayer are both less than or equal to the growth thickness of the second sublayer, and the growth temperature of the first sublayer and the growth temperature of the third sublayer are both higher than or equal to the growth temperature of the second sublayer.

[0009] In addition, the epitaxial wafer proposed according to the present invention may also have the following additional technical features:

[0010] Furthermore, the growth thickness of the first sublayer is the same as that of the third sublayer, and both the growth thickness of the first sublayer and the third sublayer are 1~2 nm.

[0011] Furthermore, the growth thickness of the second sublayer is 2~4 nm.

[0012] Furthermore, the growth temperature of the first sublayer is the same as that of the third sublayer, and the growth temperature of both the first sublayer and the third sublayer is 1000℃-1100℃.

[0013] Furthermore, the growth temperature of the second sublayer is 800℃-1000℃.

[0014] Furthermore, the growth pressure of the first sublayer and the third sublayer is 50~150 mbar, and the growth pressure of the second sublayer is 100~200 mbar.

[0015] Furthermore, the epitaxial wafer also includes a substrate, a nucleation layer, a high-resistivity buffer layer, a channel layer, an insertion layer, and a barrier layer;

[0016] The nucleation layer, high-resistivity buffer layer, channel layer, insertion layer, barrier layer, and capping layer are sequentially stacked on the substrate.

[0017] Another objective of this invention is to provide a method for preparing an epitaxial wafer, for preparing the epitaxial wafer described in any of the above-mentioned embodiments, wherein the preparation method includes, when growing the capping layer of the epitaxial wafer:

[0018] Using H2 and N2 as carrier gases and introducing the corresponding source required for growth, a GaN layer is grown to prepare the first sublayer of the capping layer;

[0019] An InGaN layer is epitaxially grown on the first sub-layer to prepare the second sub-layer of the capping layer;

[0020] On the second sublayer, a GaN layer is epitaxially grown to prepare the third sublayer of the capping layer.

[0021] Furthermore, the above-mentioned epitaxial wafer preparation method further includes, before growing the capping layer of the epitaxial wafer, the following steps:

[0022] Provide a substrate required for epitaxial growth;

[0023] A nucleation layer, a high-resistivity buffer layer, a channel layer, an insertion layer, and a barrier layer are epitaxially grown sequentially on the substrate, and a capping layer is grown on the barrier layer.

[0024] Another object of the present invention is to provide a high electron mobility transistor comprising the epitaxial wafer described in any of the preceding claims.

[0025] Compared with existing technologies, this invention sets the capping layer as a structure of sequentially stacked first, second, and third sub-layers. The first and third sub-layers are both GaN layers, while the second sub-layer is an InGaN layer. The second sub-layer has a lower work function, reducing the overall contact resistance of the capping layer. The first and third sub-layers respectively isolate the barrier layer and the second sub-layer from air, preventing oxidation of the Al component in the barrier layer and the In component in the second sub-layer. This increases the effective barrier height of the barrier layer, thereby reducing gate leakage current. The growth thickness of the third sublayer is smaller than that of the second sublayer, increasing the proportion of the second sublayer in the capping layer. This can minimize the work function of the entire capping layer, thereby further reducing the ohmic contact resistance with the electrode. The growth temperature of the second sublayer is lower than that of the first and third sublayers. Under low-temperature growth conditions, the In group of the second sublayer is prevented from being analyzed, ensuring the ability of the second sublayer to reduce the work function of the entire capping layer. Ultimately, this achieves the goal of reducing the ohmic contact resistance in the epitaxial wafer, reducing on-resistance and power consumption, and thus improving the current carrying capacity of the epitaxial wafer. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of an epitaxial wafer in one embodiment of the present invention.

[0027] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0028] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] This invention addresses the problem of poor current carrying capacity caused by high ohmic contact resistance in epitaxial wafers by proposing an epitaxial wafer, an epitaxial wafer fabrication method, and a high electron mobility transistor, wherein:

[0032] Please see Figure 1 The image shows an epitaxial wafer proposed in an embodiment of the present invention, comprising a substrate 1 and a nucleation layer 3, a high-resistivity buffer layer 4, a channel layer 5, an insertion layer 6, a barrier layer 7, and a capping layer 8 sequentially stacked on the substrate 1.

[0033] Specifically, the capping layer 8 includes a first sub-layer 81, a second sub-layer 82 and a third sub-layer 83 stacked sequentially on the barrier layer 7. The first sub-layer 81 and the third sub-layer 83 are both GaN layers, and the second sub-layer 82 is an InGaN layer.

[0034] The growth thickness of the first sublayer 81 and the growth thickness of the third sublayer 83 are both less than or equal to the growth thickness of the second sublayer 82, and the growth temperature of the first sublayer 81 and the growth temperature of the third sublayer 83 are both higher than or equal to the growth temperature of the second sublayer 82.

[0035] Understandably, by setting the cap layer 8 as a structure of sequentially stacked first sub-layer 81, second sub-layer 82, and third sub-layer 83, with the first sub-layer 81 and third sub-layer 83 being GaN layers and the second sub-layer 82 being an InGaN layer, the work function of the second sub-layer 82 is relatively small, which can reduce the overall contact resistance of the cap layer 8. The first sub-layer 81 and third sub-layer 83 can respectively isolate the barrier layer 7 and the second sub-layer 82 from contact with air, preventing the Al component in the barrier layer 7 and the In component in the second sub-layer 82 from oxidation, thereby increasing the effective barrier height of the barrier layer 7 and reducing gate leakage current. The first sub-layer 8... The growth thickness of the first and third sublayers 81 and 83 is smaller than that of the second sublayer 82, which increases the proportion of the second sublayer 82 in the capping layer 8. This can minimize the work function of the entire capping layer 8, thereby further reducing the ohmic contact resistance with the electrode. The growth temperature of the second sublayer 82 is lower than that of the first and third sublayers 81 and 83. Under low-temperature growth conditions, the In group of the second sublayer 82 is prevented from being analyzed, ensuring the ability of the second sublayer 82 to reduce the work function of the entire capping layer 8. Ultimately, this achieves the goal of reducing the ohmic contact resistance in the epitaxial wafer, reducing the on-resistance and power consumption, thereby improving the current carrying capacity of the epitaxial wafer.

[0036] Furthermore, in some preferred embodiments of the present invention, the growth thickness of the first sublayer 81 is the same as the growth thickness of the third sublayer 83, and the growth temperature of the first sublayer 81 is the same as the growth temperature of the third sublayer 83. Specifically, the growth thickness of the first sublayer 81 and the growth thickness of the third sublayer 83 are both 1~2 nm, and the growth temperature of the first sublayer 81 and the third sublayer 83 are both 1000℃-1100℃.

[0037] It should be noted that when the thickness and temperature are the same, making the first sublayer 81 and the third sublayer 83 structurally identical can reduce the potential barrier difference caused by the difference in crystal quality due to inconsistent thickness or growth conditions, further reducing the work function of the entire capping layer 8, thereby reducing the ohmic contact resistance and improving the current carrying capacity.

[0038] In some optional embodiments of the present invention, the growth pressure of the first sublayer 81 and the third sublayer 83 is 50~150 mbar, for example, 50 mbar, 100 mbar and 150 mbar, etc., and the growth pressure of the second sublayer 82 is 100~200 mbar, for example, 100 mbar, 150 mbar and 200 mbar, etc.

[0039] By way of example and not limitation, in this embodiment, substrate 1 is a p-type doped Si substrate 1, nucleation layer 3 is an AlN layer, high-resistivity buffer layer 4 is an AlGaN layer, channel layer 5 is a GaN layer, insertion layer 6 is an AlN layer, and barrier layer 7 is an AlGaN layer.

[0040] In addition, a pre-laid Al layer 2 is provided between the substrate 1 and the nucleation layer 3. The pre-laid Al layer 2 can effectively suppress the interface reaction between the substrate 1 and the epitaxial structure.

[0041] On the other hand, the epitaxial wafer preparation method proposed in this invention is used to prepare the above-mentioned epitaxial wafer, and the preparation method includes the following steps:

[0042] Step S10: Provide a substrate, place the substrate in the MOCVD system, raise the chamber temperature to between 1000 and 1200°C, set the chamber pressure to between 50 and 100 mbar, and treat the substrate at high temperature for 5 to 10 minutes in an H2 atmosphere to remove oxides from the substrate surface.

[0043] The substrate is preferably a p-type doped Si substrate.

[0044] Step S11: After high-temperature treatment, a pre-laid Al layer with a thickness of 1~5nm is grown on the substrate. The growth temperature is 1000~1100℃, the pressure is 40~70 mbar, and the flow rate of the Al source is 50~200 sccm.

[0045] Step S12: After the pre-laid Al layer is grown, the temperature is adjusted to 1100℃-1200℃, and an AlN nucleation layer with a thickness of 100~300 nm is grown, with a growth pressure of 40~70 mbar.

[0046] Step S13: A carbon (C) doped AlGaN high-resistivity buffer layer is grown on the AlN nucleation layer at a growth temperature of 1000℃-1200℃ and a pressure of 40~70 mbar.

[0047] The AlGaN high-resistivity buffer layer has a thickness between 2.0 and 4.0 micrometers and a C doping concentration of 1*10⁻⁶. 19 cm -3 -1*10 20 cm -3 The Al component ranges from 0.2 to 0.8.

[0048] Step S14: A GaN channel layer is grown on a C-doped AlGaN high-resistivity buffer layer at a growth temperature of 1000℃-1150℃ and a pressure of 100~300 mbar.

[0049] The thickness of the GaN channel layer is 300~600 nm.

[0050] Step S15: An AlN insertion layer is grown on the GaN channel layer at a growth temperature of 1050℃-1150℃ and a pressure of 40~70 mbar.

[0051] The thickness of the AlN insertion layer is 1 nm.

[0052] Step S16: An AlGaN barrier layer is grown on the AlN insertion layer at a growth temperature of 1050℃-1150℃ and a pressure of 40~70 mbar.

[0053] The AlGaN barrier layer has a thickness of 20-25 nm and an Al composition of 0.20-0.25.

[0054] Step S17: Growing a capping layer on the AlGaN barrier layer. The fabrication method for growing the capping layer includes:

[0055] Using H2 and N2 as carrier gases and introducing the corresponding source required for growth, a GaN layer is grown to prepare the first sublayer of the capping layer;

[0056] An InGaN layer is epitaxially grown on the first sub-layer to prepare the second sub-layer of the capping layer;

[0057] On the second sublayer, a GaN layer is epitaxially grown to prepare the third sublayer of the capping layer.

[0058] The first and second sublayers are both 1-2 nm thick, grown at 1000℃-1100℃, and grown at 50-150 mbar; the second sublayer is 2-4 nm thick, grown at 800℃-1000℃, and grown at 100-200 mbar.

[0059] Step S18: After the epitaxial structure growth is completed, the temperature of the reaction chamber is lowered to room temperature in a nitrogen atmosphere to complete the epitaxial growth.

[0060] Furthermore, in the above-mentioned epitaxial wafer preparation process, trimethylaluminum (TMAl), trimethylgallium or triethylgallium (TMGa or TEGa), and NH3 are used as precursors for group III and group V sources, respectively, carbon tetrabromide (CBr4) is used as a precursor for carbon (C) source, and N2 and H2 are used as carrier gases.

[0061] To facilitate understanding of the present invention, a more complete description will be given below with reference to relevant embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0062] Example 1

[0063] Provide substrate;

[0064] An Al layer, an AlN nucleation layer, an AlGaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, and an AlGaN barrier layer are epitaxially grown sequentially on the substrate.

[0065] The first sublayer of GaN was grown on the AlGaN barrier layer at a growth temperature of 1000℃ and a growth pressure of 100mbar. Then, the second sublayer of InGaN was grown on the first sublayer of GaN at a growth temperature of 1000℃ and a growth pressure of 100mbar. Finally, the third sublayer of GaN was grown at a growth temperature of 1000℃ and a growth pressure of 100mbar.

[0066] The thickness of the first sublayer, the second sublayer, and the third sublayer is 2nm.

[0067] Example 2

[0068] Embodiment 2 of the present invention also proposes an epitaxial wafer and its preparation method. The difference between the epitaxial wafer and its preparation method in this embodiment and the epitaxial wafer and its preparation method in Embodiment 1 is as follows:

[0069] The thickness of the first and third sublayers is 1 nm, and the thickness of the second sublayer is 4 nm.

[0070] Example 3

[0071] Embodiment 3 of the present invention also proposes an epitaxial wafer and its preparation method. The difference between the epitaxial wafer and its preparation method in this embodiment and the epitaxial wafer and its preparation method in Embodiment 1 is as follows:

[0072] The thickness of the first and third sublayers is 1 nm, the thickness of the second sublayer is 4 nm, the growth temperature of the first and third sublayers is 1000 °C, and the growth temperature of the second sublayer is 900 °C.

[0073] Example 4

[0074] Example 4 of this invention also proposes an epitaxial wafer and its preparation method. The difference between the epitaxial wafer and its preparation method in this example and the epitaxial wafer and its preparation method in Example 1 is as follows:

[0075] The thickness of the first and third sublayers is 1 nm, the thickness of the second sublayer is 4 nm, the growth temperature of the first and third sublayers is 1000 °C, and the growth temperature of the second sublayer is 800 °C.

[0076] In order to compare with the above embodiments of the present invention, the following comparative examples are also proposed in the embodiments of the present invention.

[0077] Compare with Example 1

[0078] In Comparative Example 1 of this invention, an epitaxial wafer and its preparation method are also proposed. The difference between the epitaxial wafer and its preparation method in this embodiment and the epitaxial wafer and its preparation method in Example 1 is as follows:

[0079] In Comparative Example 1, the capping layer is a single GaN layer with a growth pressure of 100 mbar, a growth temperature of 1000℃, and a thickness of 6 nm.

[0080] Please refer to Table 1 below, which shows the parameters corresponding to Embodiments 1-4 and Comparative Example 1 of the present invention.

[0081] Table 1

[0082]

[0083] In Table 1 above, the first and third sub-layers are both GaN layers, and the second sub-layer is an InGaN layer.

[0084] In practical applications, epitaxial wafers were prepared using the preparation methods and parameters corresponding to Examples 1-4 and Comparative Example 1 of the present invention, respectively. The contact resistance and output power of the epitaxial wafers prepared in each example were tested, and the test data are shown in Table 2 below. It should be noted that, to ensure the reliability of the verification results, the preparation of epitaxial wafers for Examples 1-4 and Comparative Example 1 of the present invention should be identical in all aspects except for the aforementioned parameters. For example, the preparation processes and parameters of the other layers of the capping layer should be kept consistent.

[0085] Table 2

[0086]

[0087] Combining the data in Tables 1 and 2 above, it is clear that the embodiments of the present invention use a first sub-layer, a second sub-layer, and a third sub-layer to form a capping layer. At the same time, the first and third sub-layers are both GaN layers, and the second sub-layer is an InGaN layer. This significantly reduces the contact resistance of the prepared epitaxial wafer, improves the current carrying capacity, and ultimately increases the output power.

[0088] In addition, it can be clearly seen from the combination of Embodiment 1 and Embodiment 2 that when the thickness of the first sub-layer and the third sub-layer are significantly lower than the thickness of the second sub-layer, the contact resistance reduction effect is more obvious. This is because the proportion of the second sub-layer used to reduce the work function of the cap layer is increased, which makes the overall work function of the entire cap layer significantly reduced, thereby reducing the contact resistance.

[0089] Combining Examples 2 and 4, it is evident that when the temperatures of the first and third sublayers are significantly higher than those of the second sublayer, the contact resistance reduction effect is further enhanced. This is because the growth temperature of the second sublayer is lower than that of the first and third sublayers. Under low-temperature growth conditions, the In group of the second sublayer is prevented from being analyzed, ensuring the ability of the second sublayer to reduce the work function of the entire capping layer, ultimately achieving the goal of reducing the ohmic contact resistance in the epitaxial wafer.

[0090] In Comparative Example 1, although the capping layer is set as a GaN layer, it is only a GaN layer. However, the work function of the GaN layer is relatively large, resulting in a relatively high ohmic contact resistance with the electrode. After setting the GaN layer and the InGaN layer, the resistance is reduced. This is because the work function of the second sub-layer is smaller, which can reduce the overall work function of the capping layer. In addition, the first and third sub-layers can isolate the barrier layer and the second sub-layer from contact with air, respectively, to prevent the Al component in the barrier layer and the In component in the second sub-layer from being oxidized. This can increase the effective barrier height of the barrier layer, thereby reducing gate leakage current and ensuring the performance of the second sub-layer in reducing the overall work function of the capping layer, ultimately reducing the contact resistance.

[0091] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An epitaxial wafer, comprising a capping layer, characterized in that, The capping layer includes a first sub-layer, a second sub-layer, and a third sub-layer stacked sequentially, wherein the first sub-layer and the third sub-layer are both GaN layers, and the second sub-layer is an InGaN layer; Wherein, the growth thickness of the first sublayer and the growth thickness of the third sublayer are both less than the growth thickness of the second sublayer, and the growth temperature of the first sublayer and the growth temperature of the third sublayer are both higher than or equal to the growth temperature of the second sublayer.

2. The epitaxial wafer according to claim 1, characterized in that, The growth thickness of the first sublayer is the same as that of the third sublayer, and both the growth thickness of the first sublayer and the third sublayer are 1~2 nm.

3. The epitaxial wafer according to claim 1 or 2, characterized in that, The growth thickness of the second sublayer is 2~4 nm.

4. The epitaxial wafer according to claim 1, characterized in that, The growth temperature of the first sublayer is the same as that of the third sublayer, and the growth temperature of both the first sublayer and the third sublayer is 1000℃-1100℃.

5. The epitaxial wafer according to claim 1 or 4, characterized in that, The growth temperature of the second sublayer is 800℃-1000℃.

6. The epitaxial wafer according to claim 1, characterized in that, The growth pressure of the first sublayer and the third sublayer is 50~150 mbar, and the growth pressure of the second sublayer is 100~200 mbar.

7. The epitaxial wafer according to claim 1, characterized in that, The epitaxial wafer further includes a substrate, a nucleation layer, a high-resistivity buffer layer, a channel layer, an insertion layer, and a barrier layer; The nucleation layer, high-resistivity buffer layer, channel layer, insertion layer, barrier layer, and capping layer are sequentially stacked on the substrate.

8. A method for preparing an epitaxial wafer, characterized in that, The preparation method for growing a capping layer of the epitaxial wafer as described in any one of claims 1-7 includes: Using H2 and N2 as carrier gases and introducing the corresponding sources, GaN layers are grown to prepare the first sublayer of the capping layer; An InGaN layer is epitaxially grown on the first sub-layer to prepare the second sub-layer of the capping layer; On the second sublayer, a GaN layer is epitaxially grown to prepare the third sublayer of the capping layer.

9. The method for preparing an epitaxial wafer according to claim 8, characterized in that, Before growing the capping layer of the epitaxial wafer, the process further includes: Provide a substrate required for epitaxial growth; A nucleation layer, a high-resistivity buffer layer, a channel layer, an insertion layer, and a barrier layer are epitaxially grown sequentially on the substrate, and a capping layer is grown on the barrier layer.

10. A high electron mobility transistor, characterized in that, Includes the epitaxial wafer according to any one of claims 1 to 7.

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