A method for preparing a low-power phase change memory

Abstract

The present invention relates to a method for preparing a low-power phase change memory. The preparation method comprises: (1) growing a first dielectric layer on a substrate and forming a cylindrical bottom electrode; (2) forming a second dielectric layer on the first dielectric layer, photolithography and etching to form a longitudinal groove 1; (3) forming an "inverted letter" type phase change material layer in the groove 1, and etching back; (4) growing a third dielectric layer on the formed sidewall phase change structure, then growing a fourth dielectric layer and filling the groove 1, and polishing; (5) growing a conductive film layer, and forming longitudinal strip-shaped conductive lines by photolithography and etching; (6) growing a fifth dielectric layer, then growing a sixth dielectric layer and filling the grooves 2 between the conductive lines, and polishing; (7) photolithography and etching of a circular hole 1, filling the hole with a conductive material, and then polishing to form a top electrode. The phase change material layer prepared by the method exists in a sheet form, which greatly reduces the volume of the phase change material and is conducive to reducing power consumption.

Description

Technical Field

[0001] The invention belongs to the field of preparation of semiconductor memory, and in particular relates to a preparation method of a low-power phase change memory. Background Art

[0002] The continuous development of machine learning and artificial intelligence technologies has put forward higher requirements for the storage of massive data, such as high storage density, large storage capacity, fast read and write speed, low power consumption, small cell crosstalk, excellent thermal stability, etc. Traditional memories are difficult to meet all of them, and new memories and storage structures have emerged.

[0003] Memory usually exists in the internal circuits, semiconductor circuits and integrated circuits of computers or other electronic devices. Due to the von Neumann architecture, memory is divided into internal memory and external memory, each with different tasks and functions. The internal memory is a temporary storage area when executing a program, and all data will be lost after power failure; the external memory is used to store original data and calculation results, which need to be stored for a long time, and the data will not be lost after power failure. The most prominent feature of the internal memory is the fast access speed, but the capacity is small and the price is expensive; the characteristics of the external memory are large capacity, low price, but slow access speed. The internal memory is used to store programs and data that are needed immediately; the external memory is used to store programs and data that are not used temporarily. Information is often frequently exchanged between the internal memory and the external memory.

[0004] Phase Change Random Access Memory (PCRAM) is a memory based on the Ovsinski electron effect proposed by Ovsinski in the late 1960s. It is a new type of non-volatile memory that uses chalcogenide materials to reversibly convert between crystalline and amorphous states under pulses of different widths and intensities to ultimately achieve information storage. Its amorphous and crystalline states exhibit different reflective and resistive properties, so the amorphous and crystalline states can be used to represent "0" and "1" in the circuit to store data. Phase change memory has many advantages such as low power consumption, fast reading speed, strong stability, high storage density, no physical limitations in the process, and compatibility with traditional CMOS processes, so it has received widespread attention.

[0005] Generally, there are two ways to improve the performance of phase change memory: 1. Modify the phase change material by doping different base materials to improve the performance of the phase change material. 2. Improve the device performance of the phase change memory unit by optimizing the structure of the device.

[0006] CGeSbTe(UnderstandingPhase-ChangeBehaviorsofCarbon-DopedGe2Sb2Te5

[0007] for Phase-Change Memory Application, Xilin Zhou, Applied Materials & Interfaces, 2014, 14207-14214), TaSbTe (Phase change memory based on TaeSbTe alloy toward universal memory, Yuan Xue, Materials Today Physics, 2020, 100266), InGeSbTe (Phase-change memory based on matched Ge-Te, Sb-Te, and In-Te octahedrons: Improved electrical performances and robust thermal stability, Ruobing Wang, Info Mat, 2021, 12233) and other materials have been proven to have excellent phase change properties. Compared with traditional Ge2Sb2Te5, they all show faster phase change speed and better thermal stability. Among them, the CGST ten-year data retention temperature reaches 112°C, while TaST and InGST reach even better 165°C and 180°C respectively, which are much higher than GST's 89°C. This has a huge improvement effect on the thermal stability of the memory.

[0008] Since the phase change films produced by chemical vapor deposition (CVD) and atomic layer deposition (ALD) have poor density and the related phase change precursors are expensive, the films grown by physical vapor deposition (PVD) technology are relatively dense, and the target material is relatively cheap, the film deposition uniformity is good, and it is suitable for large-scale production, so it is widely used in the deposition process of phase change materials. The phase change memory device with a restricted structure has attracted widespread attention due to its small phase change area, low power consumption and excellent consistency. The biggest disadvantage of physical vapor deposition is that the step coverage is poor, and it is difficult to fill the deep hole or deep groove with phase change material, which to a certain extent limits its further development. In 2013, IBM developed a sidewall process for phase change materials (A Scalable Volume-Confined Phase Change Memory Using PhysicalVapor Deposition, SCLai, VLSI, 2013), and explained that this semi-restricted structure has certain advantages in reducing power consumption, but the phase change material on its sidewall is etched after SiN deposition. Since SiN is generally a high-temperature process, we found that large areas of phase change materials are prone to escape inside high-temperature cavities, causing cavity contamination. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a method for preparing a low-power phase change memory to reduce the volume of the phase change material in the device. At the same time, this semi-restricted structure is also beneficial to reduce etching damage and improve yield.

[0010] The present invention provides a method for preparing a low-power phase change memory, comprising:

[0011] (1) providing a substrate, growing a first dielectric layer on the substrate, and forming a cylindrical bottom electrode embedded in the first dielectric layer and with the top exposed;

[0012] (2) forming a second dielectric layer on the first dielectric layer including the cylindrical bottom electrode in step (1), and performing photolithography and etching on the second dielectric layer to form a longitudinal groove, wherein the bottom surface of the groove rests on the upper surface of the first dielectric layer, and two side surfaces of the groove are respectively located on the center lines of two longitudinally adjacent rows of cylindrical bottom electrodes on the first dielectric layer, so that half of the area of ​​each bottom electrode is exposed on the bottom surface of the groove;

[0013] (3) in step (2), a phase change material layer of the "inverted letter "J" is formed in the groove, and the phase change material layer is etched back so that the phase change material outside the groove and at the bottom of the groove is completely etched away, leaving only the phase change material on the side wall of the groove, and the bottom of the phase change material on the side wall is in contact with the bottom electrode below;

[0014] (4) growing a third dielectric layer on the sidewall phase change structure formed in step (3) as a protective layer for the phase change material on the sidewall, growing a fourth dielectric layer on the third dielectric layer and filling the groove, and polishing to remove the material outside the groove until the top of the sidewall phase change structure is exposed;

[0015] (5) growing a conductive film layer on the overall structure polished in step (4), and forming longitudinal strip-shaped conductive lines by photolithography and etching, wherein the bottom center of the conductive line is located on the sidewall phase change structure;

[0016] (6) growing a fifth dielectric layer on the structure formed in step (5) as a protective layer for the conductive lines, growing a sixth dielectric layer on the fifth dielectric layer to fill the grooves between the conductive lines, and then planarizing the surface of the sixth dielectric layer by polishing;

[0017] (7) Performing circular hole photolithography and etching on the sixth dielectric layer flattened in step (6), wherein the center of the circular hole is located on the longitudinal center line of the conductive line, filling the circular hole with conductive material until it is full, and then polishing and removing the conductive material outside the circular hole until it is flush with the upper surface of the sixth dielectric layer to serve as a top electrode.

[0018] Preferably, in step (1), the substrate is a semiconductor substrate; the material of the first dielectric layer is SiO2, and the thickness is 150-300 nm.

[0019] Preferably, the semiconductor substrate material includes Si, Ge or SiC.

[0020] Preferably, the growth method in step (1) includes chemical vapor deposition, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

[0021] Preferably, in step (1), the cylindrical bottom electrode material is selected from W, Pt, Al, Ag or TiN, and the pore size is 50-100 nm; the cylindrical bottom electrode is formed by sputtering or chemical vapor deposition.

[0022] Preferably, in step (2), the material of the second dielectric layer is selected from SiO2 or SiN, and has a thickness of 150nm to 270nm.

[0023] Preferably, the second dielectric layer in step (2) is formed by chemical vapor deposition, and the deposition temperature is not higher than 400°C.

[0024] Preferably, the photolithography in step (2) adopts a KrF scanning stepper.

[0025] Preferably, the etching method of the groove in step (2) is reactive ion etching (RIE) or plasma coupled etching (ICP); the width of the groove is 200nm to 400nm; and the verticality of the side wall is 70° to 90°.

[0026] Preferably, the etching stop point in step (2) is the upper surface of the first dielectric layer, the bottom of the groove exposes the upper surface of the bottom electrode, and an over-etching depth of 10 to 30 nm is allowed.

[0027] Preferably, before the phase change material layer is formed in step (3), the wafer after step (2) is subjected to soft etching pretreatment using ICP etching to increase the adhesion of the phase change film. The etching gas is Ar, the etching power is 300 W, and the etching time is 5 s.

[0028] Preferably, the phase change material layer in step (3) is formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0029] Preferably, the process parameters of the physical vapor deposition are: temperature not higher than 300°C, DC power of 100W to 500W, RF power of 10 to 50W, Ar is introduced to generate plasma to bombard the target material, Ar flow rate is 15 to 75 sccm, and the chamber pressure is maintained at 0.08 to 0.2 Pa.

[0030] Preferably, the phase change material layer in step (3) is selected from In x Ge y Sb z Te (1-x-y-z) , u Sb v Te (1-u-v) or C x Ge y Sb z Te (1-x-y-z) , where 0≤u<1, 0≤v<1, 0≤x<1, 0≤y<1, 0≤z<1, u+v≤1, x+y+z≤1.

[0031] Preferably, in step (3), the thickness of the phase change film outside the groove is 20nm to 80nm, and the thickness of the phase change film on the inner side wall of the groove is 10nm to 50nm.

[0032] Preferably, the back etching in step (3) includes reactive ion etching (RIE) or plasma coupled etching (ICP). The temperature in the middle and edge of the chuck can be adjusted to fine-tune the etching speed in the middle and edge to achieve the purpose of adjusting the etching uniformity.

[0033] Preferably, the process parameters of the ICP etching are: etching gas pressure of 3 to 8 mTorr, etching power of 200 W to 700 W, etching bias of 300 to 500 V, etching gas of two or three components of HBr, Cl2, CF4, He, and Ar (for example, HBr / He or HBr / Ar, in a ratio of 1:10 to 2:5), and the etching goal is to completely etch all phase change materials outside the groove and allow 5-10 nm of over-etching, and completely etch the bottom of the groove, leaving only the side wall with a "1"-shaped structure phase change material, and the bottom is connected to the bottom electrode.

[0034] Preferably, in step (3), after the back etching, a N2 / O2 gas combination is used to remove the additional polymer produced on the surface after etching, and the gas ratio is 1:1 to 5:4.

[0035] Preferably, in step (4), the growth method of the third dielectric layer and the fourth dielectric layer includes physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0036] Preferably, the deposition temperature of the third dielectric layer is not higher than 250°C.

[0037] Preferably, the fourth dielectric layer is deposited in two steps. The first step is to deposit SiO2 using a high aspect ratio process (HARP) with a growth temperature of 350°C and a thickness of 80 to 150 nm. The second step is to grow SiO2 using a conventional process with a precursor of tetraethyl orthosilicate (TEOS) at a growth temperature of 250°C and a thickness of 200 to 300 nm.

[0038] Preferably, in step (4), the third dielectric layer serves as a phase change material protection layer and also as a polishing stop layer.

[0039] Preferably, in step (4), the material of the third dielectric layer is SiN, and the thickness is 5 to 20 nm.

[0040] Preferably, in step (4), the material of the fourth dielectric layer is SiO2; and the polishing is chemical mechanical polishing.

[0041] Preferably, the chemical mechanical polishing uses an alkaline polishing solution, and the polishing rate of the fourth dielectric layer material is 120 nm / min.

[0042] Preferably, in step (4), the polishing to remove the material outside the groove until the top of the sidewall phase change structure is exposed is: chemical mechanical polishing is used to remove the material outside the groove, while allowing a certain amount of over-polishing to ensure that the top of the "1"-shaped phase change structure is completely exposed, and the phase change structure is over-polished by 10 to 20 nm.

[0043] Preferably, the growth method of the conductive film layer in step (5) includes physical vapor deposition or chemical vapor deposition.

[0044] Preferably, the physical vapor deposition is reactive sputtering, and the process parameters of reactive sputtering are: using Ti target material, the sputtering gas is a N2 / Ar combination, the gas ratio is 1:2 to 1:1, and the power is 5000 to 8000W.

[0045] Preferably, in step (5), the conductive film layer material is TiN, and the thickness is 30-40 nm.

[0046] Preferably, in step (5), the center line of the conductive line is located directly above the center line of the sidewall phase change material, and the width of the conductive line is 180-250 nm.

[0047] Preferably, the etching in step (5) includes reactive ion etching (RIE) or plasma coupled etching (ICP).

[0048] Preferably, the etching process parameters in step (5) are: etching pressure of 3-5 mtorr, power of 800 W, voltage of 100-150 V, etching gas combination of BCl3 / Cl2, and gas ratio of 1:1-1:2.

[0049] Preferably, in step (5), the over-etching of the conductive film layer is as follows: the etching pressure is 3-5 mtorr, the power is 800 W, the etching bias is 120-150 V, the etching gas combination is HBr / He, and the gas ratio is 1:3-2:3.

[0050] Preferably, in step (6), the material of the fifth dielectric layer is SiN, and the thickness is 10-20 nm.

[0051] Preferably, the material of the sixth dielectric layer in step (6) is SiO2.

[0052] Preferably, in step (6), the fifth dielectric layer and the sixth dielectric layer are grown by chemical vapor deposition.

[0053] Preferably, the growth temperature of the fifth dielectric layer is not higher than 250°C.

[0054] Preferably, the sixth dielectric layer is grown by deposition in two steps. The first step is to deposit SiO2 using a high aspect ratio process (HARP) with a growth temperature of 350°C and a thickness of 300-400nm. The second step is to grow SiO2 using a conventional process with a precursor of tetraethyl orthosilicate (TEOS) at a growth temperature of 250°C and a thickness of 200nm.

[0055] Preferably, the polishing in steps (6) and (7) is chemical mechanical polishing.

[0056] Preferably, the chemical mechanical polishing uses an alkaline polishing solution.

[0057] Preferably, in the step (7), the photolithography is performed by immersion exposure; and the etching is performed by ICP etching.

[0058] Preferably, in step (7), the diameter of the circular hole is 50 nm to 100 nm, and the depth of the hole is 100 nm to 150 nm; the lower surface of the circular hole is in contact with the upper surface of the conductive line.

[0059] Preferably, the method of filling the conductive material in step (7) is physical vapor deposition; the conductive material includes W, TiN, Al / Cu alloy or Ag.

[0060] Preferably, the phase change memory comprises: at least one lower electrode embedded in a substrate; a blade-shaped deformation material structure connected to the upper part of the lower electrode, and an upper electrode connected to the upper part of the phase change material structure.

[0061] The present invention also provides a phase change memory prepared by the above preparation method.

[0062] The present invention also provides an application of the phase change memory in fixed-line or wireless communication equipment.

[0063] The phase change memory structure involved in the present invention is a semi-confined structure.

[0064] The present invention uses a plasma coupled etching method for back etching. Since the method can realize the patterning of phase change materials without using a photolithography method, the cost of the phase change unit preparation process is greatly reduced; since the thickness of the phase change material of the sidewall structure is easy to control and is not limited by the photolithography process, the phase change area of ​​the phase change memory can be reduced by reducing the deposition thickness of the phase change material, thereby realizing the preparation of a low-power phase change memory device.

[0065] Beneficial Effects

[0066] The phase change material layer of the present invention exists in the form of a sheet, which greatly reduces the volume of the phase change material and is conducive to reducing power consumption; at the same time, the etching method is used for etching without the need for a photolithography process, and is not limited by the photolithography process node, which greatly reduces the process cost; the phase change material is deposited in a groove with a smaller aspect ratio during the deposition process, and will not cause the filling problem of high aspect ratio holes or grooves similar to other restrictive structures, so as to realize this restrictive small-area phase change structure, avoiding the problem of high process cost of CVD or ALD; because the phase change material is in a vertical state, in the process of etching back, except for the top In addition, other areas are less directly bombarded by plasma and therefore suffer less etching damage. The phase change material directly etched on the top will be removed in the chemical mechanical polishing process. Therefore, the phase change material in the final device suffers little etching damage, which is beneficial to improving the reliability and yield of the device. We choose to directly etch the phase change material instead of depositing the passivation layer directly after the phase change material is deposited. After etching, the phase change material only exists in a small area of ​​the side wall, which avoids the contamination of the CVD chamber by the escape of metal atoms in the large-area phase change area in the subsequent SiN deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 It is a schematic diagram of the cross section of the complete device;

[0068] Figure 2 is a schematic diagram of a semiconductor substrate, a first dielectric layer and a bottom electrode;

[0069] Figure 3 is a schematic diagram after the second dielectric layer is deposited;

[0070] Figure 4 A schematic diagram of etching the second dielectric layer to form a groove;

[0071] Figure 5 Schematic diagram of the phase change material after being deposited above the groove;

[0072] Figure 6 A schematic diagram showing that only the sidewall phase change material is left after the phase change material is etched back;

[0073] Figure 7 A schematic diagram of depositing a third dielectric layer as a protective layer;

[0074] Figure 8 is a schematic diagram of filling the fourth dielectric layer;

[0075] Fig. 9 A schematic diagram of chemical mechanical polishing of the fourth dielectric layer;

[0076] Fig.10 is a schematic diagram of deposition of a conductive thin film layer;

[0077] Fig.11 It is a schematic diagram of a stripe structure formed after the conductive film layer is subjected to photolithography and etching;

[0078] Fig.12 A schematic diagram of depositing a fifth dielectric layer as a conductive film protection layer;

[0079] Fig.13 is a schematic diagram of the sixth dielectric layer after filling and planarization process;

[0080] Fig.14 A schematic diagram of a process of performing photolithography and etching on the sixth dielectric layer, filling with a conductive material, and performing a planarization process;

[0081] Fig.15 This is a schematic diagram of a typical T-type phase change memory;

[0082] Fig.16 Electrical simulation diagrams of the T-type and sidewall-type structures of the present invention.

[0083] Description of reference numerals:

[0084] 100 semiconductor substrate;

[0085] 200 a first dielectric layer;

[0086] 201 bottom electrode;

[0087] 300 second dielectric layer;

[0088] 301 phase change material layer;

[0089] 302 a third dielectric layer;

[0090] 303 fourth dielectric layer;

[0091] 400 conductive film layer;

[0092] 401 fifth dielectric layer;

[0093] 402 sixth dielectric layer;

[0094] 403 top electrode. DETAILED DESCRIPTION

[0095] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0096] Example 1

[0097] This embodiment provides a method for preparing a low-power phase change memory having a sidewall phase change material structure, comprising the following steps:

[0098] Step S1: as shown in the attached Figure 2 As shown, a substrate 100 is provided, the substrate material is Si, a first dielectric layer 200 is grown on the substrate by CVD method, the growth temperature is 400°C, the first dielectric layer 200 is SiO2, the thickness is 200nm, and a cylindrical bottom electrode 201 embedded therein and exposed at the top is formed, the bottom electrode material is W, grown by chemical vapor deposition method, the pore size is 60nm, and the distance between adjacent bottom electrodes is 300nm. In other embodiments, the bottom electrode can also adopt other sizes.

[0099] Step S2: As shown in the attached Figure 3 and attached Figure 4 As shown, a second dielectric layer 300 is formed on the first dielectric layer including the bottom electrode. The second dielectric layer is made of SiO2 and grown by chemical vapor deposition. The deposition temperature is 400°C and the deposition thickness is set to 170nm. The second dielectric layer 200 is etched by KrF scanning stepper photolithography and RIE etching process to form a longitudinal groove. The width of the groove is set to 400nm, the verticality of the groove sidewall is 85°, the bottom surface of the groove stays on the upper surface of the first dielectric layer 200, the bottom of the groove exposes the upper surface of the bottom electrode, and the two side surfaces of the groove are respectively located on the center lines of two adjacent rows of cylindrical bottom electrodes 201 on the first dielectric layer 200, so that half of the area of ​​each bottom electrode is exposed on the bottom surface of the groove, and an over-etching depth of 15nm is allowed.

[0100] Step S3: As shown in the attached Figure 5As shown, before the growth of the phase change material, ICP etching is used to perform soft etching pretreatment on the wafer after the S2 step to increase the adhesion of the phase change film. The etching gas is Ar, the etching power is 300W, and the etching time is 5s. The "inverted letter" phase change material layer 301 is grown in the groove by physical vapor deposition method. The phase change material is C 0.16 Ge 0.187 Sb 0.187 Te 0.466 , the growth temperature is not higher than 230°C, the DC power is 300W, the RF power is 20W, the Ar flow rate is 30 to 15sccm, the chamber pressure is maintained at 0.1Pa, the thickness of the phase change material outside the groove is 60nm, and the thickness of the phase change film on the inner wall of the groove is 45nm.

[0101] Step S4: As shown in the attached Figure 6 As shown, the phase change material layer 301 is etched back using an ICP etching method, the etching pressure is 5mtorr, the etching power is 700W, the etching bias is 300V, and the etching gas combination is HBr / He, the ratio is 1:5, so that the phase change material outside the groove and at the bottom of the groove is completely etched, and the over-etching depth of the bottom of the groove is allowed to be 5nm, leaving only the phase change material on the side wall of the groove, and the bottom of the phase change material on the side wall is in contact with the bottom electrode 201 below. The additional polymer produced after etching is removed by using a N2 / O2 gas combination, and the gas ratio is 5:4. Since the edge etching rate is faster than the middle, the chuck edge temperature is reduced to keep the edge etching rate consistent with the wafer middle etching rate.

[0102] Step S5: As shown in the attached Figure 7 As shown, a third dielectric thin layer 302 is chemically vapor deposited on the formed sidewall phase change structure 301, with a deposition temperature of 200° C., a thickness of 10 nm, and a material of SiN, as a protective layer for the phase change material on the sidewall and as a stop layer for chemical mechanical polishing in step S7.

[0103] Step S6: As shown in the attached Figure 8 As shown, a fourth dielectric layer 303 is grown by chemical vapor deposition on the third dielectric film layer 302 and fills the grooves. The material is SiO2, which is deposited in two steps. The first step is to deposit SiO2 using a high aspect ratio process (HARP) with a growth temperature of 350°C and a thickness of 110nm. The second step is to grow SiO2 using a conventional process, and the precursor is tetraethyl orthosilicate (TEOS) with a growth temperature of 250°C and a thickness of 200nm.

[0104] Step S7: Fig. 9As shown, chemical mechanical polishing is used to remove the material outside the groove, and a certain amount of over-polishing is allowed to ensure that the top of the "1"-shaped phase change structure is completely exposed, and the phase change structure is over-polished by about 15nm. Among them, the chemical mechanical polishing uses an alkaline polishing liquid, and the polishing rate of the fourth dielectric layer material is 120nm / min.

[0105] Step S8: Fig.10 As shown, physical vapor deposition is used to grow the conductive film layer 400, the material is TiN, the specific method is reactive sputtering, a Ti target is used, the sputtering gas is a combination of N2 / Ar, the gas ratio is 1:2, the power is 7400W, and the film thickness is 40nm. Fig.11 As shown, the ICP method is used to perform longitudinal line etching on the conductive film layer to form longitudinal strip-shaped conductive lines. The center line of the line is located directly above the center line of the sidewall phase change material, and the line width is 200nm; the conductive film layer etching pressure is 3mtorr, the power is 800W, the etching bias is 120V, the etching gas combination used is BCl3 / Cl2, and the gas ratio is 2:3; an over-etching step is added to the conductive film layer, the etching pressure is 3mtorr, the power is 800W, the etching bias is 120V, the etching gas combination used is HBr / He, the gas ratio is 2:5, and the over-etching depth is about 15nm.

[0106] Steps S9 & S10: As attached Fig.12 As shown, a fifth dielectric thin layer 401 is grown on the structure formed in S8 by chemical vapor deposition as a protective layer for the conductive line 400. The material is SiN, the film thickness is 20 nm, and the growth temperature is 200° C. Fig.13 As shown, a sixth dielectric layer 402 is grown on the fifth dielectric layer 401 by chemical vapor deposition and fills the grooves between the conductive lines. The material is SiO2, which is deposited in two steps. First, SiO2 is deposited by high aspect ratio process (HARP), the growth temperature is 350°C, and the thickness is 350nm. The second step is to grow SiO2 by conventional process, the precursor is tetraethyl orthosilicate (TEOS), the growth temperature is 250°C, and the thickness is 200nm. Then, the upper surface of the sixth dielectric layer 402 is flattened by chemical mechanical polishing, and an alkaline polishing liquid is used as the polishing liquid for chemical mechanical polishing.

[0107] Steps S11 & S12: As shown in the attached Fig.14As shown, photolithography and etching processes are performed on the planarized sixth dielectric layer 402, the photolithography uses immersion exposure technology, and the etching uses ICP etching, and circular hole etching is performed on the sixth dielectric layer 402, the diameter of the circular hole is 60nm, the center of the hole is located on the longitudinal center line of the conductive line, and the lower surface of the hole is in contact with the upper surface of the conductive film layer line 400; physical vapor deposition is used to fill the hole with conductive material until it is filled, and the filling material is selected from W. Then chemical mechanical polishing is performed to remove the conductive material outside the hole until it is flush with the upper surface of the sixth dielectric layer, leaving only the conductive material in the hole as the top electrode 403, and the top electrode diameter is 60nm.

[0108] COMSOL software was used to analyze the traditional T-shaped structure (such as Fig.15 ) and a sidewall phase change storage structure storage unit are simulated, the given current is 0.4mA, the diameter of the cylindrical bottom electrode is 60nm, and the temperature on the line passing through the center of the cylindrical electrode and the center of the phase change material is collected, such as Fig.16 As shown, the maximum temperature of the phase change unit region using the sidewall structure is 40% higher than that of the T-type structure. In other words, when the phase change material reaches the required melting temperature, the phase change unit of the sidewall structure requires a smaller current.

Claims

1. A method for preparing a low-power phase change memory, comprising: (1) providing a substrate, growing a first dielectric layer on the substrate, and forming a cylindrical bottom electrode embedded in the first dielectric layer and with the top exposed; (2) forming a second dielectric layer on the first dielectric layer including the cylindrical bottom electrode in step (1), and performing photolithography and etching on the second dielectric layer to form a longitudinal groove, wherein the bottom surface of the groove rests on the upper surface of the first dielectric layer, and two side surfaces of the groove are respectively located on the center lines of two longitudinally adjacent rows of cylindrical bottom electrodes on the first dielectric layer, so that half of the area of ​​each bottom electrode is exposed on the bottom surface of the groove; (3) in step (2), a "reverse-Y" type phase change material layer is formed in the groove, and the phase change material layer is etched back, so that the phase change material outside the groove and at the bottom of the groove is completely etched away, leaving only the phase change material on the side wall of the groove, and the bottom of the phase change material on the side wall is in contact with the bottom electrode below; wherein the back etching includes reactive ion etching or plasma coupled etching; (4) growing a third dielectric layer on the sidewall phase change structure formed in step (3), growing a fourth dielectric layer on the third dielectric layer to fill the groove, and polishing to remove the material outside the groove until the top of the sidewall phase change structure is exposed; (5) growing a conductive film layer on the overall structure polished in step (4), and forming longitudinal strip-shaped conductive lines by photolithography and etching, wherein the bottom center of the conductive line is located on the sidewall phase change structure; (6) growing a fifth dielectric layer on the structure formed in step (5), growing a sixth dielectric layer on the fifth dielectric layer to fill the grooves between the conductive lines, and then planarizing the surface of the sixth dielectric layer by polishing; (7) Performing circular hole photolithography and etching on the sixth dielectric layer flattened in step (6), wherein the center of the circular hole is located on the longitudinal center line of the conductive line, filling the circular hole with conductive material until it is full, and then polishing and removing the conductive material outside the circular hole until it is flush with the upper surface of the sixth dielectric layer to serve as a top electrode.

2. The preparation method according to claim 1, characterized in that: In the step (1), the substrate is a semiconductor substrate; the material of the first dielectric layer is SiO2, and the thickness is 150 to 300 nm; the growth method includes chemical vapor deposition, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition; the cylindrical bottom electrode material is selected from W, Pt, Al, Ag or TiN, and the pore size is 50 to 100 nm; the method of forming the cylindrical bottom electrode includes sputtering or chemical vapor deposition.

3. The preparation method according to claim 1, characterized in that: In the step (2), the material of the second dielectric layer is selected from SiO2 or SiN, and the thickness is 150nm to 270nm; the second dielectric layer is formed by chemical vapor deposition, and the deposition temperature is not higher than 400°C; the groove is etched by reactive ion etching or plasma coupled etching; the width of the groove is 200nm to 400nm; and the verticality of the side wall is 70° to 90°.

4. The preparation method according to claim 1, characterized in that: In the step (3), before the phase change material layer is formed, the wafer after the step (2) is subjected to soft etching pretreatment by ICP etching; the phase change material layer is formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition; the material of the phase change material layer is selected from In x Ge y Sb z Te (1-x-y-z) , u Sb v Te (1-u-v) or C x Ge y Sb z Te (1-x-y-z) , wherein 0≤u<1, 0≤v<1, 0≤x<1, 0≤y<1, 0≤z<1, u+v≤1, x+y+z≤1; the thickness of the phase change film outside the trench is 20nm~80nm, and the thickness of the phase change film on the inner side wall of the trench is 10nm~50nm; the back etching includes RIE or ICP etching.

5. The preparation method according to claim 1, characterized in that: In the step (4), the growth method of the third dielectric layer and the fourth dielectric layer includes physical vapor deposition, chemical vapor deposition or atomic layer deposition; the material of the third dielectric layer is SiN, with a thickness of 5 to 20 nm; the material of the fourth dielectric layer is SiO2; and the polishing is chemical mechanical polishing.

6. The preparation method according to claim 1, characterized in that: The growth method of the conductive film layer in step (5) includes physical vapor deposition or chemical vapor deposition; the conductive film layer material is TiN, and the thickness is 30-40nm; the center line of the conductive line is located directly above the center line of the sidewall phase change material, and the width of the conductive line is 180-250nm.

7. The preparation method according to claim 1, characterized in that: In the step (6), the material of the fifth dielectric layer is SiN with a thickness of 10-20 nm; the material of the sixth dielectric layer is SiO2; and the growth method of the fifth dielectric layer and the sixth dielectric layer is chemical vapor deposition.

8. The preparation method according to claim 1, characterized in that: In the step (7), the photolithography adopts immersion exposure; The etching is performed by ICP etching; the aperture of the circular hole is 50nm to 100nm; the lower surface of the circular hole is in contact with the upper surface of the conductive line; the method of filling the conductive material is physical vapor deposition; the conductive material includes W, TiN, Al / Cu alloy or Ag.

9. A phase change memory prepared by the preparation method as claimed in claim 1.

10. Use of the phase change memory according to claim 9 in a fixed-line or wireless communication device.

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