Preparation method of air insulation layer based on back-to-back integration and semiconductor device

Abstract

The present invention belongs to the field of semiconductor device preparation, and specifically relates to a method for preparing an air insulation layer based on back-to-back integration and a semiconductor device, wherein the method for preparing the air insulation layer comprises the following steps: Step 1: sequentially performing a silicon photonic front-end process and a silicon photonic back-end process on a first SOI wafer, wherein the back-end process does not include making a thermal adjustment electrode; bonding with a carrier wafer; and removing the silicon substrate of the first SOI wafer; Step 2: etching and hollowing out to form an air insulation layer, bonding an epitaxial wafer to the first wafer, wherein the epitaxial wafer isolates the air insulation layer from the outside to form a closed cavity. The air insulation layer formed by the present invention can reduce the complexity of the process design while reducing the additional power consumption brought by the thermal adjustment device, and at the same time, improve the stability of the semiconductor device without affecting the subsequent process and packaging; the size and depth controllability of the formed air insulation layer are increased, thereby improving the process reliability.

Description

Technical Field

[0001] The invention relates to the field of semiconductor device preparation, and in particular to a method for preparing an air insulation layer based on back-to-back integration and a semiconductor device. Background Art

[0002] The silicon-on-insulator (SOI) silicon photonics process itself has a relatively complete set of optical component systems, including various passive devices, electro-optic modulators, and photodetectors. Among them, some devices are sensitive to temperature and have low process tolerances, and usually need to be calibrated through thermo-optical modulation. Thermo-optical modulation is one of the important modulation methods in silicon-based optoelectronic technology, and the devices that require thermo-optical modulation are thermal tuning devices. Thermo-optical modulation will bring additional power consumption, and the high power consumption of thermal tuning will affect the overall power consumption of the system. Existing research has slowed down the heat diffusion rate by partially hollowing out / bottom hollowing out to form an air insulation layer, thereby reducing the power consumption of thermal tuning devices.

[0003] In the prior art, in the silicon photonics process with an air insulation layer, the first step is the silicon photonics front-end process, the second step is the silicon photonics back-end process (including the preparation of thermal adjustment electrodes), and the third step is "vertical deep etching + horizontal hollowing" to form an air insulation layer. The formation of the air insulation layer is the last process. Problems with the above process methods: 1. When forming the air insulation layer, it is necessary to avoid all metal wiring that has been prepared in the silicon photonics back-end process, which increases the complexity of the process design; 2. After the air insulation layer is formed, it will be exposed to the outside in the form of a large-area open cavity, affecting the stability of the device. This large-area suspended structure similar to MEMS requires high-isolation packaging, which increases the difficulty and cost of packaging. Summary of the invention

[0004] In order to solve all or part of the above-mentioned technical problems, the purpose of the present invention is to provide a method for preparing an air insulation layer based on back-to-back integration and a semiconductor device, wherein the formed air insulation layer can reduce the additional power consumption caused by the thermal adjustment device while reducing the complexity of the process design, and at the same time, improve the stability of the semiconductor device without affecting subsequent processes and packaging; the size and depth controllability of the formed air insulation layer are increased, thereby improving process reliability.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides a method for preparing an air insulation layer based on back integration, comprising the following steps:

[0007] Step 1: sequentially performing silicon photonic front-end process and silicon photonic back-end process on the first SOI wafer, wherein the back-end process does not include making a thermal adjustment electrode; bonding with a carrier wafer; and removing the silicon substrate of the first SOI wafer;

[0008] Step 2: Etching and hollowing out to form an air insulation layer, bonding the epitaxial wafer to the first wafer, and the epitaxial wafer isolating the air insulation layer from the outside to form a closed cavity.

[0009] In the present invention, in the silicon photonic process of semiconductor devices, before the epitaxial wafer is bonded to the wafer, an air insulation layer is formed by etching and hollowing out in the area where heat diffusion needs to be slowed down. The air insulation layer has an obstructive effect on heat conduction, which can slow down the heat diffusion rate, thereby reducing the additional power consumption caused by thermal light modulation. At the same time, by utilizing the process of bonding the epitaxial wafer to the wafer, the air insulation layer is isolated from the outside world through the epitaxial wafer to form a closed cavity, so that the air insulation layer is no longer exposed to the outside, thereby improving the stability of the semiconductor device; and there is no need to perform high-isolation packaging on the air insulation layer later, so it will not affect the subsequent process and packaging, thereby reducing the difficulty and cost of packaging.

[0010] The SOI wafer used in the present invention has a top silicon layer, an insulating layer and a silicon substrate, and can be used for the back integration process of semiconductor devices. Silicon is an indirect bandgap material and cannot emit light directly. Therefore, the integration of silicon-based light sources is an important challenge for the development of silicon light. In order to solve the problem that silicon cannot emit light directly, the present invention uses heterogeneous materials with excellent luminescence performance as optoelectronic application materials. However, the lattice constant mismatch between heterogeneous materials and silicon is large, and the heterogeneous materials obtained by direct epitaxial growth on silicon have many defects and poor quality, making it difficult to prepare semiconductor devices that meet the requirements. Therefore, the present invention uses epitaxial wafers (mainly formed by heterogeneous materials) to bond with silicon-based optical devices to hybrid integrated semiconductor devices, which can overcome the shortcomings of low luminescence efficiency and weak photoelectric effect of silicon-based materials, and can also effectively reduce packaging costs, improve yield and reliability.

[0011] The method further includes step 3: performing a patterning process on the epitaxial wafer to produce a target device. The target device may include devices such as lasers, and the epitaxial wafer material used may be determined according to the type of the target device. The epitaxial wafer may be photolithographically etched to form a main structure such as a laser. The epitaxial wafer includes multiple material layers, and the composition of the material layers is adjusted and selected as needed.

[0012] The method further includes step 4: making a thermal adjustment electrode and making a subsequent metal lead electrode. A thermal adjustment electrode can be formed on a portion of the upper surface of the epitaxial wafer to overlap the thermal adjustment device in a vertical direction. The thermal adjustment electrode is made after the air insulation layer is formed and sealed in step 2. Therefore, the formation process of the air insulation layer is not affected by the electrode, especially the thermal adjustment electrode, and the metal wiring, which can reduce the difficulty of process design.

[0013] After the thermal adjustment electrode is formed, a second dielectric layer is filled above the first wafer and the epitaxial wafer, and the thermal adjustment electrode is led out by arranging a metal through hole in the second dielectric layer.

[0014] In step 1, the front-end process includes etching the top silicon layer of the first wafer to form a thermal tuning device, and forming a dielectric layer covering the thermal tuning device. The thermal tuning device is a device that needs to perform thermal light modulation, and the formed air insulation layer is used to slow down the heat diffusion around the thermal tuning device. The dielectric layer can be a silicon dioxide dielectric layer, as the first dielectric layer, or it can be silicon nitride or silicon oxynitride, etc.

[0015] The thermal adjustment device is a silicon-based micro-ring resonator. The semiconductor device formed based on the silicon-based micro-ring resonator has a higher integration level than the traditional silicon-based optical device.

[0016] In step 1, the front-end process also includes etching the top silicon of the first wafer to form an active device, and covering the top of the active device with the dielectric layer; the back-end process includes interconnecting the active device with a metal circuit. The material of the metal circuit includes but is not limited to tungsten or copper material. The front-end process may also include etching the top silicon of the first wafer to form a passive device. The active device includes one or more of a modulator, a detector and an optical amplifier. The passive device includes a silicon waveguide and a silicon grating, etc.

[0017] In step 2, the method for forming the air insulation layer includes longitudinally etching the dielectric layer where the heat regulating device is located. Longitudinal deep etching is performed in the area where heat diffusion needs to be slowed down to form a longitudinal air cavity, thereby achieving the effect of local insulation. The longitudinal air cavity may be one or more. The longitudinal etching may be performed to the dielectric layer or to the carrier wafer.

[0018] After the dielectric layer where the heat regulating device is located is etched longitudinally, it is etched transversely to hollow out the bottom so that the bottom is connected. When multiple longitudinal air cavities are formed, the bottoms of the multiple longitudinal air cavities are hollowed out so that the bottoms of the longitudinal air cavities are connected, and the area where the heat diffusion needs to be slowed down becomes a suspended structure. When only one longitudinal air cavity is formed, the bottom of the longitudinal air cavity can also be etched and hollowed out, and the area where the heat diffusion needs to be slowed down does not become a suspended structure.

[0019] The processes of the longitudinal etching and the transverse etching are dry etching or wet etching. When performing transverse etching, an ultra-high selectivity dry etching process can be adopted, and the selectivity of the ultra-high selectivity dry etching is ≥1000.

[0020] The method for forming the air insulation layer comprises the following steps:

[0021] Pre-step: before bonding with the carrier wafer, the dielectric layer where the thermal adjustment device is located is longitudinally etched to the silicon substrate of the first wafer to form a longitudinal groove, and the longitudinal groove is filled with a predetermined material; after the predetermined material is filled, a protective layer covering the predetermined material is formed;

[0022] Forming step: After bonding with the carrier wafer, the silicon substrate and the predetermined material are removed by a wet etching process to form an air insulation layer. The longitudinal grooves are first etched, and the air insulation layer can be easily formed by filling with the predetermined material. The shape, size and depth of the air insulation layer can be easily adjusted, which greatly reduces the complexity of the preparation process of the air insulation layer.

[0023] The purpose of longitudinally etching to the silicon substrate of the first wafer is to facilitate the subsequent removal of the silicon substrate and the predetermined material by a wet etching process, so that the silicon substrate and the predetermined material can be removed simultaneously by one wet etching step.

[0024] The filling area of ​​the predetermined material is inside the longitudinal groove, or inside and above the longitudinal groove. When the predetermined material is only filled inside the longitudinal groove, the formed air insulation layer is one or more longitudinal air cavities. When the predetermined material is filled inside and above the longitudinal groove, after the predetermined material located above the longitudinal groove is removed, a transverse air cavity is formed, and the longitudinal air cavity can be penetrated.

[0025] The predetermined material is selected from one or more of single crystal silicon, polycrystalline silicon and amorphous silicon.

[0026] The epitaxial wafer is made of materials that are not suitable for direct epitaxial growth on the original substrate, such as III-V compounds or lithium niobate. For example, when the semiconductor device to be prepared is a semiconductor laser, III-V compounds can be used as epitaxial wafer materials; when the semiconductor device to be prepared is a semiconductor modulator, lithium niobate can be used as epitaxial wafer material, such as lithium niobate film.

[0027] The present invention also provides a semiconductor device, the semiconductor device has an air insulation layer, and the air insulation layer is prepared by the above-mentioned preparation method. The semiconductor device also includes: a thermal adjustment device formed on the first wafer; an epitaxial wafer, isolating the air insulation layer from the outside to form a closed cavity. The semiconductor device provided by the present invention has low overall power consumption and high stability, and the thermal adjustment device in the semiconductor device is a low-power silicon photonic thermal adjustment device, which can be compatible with silicon photonic mass production processes.

[0028] Compared with the prior art, the present invention has at least the following beneficial effects:

[0029] 1. In the present invention, in the silicon photonic process of semiconductor devices, before the epitaxial wafer is bonded to the wafer, an air insulation layer is formed by etching and hollowing out the area where heat diffusion needs to be slowed down. The air insulation layer has an inhibitory effect on heat conduction, which can slow down the speed of heat diffusion, thereby reducing the additional power consumption caused by thermo-optical modulation. At the same time, by utilizing the process of bonding the epitaxial wafer to the wafer, the epitaxial wafer is covered on top of the air insulation layer, so that the air insulation layer is isolated from the outside to form a closed cavity. The air insulation layer is no longer exposed to the outside, which improves the stability of the semiconductor device; and there is no need to perform high-isolation packaging on the air insulation layer later, so it will not affect the subsequent process and packaging, reducing the difficulty and cost of packaging.

[0030] 2. The manufacturing process of the heat-adjusting electrode in the present invention is after the air insulation layer is formed and sealed in step 2. Therefore, the formation process of the air insulation layer is not affected by the electrode, especially the heat-adjusting electrode and the metal wiring, which can reduce the difficulty of process design. The present invention can adjust the size, depth and shape of the air insulation layer as needed, increase the controllability of the air insulation layer formation process, improve the process reliability, and the adjustment process will not be affected by the position of the electrode, especially the heat-adjusting electrode and the metal wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 This is a flow chart of a method for preparing a semiconductor device in Embodiment 1 of the present invention.

[0033] Figure 2 It is a process schematic diagram of a method for preparing a semiconductor device in Embodiment 1 of the present invention.

[0034] Figure 3 It is a schematic diagram of the structure of the semiconductor device prepared in Example 1 of the present invention.

[0035] Figure 4 This is a flow chart of a method for preparing a semiconductor device in Embodiment 2 of the present invention.

[0036] Figure 5 It is a process schematic diagram of a method for preparing a semiconductor device in Embodiment 2 of the present invention.

[0037] Figure 6 It is a schematic diagram of the structure of the semiconductor device prepared in the second embodiment of the present invention.

[0038] Figure 7It is a top view of the microring resonator in Embodiment 1 and Embodiment 2 of the present invention.

[0039] Figure 8 It is a top view of the microring resonator after the air insulation layer is formed in the first and second embodiments of the present invention.

[0040] Fig. 9 It is a top view of the microring resonator after the thermal adjustment electrode is prepared in Example 1 and Example 2 of the present invention.

[0041] Fig.10 This is a top view of the microring resonator after being filled with a predetermined material in the second embodiment of the present invention.

[0042] Figure numerals: 100-SOI wafer; 110-silicon substrate; 120-insulating layer; 130-top silicon; 140-first dielectric layer; 150-protective layer; 200-microring resonator; 210-air insulation layer; 220-longitudinal groove; 230-predetermined material; 300-silicon photonic devices supporting the laser; 400-other silicon photonic active devices; 410-metal circuit; 500-other silicon photonic passive devices; 600-carrier wafer; 700-epitaxial wafer; 710-laser electrode; 720-thermal adjustment electrode; 730-second dielectric layer; 740-metal through hole; 750-laser. DETAILED DESCRIPTION

[0043] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The steps in the following embodiments do not correspond one to one with the steps in the content of the invention. In the following specific implementation, the preparation of a semiconductor laser is taken as an example to illustrate the content and principle of the technical solution of the present invention. It should be noted that the technical solution of the present invention can also be used to prepare other semiconductor devices that require an air insulation layer, such as detectors, modulators, and optical amplifiers. The semiconductor laser in the following specific implementation is a silicon-based microring tunable laser prepared based on a silicon-based microring resonator, wherein the silicon-based microring resonator is a device that requires thermal optical modulation, i.e., a type of thermal tuning device. In addition, the technical solution of the present invention can also be used to prepare semiconductor devices including other thermal regulation devices.

[0045] Silicon-based microring structures have the advantages of small size and easy integration. Therefore, optoelectronic modulators, signal differentiators, phase shifters, wavelength converters and other devices can be formed based on microring / microcavity structures, and the integration of the formed devices is better than that of traditional silicon-based optical devices. Microring resonators are often used in wavelength tunable lasers due to their filtering characteristics. Depending on the microring material, they can be divided into III-V group (InP, GaAs, etc.) microring lasers and IV group (Si, Ge, etc.) microring lasers. Among them, the advantage of III-V group microrings is that they can be monolithically integrated with gain elements, which makes it easy to assemble devices later, but the production cost is relatively high; the advantage of IV group microrings is that they are low cost, but they need to be hybrid integrated with III-V group gain chips.

[0046] The III-V materials are responsible for providing gain output, and the IV microring resonator is responsible for mode selection and wavelength tuning. During the tuning process, the refractive index of the IV material is changed mainly by local electrode heating, thereby changing the lasing wavelength. In the following embodiments, IV silicon-based microring resonators, epitaxial wafers formed by III-V compounds, etc. are used for hybrid integration to prepare semiconductor lasers.

[0047] Silicon-based microring structures are sensitive to temperature and have low process tolerances, and often require thermal adjustment for calibration. The additional power consumption caused by thermal adjustment is 1-4pJ. For short-distance transmission on or between chips, the overall power consumption should be controlled below 1pJ. In order to reduce the overall power consumption, existing research has slowed down the heat diffusion rate by partially hollowing out / hollowing out the bottom to form an air insulation layer, which can reduce the power consumption of silicon-based microring structures by at least 10 times.

[0048] Embodiment 1

[0049] This embodiment provides a method for preparing an air insulation layer based on back integration and a semiconductor device. Taking a silicon-based micro-ring tunable laser as an example, refer to Figure 1-3 , Figure 7-9 The method for preparing the silicon-based microring tunable laser comprises the following steps:

[0050] An SOI wafer 100 is provided, and the SOI wafer 100 includes a silicon substrate 110, an insulating layer 120 and a top silicon 130; the material of the insulating layer 120 is silicon dioxide. In fact, the substrate material can also be selected from other types of materials, such as germanium silicon materials, etc., as long as it can be removed in subsequent steps. The material of the insulating layer 120 can also be silicon nitride or silicon nitride oxide. The insulating layer 120 can achieve full dielectric isolation between the top silicon 130 and the silicon substrate 110 to reduce parasitic capacitance and improve the operating speed. In addition, since the parasitic capacitance is reduced, leakage can also be reduced, and the power consumption of the device implemented on the top silicon 130 can be reduced. In addition, using the SOI wafer 100 to implement the silicon photonic process can also eliminate the latch effect, suppress the interference of the pulse current in the silicon substrate 110 on the top silicon 130, reduce soft errors, etc., and it can also be compatible with the existing silicon photonic process.

[0051] S1. The top silicon 130 of the SOI wafer 100 is patterned, photolithographically etched, and formed into micro-ring resonators 200, silicon waveguides and distributed Bragg reflection gratings and other silicon optical devices 300 that are matched with lasers, other silicon optical active devices 400, and other silicon optical passive devices 500. In other embodiments, active devices or passive devices such as modulators, filters, photodetectors, and optical amplifiers may also be formed. Etching includes dry etching or wet etching.

[0052] S2, a silicon dioxide first dielectric layer 140 is covered on the microring resonator 200, the silicon optical device 300 supporting the laser, other silicon optical active devices 400, and other silicon optical passive devices 500, and then a planarization process is performed. In other embodiments, the material of the first dielectric layer 140 can also be silicon nitride or silicon oxynitride.

[0053] S3. Interconnecting metal circuits 410 on other silicon photonic active devices 400 . The material of the metal circuits 410 includes but is not limited to tungsten or copper.

[0054] S4, flipping and bonding the front side of the SOI wafer 100 and the carrier wafer 600 at room temperature, and annealing at high temperature.

[0055] S5, thinning and removing the silicon substrate 110 on the SOI wafer 100. This embodiment uses a backside integration method to complete the preparation of the semiconductor device.

[0056] S6, longitudinally deeply etch the area where the microring resonator 200 is located, and then etch to the carrier wafer 600, and then hollow out the carrier wafer 600 laterally to make the bottom connected, forming an air insulation layer 210. The longitudinal deep etching is dry etching, and the lateral hollowing is wet etching. In other embodiments, an ultra-high selectivity dry etching process with a selectivity ≥ 1000 can also be used for lateral hollowing. Figure 7 and Figure 8 , vertical deep etching is performed in the middle and on both sides of the microring of the microring resonator 200 to form three vertical air cavities, and the bottoms of the three vertical air cavities are hollowed out so that the bottoms of the vertical air cavities are connected, and the microring resonator 200 and the first dielectric layer 140 material around it as a whole form a suspended structure with the carrier wafer 600. In other embodiments, only vertical deep etching can be performed to form the vertical air cavities without horizontal hollowing out at the bottom of the vertical air cavities. In this case, the microring resonator 200 and the first dielectric layer 140 material around it do not form a suspended structure with the carrier wafer 600.

[0057] During the longitudinal etching and bottom hollowing, the electrodes, especially the thermal adjustment electrodes and the metal wiring have not been prepared yet. Therefore, the range of etching and hollowing can be adjusted as needed, thereby affecting the size, depth and shape of the air insulation layer 210. During the longitudinal etching, the etching depth can be controlled. When the etching depth is small, the air insulation layer 210 is formed in the first dielectric layer 140 without contacting the carrier wafer 600, so that a suspended structure is formed between the bottom of the microring resonator 200 and the first dielectric layer 140. The controllability of the size and depth of the air insulation layer 210 is increased, which improves the process reliability.

[0058] S7. Bond the indium phosphide epitaxial wafer 700 to the insulating layer 120 in the SOI wafer 100 at room temperature. The bonding position is only in the area where the laser needs to be prepared, that is, above the microring resonator 200 and the silicon waveguide and distributed Bragg reflection grating and other silicon optical devices 300 that are matched with the laser. The indium phosphide epitaxial wafer 700 isolates the air insulation layer 210 from the outside to form a closed cavity.

[0059] In this embodiment, the material of the epitaxial wafer 700 is indium phosphide in the III-V group compound semiconductor. In other embodiments, aluminum phosphide, gallium phosphide, aluminum arsenide, gallium arsenide, indium arsenide, aluminum nitride, gallium nitride, indium nitride, and their ternary and quaternary compounds can also be used. When preparing other semiconductor devices such as modulators, lithium niobate film can be selected as the epitaxial wafer 700.

[0060] The indium phosphide epitaxial wafer 700 isolates the air insulation layer 210 from the outside to form a closed cavity, which can improve the stability of the semiconductor device without affecting subsequent processes and packaging.

[0061] S8. Perform high temperature annealing on the indium phosphide epitaxial wafer 700 to thin it and perform planarization treatment.

[0062] S9, patterning the indium phosphide epitaxial wafer 700 to form a laser 750. Before bonding the epitaxial wafer 700 to the insulating layer 120 in the SOI wafer 100, at least one functional film is formed on the epitaxial wafer 700 for patterning to form a desired active device such as the laser 750.

[0063] S10, depositing a laser electrode 710 (such as gold, platinum and other materials) on an indium phosphide epitaxial wafer 700 above a silicon optical device 300 supporting a laser 750, and depositing a thermal adjustment electrode 720 (such as titanium nitride and other materials) of the microring resonator 200 on an indium phosphide epitaxial wafer 700 above the microring resonator 200. The thermal adjustment electrode 720 and the microring resonator 200 overlap in a vertical direction. In other embodiments, the laser electrode 710 and the microring resonator thermal adjustment electrode 720 may also be formed by etching a metal layer in the epitaxial wafer 700.

[0064] S11, silicon dioxide is filled on the SOI wafer 100 bonded with the indium phosphide epitaxial wafer 700 as the second dielectric layer 730, and a planarization process is performed. In other embodiments, the material of the second dielectric layer 730 may also be silicon nitride or silicon oxynitride.

[0065] S12, opening a metal through hole 740 to lead out the electrodes of the laser 750, the microring resonator 200 and other active devices 400. The preparation method of the metal through hole 740 is to form a plurality of back holes by etching, and the back holes extend from the surface of the silicon dioxide dielectric layer away from the epitaxial wafer 700 to the corresponding electrodes respectively, and are filled with a conductive material (such as tungsten or copper) to provide electrical connectivity.

[0066] The silicon-based micro-ring tunable laser prepared according to the above preparation method has a structure referring to Figure 3, including a carrier wafer 600, a microring resonator 200 in a first dielectric layer 140 above the carrier wafer 600, silicon photonic devices 300 such as optical waveguides and gratings that are compatible with the laser, other silicon photonic active devices 400 and other silicon photonic passive devices 500, and an air insulation layer 210 is formed around the microring resonator 200. Other silicon photonic active devices 400 are connected to metal circuits 410. An epitaxial wafer 700 is formed above the microring resonator 200 and silicon photonic devices 300 such as optical waveguides and gratings that are compatible with the laser, and a laser 750 is formed on the epitaxial wafer 700. A thermal tuning electrode 720 and a laser electrode 710 are provided on the epitaxial wafer 700 at the overlapping part in the vertical direction with the microring resonator 200 and the silicon optical devices 300 supporting the laser, such as optical waveguides and gratings. A second dielectric layer 730 is also provided on the epitaxial wafer 700. Metal through holes 740 are opened inside the first dielectric layer 140 and the second dielectric layer 730 to lead out the laser electrode 710, the thermal tuning electrode 720 and the electrodes of other silicon optical active devices 400.

[0067] Embodiment 2

[0068] This embodiment provides a method for preparing an air insulation layer based on back integration and a semiconductor device. Taking a silicon-based micro-ring tunable laser as an example, refer to Figure 4-10 The method for preparing the silicon-based microring tunable laser comprises the following steps:

[0069] An SOI wafer 100 is provided. The SOI wafer 100 includes a silicon substrate 110, an insulating layer 120 and a top silicon layer 130. The insulating layer 120 is made of silicon dioxide.

[0070] S1. The top silicon 130 of the SOI wafer 100 is patterned, photolithographically etched, and formed into microring resonators 200, silicon waveguides, distributed Bragg reflection gratings, and other silicon optical devices 300 that are compatible with the laser, other silicon optical active devices 400, and other silicon optical passive devices 500.

[0071] S2, a first dielectric layer 140 of silicon dioxide is covered on the microring resonator 200, the silicon optical device 300 supporting the laser, other silicon optical active devices 400, and other silicon optical passive devices 500, and then a planarization process is performed. The thickness of the first dielectric layer 140 in S2 of this embodiment directly affects the depth of the air insulation layer 210.

[0072] S3, longitudinally etching the middle and both sides of the microring of the microring resonator 200 to form longitudinal grooves 220. The etching method can be dry etching or wet etching. This step is a preliminary step A for forming the air insulation layer 210. The size of the longitudinal grooves 220 formed by the longitudinal etching directly affects the size of the air insulation layer 210.

[0073] S4, filling single crystal silicon as the predetermined material 230 inside and above the longitudinal groove 220, and performing a graphic process. This step is a pre-step B for forming the air insulation layer 210. The shape of the air insulation layer 210 is formed by a graphic process. In this embodiment, the predetermined material 230 is filled inside and above the longitudinal groove 220, and both a longitudinal air cavity and a transverse air cavity are formed when hollowing out later. In other embodiments, the predetermined material 230 can also be filled only inside the longitudinal groove 220, and only a longitudinal air cavity is formed when hollowing out later. The filling position of the predetermined material 230 also directly affects the shape of the air insulation layer 210. The predetermined material 230 in this embodiment uses single crystal silicon, and in other embodiments, polycrystalline silicon or amorphous silicon and other materials can also be used. The predetermined material 230 uses single crystal silicon, polycrystalline silicon or amorphous silicon and other materials, which are the same or similar to the material of the silicon substrate 110 on the SOI wafer 100, so that the silicon substrate 110 and the predetermined material 230 can be removed simultaneously in one step later.

[0074] S5, after filling the predetermined single crystal silicon material 230, continue to fill silicon dioxide as a protective layer 150 on the SOI wafer 100, and perform a planarization process to cover the predetermined single crystal silicon material 230. This step is a preliminary step C of forming the air insulation layer 210.

[0075] S6. Interconnecting metal circuits 410 on other silicon photonic active devices 400. The material of the metal circuits 410 includes but is not limited to tungsten or copper.

[0076] S7, flipping and bonding the front side of the SOI wafer 100 and the carrier wafer 600 at room temperature, and annealing at high temperature.

[0077] S8, thinning the silicon substrate 110 on the SOI wafer 100, removing the silicon substrate 110 and the predetermined single crystal silicon material 230 by a wet etching process, and forming an air insulation layer 210. The silicon substrate 110 and the predetermined material 230 are removed by using the high selectivity of tetramethylammonium hydroxide (TMAH). The air insulation layer 210 is formed in the middle, both sides and part of the bottom of the microring of the microring resonator 200, so that a suspended structure is formed between the bottom of the microring resonator 200 and the carrier wafer 600. In other embodiments, when the thickness of the first dielectric layer 140, the size of the longitudinal groove 220 and the filling position of the predetermined material 230 in S2 of this embodiment are changed, the depth, size and shape of the formed air insulation layer 210 will change accordingly, which increases the controllability and improves the process reliability.

[0078] S9. Bond the indium phosphide epitaxial wafer 700 to the insulating layer 120 in the SOI wafer 100 at room temperature. The bonding position is only in the area where the laser needs to be prepared, that is, above the microring resonator 200 and the silicon waveguide and distributed Bragg reflection grating and other silicon optical devices 300 that are matched with the laser. The indium phosphide epitaxial wafer 700 isolates the air insulation layer 210 from the outside to form a closed cavity.

[0079] S10, performing high temperature annealing on the indium phosphide epitaxial wafer 700, thinning and planarizing.

[0080] S11 , patterning the indium phosphide epitaxial wafer 700 to form a laser 750 . Before bonding the epitaxial wafer 700 to the insulating layer 120 in the SOI wafer 100 , at least one functional film is formed on the epitaxial wafer 700 for patterning to form a desired active device such as the laser 750 .

[0081] S12, depositing a laser electrode 710 (such as gold, platinum and other materials) onto an indium phosphide epitaxial wafer 700 above a silicon optical device 300 supporting the laser, and depositing a thermal adjustment electrode 720 (such as titanium nitride and other materials) of the microring resonator 200 onto the indium phosphide epitaxial wafer 700 above the microring resonator 200. The thermal adjustment electrode 720 and the microring resonator 200 overlap in a vertical direction.

[0082] S13, filling silicon dioxide as the second dielectric layer 730 on the SOI wafer 100 bonded with the indium phosphide epitaxial wafer 700, and performing a planarization process.

[0083] S14, opening a metal through hole 740 to lead out the electrodes of the laser 750, the microring resonator 200 and other active devices 400.

[0084] The silicon-based micro-ring tunable laser prepared according to the above preparation method has a structure referring to Figure 6, including a carrier wafer 600, a microring resonator 200 in a first dielectric layer 140 above the carrier wafer 600, silicon photonic devices 300 such as optical waveguides and gratings that are compatible with the laser, other silicon photonic active devices 400 and other silicon photonic passive devices 500. An air insulation layer 210 is formed around the microring resonator 200, a protective layer 150 is formed above the air insulation layer 210, and other silicon photonic active devices 400 are connected to metal circuits 410. An epitaxial wafer 700 is formed above the microring resonator 200 and the silicon photonic devices 300 such as optical waveguides and gratings that are compatible with the laser, and a laser 750 is formed on the epitaxial wafer 700. A thermal tuning electrode 720 and a laser electrode 710 are provided on the epitaxial wafer 700 at the overlapping part in the vertical direction with the microring resonator 200 and the silicon optical devices 300 supporting the laser, such as optical waveguides and gratings. A second dielectric layer 730 is also provided on the epitaxial wafer 700. Metal through holes 740 are provided inside the first dielectric layer 140 and the second dielectric layer 730 and the protective layer 150 to lead out the laser electrode 710, the thermal tuning electrode 720 and the electrodes of other silicon optical active devices 400.

[0085] For steps in Example 2 that are similar or identical to those in Example 1, reference can be made to the specific contents in Example 1.

[0086] The technical solution of the present invention can be used to prepare various semiconductor devices that require an air insulation layer, and is not limited to the silicon-based microring tunable laser 750 in the above embodiment that requires an air insulation layer to reduce thermal power consumption. The thermal tuning device in the technical solution of the present invention is not limited to the microring resonator 200, but can also be other types of resonators or other devices that require thermal optical modulation.

[0087] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing an air insulation layer based on back integration, characterized in that: The following steps are involved: Step 1: sequentially performing a silicon photonic front-end process and a silicon photonic back-end process on a first SOI wafer, wherein the back-end process does not include making a thermal adjustment electrode; the front-end process includes etching the top silicon layer of the first wafer to form a thermal adjustment device, and forming a dielectric layer covering the thermal adjustment device; and bonding with a carrier wafer; Removing the silicon substrate of the first SOI wafer; Step 2: Etching to hollow out an air insulation layer, bonding the epitaxial wafer to the first wafer, the epitaxial wafer isolating the air insulation layer from the outside to form a closed cavity, and the method for forming the air insulation layer includes longitudinally etching the dielectric layer where the thermal adjustment device is located.

2. The method for preparing the air insulation layer based on back integration according to claim 1, characterized in that: The method also includes step three: performing a patterning process on the epitaxial wafer to produce a target device.

3. The method for preparing the air insulation layer based on back integration according to claim 2, characterized in that: The method also includes step 4: making a thermal adjustment electrode and making a subsequent metal lead-out electrode.

4. The method for preparing the air insulation layer based on back integration according to claim 1, characterized in that: The thermal adjustment device is a silicon-based microring resonator.

5. The method for preparing the air insulation layer based on back integration according to claim 1, characterized in that: In the step 1, the front-end process also includes etching the top silicon of the first wafer to form an active device, and covering the active device with the dielectric layer; the back-end process includes interconnecting the active device with a metal circuit.

6. The method for preparing the air insulation layer based on back integration according to claim 1, characterized in that: After the dielectric layer where the heat regulating device is located is etched longitudinally, it is etched transversely to hollow it out so that the bottom is connected.

7. The method for preparing the air insulation layer based on back integration according to claim 6, characterized in that: The processes of the longitudinal etching and the lateral etching are dry etching or wet etching.

8. The method for preparing the air insulation layer based on back integration according to claim 1, characterized in that: The method for forming the air insulation layer comprises the following steps: Pre-step: before bonding with the carrier wafer, the dielectric layer where the thermal adjustment device is located is longitudinally etched to the silicon substrate of the first wafer to form a longitudinal groove, and the longitudinal groove is filled with a predetermined material; after the predetermined material is filled, a protective layer covering the predetermined material is formed; Forming step: After bonding with the carrier wafer, the silicon substrate and the predetermined material are removed by a wet etching process to form an air insulation layer.

9. The method for preparing the air insulation layer based on back integration according to claim 8, characterized in that: The filling area of ​​the predetermined material is inside the longitudinal groove, or inside and above the longitudinal groove.

10. The method for preparing the air insulation layer based on back integration according to claim 8, characterized in that: The predetermined material is selected from one or more of single crystal silicon, polycrystalline silicon and amorphous silicon.

11. A semiconductor device, characterized in that: The semiconductor device has an air insulation layer, and the air insulation layer is prepared by the method for preparing an air insulation layer based on back-to-back integration according to any one of claims 1 to 10.

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