A bridge arm crosstalk suppression circuit and method

Abstract

An embodiment of the present application provides a bridge arm crosstalk suppression circuit and method, which includes: a first output end of a first driver chip is connected to a first input end of a first negative voltage regulation circuit; a second output end of the first driver chip is connected to the gate of an upper bridge arm; a second input end of the first negative voltage regulation circuit is respectively connected to the gate of the upper bridge arm; an output end of the first negative voltage regulation circuit is connected to the source of the upper bridge arm; a first negative voltage regulation circuit is used to be sensitive to changes in the gate voltage of the upper bridge arm, and to adjust the negative voltage between the gate and the source of the upper bridge arm in response to changes in the gate voltage of the upper bridge arm to suppress crosstalk to the upper bridge arm; a first output end of a second driver chip is connected to a first input end of a second negative voltage regulation circuit; a second output end of the second driver chip is connected to the gate of a lower bridge arm; a second input end of the second negative voltage regulation circuit is respectively connected to the gate of the lower bridge arm, and an output end of the second negative voltage regulation circuit is connected to the source of the lower bridge arm.

Description

Technical Field

[0001] The present application relates to the technical field of bridge arm crosstalk suppression, and in particular to a bridge arm crosstalk suppression circuit and method. Background Art

[0002] In the bridge arm crosstalk related technology, through the coordinated modulation between the two totem pole structures, a large negative voltage is applied between the gate and source of the switching tube when crosstalk occurs. The positive voltage spike caused by the crosstalk is superimposed on the large negative voltage to ensure that the voltage between the gate and source of the switching tube is below the threshold voltage; after the crosstalk ends, a smaller negative voltage is applied between the gate and source of the switching tube; it is necessary to provide an additional negative driving voltage and two totem pole structures for each switching tube silicon carbide metal oxide semiconductor field effect transistor (SiC Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET) in the bridge arm. The cost and complexity of the bridge arm crosstalk suppression circuit are high, and its practical value is limited. Summary of the Invention

[0003] The embodiments of the present application aim to provide a bridge arm crosstalk suppression circuit and method.

[0004] In a first aspect, an embodiment of the present application provides a bridge arm crosstalk suppression circuit, comprising:

[0005] An upper bridge arm, a lower bridge arm, a first driver chip and a first negative voltage regulating circuit corresponding to the upper bridge arm, and a second driver chip and a second negative voltage regulating circuit corresponding to the lower bridge arm;

[0006] The first output terminal of the first driver chip is connected to the first input terminal of the first negative voltage regulation circuit; the second output terminal of the first driver chip is connected to the gate of the upper bridge arm; the second input terminal of the first negative voltage regulation circuit is connected to the gate of the upper bridge arm; the output terminal of the first negative voltage regulation circuit is connected to the source of the upper bridge arm; the first negative voltage regulation circuit is used to be sensitive to the gate voltage change of the upper bridge arm and adjust the negative voltage between the gate and source of the upper bridge arm in response to the gate voltage change of the upper bridge arm to suppress crosstalk to the upper bridge arm;

[0007] The first output end of the second driver chip is connected to the first input end of the second negative voltage regulation circuit; the second output end of the second driver chip is connected to the gate of the lower bridge arm; the second input end of the second negative voltage regulation circuit is connected to the gate of the lower bridge arm; the output end of the second negative voltage regulation circuit is connected to the source of the lower bridge arm; the second negative voltage regulation circuit is used to be sensitive to the gate voltage change of the lower bridge arm, and adjust the negative voltage between the gate and source of the lower bridge arm in response to the gate voltage change of the lower bridge arm to suppress crosstalk to the lower bridge arm.

[0008] In a second aspect, an embodiment of the present application provides a bridge arm crosstalk suppression method, which is applied to the bridge arm crosstalk suppression circuit described above, and the method includes:

[0009] The first negative voltage regulating circuit is sensitive to a gate voltage change of the upper bridge arm, and in response to the gate voltage change of the upper bridge arm, regulates a negative voltage between the gate and the source of the upper bridge arm to suppress crosstalk to the upper bridge arm;

[0010] The second negative voltage regulating circuit is sensitive to the gate voltage change of the lower bridge arm, and in response to the gate voltage change of the lower bridge arm, regulates the negative voltage between the gate and the source of the lower bridge arm to suppress crosstalk to the lower bridge arm.

[0011] In an embodiment of the present application, a first negative voltage regulation circuit is set between the gate of the upper bridge arm and the first driver chip corresponding to the upper bridge arm, the first negative voltage regulation circuit is used to sense the gate voltage change of the upper bridge arm, and the negative voltage between the gate and the source of the upper bridge arm is adjusted in response to the gate voltage of the upper bridge arm to suppress crosstalk to the upper bridge arm; a second negative voltage regulation circuit is set between the gate of the lower bridge arm and the second driver chip corresponding to the lower bridge arm, the second negative voltage regulation circuit is used to sense the gate voltage change of the lower bridge arm, and the negative voltage between the gate and the source of the lower bridge arm is adjusted in response to the gate voltage of the lower bridge arm to suppress crosstalk to the lower bridge arm. When the upper bridge arm includes at least one upper switch tube connected in parallel and the lower bridge arm includes at least one lower switch tube connected in parallel, since only one first negative voltage regulation circuit needs to be configured for the upper bridge arm and only one second negative voltage regulation circuit needs to be configured for the lower bridge arm, there is no need to configure the first negative voltage regulation circuit for each upper switch tube in the upper bridge arm and the second negative voltage regulation circuit for each lower switch tube in the lower bridge arm, and there is no need to provide an additional negative drive circuit. Therefore, the cost and complexity of the circuit are low and the practical value is high.

[0012] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to illustrate the technical solutions of the present application.

[0014] Figure 1 A circuit diagram of a bridge structure composed of SiC MOSFETs in the related art;

[0015] Figure 2a for Figure 1 Schematic diagram of the voltage change curve across Q1 and Q2 when Q1 changes from the off state to the on state in the bridge structure shown;

[0016] Figure 2b for Figure 1 Schematic diagram of the voltage change curve across Q1 and Q2 when Q1 changes from the on state to the off state in the bridge structure shown;

[0017] Figure 3 A circuit diagram of a crosstalk suppression circuit for parallel SiC MOSFETs in the related art;

[0018] Figure 4 A circuit diagram of another crosstalk suppression circuit for parallel SiC MOSFETs in the related art;

[0019] Figure 5 A circuit diagram of another crosstalk suppression circuit for parallel SiC MOSFETs in the related art;

[0020] Figure 6 A schematic diagram of the structure of a bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0021] Figure 7 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0022] Figure 8 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0023] Figure 9 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0024] Figure 10 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0025] Figure 11 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0026] Figure 12 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application;

[0027] Figure 13 A crosstalk suppression circuit of a bridge structure composed of SiC MOSFETs provided in an embodiment of the present application;

[0028] Figure 14 for Figure 13 The working signal timing diagram of the crosstalk suppression circuit of the bridge structure shown;

[0029] Figure 15A crosstalk suppression circuit of a bridge structure composed of parallel SiC MOSFETs provided in an embodiment of the present application;

[0030] Figure 16 A schematic diagram of the implementation flow of a bridge arm crosstalk suppression method is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0031] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the embodiments provided herein are merely intended to explain the present application and are not intended to limit the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than providing all embodiments for implementing the present application. In the absence of conflict, the technical solutions described in the embodiments of the present application may be implemented in any combination.

[0032] It should be noted that, in the embodiments of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or apparatus comprising a series of elements includes not only the elements explicitly stated, but also other elements not explicitly listed, or also includes elements inherent to the implementation of the method or apparatus. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other related elements (such as steps in the method or units in the apparatus, for example, a unit may be a portion of a circuit, a portion of a processor, a portion of a program or software, etc.) in the method or apparatus comprising the element.

[0033] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "U and / or W" can represent three situations: the existence of U alone, the existence of both U and W, and the existence of W alone. Furthermore, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of items. For example, "at least one of U, W, and V" can represent any one or more elements selected from the set consisting of U, W, and V.

[0034] Due to its fast switching speed, low loss, high thermal conductivity, high switching speed, and high operating frequency, SiC MOSFETs are more suitable for high-speed and high-power applications and are increasingly used in power electronics circuits. However, compared to traditional insulated gate bipolar transistors (IGBTs) or silicon-based MOSFETs, SiC MOSFETs also bring new challenges.

[0035] For SiC MOSFETs with a bridge structure, when one of the upper and lower switch tubes in the same bridge arm remains in the off state and the other switch tube (pair of switches) is turned on, crosstalk will occur, increasing or decreasing the voltage between the gate and source of the switch tube when it remains in the off state, which may cause the risk of bridge arm penetration or device damage.

[0036] Figure 1 This is a circuit diagram of a bridge structure composed of SiC MOSFETs in related technology, such as Figure 1 As shown, the bridge structure includes an upper bridge arm 10, a lower bridge arm 11, a driving voltage signal Vgs1 and a line equivalent resistance Ri1 of the upper bridge arm 10, a driving voltage signal Vgs2 and a line equivalent resistance Ri2 of the lower bridge arm 11, and a load L1; wherein the upper bridge arm 10 includes a first SiC MOSFET Q1; wherein Q1 includes a parasitic capacitor Cgd1 connected between the gate and drain of Q1, a parasitic capacitor Cgs1 connected between the gate and source of Q1, and a parasitic capacitor Cds1 connected between the drain and source of Q1; the lower bridge arm 11 includes a second SiC MOSFET Q2; wherein Q2 includes a parasitic capacitor Cgd2 connected between the gate and drain of Q2, a parasitic capacitor Cgs2 connected between the gate and source of Q2, and a parasitic capacitor Cds2 connected between the drain and source of Q2;

[0037] Vgs1 is connected between the gate and source of Q1, providing a control voltage signal to Q1; Ri1 is the line resistance between Vgs1 and the gate of Q1; the source of Q1 is connected to the drain of Q2; the drain of Q1 is connected to the positive electrode Vdc+ of the DC voltage source; Vgs2 is connected between the gate and source of Q2, providing a control voltage signal to Q2; Ri2 is the line resistance between Vgs2 and the gate of Q2; the source of Q2 is connected to the ground terminal (Vdc-) of the DC voltage source; the common connection point of Q1 and Q2 is connected to L1.

[0038] It is understandable that there are two situations:

[0039] Case 1: When both Q1 and Q2 are off, if the bridge arm current flows outward (from the common connection point of Q1 and Q2 to L1), that is, the current flows through the body diode in Q2 and continues through the body diode in Q2; at this time, Vds2 on Q2 = 0, and Vds1 on Q1 = Vdc;

[0040] If Q1 switches from the off state to the on state, current flows from Q2 to Q1, causing Q2's Vds2 voltage to rapidly rise to Vdc, while Q1's Vds1 drops from Vdc to 0. As can be seen, due to Q1's rapid turn-on, the dv / dt (speed of voltage change) across Q1 is very large. This dv / dt across Q1 generates a drain-to-gate current through Q2's parasitic capacitance Cgd2, which charges Cgd2 and raises the voltage across Cgd2. This current flows either through parasitic capacitance Cgs2 or through Q2's drive circuit. The current flowing through Cgs2 charges Cgs2 and raises the voltage across Vgs2. Therefore, even when Q2 is off, Vgs2 will still experience a voltage rise. If the Vgs2 rise exceeds Q2's voltage threshold Vth, Q2 will be mistakenly turned on, leading to a bridge arm punch-through.

[0041] Case 2: When Q2 is off and Q1 is on, Vds2 on Q2 = Vdc, and Vds1 on Q1 = 0.

[0042] If the bridge arm current is flowing outward (from the common connection point of Q1 and Q2 to L1), when Q1 switches from on to off, Vds1 on Q1 will rapidly change from 0 to Vdc, and then Vds1 on Q1 will rapidly drop from Vdc to 0. This voltage change on Q1 will also produce a high dv / dt (voltage change), generating a discharge current through Cgd2 on Q2. The portion of this current flowing through Cgs2 on Q2 will cause Vgs2 to drop. If the drop in Vgs2 is too large, the Vgs2 voltage will fall below the minimum voltage allowed for Q2, causing damage to Q2.

[0043] Figure 2a for Figure 1 The voltage change curve diagram of Q1 and Q2 when Q1 changes from the off state to the on state in the bridge structure shown in FIG. Figure 2a As shown, curve 201 represents the voltage change of the driving voltage signal Vgs1; it can be seen that at time t, Vgs1 changes from a low level to a high level;

[0044] Curve 202 represents the voltage change of the drain-source voltage Vds1 of Q1 in response to the voltage change of Vgs1. It can be seen that Q1 responds to the voltage change of Vgs1 at time t, gradually decreasing from Vdc to 0 from time t.

[0045] Curve 203 shows the voltage change of the drain-source voltage Vds2 of Q2 in response to the voltage change of Vgs1 when Q2 is in the off state. It can be seen that Vds2 gradually increases from 0 to Vdc starting from time t.

[0046] Curve 204 represents the voltage change of the voltage Vgs2 between the gate and drain of Q2 (the driving voltage of Q2) in response to the voltage change of Vgs1 when Q2 is in the off state; it can be seen that Vgs2 will gradually increase from 0 starting from time t, increase to a first specific positive value at time t', then gradually decrease to a second specific negative value, and finally gradually return to 0; that is, when Q2 remains in the off state, when Q1 (Q2's counterpart) switches from the off state to the on state, crosstalk will occur, increasing the voltage between the gate and source of Q2 (Q2's driving voltage).

[0047] Figure 2b for Figure 1 The voltage change curve diagram of Q1 and Q2 when Q1 changes from the on state to the off state in the bridge structure shown in FIG. Figure 2b As shown, curve 205 represents the voltage change of the driving voltage signal Vgs1; it can be seen that at time t*, Vgs1 changes from a high level to a low level;

[0048] Curve 206 shows the voltage change of the drain-source voltage Vds1 of Q1 in response to the voltage change of Vgs1. It can be seen that Q1 responds to the level change of Vgs1 at time t*, and the voltage gradually rises from 0 to Vdc from time t*.

[0049] Curve 207 shows the voltage change of Vds2 between the drain and source of Q2 in response to the voltage change of Vgs1 when Q2 is in the off state. It can be seen that Vds2 gradually decreases from Vdc to 0 starting from time t*.

[0050] Curve 208 represents the voltage change of Vgs2 (driving voltage of Q2) between the gate and drain of Q2 in response to the voltage change of Vgs1 when Q2 is in the off state; it can be seen that Vgs2 will gradually decrease from 0 starting from time t*, drop to the negative third specific value at time t**, then gradually increase to the positive fourth specific value, and finally gradually return to 0; that is, when Q2 remains in the off state, when Q1 (Q2's counterpart) switches from the on state to the off state, crosstalk will occur, reducing the voltage between the gate and source of Q2 (Q2 driving voltage).

[0051] From the above analysis, it can be seen that crosstalk is particularly obvious in the application of SiC MOSFET. If it is not suppressed, the risk is relatively high, which may cause the risk of bridge arm punch-through or lead to device damage.

[0052] It is understandable that when power electronic converters are used in high-power fields, SiC MOSFETs need to be used in parallel. Since the SiC MOSFETs connected in parallel at the upper and lower bridge arms share the same drive signal, crosstalk will occur on each parallel SiC MOSFET. At the same time, since the turn-on and turn-off speeds of the parallel SiC MOSFETs are not synchronized, it becomes more difficult to effectively suppress the crosstalk of the parallel SiC MOSFETs.

[0053] Figure 3 FIG. 1 is a circuit diagram of a crosstalk suppression circuit for a parallel SiC MOSFET in the related art, such as Figure 3 As shown in FIG, the crosstalk suppression circuit connects a parallel capacitor Ci between the gate and source of each of n parallel-connected SiC MOSFETs Q3 to Qn+3, where i is any positive integer from 3 to n+3. It can be understood that Rg is the equivalent resistance of the connection line when the drive voltage signal is connected to the SiC MOSFET.

[0054] It can be seen that, while the crosstalk current remains unchanged, increasing the gate capacitance Ci can buffer and reduce the dv / dt (voltage change) of the SiC MOSFET, thereby reducing the voltage change on the SiC MOSFET. This method is effective in suppressing crosstalk, but the additional parallel capacitance will slow down the switching speed, thereby increasing the switching loss of the SiC MOSFET, which is contrary to the original intention of using SiC MOSFET.

[0055] Figure 4 FIG. 1 is a circuit diagram of another crosstalk suppression circuit for parallel SiC MOSFETs in the related art, such as Figure 4 As shown, Figure 4 and Figure 3 The n parallel-connected SiC MOSFETs Q3 to SiC MOSFET Qn+3 are identical except that: Figure 4 In the crosstalk suppression circuit, the gate of each SiC MOSFET is connected to the built-in Miller clamp pin of the driver chip 401 to implement Miller clamping. In this way, when the SiC MOSFET is turned off, the MOSFET inside the driver chip 401 is always in the on state, thereby lowering the voltage between the gate and the source, thereby playing a clamping role.

[0056] If the driver chip 401 is an external Miller clamp, a PNP or NPN transistor, a P-type MOSFET or an N-type MOSFET, must be added. This is also referred to as the direct connection method. When this direct connection method is applied to parallel SiC MOSFETs, the following issues may occur, resulting in unsatisfactory clamping results:

[0057] The transmission paths from the driver chip 401 to the gates of Q3 to Qn+3 are different, and the gate drive turn-on and turn-off resistance values ​​of Q3 to Qn+3 are different. The turn-on and turn-off processes of Q3 to Qn+3 are significantly out of sync, and the Miller clamp is forced to turn on, thereby damaging the SiCMOSFET.

[0058] Figure 5 FIG. 1 is a circuit diagram of another crosstalk suppression circuit for parallel SiC MOSFETs in the related art, as shown in FIG. Figure 5 As shown, the crosstalk suppression circuit includes two circuits, the upper circuit includes: a first voltage totem pole structure circuit 50, a second voltage totem pole structure circuit 51, a first driving resistor circuit 52, a first low-impedance loop 53 and an upper tube 54; the lower circuit includes: a third voltage totem pole structure circuit 55, a fourth voltage totem pole structure circuit 56, a second driving resistor circuit 57, a second low-impedance loop 58 and a lower tube 59;

[0059] Among them, the output end of the first voltage totem pole structure circuit 50 is connected to the input end of the second voltage totem pole structure circuit 51; the output end of the second voltage totem pole structure circuit 51 is connected to the input end of the first driving resistor circuit 52, the input end of the first driving resistor circuit 52 is connected to the gate of the upper tube 54, one end of the first low-impedance loop 53 is connected to the gate of the upper tube 54, and the other end of the first low-impedance loop 53 is connected to the source of the upper tube 54; the output end of the third voltage totem pole structure circuit 55 is connected to the input end of the fourth voltage totem pole structure circuit 56; the output end of the fourth voltage totem pole structure circuit 56 is connected to the input end of the second driving resistor circuit 57, and the output end of the second driving resistor circuit 57 is connected to the gate of the lower tube 59; one end of the second low-impedance loop 58 is connected to the gate of the lower tube 59, and the other end of the second low-impedance loop 58 is connected to the source of the lower tube 59.

[0060] The first voltage totem pole structure circuit 50 includes a first switch tube S 1(H) , the second switch tube, S 2(H) , the first positive power supply U G,on1 , first negative power supply U G,off1 ; The first switch tube S 1(H) The drain is connected to the first positive power supply U G,on1 , the first switch tube S 1(H) The source of the second switch S 2(H) The drain of the second switch tube S 2(H) The source is connected to the first negative power supply U G,off1 ;

[0061] The second voltage totem pole structure circuit 51 includes a third switch tube S 3(H) , four switch tubes S 4(H)and the second negative power supply U G,off2 ; The third switch tube S 3(H) The drain of the first switch tube S 1(H) The source of the second switch tube S 2(H) The drain of the third switch tube S 3(H) The source of the fourth switch S 4(H) The drain of the fourth switch tube S 4(H) The source is connected to the second negative power supply U G,off2 ;

[0062] The first driving resistor circuit 52 includes a first driving resistor R G,on(H) , the second driving resistor R G,off(H) ; The first diode D 1(H) , the second diode D 2(H) ; The first driving resistor R G,on(H) One end of the first diode D 1(H) anode of the second diode D 2(H) The anode of the second drive resistor R G,off(H) One end of the first driving resistor D 1(H) The other end of the third switch tube S 3(H) The source of the fourth switch tube S 4(H) The drain of the second diode D 2(H) The cathode connection of the second driving resistor R G,off(H) The other end of the first diode D 1(H) cathode connection;

[0063] The first low impedance loop 53 includes a first capacitor C 1(H) and the fifth diode D 3(H) , the first capacitor C 1(H) One end of the first diode D 1(H) The cathode of the second drive resistor R G，off(H) The other end of the first capacitor C 1(H) The other end is connected to the fifth diode D 3(H) The cathode of the fifth diode D 3(H) The anode of is connected to the source of the upper tube 54;

[0064] Among them, C GD(H) is the parasitic capacitance between the gate and drain of the upper tube 54; C GS(H) is the parasitic capacitance between the gate and source of the upper tube 54; C DS(H) is the parasitic capacitance between the source and drain of the upper tube 54; R G,int(H) is the equivalent impedance of the upper tube 54; C GD(L) is the parasitic capacitance between the gate and drain of the lower tube 59; C GS(L)is the parasitic capacitance between the gate and source of the lower tube 59; C DS(L) is the parasitic capacitance between the source and drain of the upper tube 59; R G,int(L) is the equivalent impedance of the lower tube 59;

[0065] Since the components and structures of the upper circuit and the lower circuit are exactly the same, the specific circuits in the lower circuit will not be described in detail here.

[0066] As can be seen, when crosstalk occurs in the same bridge arm, the transistor (upper or lower) remains off. When the switch (lower or upper) is turned on, two levels of negative voltage are applied to the gate and source. Through the coordinated modulation of the two totem pole structures, a higher negative voltage is applied between the gate and source when crosstalk occurs. The positive voltage spike caused by the crosstalk is superimposed on the higher negative voltage, ensuring that the voltage between the gate and source remains below the threshold voltage. After the crosstalk ends, a lower negative voltage is applied between the gate and source. This prevents crosstalk-induced shoot-through in the bridge arm. During the normal shutdown period of the upper or lower switch, a normal shutdown voltage is applied to the gate and source of the upper or lower switch, maintaining the normal operating life of the upper or lower switch. However, the need to provide an additional negative drive voltage and two totem pole structures for each switch in the bridge arm increases the cost and complexity of the bridge arm crosstalk suppression circuit, limiting its practical value.

[0067] Based on the above technical problems, the embodiment of the present application provides a bridge arm crosstalk suppression circuit, such as Figure 6 As shown, the bridge arm crosstalk suppression circuit includes: an upper bridge arm 60, a lower bridge arm 61, a first driver chip 62 and a first negative voltage regulation circuit 63 corresponding to the upper bridge arm 60, and a second driver chip 64 and a second negative voltage regulation circuit 65 corresponding to the lower bridge arm 61;

[0068] The first output end of the first driver chip 62 is connected to the first input end of the first negative voltage regulation circuit 63; the second output end of the first driver chip 62 is connected to the gate of the upper bridge arm 60; the second input end of the first negative voltage regulation circuit 63 is connected to the gate of the upper bridge arm 60; the output end of the first negative voltage regulation circuit 63 is connected to the source of the upper bridge arm 60; the first negative voltage regulation circuit 63 is used to be sensitive to changes in the gate voltage of the upper bridge arm 60, and to adjust the negative voltage between the gate and source of the upper bridge arm 60 in response to the changes in the gate voltage of the upper bridge arm 60, so as to suppress crosstalk to the upper bridge arm 60;

[0069] The first output end of the second driving chip 64 is connected to the first input end of the second negative voltage regulating circuit 65; the second output end of the second driving chip 64 is connected to the gate of the lower bridge arm 61; the second input end of the second negative voltage regulating circuit 65 is respectively connected to the gate of the lower bridge arm 61; the output end of the second negative voltage regulating circuit 65 is connected to the source of the lower bridge arm 61; the second negative voltage regulating circuit 65 is used to be sensitive to the gate voltage change of the lower bridge arm 61, and adjust the negative voltage between the gate and source of the lower bridge arm 61 in response to the gate voltage change of the lower bridge arm 61 to suppress crosstalk to the lower bridge arm 61.

[0070] Here, the first output terminal of the first driver chip 62 may be a power supply terminal of the first driver chip 62. The first output terminal of the second driver chip 64 may be a power supply terminal of the second driver chip 64. The power supply terminals of the first driver chip 62 or the second driver chip 64 may include a first power supply terminal, a second power supply terminal, and a ground terminal; wherein the first power supply terminal may be -Vee, and the second power supply terminal may be +Vcc.

[0071] The second output end of the first driver chip 62 may be a driving signal output end of the first driver chip 62 ; the second output end of the second driver chip 64 may be a driving signal output end of the second driver chip 64 .

[0072] The first input end of the first negative voltage regulation circuit 63 can represent the power input end of the first negative voltage regulation circuit 63; the first input end of the second negative voltage regulation circuit 65 can represent the power input end of the second negative voltage regulation circuit 65; the second input end of the first negative voltage regulation circuit 63 represents the input end of the sensitive signal to be regulated of the first negative voltage regulation circuit 63; the second input end of the second negative voltage regulation circuit 65 represents the input end of the sensitive signal to be regulated of the second negative voltage regulation circuit 65.

[0073] It can be understood that the upper bridge arm 60 can include at least one upper switch tube connected in parallel; the lower bridge arm 61 can include at least one lower switch tube connected in parallel; it can be understood that the source of each switch tube in the upper switch tube or lower switch tube connected in parallel is interconnected; the drain of each switch tube in the upper switch tube or lower switch tube connected in parallel is also connected to each other; therefore, the source of the upper bridge arm 60 represents the source of each upper switch tube in the upper bridge arm 60; the source of the lower bridge arm 61 represents the source of each lower switch tube in the lower bridge arm 61.

[0074] At the same time, since the gate of the upper bridge arm 60 includes the gate of each upper switch tube, the second input end of the first negative voltage regulation circuit 63 includes an input terminal corresponding to the gate of each upper switch tube; since the gate of the lower bridge arm 61 includes the gate of each lower switch tube, the second input end of the second negative voltage regulation circuit 65 includes an input terminal corresponding to the gate of each lower switch tube.

[0075] In an embodiment of the present application, a first negative voltage regulation circuit is set between the gate of the upper bridge arm and the first driver chip corresponding to the upper bridge arm, the first negative voltage regulation circuit is used to sense the gate voltage change of the upper bridge arm, and the negative voltage between the gate and the source of the upper bridge arm is adjusted in response to the gate voltage of the upper bridge arm to suppress crosstalk to the upper bridge arm; a second negative voltage regulation circuit is set between the gate of the lower bridge arm and the second driver chip corresponding to the lower bridge arm, the second negative voltage regulation circuit is used to sense the gate voltage change of the lower bridge arm, and the negative voltage between the gate and the source of the lower bridge arm is adjusted in response to the gate voltage of the lower bridge arm to suppress crosstalk to the lower bridge arm. When the upper bridge arm includes at least one upper switch tube connected in parallel and the lower bridge arm includes at least one lower switch tube connected in parallel, since only one first negative voltage regulation circuit needs to be configured for the upper bridge arm and only one second negative voltage regulation circuit needs to be configured for the lower bridge arm, there is no need to configure the first negative voltage regulation circuit for each upper switch tube in the upper bridge arm and the second negative voltage regulation circuit for each lower switch tube in the lower bridge arm, and there is no need to provide an additional negative drive circuit. Therefore, the cost and complexity of the circuit are low and the practical value is high.

[0076] Figure 7 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the bridge arm crosstalk suppression circuit includes an upper bridge arm 70, a lower bridge arm 71, a first driver chip 72 and a first negative voltage regulation circuit 73 corresponding to the upper bridge arm 70, a second driver chip 74 and a second negative voltage regulation circuit 75 corresponding to the lower bridge arm 71; the first negative voltage regulation circuit 73 includes a first gate voltage sensing circuit 731 and a first sub-regulation circuit 732;

[0077] The first power supply terminal of the first output terminal of the first driver chip 72 is connected to the first power supply terminal of the first sub-regulation circuit 732; the second power supply terminal of the first output terminal of the first driver chip 72 is connected to the second power supply terminal of the first sub-regulation circuit 732; the ground terminal of the first output terminal of the first driver chip 72 is connected to the ground terminal of the first sub-regulation circuit 732; the second output terminal of the first driver chip 72 is connected to the gate of the upper bridge arm 70; the input terminal of the first gate voltage sensitive circuit 731 is connected to the gate of the upper bridge arm 70; the output terminal of the first gate voltage sensitive circuit 731 is connected to the input terminal of the first sub-regulation circuit 732; and the output terminal of the first sub-regulation circuit 732 is connected to the source of the upper bridge arm 71;

[0078] The first gate voltage sensing circuit 731 is configured to sense a gate voltage change of the upper bridge arm 70 and transmit the gate voltage change of the upper bridge arm 70 to the first sub-regulation circuit 732;

[0079] The first sub-regulation circuit 732 is configured to regulate the negative voltage between the gate and the source of the upper bridge arm 70 in response to a change in the gate voltage of the upper bridge arm 70 , so as to suppress crosstalk to the upper bridge arm 70 ;

[0080] The first output terminal of the second driving chip 74 is connected to the first input terminal of the second negative voltage regulating circuit 75; the second output terminal of the second driving chip 74 is connected to the gate of the lower bridge arm 71; the second input terminal of the second negative voltage regulating circuit 75 is connected to the gate of the lower bridge arm 71; and the output terminal of the second negative voltage regulating circuit 75 is connected to the source of the lower bridge arm 71.

[0081] The second negative voltage regulating circuit 75 is used to be sensitive to the gate voltage change of the lower bridge arm 71 and to regulate the negative voltage between the gate and source of the lower bridge arm 71 in response to the gate voltage change of the lower bridge arm 71 to suppress crosstalk to the lower bridge arm 71 .

[0082] In an embodiment of the present application, the gate voltage change of the upper bridge arm is sensed by the first gate voltage sensitive circuit, and the gate voltage change of the upper bridge arm is transmitted to the first sub-regulation circuit. The first sub-regulation circuit adjusts the negative voltage between the gate and source of the upper bridge arm in response to the gate voltage change of the upper bridge arm, thereby suppressing crosstalk to the upper bridge arm.

[0083] Figure 8 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, an upper bridge arm 80, a lower bridge arm 81, a first driver chip 82 and a first negative voltage regulation circuit 83 corresponding to the upper bridge arm 80, a second driver chip 84 and a second negative voltage regulation circuit 85 corresponding to the lower bridge arm 81; the first negative voltage regulation circuit 83 includes a first gate voltage sensing circuit 831 and a first sub-regulation circuit 832; the first gate voltage sensing circuit 831 includes at least a first series branch 831' formed by a first resistor and a second resistor in series;

[0084] The first power supply terminal of the first output terminal of the first driver chip 82 is connected to the first power supply terminal of the first sub-regulation circuit 832; the second power supply terminal of the first output terminal of the first driver chip 82 is connected to the second power supply terminal of the first sub-regulation circuit 832; the ground terminal of the first output terminal of the first driver chip 82 is connected to the ground terminal of the first sub-regulation circuit 832; the second output terminal of the first driver chip 82 is connected to the gate of the upper bridge arm 80; the first series branch 831' is connected between the gate of the upper bridge arm 80 and the first power supply terminal of the first sub-regulation circuit 832; the common node of the first resistor and the second resistor is connected to the input terminal of the first sub-regulation circuit 832; and the output terminal of the first sub-regulation circuit 832 is connected to the source of the upper bridge arm 80.

[0085] The first series branch 831' is used to sense the gate voltage change of the upper bridge arm 80 and transmit the gate voltage change of the upper bridge arm 80 to the first sub-regulation circuit 832 through the voltage change at the common node of the first resistor and the second resistor;

[0086] The first sub-regulation circuit 832 is configured to regulate the negative voltage between the gate and source of the upper bridge arm 80 in response to a change in the gate voltage of the upper bridge arm 80 , so as to suppress crosstalk to the upper bridge arm 80 ;

[0087] The first output terminal of the second driving chip 84 is connected to the first input terminal of the second negative voltage regulating circuit 85; the second output terminal of the second driving chip 84 is connected to the gate of the lower bridge arm 81; the second input terminal of the second negative voltage regulating circuit 85 is respectively connected to the gate of the lower bridge arm 81; the output terminal of the second negative voltage regulating circuit 85 is connected to the source of the lower bridge arm 81;

[0088] The second negative voltage regulating circuit 85 is used to be sensitive to the gate voltage change of the lower bridge arm 81 and to regulate the negative voltage between the gate and source of the lower bridge arm 81 in response to the gate voltage change of the lower bridge arm 81 to suppress crosstalk to the lower bridge arm 81 .

[0089] In some possible implementations, the first gate voltage sensing circuit 831 may include one first series branch 831', or may include multiple first series branches 831', the specific number of which is determined by the number of upper switching tubes included in the upper bridge arm 80. However, it is certain that each upper switching tube corresponds to one first series branch 831'.

[0090] In some embodiments, the first gate voltage sensitive circuit 831 includes a first sub-sensitive circuit corresponding to each upper switch tube; the input end of each first sub-sensitive circuit is connected to the gate of the corresponding upper switch tube; the output end of each first sub-sensitive circuit is connected to the input end of the first sub-regulation circuit; and each sub-sensitive circuit includes a corresponding first series branch.

[0091] In an embodiment of the present application, since the first gate voltage sensitive circuit includes at least a first series branch formed by a first resistor and a second resistor connected in series, and the first series branch is connected across the gate of the upper bridge arm and the first power supply terminal of the first sub-regulation circuit, the first series branch can be sensitive to the gate voltage change of the upper bridge arm, so that the voltage at the common node of the first resistor and the second resistor follows the change. At the same time, since the common node of the first resistor and the second resistor is connected to the first sub-regulation circuit, the gate voltage change of the sensitive upper bridge arm can be transmitted to the first sub-regulation circuit, so that the first sub-regulation circuit can perform voltage regulation according to the gate voltage change.

[0092] Figure 9 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application is shown in FIG. Figure 9 As shown, an upper bridge arm 90, a lower bridge arm 91, a first driver chip 92 and a first negative voltage regulation circuit 93 corresponding to the upper bridge arm 90, a second driver chip 94 and a second negative voltage regulation circuit 95 corresponding to the lower bridge arm 91; the first negative voltage regulation circuit 93 includes a first gate voltage sensing circuit 931 and a first sub-regulation circuit 932; the first sub-regulation circuit 932 includes a first voltage stabilization circuit 9321 and a first voltage regulation circuit 9322;

[0093] The first power supply terminal of the first output terminal of the first driver chip 92 is connected to the first power input terminal of the first voltage regulating circuit 9321 and the first voltage regulating circuit 9322; the second power supply terminal of the first output terminal of the first driver chip 92 is connected to the first voltage regulating circuit 9321 and the second power input terminal of the first voltage regulating circuit 9322; the ground terminal of the first output terminal of the first driver chip 92 is connected to the output terminal of the first voltage regulating circuit 9322 and the source of the upper bridge arm 90; the second output terminal of the first driver chip 92 is connected to the gate of the upper bridge arm 90; the input terminal of the first gate voltage sensitive circuit 931 is connected to the gate of the upper bridge arm 90; the output terminal of the first gate voltage sensitive circuit 931 is connected to the input terminal of the first voltage regulating circuit 9321; the output terminal of the first voltage regulating circuit 9321 is connected to the input terminal of the first voltage regulating circuit 9322;

[0094] The first gate voltage sensing circuit 931 is configured to sense a gate voltage change of the upper bridge arm 90 and transmit the gate voltage change of the upper bridge arm 90 to the first voltage stabilizing circuit 9321;

[0095] The first voltage stabilizing circuit 9321 is configured to adjust its own output voltage in response to a change in the gate voltage of the upper bridge arm 90;

[0096] The first voltage regulating circuit 9322 is configured to adjust its own output voltage in response to the adjusted output voltage of the first voltage stabilizing circuit 9321, so as to adjust the negative voltage between the gate and source of the upper bridge arm 90 and suppress crosstalk to the upper bridge arm 90;

[0097] The first output terminal of the second driving chip 94 is connected to the first input terminal of the second negative voltage regulating circuit 95; the second output terminal of the second driving chip 94 is connected to the gate of the lower bridge arm 91; the second input terminal of the second negative voltage regulating circuit 95 is respectively connected to the gate of the lower bridge arm 91; the output terminal of the second negative voltage regulating circuit 95 is connected to the source of the lower bridge arm 91;

[0098] The second negative voltage regulating circuit 95 is configured to regulate the negative voltage between the gate and the source of the lower bridge arm 91 according to the gate voltage of the lower bridge arm 91 , so as to suppress crosstalk to the lower bridge arm 91 .

[0099] In an embodiment of the present application, the gate voltage change of the upper bridge arm is sensed by a first gate voltage sensitive circuit, and the gate voltage change of the upper bridge arm is transmitted to the first voltage stabilizing circuit; the first voltage stabilizing circuit adjusts its own output voltage in response to the gate voltage change of the upper bridge arm; the first voltage regulating circuit adjusts its own output voltage in response to the adjusted output voltage of the first voltage stabilizing circuit to adjust the negative voltage between the gate and source of the upper bridge arm, thereby suppressing the crosstalk of the upper bridge arm.

[0100] Figure 10 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application is shown in FIG. Figure 10 As shown, an upper bridge arm 100, a lower bridge arm 101, a first driver chip 102 and a first negative voltage regulation circuit 103 corresponding to the upper bridge arm 100, a second driver chip 104 and a second negative voltage regulation circuit 105 corresponding to the lower bridge arm 101; the first negative voltage regulation circuit 103 includes a first gate voltage sensing circuit 1031 and a first sub-regulation circuit 1032; the first sub-regulation circuit 1032 includes a first voltage stabilizing circuit 1032' and a first voltage regulation circuit 1032"; the first voltage stabilizing circuit 1032' includes a three-terminal voltage regulator 1032* and a third resistor 1032**;

[0101] The first power supply terminal of the first output terminal of the first driver chip 102 is connected to the positive electrode of the three-terminal regulator 1032* and the first power supply input terminal of the first voltage regulating circuit 1032"; the second power supply terminal of the first output terminal of the first driver chip 102 is connected to the second end of the third resistor 1032** and the second power supply input terminal of the first voltage regulating circuit 1032"; the ground terminal of the first output terminal of the first driver chip 102 is connected to the output terminal of the first voltage regulating circuit 1032" and the source of the upper bridge arm 100; The second output terminal of the first driver chip 102 is connected to the gate of the upper bridge arm 100; the input terminal of the first gate voltage sensitive circuit 1031 is connected to the gate of the upper bridge arm 100; the output terminal of the first gate voltage sensitive circuit 1031 is connected to the reference electrode of the three-terminal regulator 1032*; the negative electrode of the three-terminal regulator 1032* is connected to the first end of the third resistor 1032**; the common connection point between the third resistor 1032** and the three-terminal regulator 1032* is connected to the input terminal of the first voltage regulation circuit 1032";

[0102] The first gate voltage sensing circuit 1031 is configured to sense a gate voltage change of the upper bridge arm 100 and transmit the gate voltage change of the upper bridge arm 100 to the three-terminal regulator 1032*;

[0103] The three-terminal voltage regulator 1032* is used to adjust its own impedance in response to the gate voltage change of the upper bridge arm 100, so that the current flowing through itself changes;

[0104] The third resistor 1032** is configured to adjust the voltage at a common connection point between the third resistor 1032** and the three-terminal regulator 1032* in response to a change in the current of the three-terminal regulator 1032*;

[0105] The first voltage regulating circuit 1032″ is configured to regulate its own output voltage in response to the regulated voltage at the common connection point between the third resistor 1032** and the three-terminal regulator 1032*, so as to regulate the negative voltage between the gate and source of the upper bridge arm 100, thereby suppressing crosstalk to the upper bridge arm 100;

[0106] The first output terminal of the second driver chip 104 is connected to the first input terminal of the second negative voltage regulation circuit 105; the second output terminal of the second driver chip 104 is connected to the gate of the lower bridge arm 101; the second input terminal of the second negative voltage regulation circuit 105 is respectively connected to the gate of the lower bridge arm 101; the output terminal of the second negative voltage regulation circuit 105 is connected to the source of the lower bridge arm 101;

[0107] The second negative voltage regulating circuit 105 is configured to regulate the negative voltage between the gate and the source of the lower bridge arm 101 according to the gate voltage of the lower bridge arm 101 , so as to suppress crosstalk to the lower bridge arm 101 .

[0108] In an embodiment of the present application, the first voltage stabilization circuit includes a three-terminal voltage regulator and a third resistor, and the gate voltage change of the upper bridge arm is sensed by the first gate voltage sensitive circuit, and the gate voltage change of the upper bridge arm is transmitted to the three-terminal voltage regulator; the three-terminal voltage regulator adjusts its own impedance in response to the gate voltage change of the upper bridge arm, so that the current flowing through itself changes; the third resistor adjusts the voltage at the common connection point between the third resistor and the three-terminal voltage regulator in response to the current change on the three-terminal voltage regulator; the first voltage regulation circuit adjusts its own output voltage in response to the voltage at the common connection point between the adjusted third resistor and the three-terminal voltage regulator to adjust the negative voltage between the gate and source of the upper bridge arm, thereby suppressing the crosstalk of the upper bridge arm.

[0109] Figure 11 This is a schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application, such as Figure 11 As shown, an upper bridge arm 110, a lower bridge arm 111, a first driver chip 112 and a first negative voltage regulation circuit 113 corresponding to the upper bridge arm 110, a second driver chip 114 and a second negative voltage regulation circuit 115 corresponding to the lower bridge arm 111; the first negative voltage regulation circuit 113 includes a first gate voltage sensing circuit 1131 and a first sub-regulation circuit 1132; the first sub-regulation circuit 1132 includes a first voltage stabilization circuit 1132' and a first voltage regulation circuit 1132"; the first voltage regulation circuit 1132" includes a fourth resistor 1132*, a fifth resistor 1132** and a first transistor 1132***;

[0110] The first power supply terminal of the first output terminal of the first driver chip 112 is connected to the first power supply input terminal of the first voltage stabilizing circuit 1132' and the emitter of the first transistor 1132***; the second power supply terminal of the first output terminal of the first driver chip 112 is connected to the second power supply input terminal of the first voltage stabilizing circuit 1132' and the second end of the fifth resistor 1132**; the ground terminal of the first output terminal of the first driver chip 112 is connected to the collector of the first transistor 1132*** and the source of the upper bridge arm 110; the second output terminal of the first driver chip 112 is connected to the gate of the upper bridge arm 110; the first gate The input end of the gate voltage sensing circuit 1131 is connected to the gate of the upper bridge arm 110; the output end of the first gate voltage sensing circuit 1131 is connected to the input end of the first voltage stabilizing circuit 1132'; the output end of the first voltage stabilizing circuit 1132' is connected to the first end of the fourth resistor 1132*; the second end of the fourth resistor 1132* is connected to the base of the first transistor 1132***; the collector of the first transistor 1132*** is connected to the first end of the fifth resistor 1132**; and the common node between the fifth resistor 1132** and the first transistor 1132*** is connected to the source of the upper bridge arm 110;

[0111] The first gate voltage sensing circuit 1131 is configured to sense a gate voltage change of the upper bridge arm 110 and transmit the gate voltage change of the upper bridge arm 110 to the first voltage stabilizing circuit 1132 ′;

[0112] The first voltage stabilizing circuit 1132' is configured to adjust its own output voltage in response to a change in the gate voltage of the upper bridge arm 110;

[0113] The fourth resistor 1132* is configured to adjust the base current of the first transistor 1132*** in response to the adjusted output voltage of the first voltage stabilizing circuit 1132';

[0114] The first transistor 1132*** is configured to adjust the current on its collector in response to the adjusted base current;

[0115] The fifth resistor 1132** is configured to adjust the voltage at a common node between the fifth resistor 1132** and the first transistor 1132*** in response to the adjusted current on the collector of the first transistor 1132***, thereby adjusting the negative voltage between the gate and the source of the upper bridge arm 110 and suppressing crosstalk to the upper bridge arm 110;

[0116] The first output terminal of the second driver chip 114 is connected to the first input terminal of the second negative voltage regulation circuit 115; the second output terminal of the second driver chip 114 is connected to the gate of the lower bridge arm 111; the second input terminal of the second negative voltage regulation circuit 115 is respectively connected to the gate of the lower bridge arm 111; the output terminal of the second negative voltage regulation circuit 115 is connected to the source of the lower bridge arm 111;

[0117] The second negative voltage regulation circuit 115 is used to be sensitive to the gate voltage change of the lower bridge arm 111 and regulate the negative voltage between the gate and source of the lower bridge arm 111 in response to the gate voltage change of the lower bridge arm 111 to suppress crosstalk to the lower bridge arm 111.

[0118] In an embodiment of the present application, the first voltage regulation circuit includes a fourth resistor, a fifth resistor and a first transistor; the base current of the first transistor is adjusted in response to the adjusted output voltage of the first voltage stabilizing circuit through the fourth resistor; the first transistor adjusts the current on its own collector in response to the adjusted base current; the fifth resistor adjusts the voltage on the common node of the fifth resistor and the first transistor in response to the adjusted current on the collector of the first transistor, thereby realizing negative voltage regulation between the gate and source of the upper bridge arm and suppressing crosstalk to the upper bridge arm.

[0119] Figure 12 A schematic diagram of the structure of another bridge arm crosstalk suppression circuit provided in an embodiment of the present application is shown in FIG. Figure 12 As shown, the bridge arm crosstalk suppression circuit includes an upper bridge arm 120, a lower bridge arm 121, a first driver chip 122 and a first negative voltage regulation circuit 123 corresponding to the upper bridge arm 120, and a second driver chip 124 and a second negative voltage regulation circuit 125 corresponding to the lower bridge arm 121; the first negative voltage regulation circuit 123 includes a first gate voltage sensitive circuit 1231, a first sub-regulation circuit 1232 and a voltage regulator tube 1233;

[0120] The first power supply terminal of the first output terminal of the first driver chip 122 is connected to the first power supply terminal of the first sub-regulation circuit 1232 and the anode of the voltage regulator 1233; the second power supply terminal of the first output terminal of the first driver chip 122 is connected to the second power supply terminal of the first sub-regulation circuit 1232; the ground terminal of the first output terminal of the first driver chip 122 is connected to the ground terminal of the first sub-regulation circuit 1232 and the cathode of the voltage regulator 1233; the second output terminal of the first driver chip 122 is connected to the gate of the upper bridge arm 120; the input terminal of the first gate voltage sensitive circuit 1231 is connected to the gate of the upper bridge arm 120; the output terminal of the first gate voltage sensitive circuit 1231 is connected to the input terminal of the first sub-regulation circuit 1232; and the output terminal of the first sub-regulation circuit 1232 is connected to the source of the upper bridge arm 121;

[0121] The first gate voltage sensing circuit 1231 is configured to sense a gate voltage change of the upper bridge arm 120 and transmit the gate voltage change of the upper bridge arm 120 to the first sub-regulation circuit 1232;

[0122] The first sub-regulation circuit 1232 is configured to regulate the negative voltage between the gate and the source of the upper bridge arm 120 in response to a change in the gate voltage of the upper bridge arm 120 , so as to suppress crosstalk to the upper bridge arm 120 ;

[0123] The voltage regulator 1233 is used to clamp the voltage between the output terminal of the first sub-regulation circuit 1232 and the first power supply terminal of the first sub-regulation circuit 1232 to a preset voltage;

[0124] The first output terminal of the second driver chip 124 is connected to the first input terminal of the second negative voltage regulation circuit 125; the second output terminal of the second driver chip 124 is connected to the gate of the lower bridge arm 121; the second input terminal of the second negative voltage regulation circuit 125 is respectively connected to the gate of the lower bridge arm 121; the output terminal of the second negative voltage regulation circuit 125 is connected to the source of the lower bridge arm 121;

[0125] The second negative voltage regulating circuit 125 is configured to regulate the negative voltage between the gate and the source of the lower bridge arm 121 according to the gate voltage of the lower bridge arm 121 , so as to suppress crosstalk to the lower bridge arm 121 .

[0126] It is understandable that the voltage regulator tube 1233 may be a Schottky diode; the clamping voltage of the voltage regulator tube 1233 , ie, the preset voltage, may be 2.5V.

[0127] In some possible implementations, the voltage regulator tube 1233 is a first voltage regulator diode; the positive electrode of the first voltage regulator diode is connected to the first power supply end of the first sub-regulation circuit 1232; and the negative electrode of the first voltage regulator diode is connected to the output end of the first sub-regulation circuit 1232.

[0128] In an embodiment of the present application, by arranging a voltage regulator diode between the output end of the first sub-regulation circuit and the first power supply end of the first sub-regulation circuit, the voltage between the output end of the first sub-regulation circuit and the first power supply end of the first sub-regulation circuit can be clamped to a preset voltage, that is, the negative driving voltage between the gate and the source of the upper bridge arm is clamped to the driving voltage, thereby achieving crosstalk suppression of the upper bridge arm.

[0129] Figure 13 A crosstalk suppression circuit of a bridge structure composed of SiC MOSFETs provided in an embodiment of the present application is as follows: Figure 13 As shown, the crosstalk suppression circuit of the bridge structure includes: an upper bridge arm 130, a lower bridge arm 131, a line equivalent resistance Rg1 of the upper bridge arm 130, a line equivalent resistance Rg2 of the lower bridge arm 131, a driving chip 132 and a crosstalk suppression circuit 133 corresponding to the upper bridge arm 130, a driving chip 134 and a crosstalk suppression circuit 135 corresponding to the lower bridge arm 131, and a load L2.

[0130] Among them, the upper bridge arm 130 and the lower bridge arm 131 correspond to Figure 1 The upper bridge arm 10 and the lower bridge arm 11; the upper bridge arm 130 includes a first SiC MOSFET Q1; wherein Q1 includes a parasitic capacitor Cgd1 connected between the gate and drain of Q1, a parasitic capacitor Cgs1 connected between the gate and source of Q1, and a parasitic capacitor Cds1 connected between the drain and source of Q1; the lower bridge arm 131 includes a second SiC MOSFET Q2; wherein Q2 includes a parasitic capacitor Cgd2 connected between the gate and drain of Q2, a parasitic capacitor Cgs2 connected between the gate and source of Q2, and a parasitic capacitor Cds2 connected between the drain and source of Q2.

[0131] Since the composition and connection of the first part of the circuit consisting of the upper bridge arm 130, the line equivalent resistor Rg1, the driver chip 132 and the crosstalk suppression circuit 133 are exactly the same as the second part of the circuit consisting of the lower bridge arm 131, the line equivalent resistor Rg2, the driver chip 134 corresponding to the lower bridge arm 131 and the crosstalk suppression circuit 135 are exactly the same, only the second part of the circuit is described in detail here and will not be repeated here.

[0132] Figure 13In the figure, the driver chip 134 includes a first power port -Vee2, a second power port +Vcc2, a third power port 0V and a drive signal output port Vg2; Vg2 is connected to one end of Rg2, and the other end of Rg2 is connected to the gate of Q2; here, Rg2 can be formed by two resistors in parallel; between +Vcc2 and -Vee2, and between +Vcc1 and -Vee1, an external power supply is used for power supply, and the voltage of the external power supply can be +20V.

[0133] The crosstalk suppression circuit 135 includes an eleventh resistor R11 to a fifteenth resistor R15, a second three-terminal regulator D3, a second Zener diode D4, and a second transistor T2;

[0134] Among them, the source of Q2 is directly connected to the 0V port of the driver chip 134; the series branch formed by R14 and R15 in series is connected between the gate of Q2 and -Vee2; the common node of R14 and R15 is connected to the reference pole of D3; the anode of D3 is connected to -Vee2; the cathode of D3 is connected to one end of R11; the other end of R11 is connected to +Vcc2; the common node of R11 and D3 is connected to one end of R13, and the other end of R13 is connected to the base of T2; the emitter of T2 is connected to -Vee2; the collector of T2 is connected to one end of R12; the other end of R12 is connected to +Vcc2; the common node of R12 and T2 is connected to the common node of the 0V port and the source of Q2; the source of Q2 is connected to the cathode of D4; and the anode of D4 is connected to -Vee2.

[0135] It can be understood that the gate of Q2 is connected to the input terminal of D3 after being divided by R14 and R15, so that the voltage change on the gate of Q2 can be transmitted to D3; D3 adjusts its own internal resistance according to the voltage change on its own input terminal, so that the current flowing through D3 changes with the voltage change on the input terminal, and then the base current of T2 (auxiliary transistor) can be changed to change the current flowing through R12 and the voltage on R12. Since the voltage between +Vcc2 and -Vee2 is constant, the voltage between 0V and -Vee2 changes, that is, the negative drive voltage between the gate and the source changes accordingly.

[0136] Here, D4 ​​is connected across the 0V terminal and -Vee2 to ensure that the voltage between the 0V terminal and -Vee2 is clamped to within the negative voltage safety threshold of Q2 (which can be 5V).

[0137] D3 may be TL431 or the like, and the built-in reference voltage of D3 is lower than the clamping voltage of D4 (for example, it may be 2.5V).

[0138] The basic principle of the second part of the circuit is:

[0139] When a positive crosstalk voltage appears on the gate of Q2, the voltage at the input end of D3 increases, the current flowing through R11 increases, and the voltage divider on R11 increases, resulting in a decrease in the voltage drop across D3, a decrease in the base current of Q2, a decrease in the current flowing through R12, and a decrease in the voltage divider on R12. That is, the voltage between +Vcc2 and 0V decreases, and the negative voltage between 0V and -Vee2 increases, thereby automatically playing a role in crosstalk suppression.

[0140] Figure 14 for Figure 13 The working signal timing diagram of the bridge structure crosstalk suppression circuit is shown in FIG. Figure 14 As shown, reference Figure 2a and Figure 2b Curve 140 represents the voltage change of the driving signal Vgs1; curve 141 represents the voltage change of the driving signal Vgs2; curve 143 represents the voltage change of the voltage Vds2 between the drain and source of Q2 in response to the voltage change of Vgs1 when Q2 is in the off state; curve 144 represents the voltage change between +Vcc2 and 0V in response to the voltage change of Vgs1; curve 145 represents the voltage change between -Vee2 and 0V in response to the voltage change of Vgs1. By analyzing curves 140 to 145, we can see that:

[0141] Phase 1 (t0 to t1): Before t0, since Vgs2 is at a high level, the gate voltage of Q2 (Vgs2 can be 15V) is much higher than the reference voltage of D3. Therefore, the current flowing through D3 is large, the voltage drop is small, and the base current of T2 is small. At this time, the voltage difference between 0V and -Vee2 reaches its maximum, which is the clamping voltage of D4.

[0142] At time t0, Q2's drive signal Vgs2 changes from high to low. When Q2's gate voltage falls below its threshold voltage, Q2 turns off, and Q2's Vds2 voltage rises. Meanwhile, as Q2's gate voltage drops, the current flowing through D3 gradually decreases. When it reaches D3's reference voltage (2.5V), D3 turns off, and T2's base current reaches its maximum. At this point, the voltage difference between 0V and -Vee2 reaches its minimum.

[0143] Phase 2 (t1 to t2): During the dead time, both Q2 and Q1 remain off. Due to the small voltage difference between 0V and -Vee2, the reverse conduction loss of Q2 is small according to the operating curve of the SiC MOSFET.

[0144] Phase 3 (t2 to t3): Q1's gate drive signal Vgs1 changes from low to high, turning Q1 on. Crosstalk current flows, charging Cgd2. A positive crosstalk voltage appears on Q2's gate. At this time, due to the increase in the voltage on D3's input side (reference electrode), the current flowing through R11 increases, the voltage drop on D3 decreases, the current in T2's base decreases, the current in R12 decreases, the voltage between 0V and -Vee2 increases, and Q2's negative drive voltage increases again. The speed and magnitude of the change in Q2's negative drive voltage are determined by the speed and magnitude of the change in the positive crosstalk voltage.

[0145] Phase 4 (t3 to t4): The crosstalk on the gate of Q2 ends, the positive peak of the gate voltage of Q2 decreases, the voltage at the input terminal (reference pole) of D3 decreases, the current flowing through R11 decreases, the voltage drop of D3 increases, the base current of T2 increases, the voltage drop of T2 decreases, and the voltage between 0V and -Vee2 returns to the level at time t1.

[0146] Phase 5 (t4 to t5): During this period, Q1 is on and Q2 is off.

[0147] Phase 6 (t5 to t6): At t5, Q1's gate drive signal Vgs1 transitions from high to low, causing the crosstalk current to discharge Cgd2. After the crosstalk-induced oscillation of Q2's gate voltage ends, until t6, Q2's gate voltage Vgs2 rises as the drive signal Vgs2 for the lower transistor Q2 transitions from low to high. During this period, Q2's gate voltage remains low, and D3 is off, keeping the potential difference between 0V and +Vcc2 and -Vee2 constant.

[0148] Phase 7 (t6-t7): At t6, the dead time ends and Q2's gate voltage Vgs2 changes from low to high. As the voltage at D3's input increases, D3's voltage drop decreases, T2's base current decreases, and T2's voltage drop increases. At this point, Q2's negative driving voltage reaches its maximum again and is clamped by D4.

[0149] Figure 15 A crosstalk suppression circuit of a bridge structure composed of parallel SiC MOSFETs is provided in an embodiment of the present application, such as Figure 15 As shown, the bridge structure includes an upper circuit and a lower circuit. The upper circuit includes an upper bridge arm 150, a driver chip 152 corresponding to the upper bridge arm 150, and a variable negative voltage regulation circuit 153; the lower circuit includes a lower bridge arm 151, a driver chip 154 ​​corresponding to the lower bridge arm 151, and a variable negative voltage regulation circuit 155.

[0150] The upper bridge arm 150 includes n parallel SiC MOSFETs; the lower bridge arm 151 includes m parallel SiC MOSFETs; the bridge structure further includes: a line equivalent impedance Rgh and a gate voltage sensing circuit 156 corresponding to each SiC MOSFET in the upper bridge arm 150, and a line equivalent impedance Rgk and a gate voltage sensing circuit 157 corresponding to each SiC MOSFET in the lower bridge arm 151; m and n are both positive integers greater than or equal to 2;

[0151] It can be understood that the first power supply terminal (-Vee), the second power supply terminal (+Vcc), and the 0V power supply terminal (0V) of the driver chip 152 are respectively connected to the first power supply terminal, the second power supply terminal, and the 0V power supply terminal of the variable negative voltage regulation circuit 153; the first power supply terminal (-Vee), the second power supply terminal (+Vcc), and the 0V power supply terminal (0V) of the driver chip 154 ​​are respectively connected to the first power supply terminal, the second power supply terminal, and the 0V power supply terminal of the variable negative voltage regulation circuit 155;

[0152] Each gate voltage sensing circuit 156 includes two resistors R16 and R17. The series branch formed by R16 and R17 is connected between the gate of each SiC MOSFET in the upper bridge arm 150 and the -Vee of the driver chip 152. The common node of each resistor R16 and R17 is connected to the variable negative voltage regulation circuit 155, so that the sensitive gate voltage change is divided by R16 and R17 and input to the variable negative voltage regulation circuit 153.

[0153] Each gate voltage sensing circuit 157 includes two resistors R18 and R19. The series branch formed by R18 and R19 is connected between the gate of each SiC MOSFET in the upper bridge arm 150 and the -Vee of the driver chip 154. The common node of each resistor R18 and R19 is connected to the variable negative voltage regulation circuit 155, so that the sensitive gate voltage change is input to the variable negative voltage regulation circuit 155 after voltage division by the two resistors R18 and R19.

[0154] The performance parameters of each SiC MOSFET in the upper bridge arm 150 may be the same, that is, the parasitic capacitance Cgdh across the gate and drain of each SiC MOSFET, the parasitic capacitance Cgsh across the gate and source of each SiC MOSFET, and the parasitic capacitance Cdsh across the drain and source of each SiC MOSFET may also be the same;

[0155] Similarly, the performance parameters of each SiC MOSFET in the lower bridge arm 151 can be the same, that is, the parasitic capacitance Cgdk across the gate and drain of each SiC MOSFET, the parasitic capacitance Cgsk across the gate and source of each SiC MOSFET, and the parasitic capacitance Cdsk across the drain and source of each SiC MOSFET can also be the same.

[0156] Based on the above embodiments, the present application provides a method for suppressing bridge arm crosstalk, such as Figure 16 As shown, the method includes:

[0157] Step S1601: a first negative voltage regulating circuit is sensitive to a gate voltage change of an upper bridge arm, and in response to the gate voltage change of the upper bridge arm, regulates a negative voltage between the gate and the source of the upper bridge arm to suppress crosstalk to the upper bridge arm;

[0158] Step S1602: The second negative voltage regulating circuit is sensitive to the gate voltage change of the lower bridge arm, and in response to the gate voltage change of the lower bridge arm, regulates the negative voltage between the gate and source of the lower bridge arm to suppress crosstalk to the lower bridge arm.

[0159] The present invention also provides a method for suppressing crosstalk in a bridge arm, the method comprising:

[0160] Step S10: the first gate voltage sensing circuit in the first negative voltage regulating circuit senses a gate voltage change of the upper bridge arm, and transmits the gate voltage change of the upper bridge arm to the first sub-regulating circuit in the first negative voltage regulating circuit;

[0161] Step S11: the first sub-regulation circuit adjusts the negative voltage between the gate and source of the upper bridge arm in response to a change in the gate voltage of the upper bridge arm to suppress crosstalk to the upper bridge arm;

[0162] Step S12: the second gate voltage sensitive circuit in the second negative voltage regulating circuit is sensitive to the gate voltage change of the lower bridge arm, and transmits the gate voltage change of the lower bridge arm to the second sub-regulating circuit in the second negative voltage regulating circuit;

[0163] Step S13: the second sub-regulation circuit adjusts the negative voltage between the gate and the source of the lower bridge arm in response to the gate voltage change of the lower bridge arm to suppress crosstalk to the lower bridge arm.

[0164] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0165] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0166] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned implementation methods. The above-mentioned implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A bridge arm crosstalk suppression circuit, characterized in that: include: An upper bridge arm, a lower bridge arm, a first driver chip and a first negative voltage regulating circuit corresponding to the upper bridge arm, and a second driver chip and a second negative voltage regulating circuit corresponding to the lower bridge arm; The first output terminal of the first driver chip is connected to the first input terminal of the first negative voltage regulation circuit; the second output terminal of the first driver chip is connected to the gate of the upper bridge arm; The second input end of the first negative voltage regulating circuit is connected to the gate of the upper bridge arm; The output end of the first negative voltage regulating circuit is connected to the source of the upper bridge arm; the first negative voltage regulating circuit is used to adjust the negative voltage between the gate and the source of the upper bridge arm according to the gate voltage change of the upper bridge arm, so as to suppress crosstalk to the upper bridge arm; The first output terminal of the second driver chip is connected to the first input terminal of the second negative voltage regulation circuit; the second output terminal of the second driver chip is connected to the gate of the lower bridge arm; The second input terminals of the second negative voltage regulating circuit are respectively connected to the gates of the lower bridge arms; The output end of the second negative voltage regulating circuit is connected to the source of the lower bridge arm; The second negative voltage regulating circuit is used to regulate the negative voltage between the gate and source of the lower bridge arm according to the gate voltage change of the lower bridge arm, so as to suppress crosstalk to the lower bridge arm.

2. The bridge arm crosstalk suppression circuit according to claim 1, characterized in that: The first negative voltage regulation circuit includes a first gate voltage sensitive circuit and a first sub-regulation circuit; The input end of the first gate voltage sensitive circuit is connected to the gate of the upper bridge arm; the output end of the first gate voltage sensitive circuit is connected to the input end of the first sub-regulation circuit; and the output end of the first sub-regulation circuit is connected to the source of the upper bridge arm; A first power supply terminal in the first output terminal of the first driver chip is connected to a first power supply terminal of the first sub-regulation circuit; The second power supply terminal of the first output terminal of the first driver chip is connected to the second power supply terminal of the first sub-regulation circuit; the ground terminal of the first output terminal of the first driver chip is connected to the ground terminal of the first sub-regulation circuit; The first gate voltage sensitive circuit is used to transmit the gate voltage change of the upper bridge arm to the first sub-regulation circuit; The first sub-regulation circuit is configured to regulate the negative voltage between the gate and source of the upper bridge arm in response to a change in the gate voltage of the upper bridge arm, so as to suppress crosstalk to the upper bridge arm.

3. The bridge arm crosstalk suppression circuit according to claim 2, characterized in that: The first gate voltage sensitive circuit at least includes a first series branch formed by a first resistor and a second resistor in series; The first series branch is connected between the gate of the upper bridge arm and the first power supply terminal of the first sub-regulation circuit; the common node of the first resistor and the second resistor is connected to the input terminal of the first sub-regulation circuit; The first series branch is used to transmit the gate voltage change of the upper bridge arm to the first sub-regulation circuit through the voltage change at the common node of the first resistor and the second resistor.

4. The bridge arm crosstalk suppression circuit according to claim 2, characterized in that: The first sub-regulation circuit includes a first voltage stabilization circuit and a first voltage regulation circuit; The output end of the first gate voltage sensitive circuit is connected to the input end of the first voltage stabilizing circuit; the first power input end of the first voltage stabilizing circuit and the first voltage regulating circuit is connected to the first power end of the first output end of the first driver chip; the second power input end of the first voltage stabilizing circuit and the first voltage regulating circuit is connected to the second power end of the first output end of the first driver chip; The output end of the first voltage stabilizing circuit is connected to the input end of the first voltage regulating circuit; the output end of the first voltage regulating circuit is connected to the source of the upper bridge arm and the ground end of the first output end of the first driver chip; the first gate voltage sensitive circuit is used to transmit the gate voltage change of the upper bridge arm to the first voltage stabilizing circuit; The first voltage stabilizing circuit is configured to adjust its own output voltage in response to a change in the gate voltage of the upper bridge arm; The first voltage regulating circuit is used to adjust its own output voltage in response to the adjusted output voltage of the first voltage stabilizing circuit, so as to adjust the negative voltage between the gate and source of the upper bridge arm and suppress crosstalk to the upper bridge arm.

5. The bridge arm crosstalk suppression circuit according to claim 4, characterized in that: The first voltage stabilizing circuit includes a three-terminal voltage stabilizer and a third resistor; The output terminal of the first gate voltage sensitive circuit is connected to the reference terminal of the three-terminal regulator; the positive terminal of the three-terminal regulator is connected to the first power supply terminal of the first output terminal of the first driver chip; the negative terminal of the three-terminal regulator is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the second power supply terminal of the first output terminal of the first driver chip; and the common connection point between the third resistor and the three-terminal regulator is connected to the input terminal of the first voltage regulation circuit; The first gate voltage sensitive circuit is used to transmit the gate voltage change of the upper bridge arm to the three-terminal regulator; The three-terminal voltage regulator is configured to adjust its own impedance in response to a change in the gate voltage of the upper bridge arm, thereby causing a change in the current flowing through the three-terminal voltage regulator; The third resistor is used to adjust the voltage at a common connection point between the third resistor and the three-terminal regulator in response to a change in the current of the three-terminal regulator; Correspondingly, the first voltage regulation circuit is used to adjust its own output voltage in response to the voltage at the common connection point between the adjusted third resistor and the three-terminal regulator, so as to adjust the negative voltage between the gate and source of the upper bridge arm and suppress crosstalk to the upper bridge arm.

6. The bridge arm crosstalk suppression circuit according to claim 4, characterized in that: The first voltage regulating circuit includes a fourth resistor, a fifth resistor and a first transistor; The output end of the first voltage stabilizing circuit is connected to the first end of the fourth resistor; the second end of the fourth resistor is connected to the base of the first transistor; the collector of the first transistor is connected to the first end of the fifth resistor; the second end of the fifth resistor is connected to the second power supply end of the first output end of the first driver chip; the emitter of the first transistor is connected to the first power supply end of the first output end of the first driver chip; A common node between the fifth resistor and the first transistor is connected to the source of the upper bridge arm and the ground terminal of the first output terminal of the first driver chip; The fourth resistor is used to adjust the base current of the first transistor in response to the adjusted output voltage of the first voltage stabilizing circuit; The first transistor is configured to adjust the current on its collector in response to the adjusted base current; The fifth resistor is used to adjust the voltage on the common node of the fifth resistor and the first transistor in response to the adjusted current on the collector of the first transistor, thereby adjusting the negative voltage between the gate and source of the upper bridge arm and suppressing crosstalk to the upper bridge arm.

7. The bridge arm crosstalk suppression circuit according to claim 2, characterized in that: The first negative voltage regulation circuit further includes a voltage regulator tube; the voltage regulator tube is connected between the output terminal of the first sub-regulation circuit and the first power supply terminal of the first sub-regulation circuit; The voltage regulator is used to clamp the voltage between the output end of the first sub-regulation circuit and the first power supply end of the first sub-regulation circuit to a preset voltage.

8. The bridge arm crosstalk suppression circuit according to claim 7, characterized in that: The voltage regulator is a first voltage regulator diode; the positive electrode of the first voltage regulator diode is connected to the first power supply end of the first sub-regulation circuit; the negative electrode of the first voltage regulator diode is connected to the output end of the first sub-regulation circuit.

9. The bridge arm crosstalk suppression circuit according to claim 3, characterized in that: The upper bridge arm includes at least one upper switch tube connected in parallel; the lower bridge arm includes at least one lower switch tube connected in parallel; the first gate voltage sensitive circuit includes a first sub-sensitive circuit corresponding to each upper switch tube; the input end of each first sub-sensitive circuit is connected to the gate of the corresponding upper switch tube; the output end of each first sub-sensitive circuit is connected to the input end of the first sub-regulation circuit; and each sub-sensitive circuit includes a corresponding first series branch.

10. A bridge arm crosstalk suppression method, applied to the bridge arm crosstalk suppression circuit according to any one of claims 1 to 9, characterized in that: The method comprises: The first negative voltage regulating circuit regulates the negative voltage between the gate and the source of the upper bridge arm according to the gate voltage change of the upper bridge arm, so as to suppress the crosstalk to the upper bridge arm; The second negative voltage regulating circuit regulates the negative voltage between the gate and the source of the lower bridge arm according to the gate voltage change of the lower bridge arm, so as to suppress the crosstalk to the lower bridge arm.

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