A multi-source video parsing system and method for NVIDIA architecture

Abstract

The present invention relates to the technical field of video analysis, and specifically to a multi-source video analysis system and method for NVIDIA architecture, including a multi-mode video encoding module and a multi-source video clarification processing module. The architectures of the multi-mode video encoding module and the multi-source video clarification processing module are both supported by NVIDIA. This multi-source video analysis system and method for NVIDIA architecture, through the coordinated use of the multi-mode video encoding module and the multi-source video clarification processing module, and by adopting the FPGA+DSP architecture on the basis of the NVIDIA architecture as the overall architecture of the multi-source video analysis system, enables the present invention to effectively collect and analyze videos of multiple modes, namely multi-source videos, in real time and perform format conversion respectively, thereby effectively improving the analysis efficiency of multi-source videos and enabling efficient transmission of multi-source video data.

Description

Technical Field

[0001] The present invention relates to the technical field of video parsing, and specifically to a multi-source video parsing system and method for NVIDIA architecture. Background Art

[0002] Video has become the most important form of multimedia presentation due to its rich information. With the continuous improvement of people's demand for video applications and the rapid development of embedded video processing technology, video acquisition and processing systems are gradually evolving from single-channel to multi-channel, and the video image resolution is gradually converted from standard definition to high definition. The diversity of video acquisition interfaces and the exponentially increasing data pose severe challenges to multi-source video acquisition and processing systems.

[0003] For this, Chinese Patent Publication (Announcement) No.: CN109669780B discloses a video parsing method and system. The method includes: when detecting that a video parsing task is suspended, if there is a current parsing task to exit, detecting whether the current parsing task to exit and the suspended video parsing task are parsing tasks of the same dimension; if so, sending status retention information to the current parsing task to maintain the current execution state and executing the suspended video parsing task; if not, notifying the current parsing task to exit execution and releasing the GPU resources corresponding to the current parsing task. Through the method provided by the above invention, the GPU memory is fully utilized to concurrently execute multiple parsing tasks, and for successively executing tasks of the same dimension, repeated loading of the parsing model can be reduced, avoiding the time waste caused by repeated loading, and improving the video parsing efficiency and the utilization rate of the GPU.

[0004] However, when using the above method and system, there are still some problems. Firstly, the above method and system cannot perform real-time acquisition and parsing of videos in multiple modes, that is, multi-source videos, and perform format conversion separately, which will reduce the parsing efficiency of multi-source videos. Secondly, although the above invention does have a certain accelerating effect on the parsing efficiency of single-channel videos and low-definition videos, the parsing efficiency of multi-source videos, that is, multi-channel videos and high-definition videos, still cannot be accelerated, that is, it is difficult to achieve efficient transmission of multi-source video data, resulting in the inability to effectively improve the parsing efficiency.

[0005] Therefore, there is an urgent need to invent a multi-source video parsing system and method for NVIDIA architecture to solve the above problems. Summary of the Invention

[0006] The purpose of the present invention is to provide a multi-source video parsing system and method for NVIDIA architecture, so as to solve the problems in the above-mentioned background technology that the existing video parsing systems and methods cannot effectively collect and parse videos in multiple modes in real time and perform format conversion separately, which easily reduces the parsing efficiency of multi-source videos and it is very difficult to achieve efficient transmission of multi-source video data, resulting in the inability to effectively improve the parsing efficiency.

[0007] To achieve the above purpose, the present invention provides the following technical solution: A multi-source video parsing system for NVIDIA architecture, including a multi-mode video encoding module and a multi-source video clarity processing module. The multi-mode video encoding module includes a user control information and multi-mode video data acquisition function module, a video encoding function module, and a compressed bitstream output function module. The user control information and multi-mode video data function module obtains user commands and collects and preprocesses videos in different modes according to the user commands. Different video modes include standard-definition visible light videos, high-definition digital videos, and infrared videos. The video preprocessing reorganizes the input video data and converts it into the format required by the encoding algorithm on the DSP. The video encoding function module runs the encoding algorithm on the DSP side, encodes the formatted data after video processing, and stores the compressed bitstream in a predefined buffer. The compressed bitstream output function module outputs the compressed bitstream encoded on the DSP side to the airborne data transmission device, and the transmission interface between the DSP chip and the FPGA chip uses the EMIF interface integrated in the DSP chip. The multi-source video clarity processing module enhances the video data collected by the external camera and outputs the enhanced video data for screen display and use in the video analysis compressed version. Moreover, the architectures of the multi-mode video encoding module and the multi-source video clarity processing module are both supported by NVIDIA.

[0008] Preferably, the DSP is the main processor, and two DSPs are used for collaborative processing, and the FPGA is the coprocessor.

[0009] Preferably, the implementation of the video encoding function module is jointly completed by the FPGA, the DSP, and their peripheral memories, video acquisition chips, clock modules, and control modules. Its processing flow includes the following steps:

[0010] S1. The system parses the control commands passed in through the external interface. If it is a digital video, the video data enters the FPPA chip of the system through the CameraLink interface. If it is an analog video, the video data enters the FPGA through the SAA7115 video analog-to-digital conversion chip.

[0011] S2. The FPGA collects and preprocesses the video data and transmits the preprocessed video to the DSP through SRIO via SRIO.

[0012] S3 and DSP provide a hardware processing platform for HEVC compression encoding to achieve real-time processing of airborne video images;

[0013] S4. The compressed video stream is sent back to the FPGA through the EMIF interface of the DSP and output through the LVDS cable.

[0014] Preferably, the multi-source video clarity processing module includes a video valid data and control information acquisition module, a video data clarity processing module, and an enhanced video output module. The video valid data and control information acquisition module includes the acquisition and preprocessing of multi-source standard-definition visible light video and the acquisition of control information. Among them, the acquisition and preprocessing of multi-source video transmit the multi-source analog video collected from the camera to the video digital conversion chip through the SMA interface, and after preprocessing the collected video data, provide a formatted video image for the video enhancement algorithm in real time. The acquisition of control information needs to parse the user command and select one source of video from the multi-source video for preprocessing according to the user command. The video data clarity processing module parses the user command and performs video interlacing, video stabilization, video defogging, video enhancement in cloudy and rainy days, and video enhancement at night on the selected source of video according to the user's needs. The enhanced video output module receives the multi-source digital video data from the FPGA, and after digital-to-analog conversion of each source of video, it is allocated to a pair of identical video outputs.

[0015] Preferably, the processing flow of the multi-source video clarity processing module includes the following steps:

[0016] S1. Receive the user command. The host transmits the user command to the FPGA chip through the RS232 serial port. The FPGA chip receives the command and parses the user command. The user command includes controlling the video switching chip to select one source of video from the multi-source video for processing, and at the same time, controlling the selection of the video enhancement mode;

[0017] S2. The source of video selected according to the user command passes through the TVP5158 analog-to-digital conversion chip, converts it into data in standard format and transmits it to the FPGA chip. The FPGA chip preprocesses the source of video and transmits the video to the DDR3 storage area of the DSP chip through the SRIO path;

[0018] S3. Each DSP chip processes one source of video and performs clarity processing on the video according to the user's needs, including video deinterlacing, video stabilization, video defogging, video enhancement in cloudy and rainy days, and video enhancement at night;

[0019] S4. The DSP stores the processed video in the agreed storage area of the DDR3 and notifies the FPGA to read the processed video data. The FPGA chip retrieves the read video data and passes it into its internal digital-to-analog conversion module;

[0020] S5. The digital-to-analog conversion module inside the FPGA chip organizes the processed video data into a standard format and outputs it to the SAF7129 chip, which finally converts the processed video data into an analog video and outputs it to the display through the SMA interface.

[0021] A multi-source video parsing method for NVIDIA architecture. The multi-source video first enters the analog-to-digital conversion chip to obtain digital information containing YCbCr components and retrace line redundant components, and then the data is separated through the FPGA algorithm to obtain valid data containing only YCbCr. The specific steps are as follows:

[0022] S1. Obtain valid data: The A / D data of the analog-to-digital conversion of the multi-source video is used to obtain valid data;

[0023] S2. Separate and buffer the valid data: The preprocessing chip separates and organizes the converted multi-source video;

[0024] S3. Organize the video image data: The preprocessing chip separates and organizes the data of the multi-source video.

[0025] Preferably, the valid data is obtained using a valid state machine, and this state machine is completed on the FPGA chip. The steps for obtaining the valid data are as follows:

[0026] S1. The initial state is IDEL, waiting for data input. If valid data is detected, go to step S2;

[0027] S2. Detect the line start identifier SAV of the valid data. When a valid data line is detected (Vid = 1), enter the SC3 state;

[0028] S3. Detect the channel information SC3 of the state and record the channel information. When BOP = 1 is detected, transfer to SC2;

[0029] S4. Detect the second byte SC2 of the start code. When the line start flag (BOL) and the data valid signal (VDET) are both valid, enter the SC1 state;

[0030] S5. The third byte SC1 of the start code counts the lines. After reaching the current state, directly transfer to the SC0 state;

[0031] S6. The fourth byte SC0 of the start code is used to record the current field number F. When F is 0, it indicates an odd field; when F = 1, it indicates an even field. When it is detected that H is at a low level and V is at a high level, it indicates that the valid data being processed in the current frame starts, and the system enters the DATA-VLD state.

[0032] S7. The DATA-VLD state is the start of valid data, and valid data is read in the next cycle.

[0033] Preferably, during the video data acquisition process, the pixel points of the video frame are counted. If the sum of the odd-field data and the even-field data is equal to the data volume of one frame, the acquisition process continues. If the sum of the odd-field data and the even-field data is less than the data volume of one frame, it indicates that video data is lost and resynchronization is required. At this time, the system will automatically perform a soft reset and re-execute the program.

[0034] Preferably, the separation and buffering of valid data are achieved by deinterleaving the data.

[0035] Preferably, when organizing video image data during the output of camera acquisition, the even rows are scanned first, and then the odd rows are scanned.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows: This multi-source video parsing system and method for the NVIDIA architecture, through the combined use of a multi-mode video coding module and a multi-source video clarification processing module, and by adopting an FPGA+DSP architecture on the basis of the NVIDIA architecture as the overall architecture of the multi-source video parsing system, enables the present invention to effectively perform real-time acquisition and parsing of videos in multiple modes, i.e., multi-source videos, and perform format conversion separately, thereby effectively improving the parsing efficiency of multi-source videos and enabling efficient transmission of multi-source video data. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is the system module diagram of the present invention;

[0038] Figure 2 is the state diagram of the multi-source video image acquisition module of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] Please refer to Figure 1-2 , the embodiments provided by the present invention:

[0041] A multi-source video parsing system for NVIDIA architecture, including a multi-mode video encoding module and a multi-source video clarity processing module. The multi-mode video encoding module includes a user control information and multi-mode video data acquisition function module, a video encoding function module, and a compressed bitstream output function module. The user control information and multi-mode video data function module obtains user commands, and collects and preprocesses videos in different modes according to the user commands. Different video modes include standard-definition visible light video, high-definition digital video, and infrared video. The video preprocessing reorganizes the input video data and converts it into the format required by the encoding algorithm on the DSP. The video encoding function module runs the encoding algorithm on the DSP side, encodes the formatted data after video processing, and stores the compressed bitstream in a predefined buffer. The compressed bitstream output function module outputs the compressed bitstream encoded on the DSP side to the airborne data transmission device, and the transmission interface between the DSP chip and the FPGA chip uses the EMIF interface integrated in the DSP chip. The multi-source video clarity processing module enhances the video data collected by the external camera and outputs the enhanced video data for screen display and use in the video analysis compressed version. Moreover, the architectures of the multi-mode video encoding module and the multi-source video clarity processing module are both supported by NVIDIA. By adopting the FPGA+DSP architecture as the overall architecture of the multi-source video parsing system based on the NVIDIA architecture, selecting the FPGA as the main processing chip for acquisition and preprocessing, and selecting the DSP to perform compression, encoding, and execution of the core algorithm, the requirements for real-time acquisition and preprocessing of the system can be met, thereby achieving the purpose of real-time acquisition and parsing of multi-source videos and performing format conversion respectively.

[0042] Further, as Figure 1 shown, the DSP is the main processor, and two DSPs are used for collaborative processing, mainly for video encoding. The FPGA is the coprocessor, mainly for parsing video control commands, video acquisition and preprocessing, bitstream recovery and output.

[0043] Further, the implementation of the video encoding function module is jointly completed by the FPGA, the DSP, and their peripheral memories, video acquisition chips, clock modules, and control modules. Its processing flow includes the following steps:

[0044] S1. The system parses the control commands passed in through the external interface. If it is digital video, the video data enters the FPPA chip of the system through the CameraLink interface. If it is analog video, the video data enters the FPGA through the SAA7115 video analog-to-digital conversion chip.

[0045] S2. The FPGA collects and preprocesses the video data, and transfers the preprocessed video to the DSP through the SRIO via the SRIO.

[0046] S3. The DSP provides a hardware processing platform for HEVC compression encoding to achieve real-time processing of airborne video images.

[0047] S4. The compressed video stream is sent back to the FPGA through the EMIF interface of the DSP and output through the LVDS cable.

[0048] Furthermore, the multi-source video clarity processing module includes a video valid data and control information acquisition module, a video data clarity processing module, and an enhanced video output module. The video valid data and control information acquisition module includes the acquisition and preprocessing of multi-source standard-definition visible light video and the acquisition of control information. Among them, the acquisition and preprocessing of multi-source video transmit the multi-source analog video collected from the camera to the video digital conversion chip through the SMA interface, and preprocess the collected video data to provide a formatted video image for the video enhancement algorithm in real time. The acquisition of control information needs to parse the user command and select one source of video from the multi-source video for preprocessing according to the user command. In addition, it also needs to support the control of various video clarity processing methods. The video data clarity processing module parses the user command and performs video interlacing, video stabilization, video defogging, video enhancement in cloudy and rainy days, and video enhancement at night on the selected source video according to the user's needs. The enhanced video output module receives the multi-source digital video data from the FPGA, and after digital-to-analog conversion of each source of video, it is allocated to a pair of identical video outputs.

[0049] Furthermore, the processing flow of the multi-source video clarity processing module includes the following steps:

[0050] S1. Receive the user command. The host transmits the user command to the FPGA chip through the RS232 serial port. The FPGA chip receives the command and parses the user command. The user command includes controlling the video switching chip to select one source of video from the multi-source video for processing, and at the same time controlling the selection of the video enhancement mode.

[0051] S2. One source of video selected according to the user command passes through the TVP5158 analog-to-digital conversion chip, converts it into data in standard format and transfers it to the FPGA chip. The FPGA chip preprocesses the one source of video and transfers the video to the DDR3 storage area of the DSP chip through the SRIO path.

[0052] S3. Each DSP chip processes one source of video and performs clarity processing on the video according to the user's needs, including video deinterlacing, video stabilization, video defogging, video enhancement in cloudy and rainy days, and video enhancement at night.

[0053] S4. The DSP stores the processed video in the agreed storage area of the DDR3 and notifies the FPGA to read the processed video data. After the FPGA chip retrieves the read video data, it passes the data into the digital-to-analog conversion module inside it.

[0054] S5. The digital-to-analog conversion module inside the FPGA chip organizes the processed video data into a standard format and outputs it to the SAF7129 chip, which finally converts the processed video data into analog video and outputs it to the display through the SMA interface.

[0055] Furthermore, the present invention also includes a multi-source video parsing method for the NVIDIA architecture. The multi-source video first enters the analog-to-digital conversion chip to obtain digital information containing YCbCr components and flyback line redundant components, and then the data is separated through the FPGA algorithm to obtain the valid data containing only YCbCr. The specific steps are as follows:

[0056] S1. Obtain valid data: The A / D data of the analog-to-digital conversion of the multi-source video is used to obtain valid data.

[0057] S2. Separate and buffer the valid data: The preprocessing chip separates and organizes the converted multi-source video.

[0058] S3. Organize the video image data: The preprocessing chip separates and organizes the data of the multi-source video.

[0059] Furthermore, after the preprocessing chip works normally, not all of the output video data is valid data. Instead, after each row of data output is completed, a part of redundant data will be output. This data is generated during the line flyback period. Therefore, the extraction of the image valid data is responsible for selecting the valid video data from the output data of the A / D decoder for processing, while discarding the redundant data. The valid data is obtained using a valid state machine, and this state machine is completed on the FPGA chip, realizing the acquisition of valid data. After obtaining the valid data, the next step is to perform data deinterleaving and data downsampling to separate the color components of the multi-source video, so as to obtain the video data with the best effect. The steps for obtaining the valid data are as follows:

[0060] S1. Initial state IDEL, wait for data input. If valid data is detected, transfer to step S2.

[0061] S2. Detect the start-of-line identifier SAV of the valid data. When a valid data line is detected (Vid = 1), enter the SC3 state.

[0062] S3. Detect the channel information SC3 in the state and record the channel information. When BOP = 1 is detected, transfer to SC2.

[0063] S4. Detect the second byte SC2 of the start code. When the line start flag (BOL) and the data valid signal (VDET) are both valid, enter the SC1 state;

[0064] S5. For the third byte SC1 of the start code, count the lines. After reaching the current state, directly transition to the SC0 state;

[0065] S6. For the fourth byte SC0 of the start code, its function is to record the current field number F. When F is 0, it represents the odd field. When F = 1, it represents the even field. When it is detected that H is at a low level and V is at a high level, it indicates that the valid data being processed in the current frame starts, and enter the DATA-VLD state;

[0066] S7. The DATA-VLD state is the start of data validity. In the next cycle, valid data starts to be read.

[0067] Furthermore, as Figure 2 shown, during the video data acquisition process, count the pixel points of the video frame. If the sum of the odd-field data and the even-field data is equal to the data volume of one frame, continue the acquisition process. If the sum of the odd-field data and the even-field data is less than the data volume of one frame, it indicates that video data is lost and resynchronization is required. At this time, the system will automatically perform a soft reset and re-execute the program.

[0068] Furthermore, the separation and buffering of valid data are achieved by deinterleaving the data.

[0069] Furthermore, when the video image data is organized during the output of the camera acquisition, the even rows are scanned first, and then the odd rows are scanned.

[0070] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, in any regard, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to encompass all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A multi-source video parsing system for NVIDIA architecture, characterized in that: It includes a multi-mode video encoding module and a multi-source video clarity processing module. The multi-mode video encoding module includes a user control information and multi-mode video data acquisition function module, a video encoding function module, and a compressed bitstream output function module. The user control information and multi-mode video data function module obtains user commands, and collects and preprocesses videos in different modes according to the user commands. Different video modes include standard-definition visible light video, high-definition digital video, and infrared video. The video preprocessing reorganizes the input video data and converts it into the format required by the encoding algorithm on the DSP. The video encoding function module runs the encoding algorithm on the DSP side, encodes the formatted data after video processing, and stores the compressed bitstream in a predefined buffer. The compressed bitstream output function module outputs the compressed bitstream encoded on the DSP side to the airborne data transmission device, and the transmission interface between the DSP chip and the FPGA chip uses the EMIF interface integrated in the DSP chip. The multi-source video clarity processing module enhances the video data collected by the external camera and outputs the enhanced video data for screen display and use in the video analysis compressed version. Moreover, the architectures of both the multi-mode video encoding module and the multi-source video clarity processing module are supported by NVIDIA; The multi-source video clarity processing module includes a video valid data and control information acquisition module, a video data clarity processing module, and an enhanced video output module. The video valid data and control information acquisition module includes the collection and preprocessing of multi-source standard-definition visible light video and the acquisition of control information. Among them, the collection and preprocessing of multi-source video transmits the multi-source analog video collected from the camera to the video digital conversion chip through the SMA interface, and preprocesses the collected video data to provide formatted video images for the video enhancement algorithm in real time. The acquisition of control information needs to parse the user command and select one source of video from the multi-source video for preprocessing according to the user command. The video data clarity processing module parses the user command and performs video interlacing, video stabilization, video dehazing, video enhancement for cloudy and rainy days, and video enhancement for nighttime on the selected source of video according to the user's needs. The enhanced video output module receives the multi-source digital video data from the FPGA, and after digital-to-analog conversion of each source of video, it is allocated to a pair of identical video outputs; The processing flow of the multi-source video clarity processing module includes the following steps: S1. Receive the user command. The host transmits the user command to the FPGA chip through the RS232 serial port. The FPGA chip receives the command and parses the user command. The user command includes controlling the video switching chip to select one source of video from the multi-source video for processing, and at the same time, controlling the selection of the video enhancement mode; S2. One source video selected according to the user command passes through the TVP5158 analog-to-digital conversion chip, is converted into data in a standard format and transmitted to the FPGA chip. The FPGA chip preprocesses the one source video and transmits the video to the DDR3 storage area of the DSP chip through the SRIO path; S3. Each DSP chip processes the one source video and performs video clarity processing according to user requirements, including video deinterlacing, video stabilization, video defogging, video enhancement for cloudy and rainy days, and video enhancement for nighttime; S4. The DSP stores the processed video in the agreed storage area of the DDR3 and notifies the FPGA to read the processed video data. The FPGA chip retrieves the read video data and transmits it to the internal digital-to-analog conversion module; S5. The digital-to-analog conversion module inside the FPGA chip organizes the processed video data into a standard format and outputs it to the SAF7129 chip, which finally converts the processed video data into an analog video and outputs it to the display through the SMA interface.

2. A multi-source video parsing system for the NVIDIA architecture according to claim 1, characterized in that: The DSP is the main processor, and two DSPs are used for collaborative processing. The FPGA is the coprocessor.

3. A multi-source video parsing system for the NVIDIA architecture according to claim 1, characterized in that: The implementation of the video encoding function module is jointly completed by the FPGA, DSP, and their peripheral memories, video acquisition chips, clock modules, and control modules. The processing flow includes the following steps: S1. The system parses the control commands passed in through the external interface. If it is a digital video, the video data enters the FPPA chip of the system through the CameraLink interface. If it is an analog video, the video data enters the FPGA through the SAA7115 video analog-to-digital conversion chip; S2. The FPGA acquires and preprocesses the video data and transmits the preprocessed video to the DSP through the SRIO; S3. The DSP provides a hardware processing platform for HEVC compression encoding to achieve real-time processing of airborne video images; S4. The compressed video bitstream is sent back to the FPGA through the EMIF interface of the DSP and output through the LVDS cable.

4. A multi-source video parsing method for the NVIDIA architecture, implemented based on the multi-source video parsing system for the NVIDIA architecture according to any one of claims 1-3, characterized in that: The multi-source video first enters the analog-to-digital conversion chip to obtain digital information containing YCbCr components and flyback line redundant components, and then the data is separated through the FPGA algorithm to obtain valid data containing only YCbCr. The specific steps are as follows: S1. Obtain valid data: The A / D data analog-to-digital conversion of the multi-source video to obtain valid data; S2. Separation and buffering of valid data: The preprocessing chip separates and organizes the converted multi-source video; S3. Organization of video image data: The preprocessing chip separates and organizes the data of the multi-source video.

5. A multi-source video parsing method for NVIDIA architecture according to claim 4, characterized in that: The acquisition of valid data is performed using a valid state machine, and the state machine is completed on an FPGA chip. The steps for valid data acquisition are as follows: S1. Initial state IDEL, waiting for data input. If valid data is detected, go to step S2; S2. Detect the line start identifier SAV of the valid data. When a valid data line is detected (Vid = 1), enter the SC3 state; S3. Detect the channel information SC3 in the state and record the channel information. When BOP = 1 is detected, go to SC2; S4. Detect the second byte SC2 of the start code. When the line start flag (BOL) and the data valid signal (VDET) are both valid, enter the SC1 state; S5. The third byte SC1 of the start code, count the lines. After reaching the current state, directly go to the SC0 state; S6. The fourth byte SC0 of the start code, which is used to record the current field number F. When F is 0, it represents an odd field. When F = 1, it represents an even field. When H is at a low level and V is at a high level, it means that the valid data processed in the current frame starts, and enter the DATA-VLD state; S7. The DATA-VLD state is the start of data validity. The next cycle starts to read valid data.

6. A multi-source video parsing method for NVIDIA architecture according to claim 5, characterized in that: During the video data acquisition process, count the pixel points of the video frame. If the sum of the odd-field data and the even-field data is equal to the data volume of one frame, continue the acquisition process. If the sum of the odd-field data and the even-field data is less than the data volume of one frame, it means that video data is lost and resynchronization is required. At this time, the system will automatically perform a soft reset and re-execute the program.

7. A multi-source video parsing method for NVIDIA architecture according to claim 6, characterized in that, The separation and buffering of valid data are achieved by deinterleaving the data.

8. A multi-source video parsing method for NVIDIA architecture according to claim 6, characterized in that, When organizing video image data during camera acquisition output, first scan the even lines and then scan the odd lines.

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