Low-power in-memory computing bit cell

Abstract

A memory - in - computing bit cell is provided, which includes a pair of cross - coupled inverters for storing stored bits. The memory - in - computing bit cell includes a logic gate for multiplying the stored bits by input vector bits. The logic gate includes FET transistors. The source terminal of the FET transistor is connected to the output node of the cross - coupled inverter, the gate terminal of the FET transistor is connected to the input vector bit, and the drain terminal of the FET transistor is connected to the first plate of a capacitor. The second plate of the capacitor is connected to a read bit line.

Description

[0001] Priority Claim under 35 U.S.C.§119

[0002] This patent application claims the benefit of priority of U.S. Non - Provisional Application No. 16 / 779,491, filed on January 31, 2020, entitled "Low - Power In - Memory Computing Bit Cell", which is assigned to the assignee of the present application and is hereby incorporated by reference in its entirety. Technical Field

[0003] This application relates to in - memory computing, and more particularly to a low - power in - memory computing bit cell. Background Art

[0004] The computer processing of data typically uses the von Neumann architecture, where data is retrieved from memory for processing in an arithmetic and logic unit. In compute - intensive applications such as machine learning, the data flow in and out of memory becomes a bottleneck for processing speed. To address this data movement bottleneck, in - memory computing architectures have been developed, where data - processing hardware is distributed across bit cells. Summary of the Invention

[0005] According to a first aspect of the present invention, there is provided an in - memory computing memory cell, comprising: a pair of cross - coupled inverters having a first output node for a stored bit; a read bit line; a word line having a voltage responsive to an input bit; a capacitor having a first plate connected to the read bit line; and a first transfer transistor connected between the first output node and a second plate of the capacitor and having a gate connected to the word line.

[0006] According to a second aspect of the present invention, there is provided an in - memory computing memory cell, comprising a pair of cross - coupled inverters having a first output node for a stored bit; a read bit line; a capacitor having a first plate connected to the read bit line; and a first transfer gate connected between the first output node and a second plate of the capacitor, wherein the first transfer gate is configured to close in response to the input bit being true and to open in response to the input bit being false.

[0007] According to a third aspect of the present invention, there is provided a multiply - and - accumulate circuit, comprising a plurality of in - memory computing memory cells arranged in a plurality of columns, wherein each column includes a read bit line, and wherein each in - memory computing memory cell in each column includes a logic gate and includes a capacitor, the logic gate being configured to multiply an input bit by a stored bit, the capacitor having a first plate connected to the read bit line of the column and having a second plate connected to an output node of the logic gate.

[0008] According to a fourth aspect of the present invention, there is provided a method for in-memory computing, comprising: during a reset phase, charging a read bit line for a column of in-memory computing storage units to a supply voltage, while a first plate of a capacitor in each in-memory computing storage unit is connected to the read bit line and a second plate of each capacitor in each in-memory computing storage unit is grounded; during a computing phase after the reset phase in each in-memory computing storage unit, multiplying a corresponding bit of an input vector by a stored bit of the in-memory computing storage unit to drive a second plate of the capacitor of the in-memory computing storage unit through a multiplication signal, while the read bit line remains charged to the supply voltage; and during an accumulation phase after the computing phase, isolating the read bit line from a supply node of the supply voltage, while grounding a second plate of a capacitor of each in-memory computing storage unit to generate an accumulation voltage on the read bit line.

[0009] These and other advantageous features can be better understood by the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Illustrates a first in-memory computing bit cell according to one aspect of the present invention.

[0011] Figure 2A Illustrates a multiply-accumulate circuit including an array of in-memory computing bit cells according to one aspect of the present invention.

[0012] Figure 2B Illustrates a column of in-memory computing bit cells of a multiply-accumulate circuit according to one aspect of the present invention.

[0013] Figure 3 Illustrates a second in-memory computing bit cell according to one aspect of the present invention.

[0014] Figure 4 Illustrates a third in-memory computing bit cell according to one aspect of the present invention.

[0015] Figure 5 Illustrates a fourth in-memory computing bit cell according to one aspect of the present invention.

[0016] Figure 6 Is a flowchart of an exemplary in-memory computing method according to one aspect of the present invention.

[0017] Figure 7 Illustrates some example electronic systems, each electronic system including a multiply-accumulate circuit having an array of in-memory computing bit cells according to one aspect of the present invention.

[0018] Embodiments of the present invention and their advantages are best understood by reference to the following detailed description. It should be appreciated that like reference numerals are used to identify like elements shown in one or more of the accompanying drawings. Detailed Description

[0019] A memory-in-compute storage cell, such as a memory-in-compute bit cell, is provided that includes an SRAM cell that stores a bit using two cross-coupled inverters. One of the cross-coupled inverters drives a true (Q) output node using the stored bit, while the remaining cross-coupled inverter drives a complement (QB) output node using the complement of the stored bit. The memory-in-compute bit cell also includes a capacitor having a first plate connected to a read bit line (RBL). As used herein, "connected" means a direct electrical connection, although such a direct connection may be implemented through intermediate elements such as resistors, capacitors, or inductors. The Q output node is coupled to a second plate of the capacitor through a first transfer transistor such as a p-type metal oxide semiconductor (PMOS) first transfer transistor. Similarly, the QB output node is coupled to the second plate of the capacitor through a second transfer transistor such as a PMOS second transfer transistor. The Q output node is also referred to herein as the first output node. Similarly, the QB output node is also referred to herein as the second output node. An input vector bit controls the gate of the first transfer transistor, while the complement of the input vector bit controls the gate of the second transfer transistor.

[0020] The second plate for the capacitor is coupled to ground through a reset transistor such as an n-type metal oxide semiconductor (NMOS) reset transistor having a gate controlled by a read word line (RWL). During a reset phase of the memory-in-compute bit cell, the read bit line is charged high to a supply voltage VDD, and the read word line is asserted to the supply voltage VDD to charge the capacitor. During a compute phase after the reset phase, the read word line is discharged to turn off the reset transistor, while the read bit line remains charged to the supply voltage VDD. If both the input vector bit and the stored bit are true, the first transfer transistor conducts to charge the second plate of the capacitor to the supply voltage VDD. Similarly, if both the input vector bit and the stored bit are false, the second transfer transistor is conducted to charge the second plate of the capacitor. Since the first plate of the capacitor remains connected to a power node at the supply voltage VDD during the compute phase, charging the second plate to the supply voltage VDD discharges the capacitor. On the other hand, if the input vector bit and the stored bit have complementary values, during the compute phase, neither the first transfer transistor nor the second transfer transistor conducts. In this case, the second plate of the capacitor remains discharged, causing the capacitor to remain charged to the supply voltage VDD.

[0021] If the input vector bit is a low - level - active signal, the in - memory computing unit implements a XNOR (exclusive NOR) of the input vector bit and the stored bit during the computing phase, where a logical true output (capacitor charging) is obtained if the input vector bit and the stored bit have the same binary value, and a logical false output (capacitor discharging) is obtained if the input vector bit and the stored bit do not have the same binary value. If the input vector bit is a high - level - active signal, the in - memory computing bit cell may implement an XOR (exclusive OR) of the stored bit and the input vector bit.

[0022] The resulting in - memory computing bit cell is quite advantageous because the resulting capacitor is fully - rail charged (i.e., either charged to the supply voltage VDD or discharged to ground). Additionally, the transmission gate does not need to transfer a full - rail output. Also, for the resulting rail - to - rail output, the read word line that asserts the conduction of the reset transistor does not need to be asserted above the supply voltage VDD. Finally, the reset transistor and the rest of the transistors in the in - memory computing bit cell can be high - voltage (thick - oxide) transistors to limit leakage. Now, a more detailed discussion of some example in - memory computing bit cells is provided.

[0023] Now, turning to the drawings, Figure 1 An example in - memory computing bit cell 100 is shown. A pair of cross - coupled inverters 105 stores the stored bit at the true output node Q and also stores the complement of the bit at the complement output node QB. As is known in SRAM technology, when the write word line (WWL) is asserted to the supply voltage VDD to turn on the corresponding pair of NMOS access transistors M1 and M2, the stored bit is written into the in - memory computing bit cell 100 from the bit line BL and the complement bit line BLB. The access transistor M1 is also denoted herein as the first access transistor. Similarly, the access transistor M2 is also denoted herein as the second access transistor. The true output node Q is connected to the source of the PMOS first transfer transistor P1, and the drain of the PMOS first transfer transistor P1 is connected to the second plate of the capacitor C and the drain of the NMOS reset transistor M3. Similarly, the complement output node QB is connected to the source of the PMOS second transfer transistor P2, and the drain of the PMOS second transfer transistor P2 is connected to the second plate of the capacitor C and the drain of the reset transistor M3. The low - level - active input vector bit on the pre - charge word line PCWL controls the gate of the first transfer transistor P1. Similarly, the complement of the low - level - active input vector bit on the complement pre - charge word line PCWLB controls the gate of the second transfer transistor P2. For simplicity, the pre - charge word line PCWL is also denoted herein as just the word line.

[0024] The first plate of capacitor C is connected to the read bit line RBL. Before the calculation phase, capacitor C is reset during the reset phase for the in-memory computing bit cell 100. During the reset phase, the reset signal carried on the reset line is asserted to turn off the switch S1 connected between the node of the read bit line and the power supply voltage VDD. Thus, the read bit line is charged to the power supply voltage VDD during the reset phase. When the reset signal is asserted, the read word line connected to the gate of the reset transistor M3 is also asserted. The source of the reset transistor M3 is grounded so that when the read word line is asserted, the reset transistor M3 conducts to ground the second plate of capacitor C. Thus, capacitor C is charged to the power supply voltage VDD during the reset phase. During the reset phase, the precharge word line and the complement precharge word line are both charged to the power supply voltage VDD to keep both the transfer transistors P1 and P2 off.

[0025] During the calculation phase for computing the binary multiplication of the stored bit and the input vector bit, the precharge word line and the complement precharge word line are charged according to the value of the input vector bit while the reset signal is asserted to keep the read bit line charged to the power supply voltage VDD. The read word line is deasserted during the calculation phase, so the second plate of capacitor C floats with respect to ground. In a low-active embodiment, if the input vector bit is true, the precharge word line is discharged. At the same time, the complement precharge word line is then charged high to the power supply voltage VDD. Conversely, in a low-active embodiment, if the input vector bit is false, the precharge word line is charged to the power supply voltage VDD while the complement precharge word line is discharged. If the precharge word line is discharged due to the true value of the input vector bit and the stored bit is also true, the transfer transistor P1 will conduct to charge the second plate of capacitor C to the power supply voltage VDD. Since the read bit line is connected to the power supply node of the power supply voltage VDD, capacitor C is discharged due to the charging of the second plate. The same discharge of capacitor C occurs when both the stored bit and the input vector bit are false. In this case, the second transfer transistor P2 conducts during the calculation phase to charge the second plate of the capacitor. But if the input vector bit and the stored bit have complementary binary values, neither of the transfer transistors P1 and P2 will conduct. Then, the second plate remains discharged so that capacitor C remains charged. Thus, the resulting multiplication is the XNOR of the input vector bit and the stored bit. On the other hand, if the input vector bit is a high-active signal, the multiplication will be the XOR of the input vector bit and the stored bit.

[0026] The accumulation phase follows the computation phase. During the accumulation phase, the read word line is asserted while the reset signal is de-asserted. Thus, since switch S1 is opened by the de-assertion of the reset signal, the read bit line is isolated from the power supply node during the accumulation phase. Due to the assertion of the read word line to the power supply voltage VDD, the second plate of capacitor C is grounded during the accumulation phase when the reset transistor M3 is turned on.

[0027] The reset, computation, and accumulation phases apply to the in-memory computing bit cell columns in a multiply-accumulate circuit as disclosed herein. Figure 2A The example multiply-accumulate (MAC) circuit 200 shown in includes an array 220 of in-memory computing bit cells 100 arranged in rows and columns. The stored bits in the array 220 can be considered to form a matrix that is multiplied by the input vector din 225. For example, the dimension of the input vector din 225 can be 128 in the MAC circuit 200, such that the input vector din 225 ranges from the first bit din 1 of the input vector to din 128 of one hundred and twenty-eight bits. The input vector din 225 is sequentially changed such that for each instance, the input vector din 225 is multiplied by the matrix stored in the array 220, and the result is sequentially integrated in the sequential integrator 215. To perform matrix multiplication, the input vector din 225 is multiplied column by column with the contents of the array 220.

[0028] Figure 2B An example column 230 of the array 220 is shown in more detail. Each row in the array 220 is represented by a corresponding in-memory computing bit cell 100 in the column 230. For clarity of illustration, Figure 2BOnly three in-memory computing bit cells 100 are shown, but it should be appreciated that there may be in-memory computing bit cells 100 in each row of the array 220. Since the dimension of the input vector din225 is 128, there are 128 rows in the array 220. It should be appreciated that in alternative embodiments, this dimension may vary. The in-memory computing bit cell 100 for the first row in the column 230 performs the multiplication of its stored bit with the first bit din 1 of the input vector. Similarly, the in-memory computing bit cell 100 for the second row in the column 230 may perform the multiplication of its stored bit with the second bit din 2 of the input vector, and so on, such that the in-memory computing bit cell 100 for the 128th row in the column 230 may perform the multiplication of its stored bit with the last bit din 128 of the input vector. Each in-memory computing bit cell 100 in the column 230 maintains the charge of its capacitor or discharges its capacitor according to the multiplication result, and correspondingly affects the voltage of the read bit line (RBL) during the accumulation phase. Therefore, the read bit line is global for all in-memory computing bit cells 100 in the column 230. Similarly, the bit line (BL) and the complementary bit line (BLB) are also global for all in-memory computing bit cells 100 in the column 230. Figure 1 The switch S1 of Figure 1 is implemented by the PMOS transistor P4 in the column 230. In some embodiments, the reset transistor M3 is also referred to herein as the third transistor, and the transistor P4 is also referred to herein as the fourth transistor. In other embodiments, the reset transistor M3 is referred to herein as the first transistor, and the transistor P4 is referred to herein as the second transistor.

[0029] The voltage on the read bit line of column 230 during the accumulation phase represents the analog result of multiplying a row of the matrix stored in array 220 by the input vector din 225 after multiplying its stored bits by the input vector din 225. The read bit line voltage is also referred to herein as the accumulation voltage. To convert this analog result to a digital value, each column 230 includes an analog-to-digital converter (ADC) 205. In column 230, the ADC 205 is represented by comparator 235. In some embodiments, the ADC 205 can be a multi-bit ADC that provides a digital result at once, and the digital results are summed by a multi-bit summing circuit 210 to provide a multi-bit weight or digital result for the multiplication of the matrix row by the input vector din 225. When the order of the input vector din 225 changes, each instantiation of the input vector din 225 is multiplied by the bits stored in each column 230, and the multi-bit results are stored in the corresponding sequential integrator 215. Thus, in some embodiments, on a one-to-one basis, there is an ADC 205, a multi-bit summing circuit 210, and a sequential integrator 215 for each column 230. When the order of the input vector din 225 changes to form a sequential input, each sequential integrator 215 sequentially integrates the multiplication accumulation results of its column 230.

[0030] The resulting matrix multiplication is quite advantageous because the linearity of the result basically depends on whether the capacitor C of each in-memory computing bit cell 100 can be reproduced with minimal variation. This is easily achievable in modern semiconductor manufacturing technologies, such as by implementing each capacitor C as a metal layer capacitor, so that the multiply-accumulate operation is advantageously linear. In alternative embodiments, each capacitor C can be implemented using varactors, metal-insulator-metal capacitors, or other suitable structures. The linearity also depends on the ADC 205. To reduce the die space required for each ADC 205 and improve linearity, the in-memory computing bit cell 100 can be modified such that the capacitor C can be used in the operation of the ADC 205 as follows. Figure 3 An example of a modified in-memory computing bit cell 300 is shown. As discussed for the in-memory computing bit cell 100, the in-memory computing bit cell 300 can be arranged, except that a PMOS transistor P3 is introduced, the source of which is connected to the power supply node and the drain of which is connected to the second plate of the capacitor C. Additionally, switch S1 is implemented as a PMOS transistor P4, as Figure 2B shown.

[0031] The addition of transistor P3 is also advantageous because capacitor C can be reused as part of a capacitive digital-to-analog converter (CDAC), such as in an embodiment where each ADC 205 is a multi-bit successive approximation register (SAR) ADC. After the columns 300 of the in-memory computing bit cells have charged their read bit lines with the multiplication results across the columns during the accumulation phase, the read word line voltage can be sampled by another capacitor (not shown). With the sampled voltage captured by this additional capacitor, the read bit lines can then be discharged to ground. Then, the second plate of the selected capacitor C in capacitor C can be selectively driven to the supply voltage VDD by turning on transistor P3 in the selected in-memory computing bit cell 300 in the column to selectively raise the resulting sampled voltage. Specifically, a DAC signal BTP, such as controlled by a finite state machine (not shown), is discharged for the selected in-memory computing bit cell 300 to raise the sampled voltage from the column multiplication. The remaining in-memory computing bit cells 300 in the column may float the second plates of their capacitors C so as not to affect the desired raise. Alternatively, the sampled voltage can be selectively reduced by asserting their DAC signals BTP to turn on the reset transistors M3 in the selected in-memory computing bit cell 300 to ground the second plates of the selected capacitors C. In an embodiment with 128 rows of in-memory computing bit cells 300, the resulting DAC resolution may be seven bits. Generally, the resolution can be increased or decreased by correspondingly changing the array size of the bit cells 300.

[0032] Whether or not transistor P3 is included, the in-memory computing bit cell multiplication disclosed herein is not limited to using transfer transistors P1 and P2 to drive the second plates of the corresponding capacitors C. For example, the bit cell 100 in the computing memory can be modified to use the transmission gates of the in-memory computing bit cell 400 as shown Figure 4 to replace transfer transistors P1 and P2. The transmission gates also ensure that full rail signals (ground or supply voltage VDD) are passed to the second plates of the capacitors C. Specifically, the first transmission gate T1 controls whether the stored bit on the Q output node of the cross-coupled inverter 105 can pass through to affect the second plate voltage of capacitor C. Similarly, the second transmission gate T2 controls whether the complement of the stored bit on the QB output node can pass through to affect the second plate voltage of capacitor C. The precharge word line PCWLA and the complement precharge word line PCWLA_B control whether the transmission gate T1 or T2 is open or closed.

[0033] The input bit controls the state of the precharge word line PCWLA. Similarly, the complement of the input bit controls the state of the complementary precharge word line PCWLA_B. The first transmission gate T1 is configured such that the first transmission gate T1 turns off in response to the input bit being true (active low in the XNOR implementation) and turns on in response to the input bit being false. The input bit (e.g., an input vector bit) can be active low or active high, depending on whether XNOR-based multiplication or XOR-based multiplication is required. The precharge word line PCWLA drives the gate of the PMOS transistor in the first transmission gate T1. Similarly, the complementary precharge word line PCWLA_B drives the gate of the NMOS transistor in the first transmission gate T1.

[0034] This coupling is inverted in the second transmission gate T2 such that the complementary precharge word line PCWLA_B drives the gate of the PMOS transistor in the second transmission gate T2. Similarly, the precharge word line PCWLA drives the gate of the NMOS transistor in the second transmission gate T2. Thus, the second transmission gate T2 is configured such that the second transmission gate T2 turns off in response to the complementary input vector bit being true and turns on in response to the complementary input vector bit being false. During the evaluation phase of performing XNOR (or XOR)-based multiplication in the in-memory computing bit cell 400, only one of the transmission gates T1 and T2 will be off and the other will be on, depending on the binary state of the input bit. The remaining components in the in-memory computing bit cell 400 are as discussed with respect to the in-memory computing bit cell 100. For clarity of illustration, the access transistors M1 and M2, the write word line WWL, and the bit lines BL and BLB are not shown in Figure 4 the figure.

[0035] The in-memory computing bit cell 300 can also be modified to include the first transmission gate T1 and the second transmission gate T2, as shown for the in-memory computing bit cell 500 in Figure 5 the figure. The remaining components in the in-memory computing bit cell 500 are as discussed for Figure 3 the figure. For clarity of illustration, the access transistors M1 and M2, the write word line WWL, and the bit lines BL and BLB are not shown in Figure 5 the figure. The operation of the first transmission gate T1 and the second transmission gate T2 in the in-memory computing bit cell 500 is as discussed with respect to the in-memory computing bit cell 400.

[0036] Figure 6A flowchart of an example in-memory computing method is shown. The method includes an operation 600 that occurs during a reset phase and includes: charging the read bitlines of the in-memory computing storage cell columns to a supply voltage while the first plates of the capacitors in each in-memory computing storage cell are connected to the read bitlines and the second plates of each capacitor in each in-memory computing storage cell are grounded. This example of the reset phase occurs when transistor P4 is turned on and Figure 2B each read wordline of column 230 of

[0037] is asserted. The method further includes an operation 605 that occurs during a computing phase after the reset phase and includes, for each in-memory computing storage cell, multiplying the corresponding bit of the input vector by the stored bit of the in-memory computing storage cell to drive the second plate of the capacitor of the in-memory computing storage cell using a multiplication signal while the read bitlines remain charged to the supply voltage. Examples of the multiplication signal are the XNOR output signals from transfer transistors P1 and P2 in in-memory computing bit cells 100 and 300 and the XNOR output signals from the first transfer gate T1 or the second transfer gate T2 of in-memory computing bit cells 400 and 500. In an XOR logic gate embodiment, the multiplication signal is the XOR output signal.

[0038] Finally, the method includes an operation 610 that occurs during an accumulation phase after the computing phase. Operation 610 includes: isolating the read bitlines from the supply node of the supply voltage while the second plates of the capacitors of each in-memory computing storage cell are grounded to generate an accumulation voltage on the read bitlines. An example of the accumulation voltage is the read bitline voltage of any of the in-memory computing bit cells 100, 300, 400, or 500 after transistor P4 is turned off and reset transistor M3 is turned on after the computing phase.

[0039] The in-memory computing bit cells as disclosed herein can be advantageously incorporated into any suitable mobile device or electronic system. For example, as Figure 7 shown, a cellular phone 700, a laptop computer 705, and a tablet PC 710 can each include an in-memory computing bit cell having an in-memory computing bit cell according to the present invention, such as for machine learning applications. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with in-memory computing constructed according to the present invention.

[0040] It should be understood that many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the apparatus of the present invention without departing from its scope. In view of this, the scope of the present invention should not be limited to the scope of the specific embodiments shown and described herein, as these specific embodiments are only some examples thereof, but should be fully commensurate with the scope of the following appended claims and their functional equivalents.

Claims

1. A memory - in - compute storage cell, comprising: A pair of cross - coupled inverters having a first output node for storing a bit; A read bit line; A word line having a voltage responsive to an input bit; A capacitor having a first plate connected to the read bit line; And A first transfer transistor connected between the first output node and a second plate of the capacitor and having a gate connected to the word line, Wherein the pair of cross - coupled inverters includes a second output node for the complement of the stored bit; The memory - in - compute storage cell further comprises: A complement word line having a voltage responsive to the complement of the input bit; A second transfer transistor connected between the second output node and the second plate of the capacitor and having a gate connected to the complement word line; A read word line; A third transistor connected between the second plate of the capacitor and ground and having a gate connected to the read word line; A fourth transistor connected between a power node for a power supply voltage and the read bit line; and A reset line for a reset signal, wherein the gate of the fourth transistor is connected to the reset line.

2. The memory - in - compute storage cell according to claim 1, wherein both the first transfer transistor and the second transfer transistor are p - type metal - oxide - semiconductor (PMOS) transistors.

3. The memory - in - compute storage cell according to claim 1, wherein the third transistor is an n - type metal - oxide - semiconductor (NMOS) transistor, and the n - type metal - oxide - semiconductor (NMOS) transistor has a source connected to ground and a drain connected to the second plate of the capacitor.

4. The memory - in - compute storage cell according to claim 1, wherein the fourth transistor is a PMOS transistor, and the PMOS transistor has a source connected to the power node and a drain connected to the read bit line.

5. The memory - in - compute storage cell according to claim 1, further comprising: A write bit line; A complement write bit line; A first access transistor connected between the write bit line and the first output node; And A second access transistor connected between the complement write bit line and the second output node.

6. The memory - in - compute storage cell according to claim 5, further comprising: A write word line, wherein the write word line is connected to the gate of the first access transistor and connected to the gate of the second access transistor.

7. The memory - in - compute storage cell according to claim 1, further comprising a fifth transistor connected between the second plate of the capacitor and the power node.

8. The memory - in - compute storage cell according to claim 1, wherein the memory - in - compute storage cell is included in a column of an array of memory - in - compute storage cells.

9. The memory - in - compute storage cell according to claim 1, wherein the capacitor is selected from the group consisting of a metal - layer capacitor, a varactor diode, and a metal - insulator - metal capacitor.

10. The in-memory computing storage cell according to claim 3, wherein the third transistor is a thick oxide transistor.

11. An in-memory computing storage cell, comprising: A pair of cross-coupled inverters having a first output node for storing a bit; A read bit line; A capacitor having a first plate connected to the read bit line; And A first transmission gate connected between the first output node and a second plate of the capacitor, wherein the first transmission gate is configured to be closed in response to the input bit being true and to be opened in response to the input bit being false, Wherein the pair of cross-coupled inverters includes a second output node for the complement of the stored bit; The in-memory computing storage cell further comprises: A second transmission gate connected between the second output node and the second plate of the capacitor, wherein the second transmission gate is configured to be opened in response to the input bit being true and to be closed in response to the input bit being false; A read word line; A first transistor connected between the second plate of the capacitor and ground and having a gate connected to the read word line; A second transistor connected between a power node for a power supply voltage and the read bit line; and A reset line for a reset signal, wherein the gate of the second transistor is connected to the reset line.

12. The in-memory computing storage cell according to claim 11, wherein the input bit is a low-level effective signal.

13. The in-memory computing storage cell according to claim 11, wherein the first transistor is an n-type metal oxide semiconductor (NMOS) transistor, the n-type metal oxide semiconductor (NMOS) transistor having a source connected to ground and a drain connected to the second plate of the capacitor.

14. The in-memory computing storage cell according to claim 11, wherein the second transistor is a PMOS transistor, the PMOS transistor having a source connected to the power node and a drain connected to the read bit line.

15. A multiply-accumulate circuit, comprising: A plurality of in-memory computing storage cells arranged in a plurality of columns, wherein each column includes a read bit line, and wherein each in-memory computing storage cell in each column includes logic gates and includes a capacitor, the logic gates being configured to multiply an input bit by a stored bit, the capacitor having a first plate connected to the read bit line of the column and a second plate connected to an output node for a logic gate, Wherein each in-memory computing storage cell in each column further comprises: A pair of cross-coupled inverters having a first output node for storing a bit and a second output node for the complement of the stored bit; A first transmission transistor connected between the first output node and the second plate of the capacitor and having a gate connected to a word line, A complement word line having a voltage responsive to the complement of the input bit; A second transmission transistor connected between the second output node and the second plate of the capacitor and having a gate connected to the complement word line; A read word line; A first transistor, connected between the second plate of the capacitor and ground and having a gate connected to the read word line; A second transistor, connected between a power supply node for a power supply voltage and the read bit line; and A reset line for a reset signal, wherein the gate of the second transistor is connected to the reset line.

16. The multiply-accumulate circuit according to claim 15, further comprising: A plurality of analog-to-digital converters, corresponding one-to-one with the plurality of columns, each analog-to-digital converter being configured to convert the voltage of the read bit line for the corresponding column into a digital value.

17. The multiply-accumulate circuit according to claim 16, wherein each analog-to-digital converter is a multi-bit analog-to-digital converter.

18. The multiply-accumulate circuit according to claim 16, wherein each analog-to-digital converter is a successive approximation register analog-to-digital converter including a digital-to-analog converter.

19. The multiply-accumulate circuit according to claim 16, further comprising: A plurality of sequential integrators, corresponding one-to-one with the plurality of columns, wherein each sequential integrator is configured to integrate the digital values from the analog-to-digital converters of the corresponding column.

20. The multiply-accumulate circuit according to claim 15, wherein each logic gate is an XNOR (exclusive NOR) logic gate.

21. The multiply-accumulate circuit according to claim 15, wherein each logic gate is an XOR (exclusive OR) logic gate.

22. The multiply-accumulate circuit according to claim 15, wherein the multiply-accumulate circuit is integrated into a mobile device.

23. The multiply-accumulate circuit according to claim 22, wherein the mobile device is a cellular phone.

24. A method for in-memory computing, comprising: During a reset phase, charging the read bit lines for the columns of in-memory computing storage units to a power supply voltage, while the first plates of the capacitors in each in-memory computing storage unit are connected to the read bit lines, and while the second plates of each capacitor in each in-memory computing storage unit are grounded; During a computing phase after the reset phase in each in-memory computing storage unit, multiplying the corresponding bits of an input vector by the stored bits of the in-memory computing storage unit to drive the second plates of the capacitors of the in-memory computing storage unit with a multiplication signal, while the read bit lines remain charged to the power supply voltage; And During an accumulation phase after the computing phase, isolating the read bit lines from the power supply node for the power supply voltage, while the second plates of the capacitors of each in-memory computing storage unit are grounded to generate an accumulation voltage on the read bit lines, Wherein each in-memory computing storage unit in each column further comprises: A pair of cross-coupled inverters, having a first output node for a stored bit and a second output node for the complement of the stored bit; A first transfer transistor, connected between the first output node and the second plate of the capacitor and having a gate connected to a word line, A complement word line, having a voltage responsive to the complement of an input bit; A second transfer transistor, connected between the second output node and the second plate of the capacitor and having a gate connected to the complement codeword line; A read word line; A first transistor, connected between the second plate of the capacitor and ground and having a gate connected to the read word line; A second transistor, connected between a power supply node for a power supply voltage and the read bit line; and A reset line for a reset signal, wherein the gate of the second transistor is connected to the reset line.

25. The method according to claim 24, further comprising: Converting the accumulated voltage into a digital value.

26. The method according to claim 24, wherein the input vector is an input vector for a machine learning application.

27. The method according to claim 24, further comprising: Sequentially changing the input vector to produce a sequence of digital values; And Integrating the sequence of digital values.

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