Integrated Circuit Verification Method, Device, Simulation System, Electronic Device and Medium

Abstract

The present disclosure provides an integrated circuit verification method, apparatus, simulation system, electronic device, and storage medium. Among them, the method includes: obtaining a configuration file of an excitation data sequence corresponding to an integrated circuit to be tested, and constructing a test environment based on description information corresponding to the integrated circuit to be tested; wherein, the excitation data sequence includes multiple frames of excitation data; the configuration file includes configuration information corresponding to each of the multiple frames of excitation data; reading the configuration information corresponding to each frame of excitation data from the configuration file, and performing simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence; obtaining a verification result of the integrated circuit to be tested based on the simulation processing result and a true result corresponding to the excitation data sequence.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to an integrated circuit verification method, device, simulation system, electronic equipment and storage medium. Background Art

[0002] As people's requirements for image processing effects and functions become higher and higher, the market's technical requirements for image signal processing (ISP) chips in the consumer electronics field are also getting higher and higher, which has led to rapid iteration of ISP chip technology. High resolution and high frame rate have almost become the necessary level for cutting-edge ISP chips. Market demand is driving the development of ISP chips, but the development of ISP chips has also brought about the exponential increase in the complexity of the ISP chip verification process and the long verification time. Summary of the invention

[0003] The embodiments of the present disclosure at least provide an integrated circuit verification method, device, electronic device and storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides an integrated circuit verification method, comprising:

[0005] Obtaining a configuration file of a stimulus data sequence corresponding to the integrated circuit to be tested, and constructing a test environment based on description information corresponding to the integrated circuit to be tested; wherein the stimulus data sequence includes multiple frames of stimulus data; and the configuration file includes configuration information corresponding to the multiple frames of stimulus data respectively;

[0006] Reading configuration information corresponding to each frame of excitation data from the configuration file, and performing simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence;

[0007] Based on the simulation processing result and the real result corresponding to the stimulus data sequence, a verification result of the integrated circuit to be tested is obtained.

[0008] In a second aspect, an embodiment of the present disclosure further provides an integrated circuit verification device, including:

[0009] An acquisition module is used to acquire a configuration file of a stimulus data sequence corresponding to the integrated circuit to be tested, and to construct a test environment based on the description information corresponding to the integrated circuit to be tested; wherein the stimulus data sequence includes multiple frames of stimulus data; and the configuration file includes configuration information corresponding to the multiple frames of stimulus data respectively;

[0010] A simulation module, configured to read configuration information corresponding to each frame of excitation data from the configuration file, and perform simulation processing on each frame of excitation data based on the test environment and the read configuration information, so as to obtain a simulation processing result corresponding to the excitation data sequence;

[0011] A verification module, configured to obtain a verification result of the integrated circuit to be tested based on the simulation processing result and the true result corresponding to the excitation data sequence.

[0012] In a third aspect, an embodiment of the present disclosure further provides a simulation system for an integrated circuit to be tested, including: an excitation generation module, a module to be tested, and a microcontroller;

[0013] The excitation generation module is configured to sequentially read out multiple frames of excitation data in the excitation data sequence stored in a preset first storage space, and send each frame of excitation data to the module to be tested in a preset time sequence;

[0014] The microcontroller is configured to read configuration information corresponding to each frame of excitation data from a configuration file corresponding to the excitation data sequence, and send the configuration information corresponding to each frame of excitation data to the module to be tested; wherein, the configuration file is pre-stored in the microcontroller;

[0015] The module to be tested is configured to, in response to receiving each frame of excitation data and the configuration information corresponding to each frame of excitation data, perform simulation processing on each frame of excitation data based on the configuration information corresponding to each frame of excitation data, so as to obtain a simulation processing result corresponding to each frame of excitation data.

[0016] In a fourth aspect, an alternative implementation manner of the present disclosure further provides an electronic device, including a processor and a memory, where the memory stores machine-readable instructions executable by the processor, and the processor is configured to execute the machine-readable instructions stored in the memory. When the machine-readable instructions are executed by the processor, the machine-readable instructions are executed to implement the first aspect above; or including the simulation system as described in the third aspect above.

[0017] In a fifth aspect, an alternative implementation manner of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run, it executes the first aspect above, or the steps in any possible implementation manner of the first aspect.

[0018] The integrated circuit verification method disclosed in the embodiments of the present disclosure constructs a test environment by using the description information corresponding to the integrated circuit to be tested; after obtaining the configuration file of the excitation data sequence corresponding to the integrated circuit to be tested, it can automatically read the configuration information corresponding to each frame of excitation data from the configuration file, and use the test environment and the automatically read configuration information to perform simulation processing on each frame of excitation data, thereby realizing the automatic transplantation of the configuration parameters of the excitation data, improving the transplantation efficiency of the configuration parameters, and reducing the probability of errors easily occurring during the transplantation of the configuration parameters.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the technical solution of the present disclosure.

[0020] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required to be used in the embodiments. The drawings herein are incorporated into the specification and constitute a part of this specification. These drawings show the embodiments that conform to the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0022] Figure 1 Shows the flowchart of the integrated circuit verification method provided by some embodiments of the present disclosure;

[0023] Figure 2 Shows a specific schematic diagram of the test environment structure provided by some embodiments of the present disclosure;

[0024] Figure 3 Shows a specific schematic diagram of the microcontroller firmware controlling the operation of the microcontroller provided by some embodiments of the present disclosure;

[0025] Figure 4 Shows a specific schematic diagram of the microcontroller performing register configuration on multiple frames of images provided by some embodiments of the present disclosure;

[0026] Figure 5 Shows a schematic diagram of the integrated circuit verification device provided by some embodiments of the present disclosure;

[0027] Figure 6 Shows a schematic diagram of the integrated circuit verification device provided by some embodiments of the present disclosure;

[0028] Figure 7 A schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Components of the embodiments of the present disclosure described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0030] Through research, it is found that the design steps of an integrated circuit generally include: generating a behavioral description, generating a register transfer level (RTL) circuit description, converting the behavioral description or the RTL-level description into a gate-level netlist, and generating a physical layout (integrated circuit) based on the gate-level netlist. At the same time, during the process of designing an integrated circuit, in order to ensure the performance of the generated integrated circuit, it is usually necessary to verify the integrated circuit after generating the RTL description. However, with the rapid development of the integrated circuit industry, which has brought about rapid iteration of integrated circuit technologies and also increasing verification acceleration requirements for integrated circuit design, the current verification method using the Universal Verification Methodology (UVM) can no longer meet the increasing verification needs; to solve this problem, a dedicated simulation accelerator (emulator) is currently used to achieve accelerated verification of the integrated circuit.

[0031] As a type of integrated circuit, an image signal processing (ISP) chip, during its verification, each test case of the ISP usually includes multiple frames of images. In many complex scenarios, a large number of configuration parameters need to be configured for each frame of image. For example, each frame of image may require different register configurations, and the content and quantity of each register configuration may vary; for example, during the process of using the ISP to process multiple frames of video in a video stream, noise reduction and sharpening processing need to be performed on multiple frames of images respectively; therefore, it is necessary to switch the processing mode of the ISP chip to achieve different processing of images, and during different processing processes, different register parameters need to be configured for each frame of image. And the verification of integrated circuits usually includes multiple verification links; the configuration information of the excitation data sequence will be used in each verification link; different development environments are adopted in different verification links, resulting in different file formats for the files carrying the configuration information in different verification links, which causes the configuration information to need to be transplanted between different verification links. For example, currently, before verifying an integrated circuit based on an emulator, it is necessary to manually write the relevant configuration parameters of each frame of image in a manual manner; this results in a slow speed of transplanting the configuration information, an extended verification time, and a reduced verification efficiency. And because the transplantation of configuration parameters is carried out manually, it is prone to errors, which has an adverse impact on the verification process of the ISP chip.

[0032] Based on the above research, the present disclosure provides an integrated circuit verification method, which constructs a test environment by using the description information corresponding to the integrated circuit to be tested; after obtaining the configuration file of the excitation data sequence corresponding to the integrated circuit to be tested, it can automatically read the configuration information corresponding to each frame of excitation data from the configuration file, and use the test environment and the automatically read configuration information to perform simulation processing on each frame of excitation data, thereby realizing the automatic transplantation of the configuration parameters of the excitation data, improving the transplantation efficiency of the configuration parameters, and reducing the probability of errors easily occurring during the transplantation process of the configuration parameters.

[0033] In addition, during the automatic transplantation process of the configuration information in the embodiments of the present disclosure, by pre - putting the register addresses and register values to be configured for each frame of excitation data in the excitation data sequence together and storing them as a whole in a preset address space, and parsing and extracting the number of registers to be configured for each frame of image in advance through a script, the configuration information of these registers will be passed to the micro - controller in the test environment in the form of an intermediate file, and the read indication signal of the module to be tested will be passed to the micro - controller. So that whenever a read indication signal is sent to the micro - controller, the micro - controller will enter the pre - written read execution program and execute the logic of automatically configuring the registers, realizing the automatic inter - frame configuration process in the verification process of the ISP chip.

[0034] Regarding the defects existing in the above solutions, they are all the results obtained by the inventors through practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by the present disclosure for the above problems in the following text should be the contributions made by the inventors to the present disclosure during the process of the present disclosure.

[0035] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0036] To facilitate the understanding of this embodiment, first, a detailed introduction is given to an integrated circuit verification method disclosed in the embodiments of the present disclosure. The execution subject of the integrated circuit verification method provided by the embodiments of the present disclosure is generally an emulator. The emulator can provide the hardware environment and software environment required by the chip in the simulation verification link. In some possible implementation manners, the integrated circuit verification method can be implemented by a processor in the emulator calling computer-readable instructions stored in a memory.

[0037] See Figure 1 As shown, it is a flowchart of the integrated circuit verification method provided by the embodiments of the present disclosure. The method includes steps S101 to S103, where:

[0038] S101: Obtain a configuration file of an excitation data sequence corresponding to the integrated circuit to be tested, and construct a test environment based on the description information corresponding to the integrated circuit to be tested; wherein, the excitation data sequence includes multiple frames of excitation data; the configuration file includes configuration information corresponding to each frame of the excitation data respectively;

[0039] S102: Read the configuration information corresponding to each frame of excitation data from the configuration file, and perform simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence;

[0040] S103: Obtain a verification result of the integrated circuit to be tested based on the simulation processing result and the real result corresponding to the excitation data sequence.

[0041] Steps S101 to S103 of the embodiments of the present disclosure can be executed based on an automated script.

[0042] In the example of the present disclosure, after obtaining the configuration file of the excitation data sequence corresponding to the integrated circuit to be tested, and constructing a test environment based on the description information corresponding to the integrated circuit to be tested, the configuration information corresponding to each frame of excitation data is read from the configuration file, and based on the test environment and the read configuration information, each frame of excitation data is simulated to obtain the simulation result corresponding to the excitation data sequence, and based on the simulation result and the true result corresponding to the excitation data sequence, the verification result of the integrated circuit to be tested is obtained. In this process, the excitation data sequence includes multiple frames of excitation data, and the configuration file includes the configuration information corresponding to the multiple frames of excitation data respectively. These configuration information can be automatically read by the simulation accelerator, realizing the automatic transplantation of the configuration parameters of the excitation data, improving the transplantation efficiency of the configuration parameters, and reducing the probability of error in the process of transplanting the configuration parameters.

[0043] It should be noted that the integrated circuit verification method provided by the present disclosure aims to provide an automated verification method, so the possible usage scenarios may include, but are not limited to: hardware simulation, functional verification, formal verification, etc. And the integrated circuits for verification may include, but are not limited to: Image Signal Processor (ISP), central processing unit (CPU), Application Specific Integrated Circuit (ASIC), Digital Signal Processing (DSP), etc.

[0044] Taking the integrated circuit to be tested as an ISP chip as an example, the integrated circuit verification method provided by the embodiments of the present disclosure will be described below. Among them, ISP is generally used to process the output data of the image sensor, such as performing functions such as automatic exposure control, automatic gain control, automatic white balance, and color correction.

[0045] Regarding the above S101: The excitation data sequence refers to the input data composed of multiple frames of excitation data for input to the integrated circuit to be tested; taking the integrated circuit to be tested as an ISP chip as an example, this excitation data sequence is, for example, a video, and multiple frames of excitation data are, for example, multiple frames of images in the video.

[0046] The configuration file is a relevant file required for simulating the integrated circuit to be tested using the RTL code of the integrated circuit to be tested. In the configuration file, the configuration information required in the verification process of the integrated circuit to be tested is recorded.

[0047] Specifically, in many complex scenarios, different frame images in a video need to be configured with different configuration information. Taking register configuration information as an example, the content and quantity of register configurations corresponding to different images may vary. Among them, the register configuration parameters corresponding to each frame of image are different because the ISP chip may process each frame of image differently (as introduced above for ISP). Moreover, even for the same processing method, such as Bad Pixel Correction (BPC), since the content of each frame of image is different, that is, the existing bad pixels are different, it will also cause the register configuration information corresponding to each frame of image to change.

[0048] In an optional implementation manner, the embodiments of the present disclosure provide a specific method for obtaining a configuration file of an excitation data sequence corresponding to an integrated circuit to be tested, including:

[0049] Obtain the original configuration file of the excitation data sequence corresponding to the integrated circuit to be tested;

[0050] Perform format conversion on the original configuration file to obtain the configuration file of the excitation data sequence that can be recognized by the simulation accelerator.

[0051] In specific implementation, the excitation data sequence is the data sequence used to test the chip. Only by ensuring the maximum degree of freedom of the excitation source can a richer combination be provided on the input side for verifying related functions. In the embodiments of the present disclosure, the excitation data sequence includes multiple frames of excitation data, that is, multiple frames of images for testing. The register configuration parameters corresponding to these images can be obtained from the original configuration file.

[0052] Since using the simulation accelerator to verify the integrated circuit is a link in the process of verifying the integrated circuit, in different environments or systems, the recognizable file formats may be different. Therefore, the original configuration file needs to be format-converted to become the configuration file of the excitation data sequence that can be recognized by the simulation accelerator in the embodiments of the present disclosure. In different integrated circuit verification programs, some configuration files may need to be format-converted multiple times, and the formats to be converted are also different. There are various methods for performing file format conversion, which are not limited in the present disclosure.

[0053] In an optional implementation manner, the configuration file includes: a register configuration file; the register configuration file carries the register configuration information corresponding to each frame of excitation data in the excitation data sequence;

[0054] The performing format conversion on the original configuration file to obtain the configuration file of the excitation data sequence that can be recognized by the simulation accelerator includes:

[0055] Read the register configuration information corresponding to each frame of excitation data from the original configuration file in the order of each frame of excitation data in the excitation data sequence;

[0056] Write the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence according to a preset form, to obtain the configuration file.

[0057] In a specific implementation, the register configuration file can be stored in a preset address space in advance, and then based on the order of each frame of excitation data in the excitation data sequence through a script file, extract the register configuration information corresponding to each frame of excitation data, and write the extracted register configuration information into the target file in a preset form through an instruction dedicated to the simulation accelerator, to obtain a configuration file recognizable by the simulation accelerator used in the implementation of the present disclosure.

[0058] Exemplarily, the writing form of the register configuration information can be in the form of register address plus register value. For example, in terms of form, the order is the address of register 1, the value of register 1, the address of register 2, the value of register 2... the address of register n, the value of register n.

[0059] In an alternative implementation manner, the register configuration information corresponding to each frame of the excitation data includes: the register address and register value of at least one register corresponding to each frame of the excitation data;

[0060] The step of writing the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence according to a preset form to obtain the configuration file includes:

[0061] For each frame of excitation data, generate a register information with a preset data length for the register address and register value of each register corresponding to this frame of excitation data; based on the register information corresponding to at least one register respectively corresponding to this frame of excitation data, generate target register information corresponding to this frame of excitation data;

[0062] Write the target register information corresponding to multiple frames of excitation data into the target file in sequence to obtain the configuration file.

[0063] In a specific implementation, the number of registers corresponding to each frame of excitation data can be multiple, which has been described above. The size of a single register address and register value usually does not exceed 32 bits. Therefore, we use two 32-bit data concatenated together to represent the register information of a register, which is 64 bits in total. When the number of registers corresponding to a certain frame of excitation data is multiple, the register information corresponding to that frame of excitation data will be multiple sets of 64-bit data. The multiple sets of 64-bit data will constitute the target register information corresponding to that frame of excitation data. Writing the target register information corresponding to each frame of excitation data into the target file in sequence can obtain a configuration file including the configuration information corresponding to multiple frames of the excitation data respectively.

[0064] Exemplarily, for the first frame of excitation data A, the number of registers is 1, and the register name is register 1. Based on the different types and functions of the registers, the sizes of the register addresses and register values of the registers may also be different. Here, taking the register address data size of 32 bits and the register value data size of 32 bits as an example, the 32-bit register address data and the 32-bit register value data of register 1 corresponding to the first frame of excitation data A will be used as the target register information corresponding to the first frame of excitation data A. Since the target register information corresponding to the first frame of excitation data A only includes the configuration information of 1 register, the data size is 64 bits. When writing the target register information corresponding to multiple frames of excitation data into the target file in sequence later, the target register information corresponding to the first frame of excitation data A will occupy a certain 64 bits in the storage space of the target file.

[0065] Exemplarily, if the target register information corresponding to the first frame of excitation data A includes the configuration information of 3 registers, then the data size will become 192 bits. When writing the target register information corresponding to multiple frames of excitation data into the target file in sequence later, the target register information corresponding to the first frame of excitation data A will occupy a certain 192 bits in the storage space of the target file.

[0066] The description information corresponding to the integrated circuit to be tested, for example, includes: the function code of the integrated circuit to be tested, and this function code, for example, includes: Hardware Description Language (HDL) code, or Register Transfer Level (RTL) code.

[0067] Among them, the RTL code of the integrated circuit to be tested is generated using the behavioral description of the integrated circuit. The behavioral level is the description angle that best conforms to the human logical thinking mode and can be described using programming languages such as C / C++; the RTL-level description of the circuit refers to the description method of the data flow of the circuit at the register level. Among them, the goal of the behavioral description is to achieve specific functions without synthesizable restrictions, and the goal of the RTL-level description is to be synthesizable, that is, it can be converted to a gate-level circuit. When designing an integrated circuit, designers first write the code corresponding to the behavioral description using a high-level programming language such as C / C++ according to the specific requirements of the integrated circuit, and then convert the code of the behavioral description into RTL code. The conversion from the behavioral level to the RTL level can be manually translated by integrated circuit designers or use synthesis tools to convert the behavioral level to RTL, such as the high-level synthesis tool Catapult C Synthesis of Menter Graphics Corporation.

[0068] The present disclosure also provides a specific method for constructing a test environment based on the description information corresponding to the integrated circuit to be tested, including:

[0069] Based on the description information corresponding to the integrated circuit to be tested, instantiate the integrated circuit to be tested to obtain an excitation generation instance and a to-be-tested instance corresponding to the integrated circuit to be tested;

[0070] Generate the test environment based on the excitation generation instance and the to-be-tested instance.

[0071] Among them, the description information level corresponding to the integrated circuit may include, but is not limited to: register transfer level (RTL) description information, that is, a register transfer level circuit described using a hardware description language (HDL). At this level, it is necessary to describe each level of registers (registers in sequential logic) and how the signals between the registers are converted (combinational logic in sequential logic).

[0072] The test environment is the general term for the entire verification system, including each component in the verification structure, the connection relationship between components, the configuration and control of the test environment; in a more systematic sense, it also includes the compilation and simulation process, result analysis report, and coverage check, etc. Narrowly speaking, it mainly focuses on the structure and components of the verification platform, which generate various inputs required for the design and check the design functions based on this.

[0073] In a specific implementation, the test environment can be constructed using a variety of languages, such as VHDL, Verilog, Open Vera, e, System C, C / C++, SystemVerilog, etc. The present disclosure does not limit the language used to construct the verification environment. No matter which language is used to construct the verification environment, if the integrated circuit verification method in the embodiment of the present disclosure is used, it can be regarded as within the scope of the present disclosure. The test environment may include multiple modules, and these modules need to be instantiated to perform their respective functions. The module instantiation is to reference another module in one module and make relevant connections to its ports. The module instantiation establishes a description hierarchy. Signal ports can be associated by position or name, and port connections must also follow some rules. Module instantiation can be understood as module calling. For a field programmable gate array (FPGA) project, it is usually composed of a top-level module and multiple functional sub-modules. In order to realize the connection between the top-level module and the sub-module, it is necessary to instantiate (or call) between modules.

[0074] In the specific implementation, Figure 2 A specific schematic diagram of a test environment structure is shown, which includes five main modules: a microcontroller 201, a module to be tested 202, a stimulus generation module 203, an output collection module 204, and a memory module 205.

[0075] In the microcontroller 201, the role of the microcontroller 201 is to control and coordinate the entire verification environment, which usually requires a program counter, an instruction register, an instruction decoder, a timing and control circuit, as well as a pulse source, an interrupt, etc. to complete; Figure 3A specific schematic diagram showing how a microcontroller firmware controls the operation of a microcontroller is presented. The operating mode of the microcontroller 201 is described by the microcontroller firmware, which is generally written in a high-level programming language (such as C language), compiled into a firmware file in binary format through software, and then converted into a text-format initialization firmware through a script. Finally, it is stored in the program memory of the microcontroller 201 through a back-door access method. Among them, the register model will be instantiated in the test environment, and the register model can be used to operate the registers more conveniently. The two ways to access registers are front-door access and back-door access. Front-door access refers to the read and write operations performed on the register model, which realizes the physical timing access on the bus through the bus and is a real physical operation; back-door access refers to directly applying the register operations to the register variables within the device under test (DUT), without accessing through the physical bus. In actual execution, back-door access is more convenient and faster than front-door access. In order to speed up the entire verification process, the back-door access method is adopted here for register access.

[0076] The device under test module 202, that is, the ISP module to be verified, in the test environment, its function is strictly consistent with the final chip at the logical behavioral level;

[0077] The stimulus generation module 203 is also called a driver, BFM (Bus Function Model), behavioral model, or generator in some cases. The main responsibility of the stimulus generation module 203 is to simulate the interface protocol of the design adjacent to the device under test module 203 and initiate interface data transmission. In the embodiment of the present disclosure, the stimulus generation module 203 is responsible for reading out the input images initialized to the memory module 205 provided by the ISP algorithm frame by frame and sending them to the input port of the device under test in a timing manner that meets the requirements of the sensor interface;

[0078] The output collector module 204 collects the output images from the output port of the device under test module 202, stores them in the platform memory module 205, and finally compares them frame by frame with the reference results provided by the ISP algorithm to determine whether the case passes;

[0079] The memory module 205 is mainly responsible for storing input and output picture data, including the memory 2051 responsible for image input and the memory 2052 responsible for image output. Some of the underlying devices need to be generated using the corresponding development tools. Different manufacturers will provide IP for virtual memory, and some of the underlying devices can be generated using the IP for virtual memory provided by the manufacturer, such as memories, bus interfaces, bus bridges, etc.

[0080] For the above S102: The embodiments of the present disclosure provide a specific method for simulating each frame of excitation data based on the test environment and the read configuration information, including:

[0081] Configure the test environment based on the configuration information;

[0082] Use the configured test environment to simulate each frame of excitation data.

[0083] In a specific implementation, according to the different functions and performances of the design under test, the number of registers that may be used may also be different. The configuration file contains register name information, and based on the register name information, the number of register models to be instantiated in the test environment can be determined.

[0084] Exemplarily, when the register name information in the configuration file includes register 1 and register 2, during the model instantiation process, the register models to be instantiated are register 1 and register 2.

[0085] In an optional implementation manner, after obtaining the configuration file of the excitation data sequence corresponding to the integrated circuit to be tested, it may further include:

[0086] Store the configuration file in a preset storage space;

[0087] The reading of the configuration information corresponding to each frame of excitation data from the configuration file includes:

[0088] Read the configuration information corresponding to each frame of excitation data from the configuration file stored in the preset storage space.

[0089] In a specific implementation, for the convenience of subsequent use, the obtained configuration file can be stored in a certain preset storage space for waiting to be read. In response to a certain module in the test environment needing to read the corresponding configuration file, for example: a microcontroller, after the microcontroller receives the read instruction, it can directly read the information required during the integrated circuit verification process from the preset storage space, for example: the configuration information corresponding to the excitation data.

[0090] In an optional implementation manner, the reading of the configuration information corresponding to each frame of excitation data from the configuration file includes:

[0091] According to the positions of each frame of the excitation data in the excitation data sequence, each frame of the excitation data is sequentially used as the current excitation data, and the configuration information corresponding to the current excitation data is read from the configuration file.

[0092] In specific implementation, verifying a certain chip requires inputting various excitation data for verification to ensure the freedom of the current excitation data. In the verification of an ISP chip, the excitation data can be multiple frames of images. When performing simulation verification on the chip, each frame of image in the excitation data sequence can be input in sequence, that is, each frame of image is regarded as the current excitation data in turn. At the same time, as described above, each frame of image serving as excitation data has its corresponding configuration information, and the reading of these configuration information can be realized through a script file.

[0093] When reading the configuration information corresponding to the current excitation data from the configuration file, for example, the following method can be adopted:

[0094] For the case where the current excitation data is the first-frame excitation data, in response to receiving a simulation start instruction, the test environment generates a read indication signal corresponding to the current excitation data; and for the case where the current excitation data is non-first-frame excitation data, in response to completing the simulation processing of the previous excitation data corresponding to the non-first-frame excitation data, the test environment generates a read indication signal corresponding to the current excitation data;

[0095] In an optional implementation manner, reading the configuration information corresponding to the current excitation data from the configuration file based on the number of registers respectively corresponding to each frame of excitation data includes:

[0096] Based on the number of registers corresponding to the current excitation data, the original address offset data corresponding to the current excitation data, and the preset data length of the register information, read the target register information of each register corresponding to the current excitation data from the configuration file.

[0097] Among them, the configuration information respectively corresponding to each frame of excitation data includes: the number of registers respectively corresponding to each frame of excitation data;

[0098] Before reading the configuration information corresponding to each frame of excitation data from the configuration file, it further includes:

[0099] Obtain the number of registers respectively corresponding to each frame of excitation data from the configuration file;

[0100] In response to receiving the read indication signal generated by the test environment, reading the configuration information corresponding to the current excitation data from the configuration file includes:

[0101] Based on the number of registers respectively corresponding to each frame of excitation data, read the configuration information corresponding to the current excitation data from the configuration file.

[0102] In a specific implementation, the execution method described below can be automatically executed by a script file during chip verification. The excitation data may consist of multiple frames of images, and each frame in the multiple frames of images will be input as excitation data. For example, Figure 4 As shown, if the current excitation data to be input is the first frame of the image, that is, the start link of the simulation, a simulation start instruction can be sent to the microcontroller to read the first frame of the image. Usually, the register configuration of the first frame of the multiple frames of images in the excitation data is configured in the initialization stage. The microcontroller will go to the agreed address segment to fetch a fixed number (i.e., the number of registers to be configured for the first frame of the picture) of 64-bit data, that is, the data of 32-bit register address + 32-bit register value mentioned above, and then configure the 32-bit register value in the latter 32 bits into the 32-bit register address in the former 32 bits, that is, complete the register configuration of the first frame.

[0103] When the processing of the first frame of the image is completed and the registers of the second frame of the image need to be configured, the module under test will issue a read indication signal. This read indication signal is, for example, an interrupt signal sent by the module under test to the microcontroller; this read indication signal is passed to the microcontroller through the register module in the test environment. When the microcontroller receives this read indication signal and recognizes the meaning of this read, it will execute the logic of this read indication signal, that is, automatic inter-frame configuration. The microcontroller will judge which frame the current frame is by counting and calculate based on the information of the number of registers to be configured for each frame previously mastered, fetch data of a specified length from the specified address segment, and then configure the fetched 64-bit data according to the above method (configure the 32-bit register value into the corresponding 32-bit register address), and complete the register configuration of the current frame, that is, complete the inter-frame configuration.

[0104] Exemplarily, if the number of registers corresponding to the first frame image is 2 and the number of registers corresponding to the second frame image is 3, then when configuring the registers of the third frame image, the module under test will issue a read indication signal, which is transmitted to the microcontroller through the register module in the test environment. When the microcontroller receives this read indication signal and recognizes the meaning of this read, it will execute the logic of this read indication signal, that is, automatic inter-frame configuration. The microcontroller will judge that the current frame is the third frame by counting, and calculate through the register configuration information corresponding to the first frame image and the second frame image that in the preset storage space storing the configuration information, the configuration information of the 2 registers corresponding to the first frame image occupies 128 bits of the preset storage space, and the configuration information of the 3 registers corresponding to the second frame image occupies 192 bits of the preset storage space, that is, the first 320 bits of data are the register configuration data that has been read. If the number of registers corresponding to the third frame image is 1, the microcontroller only needs to start from the address after the first 320 bits of data in the storage space according to the storage order, read 64 bits of data, and configure the registers of the third frame image based on this 64 bits of data. When configuring, the first 32 bits of the 64 bits of data represent the address information of the registers corresponding to the third frame image. For example, it can be the address information of register 23. Then only need to configure the 32 bits of data representing the register value in the 64 bits of data into the address information corresponding to register 23 to complete the register configuration corresponding to the third frame image.

[0105] For the above S103, an embodiment of the present disclosure provides a specific method for obtaining the verification result of the integrated circuit to be tested based on the simulation processing result and the real result corresponding to the excitation data sequence, including:

[0106] After storing the simulation processing result in the first target result file, perform format conversion on the first target result file to obtain a target result file in the target format;

[0107] Compare the real result corresponding to the excitation data sequence with the target result file to obtain the verification result of the integrated circuit to be tested.

[0108] In a specific implementation, after the operation ends, the simulation accelerator will read the output result data from the specified address space and download it to a file through a special command of the simulation accelerator. Then it is necessary to convert this file into the data format of the final result file in the excitation data sequence to facilitate comparison. Finally, the two files are compared and the comparison result is printed to a certain file to facilitate observing whether the excitation data sequence passes. After verifying multiple excitation data sequences, the final verification result of the current verified ISP chip can be obtained according to the verification results of multiple excitation data sequences.

[0109] In the disclosed example, the interactions of the above-mentioned various modules are connected in series through a set of automated scripting languages. For example, the initialization data and instructions are input into the memory, and the results after simulating the excitation data sequence are downloaded locally and compared with the expected results.

[0110] Those skilled in the art can understand that in the above method of the specific implementation manner, the writing order of each step does not mean a strict execution order and does not constitute any limitation to the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0111] Based on the same inventive concept, an integrated circuit verification device corresponding to the integrated circuit verification method is also provided in the embodiments of the present disclosure. Since the principle of solving problems by the device in the embodiments of the present disclosure is similar to the above-mentioned integrated circuit verification method in the embodiments of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0112] Refer to Figure 5 As shown in the figure, it is a schematic diagram of an integrated circuit verification device provided by an embodiment of the present disclosure. The device includes:

[0113] An acquisition module 51, configured to acquire a configuration file of an excitation data sequence corresponding to an integrated circuit to be tested, and construct a test environment based on description information corresponding to the integrated circuit to be tested; wherein, the excitation data sequence includes multiple frames of excitation data; the configuration file includes configuration information respectively corresponding to the multiple frames of excitation data;

[0114] A simulation module 52, configured to read configuration information corresponding to each frame of excitation data from the configuration file, and perform simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence;

[0115] A verification module 53, configured to obtain a verification result of the integrated circuit to be tested based on the simulation processing result and a true result corresponding to the excitation data sequence.

[0116] In an optional implementation manner, when acquiring a configuration file of an excitation data sequence corresponding to an integrated circuit to be tested, the acquisition module 51 is configured to:

[0117] Acquire an original configuration file of the excitation data sequence corresponding to the integrated circuit to be tested;

[0118] Perform format conversion on the original configuration file to obtain a configuration file of the excitation data sequence that can be recognized by the simulation accelerator.

[0119] In an alternative embodiment, the configuration file includes: a register configuration file; the register configuration file carries register configuration information respectively corresponding to each frame of excitation data in the excitation data sequence;

[0120] When the obtaining module 51 converts the format of the original configuration file to obtain the configuration file of the excitation data sequence recognizable by the simulation accelerator, it is used for:

[0121] Read the register configuration information respectively corresponding to each frame of excitation data from the original configuration file in the order of each frame of excitation data in the excitation data sequence;

[0122] Write the register configuration information respectively corresponding to each frame of excitation data into a target file in a preset format in sequence according to a preset form to obtain the configuration file.

[0123] In an alternative embodiment, the register configuration information corresponding to each frame of the excitation data includes: the register address and register value of at least one register corresponding to each frame of the excitation data;

[0124] When the obtaining module 51 writes the register configuration information respectively corresponding to each frame of excitation data into a target file in a preset format in sequence according to a preset form to obtain the configuration file, it is used for:

[0125] For each frame of excitation data, generate a register information of a preset data length for the register address and register value of each register corresponding to this frame of excitation data; based on the register information respectively corresponding to at least one register corresponding to this frame of excitation data, generate the target register information corresponding to this frame of excitation data;

[0126] Write the target register information respectively corresponding to multiple frames of excitation data into the target file in sequence to obtain the configuration file.

[0127] In an alternative embodiment, when the obtaining module 51 constructs a test environment based on the description information corresponding to the integrated circuit to be tested, it is used for:

[0128] Based on the description information corresponding to the integrated circuit to be tested, instantiate the integrated circuit to be tested to obtain an excitation generation instance and a to-be-tested instance corresponding to the integrated circuit to be tested;

[0129] Generate the test environment based on the excitation generation instance and the to-be-tested instance.

[0130] In an alternative embodiment, when the simulation module 52 performs simulation processing on each frame of excitation data based on the test environment and the read configuration information, it is used for:

[0131] Configure the test environment based on the configuration information;

[0132] Use the configured test environment to simulate each frame of excitation data.

[0133] In an optional implementation manner, after obtaining the configuration file of the excitation data sequence corresponding to the integrated circuit to be tested, the obtaining module 51 is further configured to:

[0134] Store the configuration file in a preset storage space;

[0135] When reading the configuration information corresponding to each frame of excitation data from the configuration file, the simulation module 52 is configured to:

[0136] Read the configuration information corresponding to each frame of excitation data from the configuration file stored in the preset storage space.

[0137] In an optional implementation manner, when reading the configuration information corresponding to each frame of excitation data from the configuration file, the simulation module 52 is configured to:

[0138] According to the positions of each frame of excitation data in the excitation data sequence, sequentially use each frame of excitation data as the current excitation data, and read the configuration information corresponding to the current excitation data from the configuration file.

[0139] In an optional implementation manner, when reading the configuration information corresponding to the current excitation data from the configuration file, the simulation module 52 is configured to:

[0140] For the case where the current excitation data is the first frame of excitation data, in response to receiving a simulation start instruction, the test environment generates a read indication signal corresponding to the current excitation data; and for the case where the current excitation data is non-first-frame excitation data, in response to completing the simulation processing of the previous excitation data corresponding to the non-first-frame excitation data, the test environment generates a read indication signal corresponding to the current excitation data;

[0141] In response to receiving the read indication signal generated by the test environment, read the configuration information corresponding to the current excitation data from the configuration file.

[0142] In an optional implementation manner, the configuration information corresponding to each frame of excitation data includes: the number of registers corresponding to each frame of excitation data;

[0143] Before reading the configuration information corresponding to each frame of excitation data from the configuration file, the simulation module 52 is further configured to:

[0144] Obtain the number of registers corresponding to each frame of excitation data from the configuration file;

[0145] In response to receiving the read indication signal generated by the test environment, read the configuration information corresponding to the current excitation data from the configuration file, including:

[0146] Based on the number of registers corresponding to each frame of excitation data, read the configuration information corresponding to the current excitation data from the configuration file.

[0147] In an alternative embodiment, when the simulation module 52 reads the configuration information corresponding to the current excitation data from the configuration file based on the number of registers corresponding to each frame of excitation data, it is used for:

[0148] Based on the number of registers corresponding to the current excitation data, the original address offset data corresponding to the current excitation data, and the preset data length of the register information, read the target register information of each register corresponding to the current excitation data from the configuration file.

[0149] In an alternative embodiment, when the verification module 53 obtains the verification result of the integrated circuit under test based on the simulation processing result and the true result corresponding to the excitation data sequence, it is used for:

[0150] After storing the simulation processing result in the first target result file, perform format conversion on the first target result file to obtain a target result file in the target format;

[0151] Compare the true result corresponding to the excitation data sequence with the target result file to obtain the verification result of the integrated circuit under test.

[0152] For the description of the processing flow of each module in the device and the interaction flow between modules, reference can be made to the relevant descriptions in the above method embodiments, which will not be elaborated here.

[0153] Refer to Figure 6 As shown, the embodiments of the present disclosure further provide a simulation system for an integrated circuit under test, including: an excitation generation module 203, a module under test 202, and a microcontroller 201;

[0154] The excitation generation module 203 is configured to sequentially read out multiple frames of excitation data in the excitation data sequence stored in a preset first storage space, and send each frame of excitation data to the module under test 202 in a preset time sequence;

[0155] The microcontroller 201 is configured to read configuration information corresponding to each frame of excitation data from a configuration file corresponding to the excitation data sequence, and send the configuration information corresponding to each frame of excitation data to the module under test 202; wherein, the configuration file is pre-stored in the microcontroller 201.

[0156] The module under test 202 is configured to, in response to receiving each frame of excitation data and the configuration information corresponding to each frame of excitation data, perform simulation processing on each frame of excitation data based on the configuration information corresponding to each frame of excitation data to obtain a simulation processing result corresponding to each frame of excitation data.

[0157] Wherein, the first storage space includes, for example: Figure 6 The memory 2051 in the memory module 205 shown in.

[0158] In an alternative embodiment, it further includes: a preprocessing module 206;

[0159] The preprocessing module 206 is configured to obtain the configuration file and store the configuration file in the microcontroller 201;

[0160] and construct a test environment based on the description information corresponding to the integrated circuit to be tested, wherein the test environment includes the module under test 202.

[0161] In an alternative embodiment, when obtaining the configuration file, the preprocessing module 206 is configured to:

[0162] Obtain the original configuration file of the excitation data sequence corresponding to the integrated circuit to be tested;

[0163] Perform format conversion on the original configuration file to obtain the configuration file of the excitation data sequence that can be recognized by the simulation accelerator.

[0164] In an alternative embodiment, the configuration file includes: a register configuration file; the register configuration file carries register configuration information corresponding to each frame of excitation data in the excitation data sequence respectively;

[0165] When the preprocessing module 206 performs format conversion on the original configuration file to obtain the configuration file of the excitation data sequence that can be recognized by the simulation accelerator, it is configured to:

[0166] Read the register configuration information corresponding to each frame of excitation data from the original configuration file in the order of each frame of excitation data in the excitation data sequence;

[0167] Write the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence to obtain the configuration file.

[0168] In an optional implementation, the register configuration information corresponding to each frame of the excitation data includes: the register address and register value of at least one register corresponding to each frame of the excitation data;

[0169] When the preprocessing module 206 writes the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence to obtain the configuration file, it is used for:

[0170] For each frame of excitation data, generate a register information with a preset data length for the register address and register value of each register corresponding to this frame of excitation data; based on the register information corresponding to at least one register respectively corresponding to this frame of excitation data, generate the target register information corresponding to this frame of excitation data;

[0171] Write the target register information corresponding to multiple frames of excitation data into the target file in sequence to obtain the configuration file.

[0172] In an optional implementation, when the preprocessing module 206 stores the configuration file into the microcontroller 201, it is used for: storing the configuration file into the program memory of the microcontroller 201 through the way of backdoor access.

[0173] In an optional implementation, when the microcontroller 201 reads the configuration information corresponding to each frame of excitation data from a pre-obtained configuration file, it is used for: according to the position of each frame of the excitation data in the excitation data sequence, sequentially use each frame of the excitation data as the current excitation data, and read the configuration information corresponding to the current excitation data from the configuration file.

[0174] In an optional implementation, the module under test 202 is further used for sending a read indication signal for indicating to read the configuration information corresponding to the current excitation data to the microcontroller 201;

[0175] When the microcontroller 201 reads the configuration information corresponding to each frame of excitation data from a pre-obtained configuration file, it is used for responding to the indication signal sent by the module under test 202 and reading the configuration information corresponding to the current excitation data.

[0176] In an optional implementation,

[0177] When the module under test 202 sends a read indication signal for instructing to read the configuration information corresponding to the current excitation data to the microcontroller 201, it is used for:

[0178] For the case where the current excitation data is the first-frame excitation data, in response to receiving the simulation start instruction, generate a read indication signal corresponding to the first-frame excitation data, and send the read indication signal corresponding to the first-frame excitation data to the microcontroller 201;

[0179] For the case where the current excitation data is non-first-frame excitation data, in response to completing the simulation processing of the previous excitation data corresponding to the current excitation data, generate a read indication signal corresponding to the current excitation data.

[0180] In an optional implementation manner, the configuration information corresponding to each frame of excitation data includes: the number of registers corresponding to each frame of excitation data;

[0181] When the microcontroller 201 reads the configuration information corresponding to each frame of excitation data from the configuration file, it is used for:

[0182] Obtain the number of registers corresponding to each frame of excitation data from the configuration file;

[0183] In response to receiving the read indication signal for the configuration information corresponding to the target excitation data sent by the module under test 202, based on the number of registers corresponding to the target excitation data, the original address offset data corresponding to the target excitation data, and the preset data length of the register information, read the target register information of each register corresponding to the target excitation data from the configuration file.

[0184] In an optional implementation manner, it further includes: an output collection module 204;

[0185] The module under test 202 is further used to transmit the simulation processing result corresponding to the excitation data to the output collection module 204;

[0186] The output collection module 204 is used to store the simulation processing results corresponding to each frame of excitation data transmitted by the module under test 202 in a preset second storage space.

[0187] In an optional implementation manner, it further includes: a result processing module, which is used to read the simulation processing results corresponding to each frame of the excitation data from the second storage space, and obtain the verification result of the integrated circuit under test based on the simulation processing results and the real results corresponding to the excitation data sequence.

[0188] Here, the second storage space is as Figure 6In [the figure], the memory 2051 in the memory module 205.

[0189] Embodiments of the present disclosure also provide an electronic device, such as Figure 7 As shown, it is a schematic structural diagram of the electronic device provided by the embodiments of the present disclosure, including:

[0190] A processor 71 and a memory 72; the memory 72 stores machine-readable instructions executable by the processor 71, and the processor 71 is used to execute the machine-readable instructions stored in the memory 72. When the machine-readable instructions are executed by the processor 71, the processor 71 performs the following steps:

[0191] Obtain a configuration file of an excitation data sequence corresponding to the integrated circuit to be tested, and construct a test environment based on the description information corresponding to the integrated circuit to be tested; wherein, the excitation data sequence includes multiple frames of excitation data; the configuration file includes configuration information corresponding to each frame of the excitation data respectively;

[0192] Read the configuration information corresponding to each frame of excitation data from the configuration file, and perform simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence;

[0193] Based on the simulation processing result and the real result corresponding to the excitation data sequence, obtain a verification result of the integrated circuit to be tested.

[0194] The above-mentioned memory 72 includes an internal memory 721 and an external memory 722; the internal memory 721 here is also called the main memory, which is used to temporarily store the operation data in the processor 71 and the data exchanged with the external memory 722 such as a hard disk, and the processor 71 exchanges data with the external memory 722 through the internal memory 721.

[0195] Alternatively, the electronic device includes, such as Figure 6 The simulation system as described above.

[0196] The specific execution process of the above instructions can refer to the steps of the integrated circuit verification method described in the embodiments of the present disclosure, and will not be elaborated here.

[0197] Embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the integrated circuit verification method described in the above method embodiments. Among them, the storage medium can be a volatile or non-volatile computer-readable storage medium.

[0198] The embodiments of the present disclosure also provide a computer program product. The computer program product carries program codes, and the instructions included in the program codes can be used to execute the steps of the integrated circuit verification method described in the foregoing method embodiments. For details, reference can be made to the foregoing method embodiments and will not be elaborated herein.

[0199] Among them, the above computer program product can be specifically implemented in the form of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0200] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein. In several embodiments provided by the present disclosure, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0201] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0202] In addition, in each embodiment of the present disclosure, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0203] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing an electronic device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0204] Finally, it should be noted that the above-described embodiments are only specific implementation manners of the present disclosure, used to illustrate the technical solutions of the present disclosure, rather than limiting them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present disclosure can still modify the technical solutions recorded in the foregoing embodiments or easily conceive of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes, or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A verification method for an integrated circuit, characterized in that, comprising: obtaining a configuration file of an excitation data sequence corresponding to the integrated circuit to be tested, and constructing a test environment based on description information corresponding to the integrated circuit to be tested; wherein, the excitation data sequence includes multiple frames of excitation data; the configuration file includes configuration information corresponding to each of the multiple frames of excitation data; reading, from the configuration file, the configuration information corresponding to each frame of excitation data, and performing simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence; obtaining a verification result of the integrated circuit to be tested based on the simulation processing result and a real result corresponding to the excitation data sequence; wherein, obtaining a configuration file of an excitation data sequence corresponding to the integrated circuit to be tested includes: obtaining an original configuration file of the excitation data sequence corresponding to the integrated circuit to be tested; reading, in the order of each frame of excitation data in the excitation data sequence, the register configuration information corresponding to each frame of excitation data from the original configuration file; writing the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence according to a preset form to obtain the configuration file; the configuration file includes: a register configuration file; the register configuration file carries the register configuration information corresponding to each frame of excitation data in the excitation data sequence.

2. The method according to claim 1, characterized in that, the register configuration information corresponding to each frame of the excitation data includes: the register address and register value of at least one register corresponding to each frame of the excitation data; the writing the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence according to a preset form to obtain the configuration file includes: for each frame of excitation data, generating a register information with a preset data length for the register address and register value of each register corresponding to this frame of excitation data; generating target register information corresponding to this frame of excitation data based on the register information corresponding to at least one register respectively corresponding to this frame of excitation data; writing the target register information corresponding to multiple frames of excitation data into the target file in sequence to obtain the configuration file.

3. The method according to claim 1 or 2, characterized in that, the reading, from the configuration file, the configuration information corresponding to each frame of excitation data includes: in the position of each frame of excitation data in the excitation data sequence, sequentially taking each frame of excitation data as the current excitation data, and reading the configuration information corresponding to the current excitation data from the configuration file.

4. The method according to claim 3, characterized in that, the reading, from the configuration file, the configuration information corresponding to the current excitation data includes: For the case where the current excitation data is the first-frame excitation data, in response to receiving a simulation start instruction, the test environment generates a read indication signal corresponding to the current excitation data; and for the case where the current excitation data is non-first-frame excitation data, in response to completing the simulation processing of the previous excitation data corresponding to the non-first-frame excitation data, the test environment generates a read indication signal corresponding to the current excitation data; In response to receiving the read indication signal generated by the test environment, read the configuration information corresponding to the current excitation data from the configuration file.

5. The method according to claim 4, wherein, the configuration information corresponding to each frame of excitation data includes: the number of registers corresponding to each frame of excitation data; before reading the configuration information corresponding to each frame of excitation data from the configuration file, further includes: obtaining the number of registers corresponding to each frame of excitation data from the configuration file; In response to receiving the read indication signal generated by the test environment, reading the configuration information corresponding to the current excitation data from the configuration file includes: Based on the number of registers corresponding to the current excitation data, the original address offset data corresponding to the current excitation data, and the preset data length of the register information, read the target register information of each register corresponding to the current excitation data from the configuration file.

6. An integrated circuit verification device, wherein, comprises: an acquisition module, configured to acquire a configuration file of an excitation data sequence corresponding to an integrated circuit to be tested, and construct a test environment based on description information corresponding to the integrated circuit to be tested; wherein, the excitation data sequence includes multiple frames of excitation data; the configuration file includes configuration information corresponding to multiple frames of the excitation data respectively; a simulation module, configured to read the configuration information corresponding to each frame of excitation data from the configuration file, and perform simulation processing on each frame of excitation data based on the test environment and the read configuration information to obtain a simulation processing result corresponding to the excitation data sequence; a verification module, configured to obtain a verification result of the integrated circuit to be tested based on the simulation processing result and a true result corresponding to the excitation data sequence; when the acquisition module is configured to acquire a configuration file of an excitation data sequence corresponding to an integrated circuit to be tested, it is configured to: acquire an original configuration file of the excitation data sequence corresponding to the integrated circuit to be tested; read the register configuration information corresponding to each frame of excitation data from the original configuration file in the order of each frame of excitation data in the excitation data sequence; write the register configuration information corresponding to each frame of excitation data into a target file in a preset format in sequence to obtain the configuration file; the configuration file includes: a register configuration file; the register configuration file carries the register configuration information corresponding to each frame of excitation data in the excitation data sequence.

7. A simulation system for an integrated circuit to be tested, wherein, comprises: an excitation generation module, a module to be tested, and a microcontroller; The excitation generation module is configured to sequentially read out multiple frames of excitation data in the excitation data sequence stored in a preset first storage space, and send each frame of excitation data to the module under test in a preset time sequence; The microcontroller is configured to read configuration information corresponding to each frame of excitation data from the configuration file corresponding to the excitation data sequence, and send the configuration information corresponding to each frame of excitation data to the module under test; wherein, the configuration file is pre-stored in the microcontroller; The module under test is configured to, in response to receiving each frame of excitation data and the configuration information corresponding to each frame of excitation data, perform simulation processing on each frame of excitation data based on the configuration information corresponding to each frame of excitation data to obtain a simulation processing result corresponding to each frame of excitation data; The simulation system further includes a preprocessing module; the preprocessing module is configured to obtain the configuration file and store the configuration file in the microcontroller; When obtaining the configuration file, the preprocessing module is configured to: Obtain the original configuration file of the excitation data sequence corresponding to the integrated circuit to be tested; Read the register configuration information corresponding to each frame of excitation data from the original configuration file in the order of each frame of excitation data in the excitation data sequence; Write the register configuration information corresponding to each frame of excitation data into a target file in a preset format in a preset form in sequence to obtain the configuration file; the configuration file includes: a register configuration file; the register configuration file carries the register configuration information corresponding to each frame of excitation data in the excitation data sequence.

8. The simulation system according to claim 7, wherein, The preprocessing module is further configured to construct a test environment based on the description information corresponding to the integrated circuit to be tested, wherein the test environment includes the module under test.

9. The simulation system according to claim 7, wherein, The register configuration information corresponding to each frame of the excitation data includes: the register address and register value of at least one register corresponding to each frame of the excitation data; When writing the register configuration information corresponding to each frame of excitation data into a target file in a preset format in a preset form in sequence to obtain the configuration file, the preprocessing module is configured to: For each frame of excitation data, generate a register information with a preset data length for the register address and register value of each register corresponding to this frame of excitation data; generate target register information corresponding to this frame of excitation data based on the register information corresponding to at least one register corresponding to this frame of excitation data; Write the target register information corresponding to multiple frames of excitation data into the target file in sequence to obtain the configuration file.

10. The simulation system according to claim 9, wherein, When storing the configuration file in the microcontroller, the preprocessing module is configured to: store the configuration file in the program memory of the microcontroller through the way of backdoor access.

11. The simulation system according to any one of claims 7-10, wherein, When reading the configuration information corresponding to each frame of excitation data from a pre-obtained configuration file, the microcontroller is configured to: sequentially use each frame of the excitation data as the current excitation data according to the position of each frame of the excitation data in the excitation data sequence, and read the configuration information corresponding to the current excitation data from the configuration file.

12. The simulation system according to claim 11, wherein, the module under test is further configured to send a read indication signal to the microcontroller for indicating to read the configuration information corresponding to the current excitation data; when reading the configuration information corresponding to each frame of excitation data from a pre-obtained configuration file, the microcontroller is configured to, in response to receiving the indication signal sent by the module under test, read the configuration information corresponding to the current excitation data.

13. The simulation system according to claim 12, wherein, when sending a read indication signal to the microcontroller for indicating to read the configuration information corresponding to the current excitation data, the module under test is configured to: for the case where the current excitation data is the first frame of excitation data, in response to receiving a simulation start instruction, generate a read indication signal corresponding to the first frame of excitation data, and send the read indication signal corresponding to the first frame of excitation data to the microcontroller; for the case where the current excitation data is non-first-frame excitation data, in response to completing the simulation processing of the previous excitation data corresponding to the current excitation data, generate a read indication signal corresponding to the current excitation data.

14. The simulation system according to claim 12 or 13, wherein, the configuration information corresponding to each frame of excitation data respectively includes: the number of registers corresponding to each frame of excitation data respectively; when reading the configuration information corresponding to each frame of excitation data from the configuration file, the microcontroller is configured to: obtain the number of registers corresponding to each frame of excitation data respectively from the configuration file; in response to receiving the read indication signal for the configuration information corresponding to the target excitation data sent by the module under test, based on the number of registers corresponding to the target excitation data, the original address offset data corresponding to the target excitation data, and the preset data length of the register information, read the target register information of each register corresponding to the target excitation data from the configuration file.

15. The simulation system according to any one of claims 7-14, wherein, it further includes: an output collection module; the module under test is further configured to transmit the simulation processing result corresponding to the excitation data to the output collection module; the output collection module is configured to store the simulation processing results corresponding to each frame of excitation data transmitted by the module under test in a preset second storage space.

16. The simulation system according to claim 15, wherein, it further includes: a result processing module, configured to read the simulation processing results corresponding to each frame of the excitation data from the second storage space, and obtain the verification result of the integrated circuit under test based on the simulation processing results and the true results corresponding to the excitation data sequence.

17. An electronic device, characterized in that, comprising: a processor and a memory, the memory storing machine-readable instructions executable by the processor, the processor being configured to execute the machine-readable instructions stored in the memory, and when the machine-readable instructions are executed by the processor, the processor performs the steps of the integrated circuit verification method according to any one of claims 1 to 5; or comprising the simulation system according to any one of claims 7 to 16.

18. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium, and when the computer program is run by an electronic device, the electronic device performs the steps of the integrated circuit verification method according to any one of claims 1 to 5.

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