FPGA with built-in functional modules for forming on-chip network nodes

Abstract

The present application provides an FPGA with a built-in functional module for forming an on-chip network node, and designs the field of FPGA technology. The configurable functional module in the FPGA includes a basic resource module and a node module. The node module and the conventional basic resource module form a uniform and unified winding architecture through interconnecting resource modules. The node module can form an on-chip network node using internal resources. Through software tool layout and routing, all signal connections required by the user design can be met at the same time, including the signal connection between the input port and the output port inside the node module, and the signal connection between the node module and the basic resource module, thereby forming an on-chip network inside the FPGA. Using the FPGA with the same hardware architecture combined with different configuration code streams, layout and routing can form different on-chip networks, with high versatility and flexibility.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to an FPGA with built-in functional modules for forming on-chip network nodes. Background Art

[0002] FPGAs are widely used in mobile communications, data centers, autonomous driving, aerospace and other fields. New applications are increasingly demanding FPGA bandwidth, storage and data capabilities. Therefore, in order to optimize communication performance, more and more FPGAs are beginning to integrate on-chip networks (NOCs) internally.

[0003] When integrating on-chip networks in different FPGAs, the number of network nodes contained in the on-chip network and the connection methods between network nodes may be different. Therefore, when it is necessary to integrate on-chip networks in FPGAs, a customized method is generally adopted. This leads to an increase in workload and development time when synthesizing the full FPGA layout, and a longer FPGA design cycle. Summary of the invention

[0004] In view of the problem that the design cycle becomes longer due to the specific requirements of the FPGA integrated with the on-chip network, the inventors propose an FPGA with built-in functional modules for forming an on-chip network node. The technical solution of the present invention is as follows:

[0005] An FPGA with built-in functional modules for forming an on-chip network node, the FPGA includes a plurality of configurable functional modules and interconnection resource modules distributed around each configurable functional module;

[0006] The configurable functional modules in the FPGA include basic resource modules and node modules. Each node module contains a router, a node memory, a node controller, several input ports and several output ports. All input ports and output ports are connected to the router, the router is connected to the node memory, and the node controller controls the router.

[0007] The input ports and output ports of several node modules are connected through direct connections between the node modules and / or interconnected resource modules. The input port and / or output port of at least one node module is connected to the basic resource module through an interconnected resource module to form an on-chip network within the FPGA. Each on-chip network node in the on-chip network is formed by a node module configuration.

[0008] A further technical solution is that all node modules in the FPGA are connected to the network on chip as network on chip nodes, or there is at least one node module in the FPGA that is not connected to the network on chip as a network on chip node;

[0009] For a node module connected to the network on chip as a node of the network on chip, a node controller in the node module controls a router to realize interconnection and intercommunication between different input ports and output ports.

[0010] A further technical solution is that, for a node module that is not connected to the on-chip network as an on-chip network node, the node memory in the node module is connected to the input port and / or output port via a router to access the interconnection resource module to realize storage read and write functions.

[0011] Its further technical solution is that the node modules and basic resource modules in the FPGA are arranged to form a two-dimensional array, and the module height of each node module is equal to the module height of the BRAM module in the basic resource module, and the module width of the node module is greater than the module width of the BRAM module. The node modules that are not connected to the on-chip network as on-chip network nodes use the built-in node memory to equivalently implement the storage read and write functions of the BRAM module.

[0012] A further technical solution is that the FPGA is configured to form at least two on-chip networks with different structures according to different configuration code streams obtained, and there is at least one difference in the number, arrangement position and connection relationship between the configurable functional modules contained in the two on-chip networks with different structures.

[0013] A further technical solution is that the node modules and basic resource modules in the FPGA are arranged to form a two-dimensional array, and a plurality of node modules are stacked and arranged to form at least one column and / or at least one row in the two-dimensional array;

[0014] A node module connected in the network on chip as a network on chip node has at least one input port connected to an output port of other node modules in the same row or column via a direct connection, and / or has at least one input port connected to an output port of other node modules and / or other basic resource modules via an interconnection resource module;

[0015] A node module connected in the on-chip network as an on-chip network node has at least one output port connected to the input port of other node modules in the same row or column via a direct connection, and / or has at least one output port connected to the input port of other node modules and / or other basic resource modules via an interconnection resource module.

[0016] A further technical solution is that, for two node modules connected in the on-chip network as on-chip network nodes and connected via a direct connection:

[0017] The two node modules are located in the same row or in the same line and arranged adjacently;

[0018] Alternatively, two node modules are located in the same row or line, and a number of other node modules are spaced between the arrangement positions of the two node modules, and then other node modules between the two node modules are configured to form a direct connection.

[0019] A further technical solution is that the node modules in the FPGA are arranged at a predetermined position of the FPGA or within a predetermined range of a basic resource module of a predetermined type, and the data transmission demand of the basic resource module of the predetermined type exceeds a demand threshold.

[0020] A further technical solution is that the predetermined type of basic resource module includes at least one of a high-speed transceiver module, an HBM module and an AI module.

[0021] Its further technical solution is that the FPGA is a multi-bare chip FPGA, the FPGA includes a substrate, a silicon connection layer stacked on the substrate, and a plurality of bare chips stacked on the silicon connection layer, the bare chip has a silicon through via at least one node module, the input port and / or output port of the node module is connected to the node modules and / or basic resource modules in other bare chips through the silicon through via through the silicon connection layer wiring in the silicon connection layer; the FPGA forms an on-chip network through the configurable functional modules in the multiple bare chips.

[0022] The beneficial technical effects of the present invention are:

[0023] The present application provides an FPGA with a built-in functional module for forming an on-chip network node. The FPGA has its own node module, and the node module and the conventional basic resource module form a uniform and unified winding architecture through interconnecting resource modules. The node module can form an on-chip network node using internal resources, and through software tool layout and routing, it can simultaneously meet all signal connections required by the user's design, including the signal connection between the input port and the output port inside the node module, and the signal connection between the node module and the basic resource module, thereby forming an on-chip network inside the FPGA. Using the FPGA with the same hardware architecture combined with different configuration code streams, layout and routing can form different on-chip networks, with high versatility and flexibility.

[0024] In addition, the FPGA design is compatible with traditional array structures. Through the flexible combination of node modules and basic resource modules, an FPGA with different two-dimensional arrays inside can be formed, which facilitates the expansion and design of FPGAs of different specifications.

[0025] In addition to using internal resource configuration to form an on-chip network node, the node module inside the FPGA can also use the internal node memory to implement read and write storage functions when not used as an on-chip network node. The module has high utilization rate and strong functional compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The diagram is a schematic diagram of the arrangement of configurable functional modules within an FPGA in an embodiment.

[0027] Figure 2 The diagram is a schematic diagram of resources inside a node module in an embodiment.

[0028] Figure 3 The module structure diagram of the configurable functional modules and interconnected resource modules inside the FPGA in an embodiment.

[0029] Figure 4 The diagram is a schematic diagram of an embodiment in which node modules located in the same column are connected via direct lines.

[0030] Figure 5 It is a schematic diagram of a structure of an on-chip network across bare chips in a multi-die FPGA structure. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0032] This application provides an FPGA with built-in functional modules for forming an on-chip network node, please refer to Figure 1 The FPGA includes several configurable functional modules. The configurable functional modules in the FPGA include a basic resource module and a node module NODE. The basic resource module includes one or more of the various configurable logic resources contained in a conventional FPGA according to actual needs. The basic resource module includes CLB, PLBs, IOB, BRAM, DSP, PC, etc.

[0033] The node module NODE is a configurable functional module newly added by this application compared with the conventional FPGA. The FPGA contains multiple node modules. Please refer to Figure 2 Each node module contains a router, a node memory, a node controller, several input ports and several output ports. All input ports and output ports are connected to the router. The router is connected to the node memory, and the node controller controls the router. The structure of the router inside the node module can be the same as that of the router in the existing customized on-chip network. The router mainly includes a switch array, as well as some buffers and registers. Figure 2The internal structure of the router is not shown in detail. The input port, output port and node memory included in the node module are all connected to the switch array. The node controller can use the internal switch array to realize different conduction paths by controlling the router, including the conduction paths between different input ports and different output ports, the conduction paths between different input ports and node memories, and the conduction paths between different output ports and node memories. The node controller in the node module NODE can be implemented by a common basic resource module such as CLB.

[0034] In common FPGAs, basic resource modules are usually arranged in a two-dimensional array to form a column-based architecture. In one embodiment, the FPGA in this application also retains this common architecture, that is, the node modules and basic resource modules in the FPGA are similar. Figure 1 The arrangement shown forms a two-dimensional array. On the basis of this architecture, different types of configurable functional modules can be mixed and stacked in rows or columns. Or in another embodiment, in order to simplify the difficulty of making an FPGA that contains different configurable functional modules to form two-dimensional arrays of different sizes, the configurable functional modules are stacked and arranged along rows or columns according to the type of module, that is, the same type of configurable functional modules are stacked and arranged to form a row or a column in the two-dimensional array, and there are only configurable functional modules of this type in the row or the column. For the basic resource modules in the configurable functional modules, the arrangement structure is the same as that in the traditional FPGA, and for the node module NODE added in the present application, the same number of node modules are stacked and arranged to form at least one column and / or at least one row in the two-dimensional array. For example, in Figure 1 In the FPGA, the configurable function modules are stacked and arranged along the columns according to the module type. The CLB column only contains CLBs, the BRAM column only contains BRAMs, and similarly, the NODE column only contains node modules NODE. Thus, the required two-dimensional array can be formed by combining different configurable function modules in rows or columns, which is convenient for designing FPGAs of different specifications and types. In addition, the FPGA can also include multiple rows or columns of node modules NODE.

[0035] Different types of configurable function modules may have different sizes, so the same type of configurable function modules are stacked and arranged to form a row with equal height or a column with equal width, and different rows may have different heights or different columns may have different widths. The size of modules such as BRAM and DSP in the basic resource module is the same as that of traditional FPGA and is larger than CLB, and the size of the node module NODE newly added in this application is also larger than CLB.

[0036] The arrangement of the configurable function modules in the FPGA can be configured as needed. Considering that the node modules of the present application are mainly used as on-chip network nodes to build on-chip networks, and usually some basic resource modules with large data transmission requirements will need to use the on-chip network for data transmission to improve data transmission efficiency, so the on-chip network nodes often appear near these basic resource modules with large data transmission requirements. Therefore, in order to facilitate the construction requirements of the on-chip network, the node modules are usually arranged near these basic resource modules with large data transmission requirements. In one embodiment, the node modules in the FPGA are arranged at a predetermined position of the FPGA, and the predetermined position is common, such as the chip center of the FPGA, so that the node modules and the configurable function modules at various positions of the FPGA are relatively close. In another embodiment, the node modules in the FPGA are arranged within a predetermined range of a predetermined type of basic resource module, and the data transmission demand of the predetermined type of basic resource module exceeds the demand threshold, that is, the node modules are directly close to these basic resource modules with large data transmission demand, so that when they are used as on-chip network nodes later, they are also close to these basic resource modules so that these basic resource modules can access the on-chip network nearby. The predetermined type of basic resource module includes at least one of a high-speed transceiver module, such as a GTH module, an HBM module, and an AI module.

[0037] Each configurable function module has an interconnection resource module (INT) distributed around the configurable function module. This structure makes the entire FPGA look like a two-dimensional array formed by INT. The height of the modules in this array is consistent, and the horizontal or vertical connections between each configurable function module are connected through the interconnection resource module. Each configurable function module is designed to be aligned with the INT in height. The height of the CLB is equal to the height of the INT. The height of other configurable function modules may be greater than the height of the INT and twice the height of the INT. Figure 3 As shown, the height of CLB is the same as the height of INT, the height of BRAM is twice the height of INT, and the height of node module NODE is twice the height of INT.

[0038] The FPGA of this structure in the present application can use the built-in node module NODE to form an on-chip network according to the configuration code stream configuration. The node module is connected to the basic resource module configuration to form an on-chip network within the FPGA, and each on-chip network node in the configured on-chip network is formed by the resource configuration within a node module.

[0039] For a node module connected to the network on chip as a network on chip node, there is at least one input port connected to the output port of the node module, and there is at least one output port connected to the input port of other node modules, and there is at least one node module in the network on chip connected to the basic resource module. As described above, in one embodiment, multiple node modules are stacked and arranged in rows or columns, and there are direct connections between adjacently arranged node modules, so there are two ways to connect node modules: one is to use direct connections between node modules, and the other is to use interconnected resource modules. The connection between the node module and the basic resource module mainly uses interconnected resource modules.

[0040] Therefore, the input port and / or output port of at least one node module is connected to the basic resource module through the interconnection resource module. In addition, the input ports and output ports of several node modules are connected through the direct connection between the node modules and / or the interconnection resource module. So for any node module connected in the network on chip as a network on chip node, there is at least one input port connected to the output port of other node modules in the same row or column via a direct connection, and / or, there is at least one input port connected to the output port of other node modules and / or other basic resource modules via the interconnection resource module. And the node module has at least one output port connected to the input port of other node modules in the same row or column via a direct connection, and / or, there is at least one output port connected to the input port of other node modules and / or other basic resource modules via the interconnection resource module.

[0041] The node modules and basic resource modules in the on-chip network can be adjusted according to actual conditions. Therefore, the FPGA of the present application can be configured to form at least two on-chip networks with different structures according to the different configuration code streams obtained. There is at least one difference in the number, arrangement position and connection relationship between the configurable functional modules contained in the two on-chip networks with different structures, including the number and arrangement position of node modules, the number and arrangement position of basic resource modules, the connection relationship between node modules, and the connection relationship between node modules and basic resource modules.

[0042] In one embodiment, all node modules in the FPGA are connected to the network on chip as network on chip nodes. Alternatively, in another embodiment, there is at least one node module in the FPGA that is not connected to the network on chip as a network on chip node, that is, all or part of the node modules in the FPGA can be used to configure and implement the network on chip.

[0043] For the node modules connected to the on-chip network as on-chip network nodes, the node controller in the node module controls the router to realize the interconnection between different input ports and output ports, thereby conducting the required connection paths between the on-chip network nodes. For each on-chip network node, the data packet obtained from an input port can be temporarily stored in the node memory first, and then transmitted to the next on-chip network node through the router through the corresponding output port.

[0044] As for the node modules that are not connected to the network on chip as the network on chip nodes, it is not necessary to completely idle these node modules, but the node memories inside these node modules can be fully utilized. Therefore, in one embodiment, for the node modules that are not connected to the network on chip as the network on chip nodes, the node memories in the node modules are connected to the input port and / or output port access interconnection resource module via a router, thereby connecting to other configurable functional modules, so that other configurable functional modules can read and write the node memories in the node modules, and the node modules realize storage read and write functions, that is, realize functions similar to BRAM modules.

[0045] In order to facilitate the unified configuration and design of node modules that are not connected to the on-chip network as on-chip network nodes and the BRAM module when implementing storage read and write functions, in one embodiment, the module height of each node module is equal to the module height of the BRAM module in the basic resource module. Since the node module also includes other component structures in addition to the node memory, the module width of the node module will be greater than the module width of the BRAM module, so that the node module that is not connected to the on-chip network as an on-chip network node can use the built-in node memory to equivalently implement the storage read and write functions of the BRAM module, and can be consistent with the software processing method of the BRAM module.

[0046] Two node modules connected to the network on chip as network on chip nodes and connected via direct lines are usually node modules located in the same row or column. For node modules not in the same row or column, they usually need to be connected using interconnection resource modules. There are two main situations for two network on chip nodes connected via direct lines: (1) Two node modules are located in the same row or row and arranged adjacently, in which case one node module is connected to another node module arranged adjacently via a direct line. (2) Two node modules are located in the same row or row, and there are several other node modules between the arrangement positions of the two node modules, and the node modules in the middle are not used as network on chip nodes. Although these node modules are not connected to the network on chip as network on chip nodes, conductive lines between the input port and the output port can still be formed inside these node modules. Then, the other node modules between the two node modules as network on chip nodes are configured to form direct lines, and combined with the direct lines between adjacent node modules, the node modules arranged in intervals can still be connected via direct lines.

[0047] for example Figure 4 As shown, among the three node modules NODE-1, NODE-2, and NODE-3 stacked in the same column, NODE-1 and NODE-3 are connected to the on-chip network as on-chip network nodes, while NODE-2 is not used as an on-chip network node. Figure 3 In the data transmission path shown by the dotted line, an input port of NODE-1 is connected to INT to connect other configurable functional modules to obtain data. An input port of NODE-1 is connected to an output port of NODE-1 through a router inside NODE-1. The output port of NODE-1 is connected to an input port of NODE-2 through a direct connection between NODE-1 and NODE-2. The input port of NODE-2 is connected to an output port of NODE-2 through a router inside NODE-2. The output port of NODE-2 is connected to an input port of NODE-3 through a direct connection between NODE-2 and NODE-3. The input port of NODE-3 is connected to an output port of NODE-3 through a router inside NODE-3, and then connected to INT to connect other configurable functional modules to transmit data. As a result, NODE-1 and NODE-3, which are connected as on-chip network nodes in the on-chip network, are connected via NODE-2 through direct connections between node modules.

[0048] In addition, the FPGA described in the present application may be a conventional single-die FPGA, and the node modules and basic resource modules used to form the on-chip network are all located in the same die. Alternatively, the FPGA described in the present application is a multi-die FPGA, and the FPGA includes a substrate, a silicon connection layer stacked on the substrate, and a plurality of dies stacked on the silicon connection layer. Then at least one die in the multi-die FPGA contains a node module and a basic resource module, and the multi-die can also form an on-chip network using only the configurable function module configuration in one die. Alternatively, the multi-die FPGA forms an on-chip network through the configurable function module configuration in multiple dies. In this embodiment, at least two dies in the multi-die FPGA are provided with silicon through vias, and at least one die is provided with silicon through vias at at least one node module, so that the input port and / or output port of the node module are connected to the node modules and / or basic resource modules in other dies through silicon through vias through the silicon connection layer wiring in the silicon connection layer, thereby forming an on-chip network across dies.

[0049] Please refer to Figure 5 In the example shown, a silicon connection layer 2 is stacked on the substrate 1, and a bare die 1 and a bare die 2 are stacked on the silicon connection layer 2. A silicon through hole is provided at NODE1 in bare die 1, and a silicon through hole is provided at NODE2 in bare die 2. The GTH module in bare die 1 is connected to the input port of the node module NODE1 in bare die 1, and a silicon through hole is provided at NODE1 in bare die 1. The output port of NODE1 is led to the silicon connection layer 2 through the silicon through hole. The silicon connection layer wiring 3 in the silicon connection layer 2 is connected to the input port of the node module NODE2 in bare die 2 through the silicon through hole, and the output port of the node module NODE2 in bare die 2 is connected to the input port of the node module NODE3 in bare die 2. Thus, in the multi-bare die FPGA, a cross-bare die on-chip network is formed by combining the GTH and NODE1 in bare die 1 with the NODE2 and NODE3 in bare die 2.

Claims

1. An FPGA having a built-in functional module for forming an on-chip network node, characterized in that: The FPGA includes a plurality of configurable functional modules and interconnection resource modules distributed around each configurable functional module; The configurable function modules in the FPGA include a basic resource module and a node module, each of which includes a router, a node memory, a node controller, a plurality of input ports and a plurality of output ports, all of which are connected to the router, the router is connected to the node memory, and the node controller controls the router; The input ports and output ports of several node modules are connected through direct connections between the node modules and / or interconnection resource modules, and the input port and / or output port of at least one node module is connected to the basic resource module through the interconnection resource module to form an on-chip network in the FPGA, and each on-chip network node in the on-chip network is formed by a node module configuration; All node modules in the FPGA are connected to the network on chip as network on chip nodes, or there is at least one node module in the FPGA that is not connected to the network on chip as a network on chip node; For a node module connected to the network on chip as a node on the chip, a node controller in the node module controls a router to realize interconnection and intercommunication between different input ports and output ports; For a node module that is not connected to the network on chip as a network on chip node, a node memory in the node module is connected to an input port and / or an output port via a router to access an interconnection resource module to implement storage read and write functions.

2. The FPGA according to claim 1, characterized in that: The node modules and basic resource modules in the FPGA are arranged to form a two-dimensional array, and the module height of each node module is equal to the module height of the BRAM module in the basic resource module, the module width of the node module is greater than the module width of the BRAM module, and the node modules that are not connected to the on-chip network as on-chip network nodes use the built-in node memory to equivalently implement the storage read and write functions of the BRAM module.

3. The FPGA according to claim 1, characterized in that: The FPGA is configured to form at least two on-chip networks with different structures according to the obtained different configuration code streams, and there is at least one difference in the number, arrangement position and connection relationship between the configurable functional modules contained in the two on-chip networks with different structures.

4. The FPGA according to claim 1, characterized in that: The node modules and basic resource modules in the FPGA are arranged to form a two-dimensional array, and a plurality of node modules are stacked and arranged to form at least one column and / or at least one row in the two-dimensional array; A node module connected in the network on chip as a network on chip node has at least one input port connected to an output port of other node modules in the same row or column via a direct connection, and / or has at least one input port connected to an output port of other node modules and / or other basic resource modules via an interconnection resource module; A node module connected in the on-chip network as an on-chip network node has at least one output port connected to the input port of other node modules in the same row or column via a direct connection, and / or has at least one output port connected to the input port of other node modules and / or other basic resource modules via an interconnection resource module.

5. The FPGA according to claim 4, characterized in that: For two node modules connected in a NoC as NoC nodes and connected via a direct line: The two node modules are located in the same row or in the same line and arranged adjacently; Alternatively, two node modules are located in the same row or line, and a number of other node modules are spaced between the arrangement positions of the two node modules, and then other node modules between the two node modules are configured to form a direct connection.

6. The FPGA according to claim 1, characterized in that: The node modules in the FPGA are arranged at a predetermined position of the FPGA or within a predetermined range of a basic resource module of a predetermined type, and a data transmission demand of the basic resource module of the predetermined type exceeds a demand threshold.

7. The FPGA according to claim 6, characterized in that: The predetermined type of basic resource module includes at least one of a high-speed transceiver module, an HBM module, and an AI module.

8. The FPGA according to claim 1, characterized in that: The FPGA is a multi-bare-die FPGA, which includes a substrate, a silicon connection layer stacked on the substrate, and a plurality of bare dies stacked on the silicon connection layer. A through-silicon via is opened at at least one node module of the bare die, and the input port and / or output port of the node module are connected to the node modules and / or basic resource modules in other bare dies through the through-silicon via through the silicon connection layer wiring in the silicon connection layer; the FPGA forms an on-chip network through the configurable functional modules in multiple bare dies.

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