A method for calculating noise equivalent, a design method and device for body bias generation circuit

Abstract

The present invention relates to the technical field of transistor noise processing, and specifically relates to a method for calculating noise equivalence, a design method and device for a back-bias generation circuit. The method includes: using a noise current source and a noise voltage source to simulate and generate the noise of a MOS device; equivalently calculating the thermal noise of the drain resistance of the MOS device and the channel thermal noise of the MOS device; equivalently calculating the front-gate flicker noise of the MOS device and the back-gate flicker noise of the MOS device; and performing superposition calculation to obtain the output noise of the MOS device. By analyzing the noise of the MOS device in the FDSOI process, the present invention introduces interference signals representing noise into an ideal MOS device by using a noise current source and a noise voltage source, realizes the simulation calculation of the thermal noise of the drain resistance, the channel thermal noise, the front-gate flicker noise and the back-gate flicker noise of the MOS device, and thus accurately obtains the noise power of the MOS device in the FDSOI process.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor noise processing, and particularly to a noise equivalent calculation method, a design method and device for a back-bias generation circuit. Background Art

[0002] With the continuous reduction of the feature size of the core MOS (Metal Oxide Semiconductor) devices in integrated circuits, affected by the short-channel effect, the traditional bulk silicon devices have reached the physical limit. The FDSOI (Fully Depleted Silicon-On-Insulator) device has become an alternative to the bulk silicon MOS device.

[0003] Since the leakage current of the FDSOI device is small, compared with conventional devices and circuits, the semiconductor devices and circuits composed of MOS devices based on the FDSOI process have lower power consumption. At the same time, the back gate of the four-port FDSOI device can be used as an input port to apply a back-bias voltage, giving the designer more flexibility. Applying a back-bias voltage in the substrate of the FDSOI device can change the threshold voltage V TH Thereby adjusting the transistor operating speed, so as to achieve low-power or high-performance design, making the FDSOI device have very good application prospects.

[0004] However, in practical applications, the MOS devices based on the FDSOI process often form interference noise at the signal input and output ends due to temperature and circuit connections, affecting the input and output performance of the MOS devices based on the FDSOI process, and further affecting the performance of the semiconductor devices and circuits based on the MOS devices of the FDSOI process.

[0005] Therefore, how to accurately obtain the noise power of the MOS devices based on the FDSOI process is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0006] The purpose of the present invention is to provide a noise equivalent calculation method, a design method and device for a back-bias generation circuit to accurately obtain the noise power of the MOS devices based on the FDSOI process.

[0007] To achieve the above purpose, the embodiments of the present invention provide the following solutions:

[0008] In a first aspect, the embodiments of the present invention provide a noise equivalent calculation method for MOS devices based on the FDSOI process, the method comprising:

[0009] According to the noise formation mechanism of the MOS devices based on the FDSOI process, using a noise current source and a noise voltage source, simulate and generate the noise of the MOS devices;

[0010] Using the noise current source, equivalently calculate the drain resistance thermal noise of the MOS device and the channel thermal noise of the MOS device;

[0011] Using the noise voltage source and equivalently regarding the back gate of the MOS device as the front gate, equivalently calculate the front gate flicker noise of the MOS device and the back gate flicker noise of the MOS device;

[0012] According to the drain resistance thermal noise, the channel thermal noise, the front gate flicker noise and the back gate flicker noise, superimpose and calculate to obtain the output noise of the MOS device.

[0013] In a possible embodiment, the noise current source includes a first noise current source and a second noise current source, and the noise voltage source includes a first noise voltage source and a second noise voltage source;

[0014] The use of the noise current source and the noise voltage source to simulate and generate the noise of the MOS device includes:

[0015] Connect the first noise current source in parallel with the drain resistance of the MOS device to simulate and generate the drain resistance thermal noise;

[0016] Set the second noise current source between the drain of the MOS device and the ground to simulate and generate the channel thermal noise;

[0017] Set the first noise voltage source between the front gate of the MOS device and the ground to simulate and generate the front gate flicker noise;

[0018] Set the second noise voltage source between the back gate of the MOS device and the ground to simulate and generate the back gate flicker noise.

[0019] In a possible embodiment, the equivalent calculation of the drain resistance thermal noise of the MOS device and the channel thermal noise of the MOS device includes:

[0020] Calculate the drain resistance thermal noise power spectral density of the MOS device The specific calculation formula is:

[0021]

[0022] where k is the Boltzmann constant, T is the operating temperature, and R D is the drain resistance of the MOS device;

[0023] Calculate the channel noise power spectral density of the MOS device The specific calculation formula is:

[0024]

[0025] Among them, γ is the process parameter of the MOS device, and g m is the transconductance of the MOS device.

[0026] In a possible embodiment, the equivalent calculation of the front-gate flicker noise and the back-gate flicker noise of the MOS device includes:

[0027] Calculating the power spectral density of the front-gate flicker noise of the MOS device The specific calculation formula is:

[0028]

[0029] Among them, K is the noise constant of the MOS device, and C OX is the capacitance per unit area of the front-gate oxide, W is the front-gate width of the MOS device, L is the front-gate length of the MOS device, and f is the operating frequency;

[0030] Calculating the power spectral density of the back-gate flicker noise of the MOS device The specific calculation formula is:

[0031]

[0032] Among them, C′ OX is the capacitance per unit area of the buried oxide layer.

[0033] In a possible embodiment, the superposition calculation to obtain the output noise of the MOS device includes:

[0034] Calculating the power spectral density of the output noise power of the MOS device The specific calculation formula is:

[0035]

[0036] Among them, C′ OX is the capacitance per unit area of the buried oxide layer.

[0037] In a second aspect, an embodiment of the present invention provides a method for noise equivalent calculation of a single-ended voltage-controlled oscillator in an FDSOI process, and the method includes:

[0038] Using the calculation results obtained by any of the noise equivalent calculation methods in the first aspect, equivalently calculating the noise power spectral density PhaseNoise(Δω) of the white noise and the flicker noise of the voltage-controlled oscillator white+flicker and the noise power spectral density PhaseNoise(Δω) of the sampling noise of the voltage-controlled oscillator sample , and the specific calculation formula is:

[0039]

[0040] Among them, Δω is the current working angular frequency, ω0 is the free oscillation angular frequency of the voltage-controlled oscillator, and T0 is the total delay duration of the voltage-controlled oscillator. is the power spectral density of the channel thermal noise of the (k - 1)-th stage transistor of the voltage-controlled oscillator. is the power spectral density of the channel thermal noise of the k-th stage transistor of the voltage-controlled oscillator. is the back-gate noise of the k-th stage transistor of the voltage-controlled oscillator, g m,k is the transconductance of the k-th stage transistor of the voltage-controlled oscillator, h k is the non-normalized pulse sensitivity function. is the charging duration, I NK is the current of the NMOS transistor of the k-th stage transistor of the voltage-controlled oscillator, C K is the capacitance of the k-th stage transistor of the voltage-controlled oscillator, M is the number of stages of the voltage-controlled oscillator, I dc is the DC operating voltage of the voltage-controlled oscillator, V dd is the power supply voltage of the voltage-controlled oscillator, r ds,k-1 is the internal resistance of the (k - 1)-th stage transistor of the voltage-controlled oscillator.

[0041] In a third aspect, an embodiment of the present invention provides a method for calculating the noise equivalent of a back-bias generation circuit. The method includes:

[0042] Using the calculation result obtained by the noise equivalent calculation method described in the second aspect, equivalently calculate the noise power spectral density PhaseNoise(Δω) at the output end of the back-bias generation circuit of the FDSOI process single-ended voltage-controlled oscillator VCO , and the specific calculation formula is:

[0043]

[0044] Among them, V out is the output back-bias voltage of the back-bias generation circuit, Φ in is the input phase of the back-bias generation circuit, K PFD,CP is the signal gain of the frequency discriminator and phase detector and charge pump in the back-bias generation circuit, K LPF is the signal gain of the loop filter in the back-bias generation circuit, K VCO is the signal gain of the voltage-controlled oscillator in the back-bias generation circuit, and s is the coefficient of the Laplace transform.

[0045] In a fourth aspect, an embodiment of the present invention provides a design method for a back-bias generation circuit. The method includes:

[0046] According to the noise equivalent calculation method described in the third aspect, obtain the noise power spectral density at the output end of the back-bias generation circuit of the FDSOI process single-ended voltage-controlled oscillator;

[0047] According to the noise power spectral density, adjust the configuration parameters of the frequency discriminator and / or loop filter in the back-bias generation circuit to cancel the noise generated by the voltage-controlled oscillator at the output end of the back-bias generation circuit.

[0048] In a fifth aspect, an embodiment of the present invention provides a design device for a back-bias generation circuit, and the device includes:

[0049] A first acquisition module for obtaining the noise power spectral density at the output end of the back-bias generation circuit of the FDSOI process single-ended voltage-controlled oscillator according to the noise equivalent calculation method described in the third aspect;

[0050] A parameter adjustment module for adjusting the configuration parameters of the frequency discriminator and / or loop filter in the back-bias generation circuit according to the noise power spectral density to cancel the noise generated by the voltage-controlled oscillator at the output end of the back-bias generation circuit.

[0051] In a sixth aspect, an embodiment of the present invention provides an electronic device, including:

[0052] A memory for storing a computer program;

[0053] A processor for executing the computer program to implement the steps of the method described in any one of the first aspect, the second aspect, the third aspect, and the fourth aspect.

[0054] In a seventh aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in any one of the first aspect, the second aspect, the third aspect, and the fourth aspect are implemented.

[0055] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0056] Through the noise analysis of the FDSOI process MOS device, the present invention introduces interference signals representing noise into the ideal MOS device by using a noise current source and a noise voltage source, realizes the simulation calculation of the drain resistance thermal noise, channel thermal noise, front gate flicker noise, and back gate flicker noise of the MOS device, and thus accurately obtains the noise power of the FDSOI process MOS device. Description of the Drawings

[0057] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0058] Figure 1 is a flowchart of a method for calculating the noise equivalent of an FDSOI process MOS device provided by an embodiment of the present invention;

[0059] Figure 2 is a schematic diagram of noise equivalent analysis of an FDSOI process MOS device provided by an embodiment of the present invention;

[0060] Figure 3 is a flowchart of a method for calculating the noise equivalent of a single-ended voltage-controlled oscillator with an FDSOI process provided by an embodiment of the present invention;

[0061] Figure 4 is a schematic diagram of single-stage structure noise analysis of a single-ended voltage-controlled oscillator with an FDSOI process provided by an embodiment of the present invention;

[0062] Figure 5 is a schematic diagram of the structure of a 97-stage ring voltage-controlled oscillator provided by an embodiment of the present invention;

[0063] Figure 6 is Figure 5 a schematic diagram of noise analysis of the ring voltage-controlled oscillator shown;

[0064] Figure 7 is Figure 5 a curve graph of the back-bias input noise of the ring voltage-controlled oscillator shown;

[0065] Figure 8 is Figure 5 a curve graph of the voltage-controlled oscillator output noise of the ring voltage-controlled oscillator shown;

[0066] Figure 9 is a schematic diagram of the connection of the linear transmission model of a back-bias generation circuit provided by an embodiment of the present invention;

[0067] Figure 10 is a flowchart of a method for calculating the noise equivalent of a back-bias generation circuit provided by an embodiment of the present invention;

[0068] Figure 11 is a simulation circuit diagram of a back-bias generation circuit provided by an embodiment of the present invention;

[0069] Figure 12 is Figure 11 a schematic diagram of the simulation result of the back-bias generation circuit shown;

[0070] Figure 13 is a flowchart of a design method for a back bias generation circuit provided by an embodiment of the present invention;

[0071] Figure 14 is a schematic structural diagram of a design device for a back bias generation circuit provided by an embodiment of the present invention. Detailed implementation manners

[0072] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art belong to the scope protected by the embodiments of the present invention.

[0073] Please refer to Figure 1 , Figure 1 is a flowchart of a method for calculating the noise equivalent of an FDSOI process MOS device provided by an embodiment of the present invention, including steps 11 to 14.

[0074] Step 11: According to the noise formation mechanism of the FDSOI process MOS device, use a noise current source and a noise voltage source to simulate and generate the noise of the MOS device.

[0075] Step 12: Use the noise current source to equivalently calculate the drain resistance thermal noise of the MOS device and the channel thermal noise of the MOS device.

[0076] Step 13: Use the noise voltage source and equivalent the back gate of the MOS device to the front gate to equivalently calculate the front gate flicker noise of the MOS device and the back gate flicker noise of the MOS device.

[0077] Step 14: According to the drain resistance thermal noise, the channel thermal noise, the front gate flicker noise, and the back gate flicker noise, superimpose and calculate to obtain the output noise of the MOS device.

[0078] Specifically, since the noise formation mechanism of the FDSOI process MOS device is very complex and there are many types of noise according to different extraction methods. The inventors of the present invention found in the in-depth study of the noise formation mechanism of the FDSOI process MOS device that the white noise and flicker noise contribute more to the electronic noise of the FDSOI device, and at the same time, it is relatively easy to simulate. Therefore, it is selected to calculate the white noise and flicker noise of the FDSOI device to accurately obtain the noise power of the FDSOI device.

[0079] Specifically, white noise includes resistor thermal noise and transistor channel thermal noise, which are formed by the random movement of electrons. Flicker noise includes transistor back-gate noise and transistor front-gate noise, which are generated by the random capture and release of charge carriers at the oxide-silicon interface, resulting in flicker noise in the drain current. The back-gate has the same structure as the front-gate and generates flicker noise at the buried oxide-channel interface. The back-gate of the FDSOI device is equivalent to the front-gate, and its back-gate noise is equivalently coupled to the front-gate.

[0080] Figure 2 The following is a schematic diagram of the noise equivalent analysis of an FDSOI process MOS device provided by an embodiment of the present invention to illustrate the equivalent calculation process of this embodiment. Among them: the noise current source includes a first noise current source and a second noise current source, and the noise voltage source includes a first noise voltage source and a second noise voltage source.

[0081] Specifically:

[0082] 1) Connect the first noise current source in parallel with the drain resistance of the MOS device to simulate the generation of drain resistance thermal noise, so as to calculate the power spectral density of the drain resistance thermal noise of the MOS device where k is the Boltzmann constant, T is the operating temperature, and R D is the drain resistance of the MOS device.

[0083] 2) Set the second noise current source between the drain of the MOS device and the ground to simulate the generation of channel thermal noise, so as to calculate the power spectral density of the channel noise of the MOS device where γ is a process parameter related to the size of the MOS device, and g m is the transconductance of the MOS device.

[0084] Specifically, when the MOS device is in the saturation region, g m = μ n C OX (W / L)(V gs - V TH ); when the MOS device is in the linear region, g m = μ n C OX (W / L)V ds ; where μ n is the carrier mobility; it can be seen that the back bias voltage affects the saturation region transconductance g TH by changing the transistor threshold V m and thus affects the output noise power.

[0085] 3) Set the first noise voltage source between the front gate of the MOS device and the ground to simulate the generation of front gate flicker noise, so as to calculate the power spectral density of the front gate flicker noise of the MOS device where K is the noise constant of the MOS device, C OX is the capacitance per unit area of the front gate oxide, W is the front gate width of the MOS device, L is the front gate length of the MOS device, and f is the operating frequency.

[0086] 4) Set the second noise voltage source between the back gate of the MOS device and ground to simulate the generation of back gate flicker noise, and then calculate the back gate flicker noise power spectral density of the MOS device where C′ OX is the capacitance per unit area of the buried oxide layer.

[0087] After calculating the drain resistance thermal noise, channel thermal noise, front gate flicker noise, and back gate flicker noise, the output noise of the MOS device can be obtained by simple superposition. where C′ OX is the capacitance per unit area of the buried oxide layer.

[0088] can represent the overall output noise power spectral density of the transistor, and its physical meaning is the average noise power within a 1 Hz bandwidth of the carrier with frequency f.

[0089] In this embodiment, by performing noise analysis on the FDSOI process MOS device, interference signals representing noise are introduced into the ideal MOS device using noise current sources and noise voltage sources, realizing the simulation and calculation of the drain resistance thermal noise, channel thermal noise, front gate flicker noise, and back gate flicker noise of the MOS device, thereby accurately obtaining the noise power of the FDSOI process MOS device.

[0090] Voltage-controlled oscillators are commonly used as frequency generation modules. Among them, a voltage-controlled oscillator composed of a single-ended inverter chain is called a single-ended voltage-controlled oscillator. The inverters in a single-ended voltage-controlled oscillator can use FDSOI devices, which can effectively reduce power consumption and improve performance. By introducing a perturbation, the system amplifies this small signal and finally generates a clock signal with a period approximately twice the total delay. There is a large internal noise in a single-ended voltage-controlled oscillator compared to a differential voltage-controlled oscillator, and noise analysis needs to be performed on the ring voltage-controlled oscillator composed of FDSOI.

[0091] After obtaining the noise power of the FDSOI process MOS device, the noise level of the FDSOI process single-ended voltage-controlled oscillator can be equivalently calculated.

[0092] Such as Figure 3 shown is a flowchart of a method for equivalently calculating the noise of a single-ended voltage-controlled oscillator using the FDSOI process provided by an embodiment of the present invention, which specifically includes step 21.

[0093] Step 21: Using the calculation results obtained by any of the noise equivalent calculation methods for FDSOI process MOS devices described above, equivalently calculate the noise power spectral density of the white noise and flicker noise of the voltage-controlled oscillator and the sampling noise power spectral density of the voltage-controlled oscillator.

[0094] As Figure 4 shown in the schematic diagram of the single-stage structure noise analysis of a single-ended voltage-controlled oscillator provided by an embodiment of the present invention, the single-stage structure of the voltage-controlled oscillator is composed of an inverter and a capacitor. The noise components of the single-stage oscillator are transistor channel thermal noise, back-gate noise, and sampling noise during capacitor charging and discharging. Perform equivalent noise analysis on the single stage of the voltage-controlled oscillator:

[0095] 1) Use a noise current source to equivalently represent the channel thermal noise in the saturation region of the k-th transistor. The thermal noise power spectral density of the k-th transistor can be expressed as

[0096] 2) Use a noise voltage source to equivalently represent the channel thermal noise in the linear region of the (k - 1)-th transistor. The thermal noise power spectral density of the (k - 1)-th transistor can be expressed as

[0097] 3) Use a noise voltage source to equivalently represent the flicker noise caused by the back-gate of the k-th transistor, and equivalently represent the back-gate as the front-gate. The back-gate noise of the k-th transistor can be expressed as

[0098] 4) When the PMOS transistor in the inverter switches from the ON / OFF state, the NMOS transistor is not in the linear region but in the OFF state or the saturation state. The internal current I of the transistor NK = 2I dc , within the discharge time of Δt k , the noise power spectral density of the single stage is defined as The current I of the NMOS transistor NK deposits a voltage of ΔV K on C k . The noise power spectral density of the capacitor C K is The noise generated by the current of the NMOS transistor on C K during this period is the sampling noise. The overall charging and discharging time

[0099] Integrate the noise power spectral density function within T0 to obtain the phase noise power.

[0100] In summary, the noise power spectral density PhaseNoise(Δω) of the white noise and flicker noise of the voltage-controlled oscillator can be obtained white+flicker and the sampling noise power spectral density PhaseNoise(Δω) of the voltage-controlled oscillatorsample The specific calculation formula is as follows:

[0101]

[0102] Wherein, Δω is the current working angular frequency, ω0 is the free oscillation angular frequency of the voltage-controlled oscillator, and T0 is the total delay time length of the voltage-controlled oscillator. is the power spectral density of the channel thermal noise of the (k - 1)-th stage transistor of the voltage-controlled oscillator. is the power spectral density of the channel thermal noise of the k-th stage transistor of the voltage-controlled oscillator. is the back-gate noise of the k-th stage transistor of the voltage-controlled oscillator, g m,k is the transconductance of the k-th stage transistor of the voltage-controlled oscillator, h k is the non-normalized pulse sensitivity function. is the charging duration, I NK is the current of the NMOS transistor of the k-th stage transistor of the voltage-controlled oscillator, C K is the capacitance of the k-th stage transistor of the voltage-controlled oscillator, M is the number of stages of the voltage-controlled oscillator, I dc is the DC operating voltage of the voltage-controlled oscillator, V dd is the power supply voltage of the voltage-controlled oscillator, r ds,k-1 is the internal resistance of the (k - 1)-th stage transistor of the voltage-controlled oscillator.

[0103] To illustrate the accuracy of the calculation results of this embodiment, a case of noise simulation analysis of a voltage-controlled oscillator is also provided here.

[0104] As Figure 5 shown in the structural schematic diagram of the 97-stage ring voltage-controlled oscillator provided by the embodiment of the present invention, as Figure 6 shown is Figure 5 the noise analysis schematic diagram of the ring voltage-controlled oscillator shown in, wherein a probe element iprobe is connected in the loop to build a noise simulation circuit. As Figure 7 shown is Figure 5 the curve graph of the back-bias input noise of the ring voltage-controlled oscillator shown in, as Figure 8 shown is Figure 5 the curve graph of the output noise of the voltage-controlled oscillator of the ring voltage-controlled oscillator shown in.

[0105] Through the comparison between the simulation results and the equivalent calculation results, this embodiment can accurately obtain the output noise of the single-ended voltage-controlled oscillator in the FDSOI process by equivalent calculation.

[0106] Since the back bias voltage of the FDSOI device needs to be provided by the back bias generation circuit, and the voltage-controlled oscillator is commonly used as the frequency generation module in the back bias generation circuit to detect the operating frequency of the device under test. The back bias voltage is output through the back bias generation circuit to change the operating frequency of the device under test. The voltage-controlled oscillator in the back bias generation circuit adopts a single-ended ring structure, which has a large internal noise compared with the differential voltage-controlled oscillator. Therefore, it is necessary to analyze the noise of the ring voltage-controlled oscillator composed of FDSOI.

[0107] As Figure 9 shown is a schematic connection diagram of the linear transmission model of a back bias generation circuit provided by an embodiment of the present invention, including a phase frequency detector + charge pump module, a low-pass filter module, and a ring oscillator module. The forward transmission path consists of a phase frequency detector, a charge pump, and a low-pass filter, and the feedback loop consists of the device under test ring oscillator.

[0108] The open-loop transfer function is obtained by multiplying the gains:

[0109]

[0110] Disconnect the loop at the output position of the low-pass filter to obtain the closed-loop transfer function:

[0111]

[0112] The noise transfer function of the device under test ring oscillator is:

[0113]

[0114] The external noise transfer function of the reference clock is:

[0115] H(s)2 = H(s) close .

[0116] The internal quantization noise transfer function of the PFD+CP is:

[0117]

[0118] Then, it can be deduced that the noise power at the output of the device under test ring oscillator is:

[0119] PhaseNoise(Δω) VCO = |H(s)1| 2 [PhaseNoise(Δω) white+flicker +PhaseNoise(Δω) sample .

[0120] As Figure 10 shown is a flowchart of a noise equivalent calculation method for a back bias generation circuit provided by an embodiment of the present invention, including step 31.

[0121] Step 31: Using the calculation result obtained by the noise equivalent calculation method of the single-ended voltage-controlled oscillator in the FDSOI process, equivalently calculate the noise power spectral density at the output end of the back-bias generation circuit of the single-ended voltage-controlled oscillator in the FDSOI process.

[0122] The specific calculation formula is:

[0123]

[0124] where V out is the output back-bias voltage of the back-bias generation circuit, Φ in is the input phase of the back-bias generation circuit, K PFD,CP is the signal gain of the phase-frequency detector and charge pump in the back-bias generation circuit, K LPF is the signal gain of the loop filter in the back-bias generation circuit, K VCO is the signal gain of the voltage-controlled oscillator in the back-bias generation circuit, and s is the coefficient of the Laplace transform.

[0125] To illustrate the accuracy of the calculation result of this embodiment, a noise simulation analysis application case of the back-bias generation circuit is also provided here.

[0126] As Figure 11 shown is a simulation circuit diagram of a back-bias generation circuit provided by an embodiment of the present invention, and as Figure 12 shown is a schematic diagram of the simulation result of the back-bias generation circuit shown in Figure 11 .

[0127] Through the comparison between the simulation result and the equivalent calculation result, this embodiment can accurately equivalently calculate the output noise of the back-bias generation circuit.

[0128] After calculating PhaseNoise(Δω) VCO , it can guide the design of the actual back-bias generation circuit to cancel out the PhaseNoise(Δω) VCO noise interference signal through specific configuration when the back-bias generation circuit is working properly.

[0129] As Figure 13 shown is a flowchart of a design method of a back-bias generation circuit provided by an embodiment of the present invention, including Step 41 to Step 42.

[0130] Step 41: According to the noise equivalent calculation method described in the third aspect, obtain the noise power spectral density at the output end of the single-ended voltage-controlled oscillator in the FDSOI process in the back-bias generation circuit.

[0131] Step 42: According to the noise power spectral density, adjust the configuration parameters of the frequency discriminator and / or loop filter in the body bias generation circuit to cancel out the noise generated by the voltage-controlled oscillator at the output end of the body bias generation circuit.

[0132] Based on the same inventive concept as the method, an embodiment of the present invention further provides a design device for a body bias generation circuit, as Figure 14 shown in the structural schematic diagram of the device embodiment. The device includes:

[0133] A first acquisition module 51, configured to acquire the noise power spectral density at the output end of the single-ended voltage-controlled oscillator of the FDSOI process in the body bias generation circuit according to the noise equivalent calculation method described in the third aspect;

[0134] A parameter adjustment module 52, configured to adjust the configuration parameters of the frequency discriminator and / or loop filter in the body bias generation circuit according to the noise power spectral density to cancel out the noise generated by the voltage-controlled oscillator at the output end of the body bias generation circuit.

[0135] Based on the same inventive concept as in the foregoing embodiments, an embodiment of the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of any of the foregoing methods are implemented.

[0136] Based on the same inventive concept as in the foregoing embodiments, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of any of the foregoing methods are implemented.

[0137] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0138] In the embodiments of the present invention, through noise analysis of MOS devices in the FDSOI process, interference signals representing noise are introduced into ideal MOS devices by using noise current sources and noise voltage sources, realizing the simulation calculation of the drain resistance thermal noise, channel thermal noise, front gate flicker noise, and back gate flicker noise of MOS devices, thereby accurately obtaining the noise power of MOS devices in the FDSOI process.

[0139] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0140] The present invention will be described with reference to the flowcharts and / or block diagrams of methods, apparatuses (modules, systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded computers, or other programmable data processing devices to generate a machine, so that the instructions executed by the processors of the computer or other programmable data processing devices generate means for implementing the functions specified in one or more flows Figure 1 one or more flows and / or blocks Figure 1 or in one or more blocks.

[0141] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implement the functions specified in one or more flows Figure 1 one or more flows and / or blocks Figure 1 or in one or more blocks.

[0142] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows Figure 1 one or more flows and / or blocks Figure 1 or in one or more blocks.

[0143] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0144] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A method for calculating the noise equivalent of an MOS device in an FDSOI process, characterized in that, The method includes: According to the noise formation mechanism of MOS devices in the FDSOI process, using a noise current source and a noise voltage source, simulating and generating the noise of the MOS device; Using the noise current source, equivalently calculating the drain resistance thermal noise of the MOS device and the channel thermal noise of the MOS device; Using the noise voltage source, and equivalently calculating the front gate flicker noise of the MOS device and the back gate flicker noise of the MOS device by equivalently regarding the back gate of the MOS device as the front gate; According to the drain resistance thermal noise, the channel thermal noise, the front gate flicker noise and the back gate flicker noise, calculating and obtaining the output noise of the MOS device by superposition; The equivalently calculating the drain resistance thermal noise of the MOS device and the channel thermal noise of the MOS device includes: Calculating the power spectral density of the drain resistance thermal noise of the MOS device, and the specific calculation formula is: ； Among them, is the Boltzmann constant, is the operating temperature, is the drain resistance of the MOS device; Calculate the channel noise power spectral density of the MOS device , and the specific calculation formula is as follows: ； Among them, is the process parameter of the MOS device, is the transconductance of the MOS device; The equivalently calculating the front gate flicker noise of the MOS device and the back gate flicker noise of the MOS device includes: Calculate the front-gate flicker noise power spectral density of the MOS device , and the specific calculation formula is as follows: ； Among them, is the noise constant of the MOS device, is the capacitance per unit area of the front gate oxide, is the front gate width of the MOS device, is the front gate length of the MOS device, is the operating frequency; Calculate the back-gate flicker noise power spectral density of the MOS device , and the specific calculation formula is as follows: ； Among them, is the capacitance per unit area of the buried oxide layer.

2. The noise equivalent calculation method according to claim 1, wherein The calculating and obtaining the output noise of the MOS device by superposition includes: Calculate the output noise power spectral density of the MOS device , and the specific calculation formula is: 。 3. A method for calculating the noise equivalent of a single-ended voltage-controlled oscillator in an FDSOI process, characterized in that, The method includes: The calculation results obtained by using the noise equivalent calculation method according to any one of claims 1 to 2 are used to equivalently calculate the noise power spectral density of the white noise and flicker noise of the voltage-controlled oscillator and the sampling noise power spectral density of the voltage-controlled oscillator , and the specific calculation formula is: ； Among them, is the current working angular frequency, is the free oscillation angular frequency of the voltage-controlled oscillator, is the total delay duration of the voltage-controlled oscillator, is the channel thermal noise power spectral density of the (k - 1)-th stage transistor of the voltage-controlled oscillator, is the channel thermal noise power spectral density of the k-th stage transistor of the voltage-controlled oscillator, is the back-gate noise of the k-th stage transistor of the voltage-controlled oscillator, is the transconductance of the k-th stage transistor of the voltage-controlled oscillator, is the non-normalized pulse sensitivity function, is the charging duration, is the NMOS current of the k-th stage transistor of the voltage-controlled oscillator, is the capacitance of the k-th stage transistor of the voltage-controlled oscillator, is the number of stages of the voltage-controlled oscillator, is the DC operating voltage of the voltage-controlled oscillator, is the power supply voltage of the voltage-controlled oscillator, is the internal resistance of the (k - 1)-th stage transistor of the voltage-controlled oscillator.

4. A method for calculating the noise equivalent of a back bias generation circuit, characterized in that, The method includes: The calculation result obtained by using the noise equivalent calculation method described in claim 3 is used to equivalently calculate the noise power spectral density at the output end of the back bias generation circuit of the FDSOI process single-ended voltage-controlled oscillator , and the specific calculation formula is as follows: ； Among them, is the output back-bias voltage of the back-bias generation circuit, is the input phase of the back-bias generation circuit, is the signal gain of the phase-frequency detector and charge pump in the back-bias generation circuit, is the signal gain of the loop filter in the back-bias generation circuit, is the signal gain of the voltage-controlled oscillator in the back-bias generation circuit, is the coefficient of the Laplace transform.

5. A design method for a back bias generation circuit, characterized in that, The method includes: According to the noise equivalent calculation method described in claim 4, obtaining the power spectral density of the noise at the output end of the back bias generation circuit of a single-ended voltage-controlled oscillator in the FDSOI process; According to the power spectral density of the noise, adjusting the configuration parameters of the phase frequency detector and / or the loop filter in the back bias generation circuit to cancel the noise generated by the voltage-controlled oscillator at the output end of the back bias generation circuit.

6. A design device for a back bias generation circuit, characterized in that, The device includes: A first acquisition module, configured to obtain the power spectral density of the noise at the output end of the back bias generation circuit of a single-ended voltage-controlled oscillator in the FDSOI process according to the noise equivalent calculation method described in claim 4; A parameter adjustment module, configured to adjust the configuration parameters of the phase frequency detector and / or the loop filter in the back bias generation circuit according to the power spectral density of the noise to cancel the noise generated by the voltage-controlled oscillator at the output end of the back bias generation circuit.

7. An electronic device, characterized in that, Includes: A memory, used for storing a computer program; A processor, configured to execute the computer program to implement the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 5.

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