Wafer level chip scale packaging method

Abstract

The application provides a wafer level chip packaging method, which comprises the following steps: depositing a protective layer to cover the top surface of a deep groove structure, the top surface of a plurality of contacts, and fill the gap between the plurality of contacts; etching the protective layer to expose the top surface of the deep groove structure and the top surface of the plurality of contacts; etching the deep groove structure to form a groove structure; depositing a packaging material to cover the top surface of the remaining protective layer, the top surface of the plurality of contacts, and fill the groove structure to form a to-be-divided wafer; grinding the bottom surface of the to-be-divided wafer; and separating the plurality of chips by acid tank or laser cutting, without transverse cutting and longitudinal cutting by a scribe knife, so that the cost is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a wafer-level chip packaging method. Background Technology

[0002] In existing technologies, wafer packaging is typically diced using dicing blades for both longitudinal and transverse cuts, resulting in a large number of cuts and high costs.

[0003] Therefore, it is necessary to provide a novel wafer-level chip packaging method to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0004] The purpose of this invention is to provide a wafer-level chip packaging method to reduce costs.

[0005] To achieve the above objectives, the wafer-level chip packaging method of the present invention includes:

[0006] A wafer is provided, the wafer comprising a plurality of chips, and the chips comprising a plurality of contacts, wherein a deep trench structure is formed between the chips;

[0007] A protective layer is deposited to cover the top surface of the deep trench structure, the top surface of the contacts, and to fill the gaps between the contacts;

[0008] The protective layer is etched to expose the top surface of the deep trench structure and the top surface of several of the contacts;

[0009] The deep trench structure is etched to form a groove structure;

[0010] Deposit encapsulation material to cover the top surface of the remaining protective layer, the top surface of the contacts, and fill the groove structure to form a wafer to be diced;

[0011] The bottom surface of the wafer to be divided is ground, and then the chips are separated by acid bath or laser cutting.

[0012] The beneficial effects of the wafer-level chip packaging method are as follows: depositing a protective layer to cover the top surface of the deep trench structure, the top surface of several contacts, and filling the gaps between the contacts; etching the protective layer to expose the top surface of the deep trench structure and the top surface of several contacts; etching the deep trench structure to form a groove structure; depositing packaging material to cover the top surface of the remaining protective layer, the top surface of several contacts, and filling the groove structure to form a wafer to be diced; grinding the bottom surface of the wafer to be diced; and then separating several chips by acid bath or laser cutting, without the need for lateral and longitudinal cutting with a dicing blade, greatly reducing costs.

[0013] Optionally, before performing the grinding of the bottom surface of the wafer to be divided, the method further includes:

[0014] A protective film is applied to the top surface of the wafer to be diced, and then the wafer is flipped over.

[0015] Optionally, after performing the step of separating the chips by acid bath or laser cutting, the process further includes:

[0016] A layer of encapsulation material is deposited to cover the bottom and sides of several of the chips;

[0017] The tension of the protective film causes several of the chips to separate.

[0018] Optionally, the protective film is an adhesive tape or a UV film.

[0019] Optionally, the encapsulation material includes polyimide.

[0020] Optionally, before performing the grinding of the bottom surface of the wafer to be divided, the method further includes:

[0021] The encapsulation material is etched to expose portions of the top surface of several of the contacts.

[0022] Optionally, grinding the bottom surface of the wafer to be divided includes:

[0023] The top surface of the wafer to be divided is ground until several chips can be separated by acid bath or laser cutting. Attached Figure Description

[0024] Figure 1 This is a flowchart of the circular-level chip packaging method of the present invention;

[0025] Figure 2 This is a schematic diagram of the wafer structure in some embodiments of the present invention;

[0026] Figure 3 This is a schematic diagram of the first intermediate structure in some embodiments of the present invention;

[0027] Figure 4 This is a schematic diagram of the second intermediate structure in some embodiments of the present invention;

[0028] Figure 5 This is a schematic diagram of the third intermediate structure in some embodiments of the present invention;

[0029] Figure 6 This is a schematic diagram of the fourth intermediate structure in some embodiments of the present invention;

[0030] Figure 7 This is a schematic diagram of the fifth intermediate structure in some embodiments of the present invention;

[0031] Figure 8 This is a schematic diagram of the sixth intermediate structure in some embodiments of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0033] To address the problems existing in the prior art, embodiments of the present invention provide a wafer-level chip packaging method. (Refer to...) Figure 1 The wafer-level chip packaging method includes the following steps:

[0034] S0: A wafer is provided, the wafer including a plurality of chips, and the chips including a plurality of contacts, and a deep trench structure is formed between the chips;

[0035] S1: Deposit a protective layer to cover the top surface of the deep trench structure, the top surface of the contacts, and fill the gaps between the contacts;

[0036] S2: Etch the protective layer to expose the top surface of the deep trench structure and the top surface of the contacts;

[0037] S3: Etch the deep trench structure to form a groove structure;

[0038] S4: Deposit encapsulation material to cover the top surface of the remaining protective layer, the top surface of the plurality of contacts, and fill the groove structure to form a wafer to be diced;

[0039] S5: Grind the bottom surface of the wafer to be divided, and then separate the chips by acid bath or laser cutting.

[0040] In some embodiments, before performing the grinding of the bottom surface of the wafer to be diced, the method further includes: covering the top surface of the wafer to be diced with a protective film, and then flipping the wafer to be diced.

[0041] In some embodiments, after performing the step of separating the plurality of chips by acid bath or laser cutting, the method further includes: depositing a layer of encapsulation material to cover the bottom and sides of the plurality of chips;

[0042] The tension of the protective film causes several of the chips to separate.

[0043] In some embodiments, the protective film is an adhesive tape or a UV film.

[0044] In some embodiments, the encapsulation material includes polyimide.

[0045] In some embodiments, before performing the grinding of the bottom surface of the wafer to be divided, the method further includes: etching the packaging material to expose a portion of the top surface of the plurality of contacts. When etching the packaging material, photoresist is first coated, then exposed to obtain a photoresist pattern, and the packaging material is etched using the photoresist pattern as a mask to expose a portion of the top surface of the plurality of contacts.

[0046] In some embodiments, grinding the bottom surface of the wafer to be divided includes grinding the top surface of the wafer to be divided until the chips can be separated by acid bath or laser cutting.

[0047] Figure 2 This is a schematic diagram of the wafer structure in some embodiments of the present invention. (Refer to...) Figure 2 The wafer includes two chips, namely a first chip 100 and a second chip (not shown in the figure), and the first chip includes four contacts 101. A deep trench structure 200 is formed between the first chip 100 and the second chip.

[0048] Figure 3 This is a schematic diagram of the first intermediate structure in some embodiments of the present invention. (Refer to...) Figure 2 and Figure 3 A protective layer 300 is deposited on the wafer to cover the top surface of the deep trench structure 200, the top surface of the plurality of contacts 101, and to fill the gaps between the plurality of contacts 101, thereby forming a first intermediate structure.

[0049] Figure 4 This is a schematic diagram of the second intermediate structure in some embodiments of the present invention. (Refer to...) Figure 3 and Figure 4 Based on the first intermediate structure, the protective layer 300 is etched to expose the top surface of the deep trench structure 200 and the top surface of the contact 101 to obtain the second intermediate structure.

[0050] In some embodiments, during etching, photoresist can be deposited first, and then exposed to form a photoresist pattern. The protective layer is then etched using the photoresist pattern as a mask, thereby exposing the top surface of the deep trench structure and the top surface of the contact. The exposed top surface of the deep trench structure can be partial or complete.

[0051] Figure 5 This is a schematic diagram of the third intermediate structure in some embodiments of the present invention. (Refer to...) Figure 4 and Figure 5 Based on the second intermediate structure, the deep trench structure 200 is etched to form a groove structure 201, thereby obtaining the third intermediate structure.

[0052] Figure 6 This is a schematic diagram of the fourth intermediate structure in some embodiments of the present invention. (Refer to...) Figure 5 and Figure 6 Based on the third intermediate structure, an encapsulation material 400 is deposited to cover the top surface of the remaining protective layer 300, the top surface of several contacts 101, and to fill the groove structure 201 to form a wafer to be divided, which is the fourth intermediate structure.

[0053] Figure 7 This is a schematic diagram of the fifth intermediate structure in some embodiments of the present invention. (Refer to...) Figure 6 and Figure 7 Based on the fourth intermediate structure, a protective film 500 is covered on the top surface of the wafer to be divided. Then, the wafer to be divided is flipped 180 degrees so that the side covered with the protective film 500 is vertically facing down. Then, the bottom surface of the wafer to be divided is ground until the first chip and the second chip can be separated by acid bath or laser cutting to obtain the fifth intermediate structure.

[0054] Figure 8 This is a schematic diagram of the sixth intermediate structure in some embodiments of the present invention. (Refer to...) Figure 7 and Figure 8 Based on the fifth intermediate structure, the first chip and the second chip are separated by acid bath or laser cutting, and then a layer of encapsulation material 400 is deposited to cover the bottom and sides of the first chip 100 and the second chip to obtain the sixth intermediate structure.

[0055] In some embodiments, based on the sixth intermediate structure, the first chip and the second chip are separated by the tension of the protective film.

[0056] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A wafer-level chip packaging method, characterized in that, include: A wafer is provided, the wafer comprising a plurality of chips, and the chips comprising a plurality of contacts, wherein a deep trench structure is formed between the chips; A protective layer is deposited to cover the top surface of the deep trench structure, the top surface of the contacts, and to fill the gaps between the contacts; The protective layer is etched to expose the top surface of the deep trench structure and the top surface of several of the contacts; The deep trench structure is etched to form a groove structure; Deposit encapsulation material to cover the top surface of the remaining protective layer, the top surface of the contacts, and fill the groove structure to form a wafer to be diced; The bottom surface of the wafer to be divided is ground, and then the chips are separated by acid bath or laser cutting.

2. The wafer-level chip packaging method according to claim 1, characterized in that, Before performing the grinding of the bottom surface of the wafer to be divided, the process further includes: A protective film is applied to the top surface of the wafer to be diced, and then the wafer is flipped over.

3. The wafer-level chip packaging method according to claim 2, characterized in that, After performing the aforementioned process and then separating the chips by acid bath or laser cutting, the method further includes: A layer of encapsulation material is deposited to cover the bottom and sides of several of the chips; The tension of the protective film causes several of the chips to separate.

4. The wafer-level chip packaging method according to claim 2 or 3, characterized in that, The protective film is an adhesive tape or a UV film.

5. The wafer-level chip packaging method according to claim 1 or 3, characterized in that, The encapsulation material includes polyimide.

6. The wafer-level chip packaging method according to claim 1, characterized in that, Before performing the grinding of the bottom surface of the wafer to be divided, the process further includes: The encapsulation material is etched to expose portions of the top surface of several of the contacts.

7. The wafer-level chip packaging method according to claim 1, characterized in that, The grinding of the bottom surface of the wafer to be divided includes: The top surface of the wafer to be divided is ground until several chips can be separated by acid bath or laser cutting.

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