Soft start circuit for DC-DC converter

Abstract

An embodiment of the present disclosure provides a soft start circuit for a DC-DC converter, comprising: a ramp signal generating circuit, a first reset circuit, a ramp signal clamping circuit, a second reset circuit, and an output circuit. The ramp signal generating circuit generates a first ramp signal according to a first voltage and a second voltage, and provides the first ramp signal to the ramp signal clamping circuit via a first node. The first reset circuit resets the first node to a second voltage under the control of an enable signal of the DC-DC converter. The ramp signal clamping circuit clamps the first ramp signal to the bandgap reference voltage according to the first voltage, the second voltage, and a bandgap reference voltage from a bandgap reference voltage terminal to generate a second ramp signal, and provides the second ramp signal to the output circuit via a second node. The second reset circuit resets the second node to a second voltage under the control of an enable signal. The output circuit generates a soft start signal according to the second ramp signal and the second voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a soft start circuit for a direct current to direct current (DC-DC) converter. Background Art

[0002] With the rapid development of portable electronic products, DC-DC converters have gradually occupied an increasing market share with their many superior performances (such as high efficiency, low quiescent current, small chip area, etc.). However, there is a problem with typical DC-DC converters: a large surge current will be generated during its startup phase, making the DC-DC converter unable to work properly. In severe cases, the power switch tube in the DC-DC converter will burn out, causing losses. In order to solve this problem, a "soft start" circuit can be added to the DC-DC converter to eliminate the surge current when it is powered on. Summary of the invention

[0003] Embodiments described herein provide a soft start circuit for a DC-DC converter.

[0004] According to a first aspect of the present disclosure, a soft start circuit for a DC-DC converter is provided. The soft start circuit includes: a ramp signal generating circuit, a first reset circuit, a ramp signal clamping circuit, a second reset circuit, and an output circuit. The ramp signal generating circuit is configured to generate a first ramp signal according to a first voltage from a first voltage terminal and a second voltage from a second voltage terminal, and provide the first ramp signal to the ramp signal clamping circuit via a first node. The first reset circuit is configured to reset the first node to a second voltage under the control of an enable signal of the DC-DC converter. The ramp signal clamping circuit is configured to clamp the first ramp signal to the bandgap reference voltage according to the first voltage, the second voltage, and the bandgap reference voltage from the bandgap reference voltage terminal to generate a second ramp signal, and provide the second ramp signal to the output circuit via a second node. The second reset circuit is configured to reset the second node to a second voltage under the control of an enable signal. The output circuit is configured to generate a soft start signal according to the second ramp signal and the second voltage.

[0005] In some embodiments of the present disclosure, the ramp signal generating circuit includes: a first current source and a first capacitor. The first current source is coupled to the first voltage terminal and the first terminal of the first capacitor, and is configured to generate a first constant current according to the first voltage, and provide the first constant current to the first terminal of the first capacitor. The first terminal of the first capacitor is coupled to the first node. The second terminal of the first capacitor is coupled to the second voltage terminal.

[0006] In some embodiments of the present disclosure, the first reset circuit includes: a first transistor, wherein a control electrode of the first transistor is provided with an inverted signal of an enable signal, a first electrode of the first transistor is coupled to a second voltage terminal, and a second electrode of the first transistor is coupled to a first node.

[0007] In some embodiments of the present disclosure, the ramp signal clamp circuit includes: a second current source, a third current source, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The second current source is coupled to the first voltage terminal, the first electrode of the fourth transistor, and the second electrode of the third transistor, and is configured to generate a second constant current according to the first voltage. The third current source is coupled to the second voltage terminal and the second electrode of the fourth transistor, and is configured to generate a third constant current. The control electrode of the second transistor is coupled to the first node. The first electrode of the second transistor is coupled to the first electrode of the third transistor. The second electrode of the second transistor is coupled to the second voltage terminal. The control electrode of the third transistor is coupled to the first electrode of the fourth transistor and the second electrode of the third transistor. The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor and the control electrode of the fifth transistor. The first electrode of the fifth transistor is coupled to the second node. The second electrode of the fifth transistor is coupled to the bandgap reference voltage terminal.

[0008] In some embodiments of the present disclosure, the second constant current is greater than the third constant current.

[0009] In some embodiments of the present disclosure, the second reset circuit includes: a sixth transistor, a seventh transistor, and an eighth transistor. The control electrode of the sixth transistor is provided with an inverted signal of an enable signal. The first electrode of the sixth transistor is coupled to the second voltage terminal. The second electrode of the sixth transistor is coupled to the first electrode of the fourth transistor. The control electrode of the seventh transistor is provided with an inverted signal of an enable signal. The first electrode of the seventh transistor is coupled to the second voltage terminal. The second electrode of the seventh transistor is coupled to the second electrode of the fourth transistor. The control electrode of the eighth transistor is provided with an inverted signal of an enable signal. The first electrode of the eighth transistor is coupled to the second voltage terminal. The second electrode of the eighth transistor is coupled to the second node.

[0010] In some embodiments of the present disclosure, the output circuit includes: a first resistor, a second resistor, and a second capacitor. The first end of the first resistor is coupled to the second node. The second end of the first resistor is coupled to the first end of the second resistor and the output voltage terminal. The second end of the second resistor is coupled to the second voltage terminal. The first end of the second capacitor is coupled to the output voltage terminal. The second end of the second capacitor is coupled to the second voltage terminal.

[0011] In some embodiments of the present disclosure, the soft start circuit further includes: a start time control circuit, wherein the start time control circuit is configured to generate a start time control signal according to the first voltage and the second voltage, and provide the start time control signal to the ramp signal clamp circuit.

[0012] In some embodiments of the present disclosure, the start-up time control circuit includes: a fourth current source, a ninth transistor, a tenth transistor, and a third capacitor. The fourth current source is coupled to the first voltage terminal and the first end of the third capacitor, and is configured to generate a fourth constant current according to the first voltage, and provide the fourth constant current to the first end of the third capacitor. The control electrode of the ninth transistor is provided with an inverted signal of the enable signal. The first electrode of the ninth transistor is coupled to the second voltage terminal. The second electrode of the ninth transistor is coupled to the first end of the third capacitor and the control electrode of the tenth transistor. The first electrode of the tenth transistor is coupled to the first electrode of the second transistor. The second electrode of the tenth transistor is coupled to the second voltage terminal. The second end of the third capacitor is coupled to the second voltage terminal.

[0013] In some embodiments of the present disclosure, the third capacitor is arranged outside the package of the DC-DC converter.

[0014] According to a second aspect of the present disclosure, a soft start circuit for a DC-DC converter is provided. The soft start circuit includes: a first transistor to an eighth transistor, a first current source, a second current source, a third current source, a first resistor, a second resistor, a first capacitor, and a second capacitor. The first current source is coupled to a first voltage terminal and a first terminal of the first capacitor, and is configured to generate a first constant current according to a first voltage, and provide the first constant current to the first terminal of the first capacitor. The first terminal of the first capacitor is coupled to a control electrode of the second transistor. The second terminal of the first capacitor is coupled to a second voltage terminal. The control electrode of the first transistor is provided with an inverted signal of an enable signal of the DC-DC converter. The first electrode of the first transistor is coupled to the second voltage terminal. The second electrode of the first transistor is coupled to the first terminal of the first capacitor. The first electrode of the second transistor is coupled to the first electrode of the third transistor. The second electrode of the second transistor is coupled to the second voltage terminal. The control electrode of the third transistor is coupled to the first electrode of the fourth transistor and the second electrode of the third transistor. The second current source is coupled to the first voltage terminal, the first electrode of the fourth transistor, and the second electrode of the third transistor, and is configured to generate a second constant current according to the first voltage. The third current source is coupled to the second voltage terminal and the second electrode of the fourth transistor, and is configured to generate a third constant current. The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor and the control electrode of the fifth transistor. The first electrode of the fifth transistor is coupled to the first end of the first resistor. The second electrode of the fifth transistor is coupled to the bandgap reference voltage terminal. The second end of the first resistor is coupled to the first end of the second resistor and the output voltage terminal. The second end of the second resistor is coupled to the second voltage terminal. The first end of the second capacitor is coupled to the output voltage terminal. The second end of the second capacitor is coupled to the second voltage terminal. The control electrode of the sixth transistor is provided with an inverted signal of the enable signal. The first electrode of the sixth transistor is coupled to the second voltage terminal. The second electrode of the sixth transistor is coupled to the first electrode of the fourth transistor. The control electrode of the seventh transistor is provided with an inverted signal of the enable signal. The first electrode of the seventh transistor is coupled to the second voltage terminal. The second electrode of the seventh transistor is coupled to the second electrode of the fourth transistor. The control electrode of the eighth transistor is provided with an inverted signal of the enable signal. The first electrode of the eighth transistor is coupled to the second voltage terminal. The second electrode of the eighth transistor is coupled to the first end of the first resistor.

[0015] In some embodiments of the present disclosure, the soft start circuit further includes: a fourth current source, a ninth transistor, a tenth transistor, and a third capacitor. The fourth current source is coupled to the first voltage terminal and the first end of the third capacitor, and is configured to generate a fourth constant current according to the first voltage, and provide the fourth constant current to the first end of the third capacitor. The control electrode of the ninth transistor is provided with an inverted signal of the enable signal. The first electrode of the ninth transistor is coupled to the second voltage terminal. The second electrode of the ninth transistor is coupled to the first end of the third capacitor and the control electrode of the tenth transistor. The first electrode of the tenth transistor is coupled to the first electrode of the second transistor. The second electrode of the tenth transistor is coupled to the second voltage terminal. The second end of the third capacitor is coupled to the second voltage terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0017] Figure 1 is an exemplary circuit diagram of a soft start circuit for a DC-DC converter;

[0018] Figure 2 is an exemplary block diagram of a soft start circuit for a DC-DC converter according to an embodiment of the present disclosure;

[0019] Figure 3 yes Figure 2 An exemplary circuit diagram of a soft start circuit for a DC-DC converter is shown;

[0020] Figure 4 is another exemplary block diagram of a soft start circuit for a DC-DC converter according to an embodiment of the present disclosure; and

[0021] Figure 5 yes Figure 4 An exemplary circuit diagram of a soft start circuit for a DC-DC converter is shown.

[0022] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the transistor is called the control electrode, and the remaining two ends of the transistor are respectively called the first electrode and the second electrode. The transistors used in the embodiments of the present disclosure are mainly metal oxide semiconductors (Metal Oxide Semiconductor, MOS for short). In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Figure 1 A soft start circuit 100 for a DC-DC converter is shown. Figure 1 In the example of FIG. 1 , in the soft start circuit 100, the upper plate of the capacitor CSS is charged by the constant current source ISS, and the lower plate of the capacitor CSS is grounded. During the charging process, the voltage VSS on the upper plate of the capacitor CSS starts to rise from 0V. When the voltage VSS on the upper plate of the capacitor CSS rises to equal to the preset reference voltage, the soft start process ends.

[0027] According to the capacitor charging formula:

[0028] CSS×VSS=ISS×△T (1)

[0029] We can get:

[0030] VSS=(ISS / CSS)×△T (2)

[0031] Among them, CSS represents the capacitance value of the capacitor CSS, VSS represents the voltage value on the upper plate of the capacitor CSS, ISS represents the current value of the constant current ISS provided by the constant current source ISS, and △T represents the soft start time.

[0032] According to formula (2), the voltage VSS on the upper plate of the capacitor CSS rises at a slope of (ISS / CSS), generating a ramp signal VSS with a slope of (ISS / CSS). The time △T required for the voltage VSS on the upper plate of the capacitor CSS to rise from 0V to the preset reference voltage is the soft start time. The soft start time can be changed by changing the size of the constant current ISS provided by the capacitor CSS and the constant current source ISS.

[0033] In a DC-DC converter, a soft start circuit may be coupled to an error amplifier. The voltage VSS (also referred to as a ramp signal VSS in the context) on the upper plate of the capacitor CSS and a preset reference voltage may be provided to the control electrodes of two transistors serving as the non-inverting input terminals of the error amplifier, respectively. The output voltage of the DC-DC converter is provided to the inverting input terminal of the error amplifier as a feedback voltage after voltage division. During the soft start process, the feedback voltage gradually rises from 0V. If the non-inverting input terminal of the error amplifier is only provided with a preset reference voltage but not with a ramp signal VSS, when the DC-DC converter is enabled, the output voltage of the error amplifier will continue to be a high level (the duty cycle of the output voltage is 100%) due to the large difference between the preset reference voltage and the feedback voltage. This will cause the output signal of the DC-DC converter to generate a large surge current. Therefore, two non-inverting input terminals are provided in the error amplifier, which are provided with a ramp signal VSS and a preset reference voltage, respectively.

[0034] When the ramp signal VSS is much smaller than the preset reference voltage, the ramp signal VSS plays a leading role. At the beginning of the soft start process, the feedback voltage is close to the ramp signal VSS, and the duty cycle of the output voltage of the error amplifier gradually increases, which can eliminate the surge current when the DC-DC converter is enabled. When the ramp signal VSS is much larger than the preset reference voltage, the preset reference voltage plays a leading role. However, when the ramp signal VSS is close to the preset reference voltage, the two transistors at the in-phase input of the error amplifier are connected in parallel, and the equivalent width-to-length ratio of the transistor at the in-phase input is twice the width-to-length ratio of the transistor at the inverting input. In this way, the differential input of the error amplifier is not matched, so the output voltage of the error amplifier will increase, resulting in a higher overshoot of the output voltage at the end of the soft start.

[0035] In practical applications, it is expected that the soft start circuit in the DC-DC converter has a more stable output to avoid voltage overshoot.

[0036] The embodiment of the present disclosure provides a soft start circuit 200 for a DC-DC converter. Figure 2 FIG. 2 shows an exemplary block diagram of a soft start circuit 200 for a DC-DC converter according to an embodiment of the present disclosure. Figure 2 As shown, the soft start circuit 200 includes: a ramp signal generating circuit 210 , a first reset circuit 220 , a ramp signal clamping circuit 230 , a second reset circuit 240 , and an output circuit 250 .

[0037] The ramp signal generating circuit 210 may be coupled to the first voltage terminal V1, the second voltage terminal V2, the first reset circuit 220, and the ramp signal clamping circuit 230. The ramp signal generating circuit 210 may be configured to generate a first ramp signal according to a first voltage V1 from the first voltage terminal V1 and a second voltage V2 from the second voltage terminal V2, and provide the first ramp signal to the ramp signal clamping circuit 230 via the first node N1.

[0038] The first reset circuit 220 may be coupled to the enable signal terminal EN of the DC-DC converter, the second voltage terminal V2, the ramp signal generating circuit 210, and the ramp signal clamping circuit 230. The first reset circuit 220 may be configured to reset the first node N1 to the second voltage V2 under the control of the enable signal EN of the DC-DC converter. In some embodiments of the present disclosure, before the DC-DC converter is enabled, the first reset circuit 220 resets the first node N1 to the second voltage V2.

[0039] The ramp signal clamp circuit 230 may be coupled to the ramp signal generating circuit 210, the first reset circuit 220, the second reset circuit 240, the output circuit 250, the first voltage terminal V1, the second voltage terminal V2, and the bandgap reference voltage terminal VBG. The ramp signal clamp circuit 230 may be configured to clamp the first ramp signal to the bandgap reference voltage VBG according to the first voltage V1, the second voltage V2, and the bandgap reference voltage VBG from the bandgap reference voltage terminal VBG to generate a second ramp signal, and provide the second ramp signal to the output circuit 250 via the second node N2. In some embodiments of the present disclosure, when the second ramp signal increases to the bandgap reference voltage VBG, the voltage of the second ramp signal remains unchanged, that is, it is clamped to the bandgap reference voltage VBG.

[0040] The second reset circuit 240 may be coupled to the enable signal terminal EN of the DC-DC converter, the second voltage terminal V2, the ramp signal clamp circuit 230, and the output circuit 250. The second reset circuit 240 may be configured to reset the second node N2 to the second voltage V2 under the control of the enable signal EN. In some embodiments of the present disclosure, before the DC-DC converter is enabled, the second reset circuit 240 resets the second node N2 to the second voltage V2.

[0041] The output circuit 250 may be coupled to the ramp signal clamp circuit 230, the second reset circuit 240, the second voltage terminal V2, and the output voltage terminal VREF. The output circuit 250 may be configured to generate a soft start signal VREF according to the second ramp signal and the second voltage V2. In some embodiments of the present disclosure, the output circuit 250 may divide the second ramp signal from the ramp signal clamp circuit 230, and then filter the divided signal to generate a soft start signal VREF.

[0042] The soft start signal output by the soft start circuit 200 for a DC-DC converter according to an embodiment of the present disclosure gradually increases from 0V to a voltage value of a preset reference voltage after the DC-DC converter is enabled, and is provided to the non-inverting input terminal of the error amplifier. Figure 1 Unlike the error amplifier coupled to the soft start circuit 100 shown, the soft start circuit 200 according to the embodiment of the present disclosure has only one non-inverting input terminal of the error amplifier coupled. The output voltage of the DC-DC converter is provided to the inverting input terminal of the error amplifier as a feedback voltage after voltage division. During the soft start process, the feedback voltage gradually rises from 0V. The feedback voltage is close to the voltage of the soft start signal, and the duty cycle of the output voltage of the error amplifier gradually increases, which can avoid surge current when the DC-DC converter is enabled. In addition, the differential input terminals of the error amplifier are always matched, so that the output voltage of the DC-DC converter can be prevented from overshooting at the end of the soft start.

[0043] Figure 3 Shows Figure 2 FIG. 2 is an exemplary circuit diagram of a soft start circuit 200 for a DC-DC converter. Figure 3As shown, the ramp signal generating circuit 210 may include: a first current source IS1, and a first capacitor C1. The first current source IS1 is coupled to the first voltage terminal V1 and the first end of the first capacitor C1, and is configured to generate a first constant current IS1 according to the first voltage V1, and provide the first constant current IS1 to the first end of the first capacitor C1. The first end of the first capacitor C1 is coupled to the first node N1. The second end of the first capacitor C1 is coupled to the second voltage terminal V2. In some embodiments of the present disclosure, the first current source IS1 may include a first bias transistor (not shown in the figure). The control electrode of the first bias transistor may be provided with a first bias voltage. The first electrode of the first bias transistor is coupled to the first voltage terminal V1. The second electrode of the first bias transistor is coupled to the first end of the first capacitor C1. Under the control of the first bias voltage and the first voltage V1, the first bias transistor may generate a first constant current IS1. The magnitude of the first constant current IS1 may be adjusted by adjusting the magnitude of the first bias voltage.

[0044] The first reset circuit 220 may include: a first transistor M1. A control electrode of the first transistor M1 is provided with an inverted signal ENN of an enable signal. A first electrode of the first transistor M1 is coupled to the second voltage terminal V2. A second electrode of the first transistor M1 is coupled to the first node N1.

[0045] The ramp signal clamp circuit 230 may include: a second current source IS2, a third current source IS3, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The second current source IS2 is coupled to the first voltage terminal V1, the first electrode of the fourth transistor M4, and the second electrode of the third transistor M3, and is configured to generate a second constant current IS2 according to the first voltage V1. The third current source IS3 is coupled to the second voltage terminal V2 and the second electrode of the fourth transistor M4, and is configured to generate a third constant current IS3. The control electrode of the second transistor M2 is coupled to the first node N1. The first electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3. The second electrode of the second transistor M2 is coupled to the second voltage terminal V2. The control electrode of the third transistor M3 is coupled to the first electrode of the fourth transistor M4 and the second electrode of the third transistor M3. The control electrode of the fourth transistor M4 is coupled to the second electrode of the fourth transistor M4 and the control electrode of the fifth transistor M5. The first electrode of the fifth transistor M5 is coupled to the second node N2. The second electrode of the fifth transistor M5 is coupled to the bandgap reference voltage terminal VBG.

[0046] In some embodiments of the present disclosure, the second current source IS2 may include a second bias transistor (not shown in the figure). The control electrode of the second bias transistor may be provided with a second bias voltage. The first electrode of the second bias transistor is coupled to the first voltage terminal V1. The second electrode of the second bias transistor is coupled to the first electrode of the fourth transistor M4 and the second electrode of the third transistor M3. Under the control of the second bias voltage and the first voltage V1, the second bias transistor may generate a second constant current IS2. The magnitude of the second constant current IS2 may be adjusted by adjusting the magnitude of the second bias voltage.

[0047] In some embodiments of the present disclosure, the third current source IS3 may include a first mirror transistor (not shown in the figure). The control electrode of the first mirror transistor may be coupled to the control electrode of the external mirror transistor, and together with the external mirror transistor, form a current mirror circuit. The first electrode of the first mirror transistor is coupled to the second voltage terminal V2. The second electrode of the first mirror transistor is coupled to the second electrode of the fourth transistor M4. The gate-source current of the first mirror transistor (the third constant current IS3) may be a mirror current of the constant current generated by the external mirror transistor. The magnitude of the third constant current IS3 may be adjusted by adjusting the constant current generated by the external mirror transistor.

[0048] The second reset circuit 240 may include: a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The control electrode of the sixth transistor M6 is provided with an inverted signal ENN of an enable signal. The first electrode of the sixth transistor M6 is coupled to the second voltage terminal V2. The second electrode of the sixth transistor M6 is coupled to the first electrode of the fourth transistor M4. The control electrode of the seventh transistor M7 is provided with an inverted signal ENN of an enable signal. The first electrode of the seventh transistor M7 is coupled to the second voltage terminal V2. The second electrode of the seventh transistor M7 is coupled to the second electrode of the fourth transistor M4. The control electrode of the eighth transistor M8 is provided with an inverted signal ENN of an enable signal. The first electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. The second electrode of the eighth transistor M8 is coupled to the second node N2.

[0049] The output circuit 250 may include: a first resistor R1, a second resistor R2, and a second capacitor C2. The first end of the first resistor R1 is coupled to the second node N2. The second end of the first resistor R1 is coupled to the first end of the second resistor R2 and the output voltage terminal VREF. The second end of the second resistor R2 is coupled to the second voltage terminal V2. The first end of the second capacitor C2 is coupled to the output voltage terminal VREF. The second end of the second capacitor C2 is coupled to the second voltage terminal V2.

[0050] In an embodiment of the present disclosure, the second constant current IS2 is greater than the third constant current IS3 , so that after the DC-DC converter is enabled, the fourth transistor M4 may remain turned on.

[0051] exist Figure 3 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are N-type transistors. The second transistor M2 and the fourth transistor M4 are P-type transistors. The enable signal terminal EN of the DC-DC converter can be coupled to the input terminal of the inverter, and the output terminal of the inverter can output the inverted signal ENN of the enable signal. In order to avoid obscuring the subject matter of the present disclosure with unimportant details, Figure 3 The above-mentioned inverter is not shown in the example.

[0052] Those skilled in the art should understand that based on the above-mentioned inventive concept Figure 3 The variation of the circuit shown should also fall within the protection scope of the present disclosure. In this variation, the first transistor M1, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be P-type transistors, and the control electrodes of the first transistor M1, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be coupled to the enable signal terminal EN of the DC-DC converter to achieve the reset function of the first node N1 and the second node N2.

[0053] Combine the following Figure 3To illustrate the working process of the soft start circuit 200 for the DC-DC converter. Before the DC-DC converter is enabled, the inverted signal ENN of the enable signal is high, the first transistor M1, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned on, and the voltages of the source and drain of the first node N1, the second node N2, and the fourth transistor M4 are all pulled down to 0V. After the DC-DC converter is enabled, the inverted signal ENN of the enable signal is low, and the first transistor M1, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off. The first current source IS1 charges the first capacitor C1, and the voltage of the first node N1 gradually increases, generating a first ramp signal. As the voltage of the first node N1 gradually increases, the source voltage of the second transistor M2 and the drain voltage of the third transistor M3 also gradually increase. The second constant current IS2 generated by the second current source IS2 is greater than the third constant current IS3 generated by the third current source IS3. Under the action of the second constant current IS2 and the third constant current IS3, the fourth transistor M4 is turned on. As the voltage of the first node N1 gradually increases, the gate voltage of the fifth transistor M5 will also gradually increase. When the voltage of the first node N1 increases to the first voltage V1, the process of charging the first capacitor C1 stops. At this time, the gate voltage of the fifth transistor M5 is ultimately equal to V1-VTH4, where VTH4 represents the threshold voltage of the fourth transistor M4. The size of the fifth transistor M5 can be designed to be large enough so that the source voltage of the fifth transistor M5 is equal to the drain voltage, so that the voltage of the second node N2 is clamped to the bandgap reference voltage VBG.

[0054] In the process of charging the first capacitor C1, the voltage of the second node N2 increases from 0V to the bandgap reference voltage VBG, thereby generating a second ramp signal. The signal obtained by dividing the second ramp signal by the first resistor R1 and the second resistor R2 is filtered by the second capacitor C2 to obtain a soft start signal VREF. The soft start signal VREF can be calculated by the following formula:

[0055] VREF=VN2×R2 / (R1+R2) (3)

[0056] Wherein, VREF represents the voltage value of the soft start signal VREF, VN2 represents the voltage value of the second node N2, R1 represents the resistance value of the first resistor R1, and R2 represents the resistance value of the second resistor R2.

[0057] Since the voltage VN2 of the second node N2 is ultimately equal to the bandgap reference voltage VBG, it can be obtained that:

[0058] VREF=VBG×R2 / (R1+R2) (4)

[0059] Here, VBG represents the voltage value of the bandgap reference voltage.

[0060] By adjusting one or more of the resistance value of the first resistor R1, the resistance value of the second resistor R2, and the voltage value of the bandgap reference voltage VBG, the voltage value of the soft start signal VREF can be changed. In some embodiments of the present disclosure, the voltage value of the soft start signal VREF can be ultimately equal to the voltage value of the preset reference voltage.

[0061] After the first capacitor C1 is charged, the voltage of the second node N2 is substantially equal to the voltage of the first node N1:

[0062] VN2=VN1+VTH2+VTH3-VTH4-VTH5≈VN1 (5)

[0063] Among them, VN1 represents the voltage value of the first node N1, VN2 represents the voltage value of the second node N2, VTH2 represents the threshold voltage of the second transistor M2, VTH3 represents the threshold voltage of the third transistor M3, VTH4 represents the threshold voltage of the fourth transistor M4, and VTH5 represents the threshold voltage of the fifth transistor M5.

[0064] According to the capacitor charging formula:

[0065] C1×VN1=IS1×△T (6)

[0066] Wherein, C1 represents the capacitance value of the first capacitor C1, VN1 represents the voltage value of the first node N1, IS1 represents the current value of the first constant current IS1, and ΔT represents the soft start time.

[0067] Since the voltage VN2 of the second node N2 is ultimately equal to the bandgap reference voltage VBG, it can be obtained that:

[0068] C1×VBG=IS1×△T (7)

[0069] According to equation (7), the soft start time ΔT can be changed by adjusting one or more of the capacitance value of the first capacitor C1, the current value of the first constant current IS1, and the voltage value of the bandgap reference voltage VBG.

[0070] Refer to formula (7) and formula (1) for comparison Figure 3 The soft start circuit 200 shown is Figure 1As shown in the soft start circuit 100, it can be seen that when the power consumption (current for charging the capacitor) and the soft start time of the soft start circuit are the same, because VBG is greater than the value of VSS at the end of the soft start process (equivalent to VREF in formula (4)), the capacitance value of the first capacitor C1 in the soft start circuit 200 can be equal to VREF / VBG of the capacitance value of the capacitor CSS in the soft start circuit 100. Therefore, the area of ​​the first capacitor C1 can be smaller than the area of ​​the capacitor CSS, thereby saving the area of ​​the DC-DC converter.

[0071] In some embodiments of the present disclosure, considering that the P-type transistor and the N-type transistor have large deviations under different process angles, the third transistor M3 and the fourth transistor M4 are set in the soft start circuit 200 to offset the difference in threshold voltages of different types of transistors. If there is no third transistor M3 and fourth transistor M4, even if the initial voltage of the first node N1 is 0V before the DC-DC converter is enabled, due to the large difference in threshold voltages between the P-type transistor and the N-type transistor, when the DC-DC converter is enabled, the initial voltage of the second node N2 is higher than 0V, so the soft start signal VREF will have a higher initial value. The initial voltage value of the feedback signal of the error amplifier is 0V, and the output voltage of the error amplifier will have a higher initial value. The output voltage of the error amplifier does not rise slowly from 0V, which may cause the DC-DC converter to be unable to achieve soft start.

[0072] Therefore, an N-type third transistor M3 and a P-type fourth transistor M4 are provided in the soft start circuit 200 to offset the difference in threshold voltage between the N-type fifth transistor M5 and the P-type second transistor M2. It can be seen from formula (5) that the threshold voltage VTH2 of the second transistor M2 can be offset by the threshold voltage VTH4 of the fourth transistor M4, and the threshold voltage VTH3 of the third transistor M3 can be offset by the threshold voltage VTH5 of the fifth transistor M5. In this way, when the initial voltage of the first node N1 is 0V, the initial voltage of the second node N2 is also 0V, so that the output voltage of the error amplifier slowly rises from 0V, and the DC-DC converter achieves soft start.

[0073] Figure 4 FIG. 4 is another exemplary block diagram of a soft start circuit 400 for a DC-DC converter according to an embodiment of the present disclosure. Figure 4 In the example of FIG. 1 , the soft start circuit 400 according to the embodiment of the present disclosure is Figure 2A startup time control circuit 460 is added on the basis of the soft start circuit 400. The startup time control circuit 460 can be coupled to the enable signal terminal EN of the DC-DC converter, the first voltage terminal V1, the second voltage terminal V2, and the ramp signal clamp circuit 230. Among them, the startup time control circuit 460 can be configured to generate a startup time control signal according to the first voltage V1 and the second voltage V2, and provide the startup time control signal to the ramp signal clamp circuit 230. The ramp signal clamp circuit 230 can control the slope of the second ramp signal according to the slope of the first ramp signal and the slope of the startup time control signal, thereby controlling the soft start time of the soft start circuit 400.

[0074] Figure 5 Show Figure 4 FIG. 4 is an exemplary circuit diagram of a soft start circuit 400. Figure 5 In the example of FIG. 1 , the soft start circuit 400 according to the embodiment of the present disclosure is Figure 3 On the basis of, a start-up time control circuit 460 is added. The start-up time control circuit 460 may include: a fourth current source IS4, a ninth transistor M9, a tenth transistor M10 and a third capacitor C3. Among them, the fourth current source IS4 is coupled to the first voltage terminal V1 and the first end of the third capacitor C3, and is configured to generate a fourth constant current IS4 according to the first voltage V1, and provide the fourth constant current IS4 to the first end of the third capacitor C3. The control electrode of the ninth transistor M9 is provided with an inverted signal ENN of the enable signal. The first electrode of the ninth transistor M9 is coupled to the second voltage terminal V2. The second electrode of the ninth transistor M9 is coupled to the first end of the third capacitor C3 and the control electrode of the tenth transistor M10. The first electrode of the tenth transistor M10 is coupled to the first electrode of the second transistor M2. The second electrode of the tenth transistor M10 is coupled to the second voltage terminal V2. The second end of the third capacitor C3 is coupled to the second voltage terminal V2. In Figure 5 In the example, the first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are N-type transistors, and the second transistor M2, the fourth transistor M4, and the tenth transistor M10 are P-type transistors.

[0075] In some embodiments of the present disclosure, the third capacitor C3 may be arranged outside the package of the DC-DC converter (i.e., the chip package). The control electrode of the tenth transistor M10 may be coupled to the PIN pin PINSS of the package of the DC-DC converter. The first end of the third capacitor C3 is coupled to the PIN pin PINSS of the DC-DC converter to be coupled to the control electrode of the tenth transistor M10 via the PIN pin PINSS. In this way, the fourth current source IS4 can charge the third capacitor C3 arranged outside the package of the DC-DC converter.

[0076] The tenth transistor M10 and the second transistor M2 are both P-type transistors, and the source of the tenth transistor M10 and the source of the second transistor M2 are coupled to the source of the third transistor M3. When the upper plate voltage of the first capacitor C1 is less than the upper plate voltage of the third capacitor C3, the source voltage of the second transistor M2 is less than the source voltage of the tenth transistor M10, and the source voltage of the third transistor M3 follows the source voltage of the second transistor M2, so that the voltage of the second node N2 is equal to the upper plate voltage of the first capacitor C1. When the upper plate voltage of the first capacitor C1 is greater than the upper plate voltage of the third capacitor C3, the source voltage of the second transistor M2 is greater than the source voltage of the tenth transistor M10, and the source voltage of the third transistor M3 follows the source voltage of the tenth transistor M10, so that the voltage of the second node N2 is equal to the upper plate voltage of the third capacitor C3. It can be seen that the voltage of the second node N2 changes by following the voltage of the upper plate of the capacitor with a slower charging speed among the first capacitor C1 and the third capacitor C3. In this way, the soft-start time is determined by the capacitor which charges more slowly.

[0077] When the third capacitor C3 is not coupled to the PIN pin PINSS of the package of the DC-DC converter, the soft start time of the DC-DC converter is determined by the speed at which the first current source IS1 inside the DC-DC converter charges the first capacitor C1. In this way, the soft start circuit according to the embodiment of the present disclosure can achieve an adjustable soft start time both inside and outside the package of the DC-DC converter.

[0078] In summary, the soft start signal output by the soft start circuit for the DC-DC converter according to the embodiment of the present disclosure gradually increases from 0V to the voltage value of the preset reference voltage after the DC-DC converter is enabled, and is provided to the non-inverting input terminal of the error amplifier. The output voltage of the DC-DC converter is provided to the inverting input terminal of the error amplifier as a feedback voltage after being divided. During the soft start process, the feedback voltage gradually rises from 0V. The feedback voltage is close to the voltage of the soft start signal, and the duty cycle of the output voltage of the error amplifier gradually increases, which can avoid the surge current when the DC-DC converter is enabled. In addition, the differential input terminal of the error amplifier is always matched, so the phenomenon of voltage overshoot at the end of the soft start can be avoided. In addition, the soft start circuit can change the soft start time by adjusting the first current source, the first capacitor, the fourth current source, and the third capacitor arranged outside the package of the DC-DC converter, thereby realizing an adjustable soft start time inside and outside the package of the DC-DC converter.

[0079] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device and method according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0080] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0081] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0082] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A soft start circuit for a DC-DC converter, comprising: a ramp signal generating circuit, a first reset circuit, a ramp signal clamping circuit, a second reset circuit, and an output circuit, The ramp signal generating circuit is configured to generate a first ramp signal according to a first voltage from a first voltage terminal and a second voltage from a second voltage terminal, and provide the first ramp signal to the ramp signal clamping circuit via a first node; The first reset circuit is configured to reset the first node to the second voltage under the control of an enable signal of the DC-DC converter; The ramp signal clamping circuit is configured to clamp the first ramp signal to the bandgap reference voltage according to the first voltage, the second voltage and the bandgap reference voltage from the bandgap reference voltage terminal to generate a second ramp signal, and provide the second ramp signal to the output circuit via a second node; The second reset circuit is configured to reset the second node to the second voltage under the control of the enable signal; The output circuit is configured to generate a soft start signal according to the second ramp signal and the second voltage.

2. The soft start circuit according to claim 1, wherein: The ramp signal generating circuit comprises: a first current source and a first capacitor, The first current source is coupled to the first voltage terminal and the first terminal of the first capacitor, and is configured to generate a first constant current according to the first voltage, and provide the first constant current to the first terminal of the first capacitor; A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to the second voltage terminal.

3. The soft start circuit according to claim 1, wherein: The first reset circuit comprises: a first transistor, The control electrode of the first transistor is provided with an inverted signal of the enable signal, the first electrode of the first transistor is coupled to the second voltage terminal, and the second electrode of the first transistor is coupled to the first node.

4. The soft start circuit according to claim 1, wherein: The ramp signal clamp circuit includes: a second current source, a third current source, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The second current source is coupled to the first voltage terminal, the first electrode of the fourth transistor and the second electrode of the third transistor, and is configured to generate a second constant current according to the first voltage; The third current source is coupled to the second voltage terminal and the second electrode of the fourth transistor, and is configured to generate a third constant current; The control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first electrode of the third transistor, and the second electrode of the second transistor is coupled to the second voltage terminal; The control electrode of the third transistor is coupled to the first electrode of the fourth transistor and the second electrode of the third transistor; The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor and the control electrode of the fifth transistor; A first electrode of the fifth transistor is coupled to the second node, and a second electrode of the fifth transistor is coupled to the bandgap reference voltage terminal.

5. The soft start circuit according to claim 4, wherein: The second constant current is greater than the third constant current.

6. The soft start circuit according to claim 4 or 5, wherein: The second reset circuit includes: a sixth transistor, a seventh transistor, and an eighth transistor, The control electrode of the sixth transistor is provided with an inverted signal of the enable signal, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the fourth transistor; The control electrode of the seventh transistor is provided with the inverted signal of the enable signal, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the second electrode of the fourth transistor; The control electrode of the eighth transistor is provided with the inverted signal of the enable signal, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the second node.

7. The soft start circuit according to claim 4 or 5, further comprising: Start time control circuit, The startup time control circuit is configured to generate a startup time control signal according to the first voltage and the second voltage, and provide the startup time control signal to the ramp signal clamping circuit.

8. The soft start circuit according to claim 7, wherein: The startup time control circuit includes: a fourth current source, a ninth transistor, a tenth transistor and a third capacitor. The fourth current source is coupled to the first voltage terminal and the first terminal of the third capacitor, and is configured to generate a fourth constant current according to the first voltage, and provide the fourth constant current to the first terminal of the third capacitor; The control electrode of the ninth transistor is provided with an inverted signal of the enable signal, the first electrode of the ninth transistor is coupled to the second voltage terminal, and the second electrode of the ninth transistor is coupled to the first terminal of the third capacitor and the control electrode of the tenth transistor; A first electrode of the tenth transistor is coupled to the first electrode of the second transistor, and a second electrode of the tenth transistor is coupled to the second voltage terminal; The second terminal of the third capacitor is coupled to the second voltage terminal.

9. A soft start circuit for a DC-DC converter, comprising: a first transistor to an eighth transistor, a first current source, a second current source, a third current source, a first resistor, a second resistor, a first capacitor, and a second capacitor, The first current source is coupled to a first voltage terminal and a first terminal of the first capacitor, and is configured to generate a first constant current according to the first voltage, and provide the first constant current to the first terminal of the first capacitor; The first terminal of the first capacitor is coupled to the control electrode of the second transistor, and the second terminal of the first capacitor is coupled to the second voltage terminal; The control electrode of the first transistor is provided with an inverted signal of an enable signal of the DC-DC converter, the first electrode of the first transistor is coupled to the second voltage terminal, and the second electrode of the first transistor is coupled to the first terminal of the first capacitor; The first electrode of the second transistor is coupled to the first electrode of the third transistor, and the second electrode of the second transistor is coupled to the second voltage terminal; The control electrode of the third transistor is coupled to the first electrode of the fourth transistor and the second electrode of the third transistor; The second current source is coupled to the first voltage terminal, the first electrode of the fourth transistor and the second electrode of the third transistor, and is configured to generate a second constant current according to the first voltage; The third current source is coupled to the second voltage terminal and the second electrode of the fourth transistor, and is configured to generate a third constant current; The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor and the control electrode of the fifth transistor; A first electrode of the fifth transistor is coupled to the first end of the first resistor, and a second electrode of the fifth transistor is coupled to a bandgap reference voltage end; The second end of the first resistor is coupled to the first end of the second resistor and the output voltage end; The second end of the second resistor is coupled to the second voltage end; A first terminal of the second capacitor is coupled to the output voltage terminal, and a second terminal of the second capacitor is coupled to the second voltage terminal; The control electrode of the sixth transistor is provided with the inverted signal of the enable signal, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the fourth transistor; The control electrode of the seventh transistor is provided with the inverted signal of the enable signal, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the second electrode of the fourth transistor; A control electrode of the eighth transistor is provided with the inverted signal of the enable signal, a first electrode of the eighth transistor is coupled to the second voltage terminal, and a second electrode of the eighth transistor is coupled to the first terminal of the first resistor.

10. The soft start circuit according to claim 9, further comprising: a fourth current source, a ninth transistor, a tenth transistor and a third capacitor, The fourth current source is coupled to the first voltage terminal and the first terminal of the third capacitor, and is configured to generate a fourth constant current according to the first voltage, and provide the fourth constant current to the first terminal of the third capacitor; The control electrode of the ninth transistor is provided with the inverted signal of the enable signal, the first electrode of the ninth transistor is coupled to the second voltage terminal, and the second electrode of the ninth transistor is coupled to the first terminal of the third capacitor and the control electrode of the tenth transistor; A first electrode of the tenth transistor is coupled to the first electrode of the second transistor, and a second electrode of the tenth transistor is coupled to the second voltage terminal; The second terminal of the third capacitor is coupled to the second voltage terminal.

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