Method, System and Medium for Acquisition of Sequential Instructions of Launch Vehicle

Abstract

The present invention provides a method, system and medium for collecting time-sequence instructions of a launch vehicle, relating to the technical field of aerospace electronic equipment, including: a time-sequence collection module and a field programmable gate array (FPGA); the time-sequence collection module uses optocoupler isolation to collect time-sequence instruction signals and instruction status signals, and inputs all the collected time-sequence instruction signals and instruction status signals into the FPGA; the received time-sequence instruction signals and instruction status signals are subjected to signal shaping, and the FPGA realizes the processing and output of the time-sequence instruction signals and instruction status signals. The present invention can solve the problems of high cost and complex system caused by single-machine collection of time-sequence output in a launch vehicle.

Description

Technical Field

[0001] The present invention relates to the technical field of aerospace electronic equipment, and specifically, to a method, system and medium for retrieving timing instructions for a launch vehicle. Background Art

[0002] During the flight of a launch vehicle, a timing controller uses instructions such as ignition, takeoff, shutdown, and separation as time references, and outputs various control instructions within the specified time according to the requirements of the timing table, thereby completing various specified actions during the flight of the launch vehicle and ensuring the normal flight of the launch vehicle. Since whether these timing instructions are correctly output plays a crucial role in the normal flight of the rocket, if a certain instruction fails to be correctly output, it will directly affect the success or failure of the rocket flight. Therefore, it is necessary to collect the timing instructions output by the timing controller and then compare them with the theoretical values to determine whether the output is correct.

[0003] Currently, the timing instruction acquisition scheme adopted in rockets is to use another single machine to collect the control system time instruction signals in a bit control manner. The timing instruction parameters are collected through optocoupler isolation, and according to the received sub-frame synchronization and word code synchronization signals, the shift register is started to complete the parallel-to-serial conversion, and the collected timing instruction signals are serially output. The specific block diagram is as Figure 1 shown.

[0004] The following defects exist in the above prior art:

[0005] ① A complete product is required to receive, collect and output the timing instructions. A single product needs to go through independent and complete processes such as research, development, production, testing and inspection, resulting in poor economic benefits;

[0006] ② An independent product requires separate external interfaces such as power input and timing instruction signal input, making the system cable network complex;

[0007] ③ If it is necessary to increase the collection of the number of timing instruction channels, various additional chip devices are required, and even the product structure needs to be changed to meet the requirements, which is not convenient. Summary of the Invention

[0008] In view of the defects in the prior art, the present invention provides a method, system and medium for retrieving timing instructions for a launch vehicle.

[0009] According to a method, system and medium for retrieving timing instructions for a launch vehicle provided by the present invention, the solution is as follows:

[0010] In a first aspect, a method for retrieving timing instructions for a launch vehicle is provided. The method includes a timing retrieval module and a field programmable gate array (FPGA).

[0011] Timing acquisition steps: The timing acquisition module uses opto-isolation to collect timing instruction signals and instruction status signals, and inputs all the collected timing instruction signals and instruction status signals into the programmable logic device FPGA;

[0012] Function implementation steps: Signal shaping is performed on the received timing instruction signals and instruction status signals, and the programmable logic device FPGA implements the processing and output of the timing instruction signals and instruction status signals.

[0013] Preferably, the processing of the signals in the function implementation steps includes:

[0014] 1) Acquisition filtering of the timing acquisition signal: Each input timing instruction is filtered by a two-stage latching method to stabilize the data;

[0015] 2) Acquisition filtering of the instruction status signal;

[0016] 3) Time counting: After the single machine is powered on, the programmable logic device FPGA counts time in 1ms as the basic unit. When the status word changes, the timing needs to be cleared and re-counted with a new reference;

[0017] 4) Frame the time, timing, and instruction status in a format;

[0018] 5) Serial output the timing acquisition signal through the 422 serial port.

[0019] Preferably, the acquisition filtering of the timing acquisition signal specifically includes: The first-stage latching method performs three-stage latching and 3us filtering processing to filter out hardware glitches; The second-stage latching method performs five-stage latching and 5ms filtering processing to stabilize the data.

[0020] Preferably, the framing of the time, timing, and instruction status in a format includes: After the new timing instruction is input into the FPGA internally, it is cached at two levels, and the data in the first-level cache register and the second-level cache register are compared;

[0021] When the data in the two-level cache registers is inconsistent, it means that the input timing data has changed. At this time, the instruction data status and the current time value in the first-level cache register are stored in the FIFO through the framing logic for the final serial port data output.

[0022] In the second aspect, a system for timing instruction acquisition of a launch vehicle is provided, and the system includes:

[0023] A timing acquisition module and a programmable logic device FPGA;

[0024] Timing acquisition module: An optocoupler isolation is used to acquire timing instruction signals and instruction status signals, and all the acquired timing instruction signals and instruction status signals are input into a programmable logic device FPGA;

[0025] Function implementation module: Signal shaping is performed on the received timing instruction signals and instruction status signals, and the programmable logic device FPGA is used to implement the processing and output of the timing instruction signals and instruction status signals.

[0026] Preferably, the processing of signals in the function implementation module includes:

[0027] 1) Acquisition filtering of timing acquisition signals: Filtering processing is performed on each input timing instruction in a two-stage latching manner to stabilize the data;

[0028] 2) Acquisition filtering of instruction status signals;

[0029] 3) Time counting: After the single machine is powered on, the programmable logic device FPGA counts in units of 1 ms. When the status word changes, the timing needs to be cleared and re-counted with a new reference;

[0030] 4) Framing the time, timing, and instruction status in a format;

[0031] 5) Serial output of the timing acquisition signals through a 422 serial port.

[0032] Preferably, the acquisition filtering of the timing acquisition signals specifically includes: Three-stage latching in the first-stage latching manner and 3 us filtering processing to filter out hardware glitches; Five-stage latching in the second-stage latching manner and 5 ms filtering processing to stabilize the data.

[0033] Preferably, the framing of the time, timing, and instruction status in a format includes: After a new timing instruction is input into the FPGA, it is cached in two stages, and the data in the first-stage cache register and the second-stage cache register are compared;

[0034] When the data in the two-stage cache registers is inconsistent, it means that the input timing data has changed. At this time, the instruction data status and the current time value in the first-stage cache register are stored in the FIFO through the framing logic for the final serial port data output.

[0035] In a third aspect, a computer-readable storage medium storing a computer program is provided, characterized in that when the computer program is executed by a processor, the steps of the method are implemented.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. Compared with the previous design that used a single stand-alone machine for timing instruction acquisition, the present invention only uses one module, which is integrated inside the timing controller, greatly reducing the design complexity and significantly improving the economic efficiency.

[0038] 2. Compared with the previous design that used various gate circuit logics to build the acquisition circuit, the present invention uses a programmable logic device FPGA to complete this function. On the one hand, it can greatly improve the reliability and real-time performance of the acquisition; on the other hand, when the timing instruction channels increase, the design can be flexibly and conveniently expanded by simply changing the FPGA program.

[0039] 3. Compared with the previous implementation where the two functions of timing output and timing acquisition were realized in two stand-alone machines, the present invention integrates both in one stand-alone machine. In this way, during the stand-alone machine test, the ground test acquisition and the timing feedback output can be compared simultaneously, which is more convenient for testing and judging the timing instruction function of the stand-alone machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features, objectives, and advantages of the present invention will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0041] Figure 1 It is a block diagram of the previous timing acquisition implementation solution;

[0042] Figure 2 It is a block diagram of the composition of the timing feedback module;

[0043] Figure 3 It is a block diagram of optically isolated acquisition of timing instructions;

[0044] Figure 4 It is a logic block diagram of the FIFO input control sub-module;

[0045] Figure 5 It is a block diagram of the interface signals of the serial port information sending module;

[0046] Figure 6 It is a serial port output circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] The present invention will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that those of ordinary skill in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0048] The embodiment of the present invention provides a method for timing instruction feedback of a launch vehicle, referring to Figure 2 and Figure 3As shown in the figure, it includes: a timing acquisition module and a Field Programmable Gate Array (FPGA).

[0049] Timing acquisition steps: The timing acquisition module uses opto - isolation to collect timing instruction signals and instruction status signals, and inputs all the collected timing instruction signals and instruction status signals into the Field Programmable Gate Array (FPGA).

[0050] Function implementation steps: Signal shaping is performed on the received timing instruction signals and instruction status signals, and the Field Programmable Gate Array (FPGA) implements the processing and output of the timing instruction signals and instruction status signals.

[0051] Among them, the processing of signals in the function implementation steps includes:

[0052] 1) Acquisition filtering of timing acquisition signals: Each input timing instruction is filtered by a two - stage latching method to stabilize the data; the first - stage latching method performs three - stage latching with 3 - us filtering to filter out hardware glitches; the second - stage latching method performs five - stage latching with 5 - ms filtering to make the data stable.

[0053] 2) Acquisition filtering of instruction status signals, and the acquisition filtering method of instruction status signals is the same as that of timing instruction processing.

[0054] 3) Time counting: After the single - machine powers on, the Field Programmable Gate Array (FPGA) counts time in units of 1 ms. When the status word changes, the timing needs to be cleared and re - counted with a new reference.

[0055] 4) Frame the time, timing, and instruction status in a format.

[0056] 5) Serial output of the timing acquisition signals through the 422 serial port: After the new timing instruction is input into the FPGA, it is cached at two levels, and the data in the first - level cache register and the second - level cache register are compared.

[0057] When the data in the two - level cache registers is inconsistent, it means that the input timing data has changed. At this time, the instruction data status and the current time value in the first - level cache register are stored in the FIFO through the framing logic for the final serial port data output.

[0058] Next, a more specific description of the present invention will be given.

[0059] A method for timing instruction acquisition of a launch vehicle provided by an embodiment of the present invention, referring to Figure 2As shown, through the timing feedback module in the timing controller, the instruction output of the timing controller is feedback to itself. The timing feedback module uses optocoupler isolation to collect the timing instruction signal, and at the same time uses optocoupler isolation to collect the instruction status signals (ignition, takeoff, separation, shutdown, etc.), and inputs all the collected signals into the FPGA. The timing feedback module in this embodiment consists of an optocoupler isolation collection circuit, a NOT gate trigger shaping circuit, an LDO power supply circuit, a reset circuit, a programmable logic device FPGA, a PROM, and a crystal oscillator.

[0060] First, as shown in Figure 3 Optocoupler isolation is used to receive the instruction status signal and the timing instruction signal. Under normal conditions, since the output terminal resistor of the optocoupler is pulled up, the output is high, and the output of the subsequent NOT gate shaping circuit is low; when the timing status or the instruction status output is high, the optocoupler conducts and the output is low, and the output of the subsequent NOT gate shaping circuit is high; to ensure that the signals received by the subsequent FPGA are stable and correct, a NOT gate trigger device is used to shape the signals output by the optocoupler.

[0061] Secondly, the following functions are implemented using the FPGA:

[0062] (1) Acquisition and filtering of the timing feedback signal;

[0063] Each input timing instruction is filtered by a two-stage latching method to stabilize the data. The first-stage latching method performs three-stage latching and 3us filtering to filter out hardware glitches; the second-stage latching method performs five-stage latching and 5ms filtering to stabilize the data. The instruction input signal is latched three times by clk. Only when the signals latched continuously three times are all 111 or 000, the output register is updated. Input sequences such as 001, 010, 011, 100, 101, 110, etc. will all be filtered out. The 5ms debounce of the instruction input signal is performed. The method is that only when the signals that have been filtered by us and latched continuously five times by the ms signal are all 11111 or 00000, the output status register is updated. Input sequences with signals that are not all 1 or all 0 will all be filtered out.

[0064] (2) Acquisition and filtering of the instruction status signal;

[0065] The acquisition and filtering method of the instruction status signal is the same as that of the timing instruction processing method.

[0066] (3) Time counting;

[0067] After the single machine is powered on, the FPGA software counts time in 1ms as the basic unit; when the status word changes, such as ignition, takeoff, etc., the timing needs to be cleared and re-counted with a new reference.

[0068] (4) Frame the time, timing, and instruction status in a format;

[0069] In the FIFO input control sub-module, after the new timing instruction is input into the FPGA, it is cached at two levels. The data in the first-level cache register and the second-level cache register are compared. When the data in the two-level cache registers are inconsistent, it is determined that there is a new timing state input. At this time, the timing data state, instruction state, current timing time value, and the sum of the previous several data items in the first-level cache register are stored in the FIFO through the framing logic for the final serial port data output. The framing logic frames the current timing data state, instruction state, current timing time value, and the sum according to the protocol format as the input data of the FIFO. The comparison result of the two-level cache registers serves as the FIFO input enable. When the data in the two-level cache registers are inconsistent, the FIFO input enable is a valid value of 1. When the FIFO enable signal value is 1, the data at the input port is written into the FIFO. In this embodiment, the first-in, first-out queue FIFO (First Input First Output, FIFO) refers to a data buffer that outputs data in the order it was received. The earlier-entered data messages are read out first, and the later-entered data messages will be read out subsequently. The specific control logic block diagram is as Figure 4 shown.

[0070] (5) Serialize and output the timing acquisition signal through the 422 serial port;

[0071] In the serial port information sending module, the period is 20 ms. When the 20 ms clock positive pulse signal arrives, first check whether the FIFO is empty. If it is not empty, read out the stored data from the FIFO, including the timing data state, instruction state, timing time value, and the sum. At the same time, enable the transmission bit counter to start counting, and the data output register starts to output data bit by bit at a baud rate of 115,200. Each time a bit is output, the bit counter is decremented by one. When the count value of the bit counter is not 0, the output register is continuously enabled to output data; when the count value is 0, it indicates that the transmission of one frame of data is completed, and the output enable of the register is turned off. When the next 20 ms positive pulse signal arrives, continue to execute the above steps. In this way, as long as the FIFO is not empty, the data stored in the FIFO is continuously serially transmitted at a baud rate of 115,200 with a period of 20 ms. The specific block diagram is as shown in Figure 5, and the specific serial port output circuit is as Figure 6 shown. The output circuit uses the serial port isolation chip ADM2682 to convert the single-ended signal into a differential signal for output.

[0072] An embodiment of the present invention provides a method, system and medium for collecting timing instructions of a launch vehicle. The timing collection is performed inside a single timing controller. Compared with the previous acquisition circuit built by using logic devices such as counters and shift registers, the present method uses a programmable logic device FPGA to implement the above functions, solving the problems of high cost and complex system for collecting timing outputs of individual units in a launch vehicle.

[0073] Those skilled in the art know that in addition to implementing the system and its various devices, modules, and units provided by the present invention in the form of pure computer-readable program code, the method steps can be logically programmed to enable the system and its various devices, modules, and units provided by the present invention to be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers to achieve the same functions. Therefore, the system and its various devices, modules, and units provided by the present invention can be regarded as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be regarded as the structure within the hardware component; the devices, modules, and units for implementing various functions can also be regarded as both software modules for implementing the method and the structure within the hardware component.

[0074] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Without conflict, the embodiments of the present application and the features in the embodiments can be combined arbitrarily with each other.

Claims

1. A method for retrieving time-sequenced instructions of a launch vehicle, characterized in that, It includes: Timing acquisition step: Using opto - isolator to acquire timing instruction signals and instruction status signals, and input all the acquired timing instruction signals and instruction status signals into the Field - Programmable Gate Array (FPGA); Function implementation step: Shaping the received timing instruction signals and instruction status signals, and the FPGA realizes the processing and output of the timing instruction signals and instruction status signals; The processing of signals in the function implementation step includes: 1) Acquisition filtering of timing acquisition signals: Filtering each input timing instruction in a two - stage latching manner to stabilize the data; 2) Acquisition filtering of instruction status signals; 3) Time counting: After the single - machine powers on, the FPGA counts time in units of 1 ms. When the status word changes, the timing needs to be cleared and re - counted with a new reference; 4) Framing the time, timing, and instruction status in a format; 5) Serial - outputting the timing acquisition signals through a 422 serial port.

2. The method for retrieving time-sequenced commands for a launch vehicle according to claim 1, characterized in that, The acquisition filtering of the timing acquisition signals specifically includes: Performing three - stage latching in the first - stage latching manner and filtering for 3 us to filter out hardware glitches; Performing five - stage latching in the second - stage latching manner and filtering for 5 ms to stabilize the data.

3. The method for retrieving time-sequential instructions for a launch vehicle according to claim 1, characterized in that The framing of the time, timing, and instruction status in a format includes: After the new timing instruction is input into the FPGA, it is cached in two - levels, and the data in the first - level cache register and the second - level cache register are compared; When the data in the two - level cache registers is inconsistent, the input timing data has changed. At this time, the instruction data status and the current time value in the first - level cache register are stored in the FIFO through the framing logic for the final serial - port data output.

4. A system for retrieving time-sequenced instructions of a launch vehicle, characterized in that, It includes: A timing acquisition module and an FPGA; Timing acquisition module: Using opto - isolator to acquire timing instruction signals and instruction status signals, and input all the acquired timing instruction signals and instruction status signals into the FPGA; Function implementation module: Shaping the received timing instruction signals and instruction status signals, and the FPGA realizes the processing and output of the timing instruction signals and instruction status signals; The processing of signals in the function implementation module includes: 1) Acquisition filtering of timing acquisition signals: Filtering each input timing instruction in a two - stage latching manner to stabilize the data; 2) Acquisition filtering of instruction status signals; 3) Time counting: After the single - machine powers on, the FPGA counts time in units of 1 ms. When the status word changes, the timing needs to be cleared and re - counted with a new reference; 4) Framing the time, timing, and instruction status in a format; 5) Serial - outputting the timing acquisition signals through a 422 serial port.

5. The system for retrieving time-sequenced commands of a launch vehicle according to claim 4, wherein The acquisition filtering of the timing acquisition signals specifically includes: Performing three - stage latching in the first - stage latching manner and filtering for 3 us to filter out hardware glitches; Performing five - stage latching in the second - stage latching manner and filtering for 5 ms to stabilize the data.

6. The system for retrieving time-sequenced commands of a launch vehicle according to claim 4, wherein The framing of time, timing, and instruction status in the specified format includes: after the new timing instruction is input into the FPGA, it is cached at two levels, and the data in the first-level cache register is compared with the data in the second-level cache register; When the data in the two-level cache registers is inconsistent, it means that the input timing data has changed. At this time, the instruction data status and the current time value in the first-level cache register are stored in the FIFO through the framing logic for the final serial port data output.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method described in any one of claims 1 to 3.

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