Integrated circuit testing apparatus and method of testing thereof

Abstract

The application provides an integrated circuit testing device and a testing method thereof. The method comprises: receiving a first instruction, the first instruction indicating to perform a testing operation on at least one target device under test; generating a driving signal set and a selection signal in response to the first instruction; determining a state of each testing channel in a plurality of device under test groups based on the selection signal and a first mapping table, the state comprising one of an enabled state and a disabled state; the first mapping table comprising a correspondence between the testing channel and the device under test group, a pin to be controlled of the device under test, and the selection signal; each device under test in each device under test group has a corresponding selection signal; outputting a driving signal from the testing channel according to the driving signal set and a second mapping table; the second mapping table comprising a correspondence between a plurality of pins to be controlled of a plurality of devices under test and a plurality of driving signals in the driving signal set; and performing the testing operation on the target device under test by using the driving signal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and more specifically, to an integrated circuit testing device and a testing method thereof. Background Art

[0002] With the rapid development of semiconductor integrated circuits (ICs), the integration density of IC chips is increasing, and the functions of IC chips are becoming increasingly complex. To ensure that IC chips function properly during use, they must be tested for timing, electrical properties, and other aspects after manufacturing using IC testing equipment, such as automatic test equipment (ATE).

[0003] However, due to the limitations of integrated circuit testing equipment, there are still many problems that need to be solved during the testing process of integrated circuit chips. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides an integrated circuit testing device and a testing method thereof.

[0005] In one aspect, an embodiment of the present application provides a testing method for an integrated circuit testing device, wherein the integrated circuit testing device has multiple test channels, each of the test channels being connected to one of multiple types of controlled pins of multiple devices under test; the testing method comprising:

[0006] receiving a first instruction, wherein the first instruction instructs to perform a test operation on at least one target device under test;

[0007] generating a drive signal set and a selection signal in response to the first instruction;

[0008] Based on the selection signal, in combination with a first mapping table, a state of each test channel in a plurality of device under test groups is determined, the state including one of an enabled state and a disabled state; the first mapping table includes a correspondence between the test channel and the device under test group, the controlled pins of the device under test, and the selection signal; wherein the plurality of devices under test are divided into a plurality of device under test groups; each device under test in each of the device under test groups has a corresponding selection signal;

[0009] According to the drive signal set, in combination with a second mapping table, the test channel outputs a drive signal; the second mapping table includes a correspondence between a plurality of pins to be controlled of a plurality of devices under test and a plurality of drive signals in the drive signal set;

[0010] A test operation is performed on the target device under test using the driving signal.

[0011] In the above solution, the second mapping table includes a first sub-mapping table and a second sub-mapping table;

[0012] The step of causing the test channel to output a drive signal according to the drive signal set and in combination with a second mapping table includes:

[0013] Determining, based on the drive signal set and in combination with the first sub-mapping table, a correspondence system between a plurality of pins to be controlled of a plurality of devices under test and a plurality of drive signals in the drive signal set;

[0014] Based on the correspondence between the plurality of controlled pins of the plurality of devices under test and the plurality of driving signals in the driving signal set, in combination with the second sub-mapping table, the test channel is enabled to output the driving signal.

[0015] In the above solution, the method further includes: establishing the first sub-mapping table;

[0016] The establishing the first sub-mapping table includes:

[0017] Acquire a correspondence between a plurality of pins to be controlled of the plurality of devices under test and a plurality of driving signals in the driving signal set; wherein each of the pins to be controlled corresponds to one of the driving signals;

[0018] The obtained correspondence between the plurality of pins to be controlled of the plurality of devices under test and the plurality of driving signals in the driving signal set is stored in the first sub-mapping table.

[0019] In the above solution, the method further includes: establishing the second sub-mapping table;

[0020] The establishing of the second sub-mapping table includes:

[0021] Establish a connection relationship between the multiple test channels and the multiple pins to be controlled of the multiple devices under test, obtain the connection relationship between each type of pin to be controlled of each device under test and the multiple test channels, and generate a second sub-mapping table; wherein each test channel is connected to one or more pins to be controlled.

[0022] In the above scheme, the same type of pins to be controlled of the devices under test with the same selection signals among multiple groups of the devices under test are connected to the same test channel; the same type of pins to be controlled of at least two devices under test in each group of the devices under test are connected to the same test channel.

[0023] In the above solution, the pins to be controlled include: a data line pin, a chip select enable pin, and an output enable pin.

[0024] In the above solution, the drive signal set includes at least one of the following: a control signal, a data output signal, an input / output enable signal, and a data expectation signal.

[0025] On the other hand, the present application provides an integrated circuit testing device, comprising: a plurality of test channels, a processor, a signal generating unit, and a testing unit; wherein,

[0026] Each of the test channels is used to: connect to one of the multiple types of pins to be controlled of multiple devices under test;

[0027] The processor is configured to: receive a first instruction, wherein the first instruction instructs to perform a test operation on at least one target device under test;

[0028] The signal generating unit is configured to: generate a drive signal set and a selection signal in response to the first instruction;

[0029] The processor is further configured to: determine, based on the selection signal and in combination with a first mapping table, a state of each test channel in a plurality of device under test groups, the state including one of an enabled state and a disabled state; the first mapping table including a correspondence between the test channel and the device under test group, a pin to be controlled of the device under test, and the selection signal; wherein the plurality of devices under test are divided into a plurality of device under test groups; and each device under test in each of the device under test groups has a corresponding selection signal;

[0030] According to the drive signal set, in combination with a second mapping table, the test channel outputs a drive signal; the second mapping table includes a correspondence between each pin to be controlled of a plurality of devices under test and each drive signal in the drive signal set;

[0031] The test unit is configured to perform a test operation on the target device under test using the drive signal.

[0032] In the above solution, the signal generating unit includes an algorithmic graphics generator or a vector driver.

[0033] In the above solution, the integrated circuit testing device further includes a power supply, which is connected to the processor and controlled by the processor;

[0034] The power supply is used to provide power to the target device under test under the control of the processor.

[0035] In the above solution, the integrated circuit testing equipment includes aging testing equipment.

[0036] In an embodiment of the present application, the integrated circuit testing equipment can establish a connection relationship between multiple types of controlled pins of the device under test and multiple drive signals in the drive signal set, as well as a correspondence between each type of controlled pin of each device under test and each test channel, device under test, and device under test group through a combination of a first mapping table and a second mapping table; in this way, by applying a drive signal to the controlled pin of the target device under test, the test channel connected to the controlled pin of the target device under test is enabled, thereby realizing testing of the target device under test; in this way, by establishing a correspondence between the controlled pin of the target device under test and the test channel connected thereto, the readability and maintainability of the configuration of the integrated circuit testing equipment can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the connection between multiple test channels and multiple devices under test in an integrated circuit test device provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of an implementation flow of a testing method for an integrated circuit testing device provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of the connection relationship between a drive signal and a device under test, and between the device under test and a test channel in an integrated circuit test device provided in an embodiment of the present application;

[0040] Figure 4a A schematic diagram of a test channel mapping table provided in an embodiment of the present application;

[0041] Figure 4b A schematic diagram of a query structure of a test channel mapping table provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of grouping multiple test channels in an integrated circuit test device provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of an integrated circuit testing device performing a test operation provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the embodiments of the present invention and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0045] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0046] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0049] With the rapid development of semiconductor integrated circuits, the integration density of integrated circuit chips is increasing, and the functions of integrated circuit chips are becoming more and more complex. To ensure the normal operation of integrated circuit chips during use, they must be tested for timing, electrical properties, integrity, and other aspects using integrated circuit testing equipment after manufacturing to ensure the quality of the integrated circuit chips.

[0050] However, many current integrated circuit test devices require complex test program development before performing tests, which results in low development efficiency. In addition, during the test execution process, the test programs of the integrated circuit test devices are difficult to read and maintain, which is not conducive to the testing of integrated circuit chips.

[0051] To solve the above problems, the present application provides the following technical solutions. In order to more clearly describe the technical solutions, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] In the embodiment of the present application, an integrated circuit test device is used to implement the test of the integrated circuit chip; here, the integrated circuit test device has multiple test channels (TCh, Tester Channel), each of which is connected to one type of controlled pin among multiple types of controlled pins of multiple devices under test (DUT, Device Under Test).

[0053] Here, the device under test may include an integrated circuit chip or a device including an integrated circuit chip. For example, the device under test may be a memory device, such as a three-dimensional NAND memory; for example, the device under test may be a memory system, such as a solid-state drive (SSD).

[0054] In some embodiments, multiple devices under test can be divided into multiple device under test groups; each device under test in each device under test group can include multiple pins to be controlled, and the types of the multiple pins to be controlled are different; in other words, each device under test can include multiple types of pins to be controlled; in actual applications, each type of pin to be controlled performs different operations when receiving different instructions or driving signals.

[0055] In some embodiments, the multiple types of pins to be controlled include, but are not limited to, control pins, data output pins, input / output enable pins, and input data expectation pins. Specifically, for example, chip select enable (CE) pins, output enable (OE) pins, data queue (DQ) pins, write enable (WE) pins, read enable (RE) pins, write protect (WP) pins, and device busy / idle status (R / B) pins.

[0056] To facilitate the description of the present invention, the following example illustrates that each device under test includes a chip select enable pin, an output enable pin, and a data line pin. However, it should be noted that the pin types in the following embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0057] Here, the chip select enable pin is generally specified as active high or active low. When the specified active level is applied to the chip select enable pin of the device under test, the device under test will enter an operating state; otherwise, the device under test will be in a non-operating state and will not respond to signals sent by other devices. The output enable pin is generally specified as active high or active low. When the specified active level is applied to the output enable pin of the device under test, the device under test will output a signal; otherwise, the device under test will not output a signal. The data line pin is generally a pin for data exchange between the device under test and other devices, such as test equipment.

[0058] In some embodiments, the integrated circuit testing equipment may include multiple test channels, where each test channel can be connected to one or more pins to be controlled of the same type; and in order to improve testing efficiency, multiple pins to be controlled of the same type are usually connected to one test channel; here, the multiple pins to be controlled of the same type come from multiple devices under test respectively.

[0059] For example, Figure 1 As shown, the integrated circuit test equipment includes multiple test channels, namely Ch0, Ch1, Ch2, Ch3 and Ch4; multiple devices under test, namely a first device under test DUTA, a second device under test DUTB, a third device under test DUTC and a fourth device under test DUTD; wherein each device under test includes three types of pins to be controlled, namely CE pin, OE pin and DQ pin.

[0060] Here, Ch0 can be simultaneously connected to the CE pin in the first device under test DUTA and the CE pin in the second device under test DUTB; Ch1 can be simultaneously connected to the OE pin in the first device under test DUTA and the OE pin in the third device under test DUTC; Ch4 can be simultaneously connected to the DQ pins in the first device under test DUTA, the second device under test DUTB, the third device under test DUTC and the fourth device under test DUTD.

[0061] It should be noted that the test channel TCh is used to output a specific waveform to drive the device under test connected to the controlled pin and receive the waveform returned by the device under test connected to the controlled pin, thereby realizing testing of the device under test.

[0062] Based on the aforementioned test channel and device under test connection rules, the present application embodiment provides a test method for integrated circuit test equipment, the Figure 2 The following is a flow chart of an implementation of a testing method for an integrated circuit testing device provided in an embodiment of the present application. Figure 2 As shown, the method includes the following steps:

[0063] Step 201: Receive a first instruction, wherein the first instruction instructs to perform a test operation on at least one target device under test;

[0064] Step 202: generating a drive signal set and a selection signal in response to the first instruction;

[0065] Step 203: Determine the state of each test channel in a plurality of DUT groups based on the selection signal and in combination with a first mapping table; the state includes one of an enabled state and a disabled state; the first mapping table includes a correspondence between the test channel and the DUT group, the controlled pins of the DUT, and the selection signal; wherein the plurality of DUTs are divided into a plurality of DUT groups; and each DUT in each DUT group has a corresponding selection signal;

[0066] Step 204: Based on the drive signal set and in combination with a second mapping table, the test channel is enabled to output a drive signal; the second mapping table includes a correspondence between a plurality of pins to be controlled of a plurality of devices under test and a plurality of drive signals in the drive signal set;

[0067] Step 205: Utilize the driving signal to perform a test operation on the target device under test.

[0068] It should be understood that Figure 2 The operations shown in the figure are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0069] It should be noted that the execution entities of steps 201 to 205 described herein may all include integrated circuit testing equipment.

[0070] In some embodiments, in step 201, the integrated circuit testing device can perform a test operation on the target device under test based on the received first instruction. Here, the first instruction can be understood as a test instruction input by the tester to the integrated circuit testing device. The content indicated by the first instruction can be used to determine the target device under test on the one hand; on the other hand, it can be used to indicate the specific test operation to be performed on the determined target device under test.

[0071] In some embodiments, the integrated circuit testing equipment may perform a test operation on a device under test according to the instruction content of the first instruction, or may perform a test operation on multiple devices under test at the same time; the multiple devices under test may be multiple devices under test in the same device under test group, or may be multiple devices under test in different device under test groups. The actual situation may be selected and set according to actual needs.

[0072] In step 202 , the integrated circuit testing equipment generates a driving signal set and a selection signal in response to the first instruction.

[0073] Here, the drive signal set can be understood as a programmable data source (PDS) digital signal generated by the integrated circuit test equipment according to the content indicated by the first instruction, and the PDS digital signal can be used to drive the device under test corresponding to the corresponding test channel. In some embodiments, the drive signal set can be specifically generated by an algorithmic pattern generator (ALPG) or a vector driver (Vector Driver) in the integrated circuit test equipment. Here, the drive signal set may include multiple drive signals; the multiple drive signals may be digital signals of multiple different types. In some embodiments, the drive signal set may include at least: a chip select signal (PCE), a readout control signal (POE) and a data signal (PDQ).

[0074] It should be noted that different types of drive signals can drive corresponding types of test channels to either an enabled or disabled state. Here, the enabled state can be understood as a state to be tested. In the following embodiments, the example of a drive signal driving a corresponding test channel to an enabled state is used for illustration.

[0075] Here, the selection signal can be understood as the index information (DSI, DUT Selection Index) set for the target device under test when the integrated circuit test equipment generates a selection instruction. It should be noted that the integrated circuit test equipment in the embodiment of the present application supports the device under test selection (DSEL, DUT Selection) instruction and can generate the index information of the device under test based on the device under test selection instruction.

[0076] The integrated circuit test equipment provided in the embodiments of the present application can use a DUT selection instruction to address a target DUT, thereby determining the target DUT. The DUT selection instruction can determine that one of multiple DUTs is the target DUT, or multiple DUTs are the same.

[0077] It should be noted that, after the plurality of DUTs are divided into a plurality of DUT groups, each DUT in each of the DUT groups has a corresponding selection signal.

[0078] Next, step 203 and step 204 are executed to determine the correspondence between the selection signal and the controlled pins, test channels, device groups, and drive signals of the target device under test through the first mapping table and the second mapping table.

[0079] In some embodiments, before executing step 203 and step 204 , a first mapping table and a second mapping table need to be established first.

[0080] In some embodiments, the method further includes: establishing the first mapping table.

[0081] Here, after establishing connections between multiple test channels and multiple controlled pins of multiple devices under test, a first mapping table can be generated. In other words, the first mapping table includes the correspondence between test channels and device groups under test, the controlled pins of the devices under test, and selection signals.

[0082] Specifically, the establishment of the first mapping table includes: the integrated circuit test equipment obtains the pin to be controlled of each device under test, and distinguishes and stores the type of each pin to be controlled; at the same time, the integrated circuit test equipment obtains the connection relationship between multiple test channels and multiple pins to be controlled of multiple devices under test; then, according to the selection signal corresponding to each device under test, the corresponding relationship between the test channel, the device under test group, the pin to be controlled of the device under test, and the selection signal is established, that is, the first mapping table is generated.

[0083] Exemplarily, a DUT Group (DG) is created, wherein the multiple DUTs include DUT1A, DUT1B, DUT1C, DUT1D, DUT2A, DUT2B, DUT2C, and DUT2D. Here, the multiple DUTs are divided into two DUT groups, for example, a first DUT group (DG1) and a second DUT group (DG2). The first DUT group includes DUT1A, DUT1B, DUT1C, and DUT1D, while the second DUT group includes DUT2A, DUT2B, DUT2C, and DUT2D. Each DUT group (DG) has a corresponding DSI value. The DSI value of the first DUT group (DG1) is 1-4, while the DSI value of the second DUT group (DG2) is 1-4. Each of the multiple DUTs includes three types of pins to be controlled, such as CE, OE, and DQ. The multiple test channels include Ch0, Ch1, Ch2, Ch3, Ch4, and Ch5.

[0084] Bind the DUT PIN of the DUT to the TCh. Each TCh records its corresponding DUT PIN information as follows:

[0085] TCh0---DUT1A.CE#, DUT1B.CE#;

[0086] TCh1---DUT1A.OE#, DUT1C.OE#;

[0087] TCh2---DUT1C.CE#, DUT1D.CE#;

[0088] TCh3---DUT1B.OE#, DUT1D.OE#;

[0089] TCh4---DUT1A.DQ, DUT1B.DQ, DUT1C.DQ, DUT1D.DQ, etc.

[0090] In some embodiments, each TCh may record its corresponding DUT PIN, DUT Group, and DSEL index information as follows:

[0091] TCh0---DUT1A.CE#, DUT1B.CE#, DUT2A.CE#, DUT2B.CE#---{CE#, DG1&2, DSI 1&2};

[0092] TCh1---DUT1A.OE#, DUT1C.OE#, DUT2A.OE#, DUT2C.OE#---{OE#, DG1&2, DSI 1&3};

[0093] TCh2---DUT1C.CE#, DUT1D.CE#, DUT2C.CE#, DUT2D.CE#---{CE#, DG1&2, DSI 3&4};

[0094] TCh3--DUT1B.OE#, DUT1D.OE#, DUT2B.OE#, DUT2D.OE#---{OE#, DG1&2, DSI 2&4};

[0095] TCh4---DUT1A.DQ, DUT1B.DQ, DUT1C.DQ, DUT1D.DQ---{DQ, DG1, DSI 1, 2, 3, 4};

[0096] TCh5---DUT2A.DQ, DUT2B.DQ, DUT2C.DQ, DUT2D.DQ---{DQ, DG2, DSI 1, 2, 3, 4}.

[0097] In short, in actual operation, the integrated circuit test equipment can determine the target device under test and the enable status of the test channel connected to the target device under test according to the selection signal.

[0098] In some embodiments, the method further includes: establishing the second mapping table; where the second mapping table includes a first sub-mapping table and a second sub-mapping table;

[0099] The step of causing the test channel to output a drive signal according to the drive signal set and in combination with a second mapping table includes:

[0100] Determining, based on the drive signal set and in combination with the first sub-mapping table, a correspondence between a plurality of pins to be controlled of a plurality of devices under test and a plurality of drive signals in the drive signal set; wherein each of the pins to be controlled corresponds to one of the drive signals;

[0101] Based on the correspondence between the plurality of controlled pins of the plurality of devices under test and the plurality of driving signals in the driving signal set, in combination with the second sub-mapping table, the test channel is enabled to output the driving signal.

[0102] Here, the integrated circuit testing device obtains each driving signal in the driving signal set, distinguishes and stores the driving signal according to different types.

[0103] In some embodiments, the method further comprises: establishing the first sub-mapping table;

[0104] The establishing the first sub-mapping table includes:

[0105] The integrated circuit testing equipment arranges, based on actual needs or instructions from the tester, corresponding connections between different types of pins to be controlled of each device under test and different types of drive signals in a drive signal set, i.e., establishing a connection relationship between each type of pin to be controlled of multiple devices under test and multiple drive signals in the drive signal set; wherein each of the pins to be controlled is correspondingly connected to one of the drive signals; and storing the above connection relationship in a first sub-mapping table.

[0106] That is, the first sub-mapping table stores the connection relationship between each type of pin to be controlled of multiple devices under test and the corresponding drive signal in the drive signal set connected thereto; during the test process, by determining the drive signal, a certain type of pin to be controlled connected thereto can be determined.

[0107] Exemplarily, the integrated circuit test equipment obtains the pins to be controlled of multiple devices under test and their types (i.e., declares the DUT PIN type, such as the three types CE#, OE#, and DQ in the aforementioned example), and stores the information of each type of pin to be controlled of the multiple devices under test in the corresponding storage area; after the ALPG generates a drive signal set (multiple PDS digital signals, such as PCE, POE, and PDQ that match the three DUT PIN types in the aforementioned example), the integrated circuit test equipment obtains multiple PDS digital signals and stores the multiple PDS digital signals in the corresponding storage area; thereafter, the corresponding connection relationship between the multiple PDS digital signals and the multiple pins to be controlled of the multiple devices under test is obtained (i.e., the PDS is bound to each DUT PIN), that is, as in the aforementioned example, the mapping relationship between each DUT PIN and PDS is configured as follows: PCE-CE#; POE-OE#; PDQ-DQ. Here, the three DUT PINs have only a single function and can be driven by one PDS digital signal respectively. For other situations, please refer to the relevant pin scrambling technology.

[0108] In some embodiments, the first sub-mapping embodied by the first sub-mapping table may be as follows: Figure 3 Here, the connection relationship between each PDS digital signal and each pin to be controlled is stored in the first sub-mapping table.

[0109] It should be noted that Figure 3 The To Error capture circuit shown in FIG can be used to receive waveforms returned by the controlled pins and the device under test connected thereto. Furthermore, the connection relationship between the controlled pins and the drive signals can be configured based on the tester's actual needs. However, it should be noted that each type of controlled pin and the drive signal in the corresponding drive signal set must be of the same type.

[0110] In some embodiments, the method further comprises: establishing the second sub-mapping table;

[0111] The establishing of the second sub-mapping table includes:

[0112] Establish a connection relationship between the multiple test channels and the multiple pins to be controlled of the multiple devices under test, obtain the connection relationship between each type of pin to be controlled of each device under test and the multiple test channels, and generate a second sub-mapping table; wherein each test channel is connected to one or more pins to be controlled.

[0113] Exemplarily, after acquiring information about multiple test channels, the integrated circuit test equipment establishes corresponding connections between the multiple pins to be controlled of the multiple devices under test and the multiple test channels, and stores the corresponding connections in the second sub-mapping table. In other words, the second sub-mapping table stores the connection relationships between each type of pin to be controlled of the multiple devices under test and the test channels to which it is connected.

[0114] Here, multiple pins to be controlled of multiple devices under test can be connected to different test channels according to their types. Among them, multiple pins to be controlled of the same type in multiple devices under test can be connected to the same test channel. The second sub-mapping table can be as follows: Figure 3 shown.

[0115] In this way, after the first mapping table and the second mapping table are successfully established, step 203 and step 204 are executed.

[0116] It should be noted that the connection between the test channel TCh and the pin of the device under test (DUT PIN) is a physical connection, and the connection relationship thereof changes as the connection relationship of the device under test on the printed circuit board (PCB) changes.

[0117] During the execution of steps 203 and 204, the integrated circuit test equipment may obtain the test channel mapping table before executing the formal test items, such as Figure 4a As shown, the test channel mapping table is stored in a corresponding storage area of ​​the integrated circuit test equipment.

[0118] During the test operation, the target device under test can be determined based on the selection signal received by the integrated circuit test equipment and the relevant information in the test channel mapping table can be queried using the Structured Query Language (SQL), thereby determining the status of the test channel corresponding to the target device under test.

[0119] The test channel mapping table contains the corresponding relationship between the test channel and the selection signal, the device under test, the device under test group, the type of the pin to be controlled, etc. Figure 4a An example of this correspondence is shown in .

[0120] It should be noted that Figure 4a It is only used as an example to illustrate the test channel mapping table in the embodiment of the present application and is not used to limit the content of the test channel mapping table in the embodiment of the present application.

[0121] It should be noted that in other embodiments, the correspondence between the test channel, selection signal, device under test, device under test group, selection signal and pin to be controlled may be determined by other database query methods.

[0122] It should be noted that the test channel mapping table here may be the same as or different from the aforementioned first mapping table.

[0123] In some embodiments, the test channel mapping table may be the same as the aforementioned first mapping table, such as each TCh may record its corresponding DUT PIN, DUT Group, and DSEL Index information.

[0124] For example, assuming that the DSI value of the selection signal in the test instruction is 1, 2, 3, or 4, and the test channel TCh selects Ch0, the SQL statement can be: Select DSI from TCh_mapping where TCh = CH0; in the test channel mapping table, the query returned result is as follows: Figure 4b shown.

[0125] At this point, we can know that when the DSI value is 1 or 2, Ch0 is in the enabled state; when the DSI value is 3 or 4, Ch0 is in the disabled (non-enabled) state. That is:

[0126] DSI 1: Ch0, ON;

[0127] DSI 2: Ch0, ON;

[0128] DSI 3: Ch0, OFF;

[0129] DSI 4: Ch0, OFF.

[0130] Similarly, when the test channel TCh selects other channels, different DSI values ​​can also be obtained to determine whether the selected test channel should be in an enabled state or a disabled state.

[0131] In this way, when different DSI values ​​are obtained through SQL query, each channel should be in the enabled or disabled state. That is, we can get:

[0132] DSI 1: Ch0, ON; CH1, ON; CH2: OFF; CH3, OFF;

[0133] DSI 2: Ch0, ON; CH1, OFF; CH2: OFF; CH3, ON;

[0134] DSI 3: Ch0, OFF; CH1, ON; CH2: ON; CH3, OFF;

[0135] DSI 4: Ch0, OFF; CH1, OFF; CH2: ON; CH3, ON.

[0136] Meanwhile, during the test operation, different PDS digital signals can drive different types of controlled pins of the device under test connected thereto, so that the test channels connected to the controlled pins are in corresponding states.

[0137] Exemplary, reference Figure 1 and Figure 3 Here, the multiple devices under test include DUTA, DUTB, DUTC and DUTD; each DUT includes three types of pins to be controlled, namely CE, OE and DQ; here, the multiple test channels include Ch0, Ch1, Ch2, Ch3 and Ch4.

[0138] The three types of pins to be controlled in DUTA can be connected to Ch0, Ch1 and Ch4 respectively according to their types; here, the same test channel, such as Ch4, can be connected to the CE pin in DUTC and the CE pin in DUTD at the same time.

[0139] In this way, the integrated circuit test equipment can determine the controlled pin of the device under test connected to the drive signal by querying the second mapping table according to the PDS digital signal in the received first instruction, thereby implementing testing of the target device under test.

[0140] In an embodiment of the present application, by combining the first sub-mapping table with the second sub-mapping table, a connection relationship between multiple types of controlled pins of the device under test and multiple drive signals in the drive signal set is established, and thereby a connection relationship between each type of controlled pin of each device under test and each test channel is determined; in this way, by applying a drive signal to the controlled pin of the target device under test, the test channel connected to the controlled pin of the target device under test is enabled, thereby achieving testing of the target device under test.

[0141] It can be understood that in the above embodiment, through the combination of the first mapping table and the second mapping table, the portability of the test program used in executing the test operation is increased; the test channel is easy to configure and understand; at the same time, by refining and clarifying the connection relationship between each controlled pin of multiple devices under test and the test channel, the readability of the integrated circuit test equipment configuration for the tester is enhanced, and the maintainability of the integrated circuit test equipment is improved.

[0142] In addition, the above embodiment can also ensure that the integrated circuit test equipment supports the DUT Selection ALPG instruction; at the same time, it avoids manually configuring the output value of the DSI and the enable relationship of the TCh during the test program development stage, thereby greatly simplifying the programming difficulty of the ALPG.

[0143] It should be noted that in other embodiments, the corresponding result in the test channel mapping table corresponding to the SQL may be directly output according to the driving signal without querying the database corresponding to the SQL, thereby saving response time.

[0144] In step 205, a test operation is performed on the target device under test.

[0145] Here, after the target device under test is driven by the driving signal transmitted through the test channel, various corresponding functional tests, such as aging test, electrical parameter test, timing test, etc., can be performed on the target device under test.

[0146] In some embodiments, the method further comprises:

[0147] According to the attributes of each type of pin to be controlled of each device under test, the attributes of the test channel connected to each type of pin to be controlled of each device under test are determined.

[0148] Here, different types of controlled pins of the device under test have different properties, such as timing, DC, etc. The service program of the integrated circuit test equipment configures the timing, DC, etc. properties to the actual test channel according to the second mapping table.

[0149] Here, when there are multiple DUTs that reuse the same (group) of test channels, the multiple DUTs can be divided into different DUT groups. In addition, the target DUT can be located in the same DUT group or in multiple DUT groups.

[0150] In some embodiments, multiple devices under test are divided into multiple device under test groups, and the same type of pins to be controlled of the devices under test with the same selection signals among the multiple device under test groups are connected to the same test channel; the same type of pins to be controlled of at least two devices under test in each device under test group are connected to the same test channel.

[0151] It should be noted that the multiple device under test groups can be divided into multiple device under test groups according to actual needs; in the embodiment of the present application, the multiple devices under test are divided into two device under test groups as an example for description.

[0152] In some embodiments, the pins to be controlled include: a data line pin, a chip select enable pin, and an output enable pin.

[0153] For example, Figure 5 As shown, multiple DUTs (DUT1A, DUT1B, DUT1C, DUT1D, DUT2A, DUT2B, DUT2C, and DUT2D) are divided into a first DUT group (DG1) and a second DUT group (DG2). The first DUT group includes DUT1A, DUT1B, DUT1C, and DUT1D, while the second DUT group includes DUT2A, DUT2B, DUT2C, and DUT2D. Each of the multiple DUTs includes the three types of controllable pins described above, such as CE, OE, and DQ. Multiple test channels include Ch0, Ch1, Ch2, Ch3, Ch4, and Ch5, respectively.

[0154] Here, all data line pins in each device under test group (DG1 or DG2) are connected to the same test channel (Ch4 or Ch5); the chip select enable pins (CE pins) of at least two devices under test (DUT1A, DUT1B, DUT2A, DUT2B) in multiple device under test groups are connected to the same test channel (Ch0 or Ch2); and the output enable pins (OE pins) of at least two devices under test (DUT1A, DUT1B, DUT1C, DUT2C) in multiple device under test groups are connected to the same test channel (Ch1 or Ch3).

[0155] It should be noted that each device under test may also include other types of pins to be controlled, which have been mentioned above and will not be repeated here.

[0156] It should be noted that when multiple DUTs are assigned to different DUT groups, the aforementioned select signal is actually an instruction in the ALPG. The select signal generates an index value (DSI value) used to address a specific target DUT within the DUT group. Since the first-class pins to be controlled of each DUT in each DUT group are connected to the same first test channel, the index information (DSI) generated by the select signal simultaneously selects the corresponding DUTs in all DUT groups. Furthermore, since the second-class pins to be controlled of the corresponding DUTs in each DUT group are connected to the same second test channel, and since the third-class pins to be controlled of the corresponding DUTs in each DUT group are connected to the same third test channel, simultaneous selection of all DUTs in a DUT group (DUT Select ALL) is also supported.

[0157] In addition, it should be noted that in the above embodiments, the same type of pins to be controlled of multiple devices under test are connected to one test channel; in other embodiments, the same type of pins to be controlled of multiple devices under test can be connected to multiple test channels; that is, each pin to be controlled in the multiple devices under test is connected to a test channel; it can be understood that connecting the same type of pins to be controlled of multiple devices under test to one test channel can save channel resources.

[0158] It should be noted that, through the above connections or corresponding relationships, the selection signal and the driving signal can be selectively applied to all or part of the pins of the target device under test.

[0159] Only when all specific control pins of the device under test receive the tester's stimulus signal (including the selection signal and the drive signal) will they respond to the stimulus signal and provide feedback. At the same time, some devices under test may only have some of their control pins driven, but will not respond to the test stimulus because their operating or feedback conditions (all control pins driven) are not met. This allows individual devices under test to be selected for testing even when test channels are shared.

[0160] The following further illustrates the solution of the embodiment of the present application from another dimension. For example, Figure 6 shown.

[0161] Step 1: Generate a list of controlled pins (DUT PINs) of the device under test (DUT); the list includes the connection relationship between each type of controlled pin of each device under test and each drive signal in the drive signal set, that is, the aforementioned second mapping table.

[0162] Step 2: Map the drive signal (PDS) to the device under control pin (DUT PIN).

[0163] Step 3: Create a device under test (DUT) list. When creating a device under test (DUT), specify the device under test (DUT Group) to which the device under test (DUT) belongs and the corresponding selection signal (DSI).

[0164] Step 4: Create a DUT PIN instance table; the table includes the connection relationship between each type of DUT pin, DUT group, selection signal and multiple test channels (TCH), i.e. the first mapping table mentioned above.

[0165] The plurality of devices under test are grouped. Here, the plurality of devices under test are divided into a first device under test group (DG1) and a second device under test group (DG2). The value of the selection signal DSI is set for each device under test, such as Figure 6The TCh list shown includes the device under test number, group, index information (selection signal) of the device under test, pin type and test channel, etc., that is, the test channel mapping table mentioned above.

[0166] Here, the target device under test is tested by selecting signals and driving signals.

[0167] It is understood that the test method provided in the embodiment of the present application supports dynamic modification of test channel configuration through an application programming interface (API); supports the abstract object of the device under test pin (DUT PIN), supports the description of the connection relationship between the device under test and the test channel by binding the device under test pin and the test channel; supports the mapping of the device under test pin and the test channel to verify the enabling relationship between the mapped test channel and the DSI. In addition, by supporting the selection signal, the programming of the algorithm graph generator is simplified; by introducing the DUT PIN concept and object, the readability and maintainability of the integrated circuit test equipment configuration are improved; by mapping the DUT PIN and the test channel, there is no need to manually configure the enabling relationship between the DSI and the test channel.

[0168] An embodiment of the present application further provides an integrated circuit testing device, comprising: a plurality of test channels, a processor, a signal generating unit, and a test unit; wherein,

[0169] Each of the test channels is used to: connect to one of the multiple types of pins to be controlled of multiple devices under test;

[0170] The processor is configured to: receive a first instruction, wherein the first instruction instructs to perform a test operation on at least one target device under test;

[0171] The signal generating unit is configured to: generate a drive signal set and a selection signal in response to the first instruction;

[0172] The processor is further configured to: determine, based on the selection signal and in combination with a first mapping table, a state of each test channel in a plurality of device under test groups, the state including one of an enabled state and a disabled state; the first mapping table including a correspondence between the test channel and the device under test group, a pin to be controlled of the device under test, and the selection signal; wherein the plurality of devices under test are divided into a plurality of device under test groups; and each device under test in each of the device under test groups has a corresponding selection signal;

[0173] According to the drive signal set, in combination with a second mapping table, the test channel outputs a drive signal; the second mapping table includes a correspondence between each pin to be controlled of a plurality of devices under test and each drive signal in the drive signal set;

[0174] The test unit is configured to perform a test operation on the target device under test using the drive signal.

[0175] In some embodiments, the signal generating unit includes an algorithmic pattern generator or a vector driver.

[0176] In some embodiments, the integrated circuit testing device further includes a power supply, wherein the power supply is connected to the processor and controlled by the processor;

[0177] The power supply is used to provide power to the target device under test under the control of the processor.

[0178] Here, the power supply includes a power supply channel (Device Power Supply) for supplying power to the device under test; the power supply channel can support programmable voltage and current output, and can also be used to implement device protection, measurement and other functions according to the actual use of the integrated circuit test equipment.

[0179] In some embodiments, the integrated circuit testing equipment includes burn-in testing equipment.

[0180] In an embodiment of the present application, the integrated circuit testing equipment can establish a connection relationship between multiple types of controlled pins of the device under test and multiple drive signals in the drive signal set, as well as a correspondence between each type of controlled pin of each device under test and each test channel, device under test, and device under test group through a combination of a first mapping table and a second mapping table; in this way, by applying a drive signal to the controlled pin of the target device under test, the test channel connected to the controlled pin of the target device under test is enabled, thereby realizing testing of the target device under test; in this way, by establishing a correspondence between the controlled pin of the target device under test and the test channel connected thereto, the readability and maintainability of the configuration of the integrated circuit testing equipment can be improved.

[0181] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0182] The above merely provides the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure variations made according to the present application, or direct / indirect application in other related technical fields, shall fall within the patent protection scope of the present application.

Claims

1. A testing method for an integrated circuit testing device, characterized in that: The integrated circuit test equipment has multiple test channels, each of the test channels is connected to the same type of pins to be controlled in multiple devices under test, and each of the devices under test includes multiple different types of pins to be controlled; the testing method includes: receiving a first instruction, wherein the first instruction instructs to perform a test operation on at least one target device under test; generating a drive signal set and a selection signal in response to the first instruction; Based on the selection signal, in combination with a first mapping table, a state of the test channel connected to each target device under test in a plurality of device under test groups is determined, the state including one of an enabled state and a disabled state; the first mapping table includes a correspondence between the test channel and the device under test group, the controlled pin of the device under test, and the selection signal; wherein the plurality of devices under test are divided into a plurality of device under test groups; and each target device under test in the plurality of device under test groups has a corresponding selection signal; According to the drive signal set, in combination with a second mapping table, the test channel connected to each target device under test is caused to output a drive signal; the second mapping table includes a correspondence between a plurality of pins to be controlled of a plurality of devices under test and a plurality of drive signals in the drive signal set; wherein the type of the pins to be controlled is the same as the type of the drive signal corresponding thereto; A test operation is performed on each of the target devices under test using the driving signal.

2. The testing method according to claim 1, wherein: The second mapping table includes a first sub-mapping table and a second sub-mapping table; The step of causing the test channel to output a drive signal according to the drive signal set and in combination with a second mapping table includes: Determining, based on the drive signal set and in combination with the first sub-mapping table, a correspondence system between a plurality of pins to be controlled of a plurality of devices under test and a plurality of drive signals in the drive signal set; Based on the correspondence between the plurality of controlled pins of the plurality of devices under test and the plurality of driving signals in the driving signal set, in combination with the second sub-mapping table, the test channel is enabled to output the driving signal.

3. The testing method according to claim 2, wherein: The method further includes: establishing the first sub-mapping table; The establishing the first sub-mapping table includes: Acquire a correspondence between a plurality of pins to be controlled of the plurality of devices under test and a plurality of driving signals in the driving signal set; wherein each of the pins to be controlled corresponds to one of the driving signals; The obtained correspondence between the plurality of pins to be controlled of the plurality of devices under test and the plurality of driving signals in the driving signal set is stored in the first sub-mapping table.

4. The testing method according to claim 2, wherein: The method further includes: establishing the second sub-mapping table; The establishing of the second sub-mapping table includes: Establish a connection relationship between the multiple test channels and the multiple pins to be controlled of the multiple devices under test, obtain the connection relationship between each type of pin to be controlled of each device under test and the multiple test channels, and generate a second sub-mapping table; wherein each test channel is connected to one or more pins to be controlled.

5. The testing method according to claim 4, characterized in that: The same type of pins to be controlled of the devices under test with the same selection signals among multiple groups of the devices under test are connected to the same test channel; the same type of pins to be controlled of at least two devices under test in each group of the devices under test are connected to the same test channel.

6. The testing method according to claim 5, characterized in that: The pins to be controlled include: a data line pin, a chip select enable pin, and an output enable pin.

7. The testing method according to claim 1, wherein: The driving signal set includes at least one of the following: a control signal, a data output signal, an input / output enable signal, and a data expectation signal.

8. An integrated circuit testing device, characterized in that: include: Multiple test channels, processors, signal generating units and test units; wherein, Each of the test channels is used to: connect to the same type of pins to be controlled in a plurality of devices under test; each of the devices under test includes a plurality of pins to be controlled in different types; The processor is configured to: receive a first instruction, wherein the first instruction instructs to perform a test operation on at least one target device under test; The signal generating unit is configured to: generate a drive signal set and a selection signal in response to the first instruction; The processor is further configured to: determine, based on the selection signal and in combination with a first mapping table, a state of the test channel connected to each target device under test in a plurality of device under test groups, the state including one of an enabled state and a disabled state; the first mapping table including a correspondence between the test channel and the device under test groups, the controlled pins of the device under test, and the selection signal; wherein the plurality of devices under test are divided into a plurality of device under test groups; and each target device under test in the plurality of device under test groups has a corresponding selection signal; According to the drive signal set, in combination with a second mapping table, the test channel connected to each target device under test is caused to output a drive signal; the second mapping table includes a correspondence between each pin to be controlled of a plurality of devices under test and each drive signal in the drive signal set; wherein the type of the pin to be controlled is the same as the type of the drive signal corresponding thereto; The testing unit is configured to perform a testing operation on each of the target devices under test using the driving signal.

9. The testing device according to claim 8, characterized in that The signal generating unit includes an algorithmic pattern generator or a vector driver.

10. The testing device according to claim 8, characterized in that The integrated circuit testing device further includes a power supply, wherein the power supply is connected to the processor and controlled by the processor; The power supply is used to provide power to the target device under test under the control of the processor.

11. The testing device according to claim 8, characterized in that The integrated circuit testing equipment includes an aging testing equipment.

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