On-chip semiconductor transformer model, modeling method, device and storage medium

Abstract

The present invention discloses an on-chip semiconductor transformer model, modeling method, device and storage medium, wherein the model includes four parts: the first part is a series branch that characterizes the inductance and resistance characteristics of the primary and secondary coils of the transformer; the second part is the mutual inductance that characterizes the magnetic field coupling effect between the primary and secondary coils of the transformer and within the primary and secondary coils; the third part is the parasitic capacitance that characterizes the capacitive coupling effect between the primary and secondary coils of the transformer; and the fourth part is a substrate loss network that characterizes the substrate loss effect of the transformer. The present invention replaces the traditional CRC substrate loss network with a trapezoidal substrate loss network, and establishes an on-chip transformer model based on this. The trapezoidal substrate loss network used can better fit the loss characteristics of the gallium arsenide substrate, so that the on-chip semiconductor transformer model meets multiple processes. The present invention can be widely used in the field of passive device modeling in millimeter wave integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of passive device modeling in millimeter wave integrated circuits, and in particular to an on-chip semiconductor transformer model, a modeling method, a device and a storage medium. Background Art

[0002] With the continuous advancement of circuit manufacturing processes (such as silicon-based and gallium arsenide processes), the size of on-chip integrated circuits (ICs) is shrinking, and their operating frequencies are gradually entering the millimeter-wave band. In integrated circuit systems, on-chip transformers are widely used to implement functions such as impedance transformation, single-ended to differential conversion, and power combining. Specifically, they are used in circuit modules such as power amplifiers, power dividers, and oscillators. However, as operating frequencies increase significantly, parasitic effects in the circuits also increase significantly. This increase is not only reflected within the device and between devices, but also between the device and the semiconductor substrate. To improve the analysis and optimization efficiency of these circuit modules, it is particularly important to establish an accurate on-chip transformer model. Key performance indicators of transformers include insertion loss, coupling coefficient, and the quality factor of the primary and secondary windings. The quality factor is a good indicator of the model's fit.

[0003] In order to establish an accurate transformer model suitable for the millimeter wave frequency band, many different types of modeling schemes have been proposed in recent years, but the existing on-chip semiconductor transformer models cannot meet the needs of various processes. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, an object of the present invention is to provide an on-chip semiconductor transformer model, a modeling method, an apparatus and a storage medium.

[0005] The technical solution adopted in the present invention is:

[0006] An on-chip semiconductor transformer model, wherein the on-chip semiconductor transformer model is a six-port transformer model including four parts;

[0007] The first part is a series branch that characterizes the inductance and resistance characteristics of the primary and secondary coils of the transformer; each coil includes two series branches symmetrical about a common terminal, and the common terminal is the center tap of the coil; each of the series branches has a series inductor L 0x , a series resistor R 0x , and three series RL parallel networks;

[0008] The second part is the mutual inductance that characterizes the magnetic field coupling effect between the primary and secondary coils of the transformer and within the primary and secondary coils; the six-port transformer model includes the magnetic field coupling between each series branch;

[0009] The third part is the parasitic capacitance that characterizes the capacitive coupling effect between the primary and secondary coils of the transformer; parasitic capacitance is introduced between each port of the primary and secondary coils of the six-port transformer model;

[0010] The fourth part is the substrate loss network that characterizes the transformer substrate loss effect. A ladder-shaped substrate loss network is connected in parallel at each port of the transformer model. Each ladder-shaped substrate loss network consists of a parallel capacitor C subi0 , a parallel conductance G subi0 , and four parallel GC series structures.

[0011] Furthermore, in the first part, the series inductance and series resistance represent the inductive and resistive characteristics of the metal coil at high and low frequencies, respectively; the three series RL parallel networks represent the skin effect and proximity effect of the metal coil over a wide frequency band;

[0012] In the second part, the magnetic field coupling between each series branch is expressed by mutual inductance M 12 , M 13 , M 14 , M 23 , M 24 , M 34 express;

[0013] In the third part, there are 9 parasitic capacitors, represented by C 13 , C 14 , C 16 , C 23 , C 24 , C 26 , C 35 , C 45 and C 56 express;

[0014] In the fourth part, the GC tandem structure includes G subij and C subij , where i = 1, 2, 3, 4, 5, 6 and j = 1, 2, 3, 4.

[0015] Another technical solution adopted in the present invention is:

[0016] A modeling method for the on-chip semiconductor transformer model described above includes the following steps:

[0017] S1. Establish the transformer layout structure according to the preset design parameters;

[0018] S2. Set a port at each of the six terminals of the transformer and then perform EM simulation on the structure;

[0019] S3, converting the S parameter matrix obtained by EM simulation into a Y parameter matrix;

[0020] S4. Based on the equivalent circuit model, establish the relationship between the Y parameter matrix and the impedance or admittance of each part of the transformer model;

[0021] S5. Select fitting frequency points based on the equivalent circuit model and the relationship established in step S4, and extract lumped model parameters of the mutual inductance, parasitic capacitance, series branch, and trapezoidal substrate loss network;

[0022] S6. Establish an equivalent circuit in ADS software based on the extracted lumped model parameters;

[0023] S7. Verify the six-port fit of the transformer model according to the established equivalent circuit, and verify the first indicator;

[0024] S8, judging whether the six-port fitting degree meets the requirements. If so, further verify the two-port fitting degree of the model. Otherwise, return to S5 and adjust the fitting frequency point.

[0025] S9. Verify the two-port fit of the transformer model based on the established equivalent circuit and verify the second indicator.

[0026] Furthermore, the parameters of the trapezoidal substrate loss network are extracted by:

[0027] After EM simulation and parameter conversion, the six-port Y parameter matrix satisfies:

[0028] y i =Y 1i +Y 2i +Y 3i +Y 4i +Y 5i +Y 6i (1)

[0029] The substrate loss characteristics at port i are calculated according to formula (1);

[0030] Considering that the adopted ladder substrate loss network has a total of four parallel GC series structures, four frequency points need to be selected for fitting. These four fitting frequency points are represented by angular frequencies from small to large as ω1, ω2, ω3, and ω4;

[0031] Considering the trapezoidal substrate loss network, the conductance and capacitance can be written as:

[0032]

[0033] According to formula (2) (3) and the selected fitting frequency points, the following equations are obtained:

[0034]

[0035] All parameters of the trapezoidal substrate loss network are obtained by solving formulas (4)-(13).

[0036] Furthermore, the selection strategy of the fitting frequency point is as follows:

[0037] 1) Obtain a curve of substrate conductivity at port i versus frequency, and select four fitting frequency points on the curve;

[0038] 2) Select ω1 as the first simulation frequency point, and the selection of ω2, ω3, and ω4 should ensure that the conductivity curve of the substrate model is effectively fitted within the self-resonant frequency range and satisfies (ω2-ω1)≤(ω3-ω2)≤(ω4-ω3).

[0039] Furthermore, the first indicator in step S7 includes mutual inductance, parasitic capacitance, inductance and resistance of the series branch, and capacitance and conductance of the ladder substrate loss network.

[0040] Furthermore, the second indicator in step S9 includes a dual-port S parameter, a quality factor, and a coupling coefficient.

[0041] Another technical solution adopted in the present invention is:

[0042] A modeling device comprising:

[0043] at least one processor;

[0044] at least one memory for storing at least one program;

[0045] When the at least one program is executed by the at least one processor, the at least one processor implements the above method.

[0046] Another technical solution adopted in the present invention is:

[0047] A computer-readable storage medium stores a program executable by a processor, wherein the program executable by the processor is used to perform the method described above when executed by the processor.

[0048] The beneficial effects of the present invention are: the present invention replaces the traditional CRC substrate loss network with a trapezoidal substrate loss network, and establishes an on-chip transformer model on this basis. The adopted trapezoidal substrate loss network can better fit the loss characteristics of the gallium arsenide substrate, so that the on-chip semiconductor transformer model meets multiple processes (such as silicon-based process and gallium arsenide process). BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present invention or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 is a schematic diagram of an on-chip semiconductor transformer model in an embodiment of the present invention;

[0051] Figure 2 is a flow chart of a modeling method according to an embodiment of the present invention;

[0052] Figure 3 1 is a schematic diagram of the layout of a 1:2 transformer with a planar symmetrical non-interwinding structure according to an embodiment of the present invention;

[0053] Figure 4 2 is a comparative schematic diagram of the substrate admittance fitting effect at port 1 in an embodiment of the present invention;

[0054] Figure 5 2 is a comparative schematic diagram of the open-circuit quality factor fitting effect of the transformer primary coil in an embodiment of the present invention;

[0055] Figure 6 : is a diagram showing the fitting effect of the behavioral substrate loss model on the substrate loss in an embodiment of the present invention; wherein, Figure 6 (a) is the fitting effect of the behavioral substrate loss model on the substrate conductivity. Figure 6 (b) The fitting effect of the behavioral substrate loss model on the substrate capacitance. DETAILED DESCRIPTION

[0056] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided for ease of explanation only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0057] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0058] In the description of the present invention, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0059] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0060] According to the number of ports, the modeling schemes can be divided into four-port transformer and six-port transformer. According to the parameter extraction method, the modeling schemes can be divided into closed-form equation-based and network parameter-based.

[0061] Existing document 1 proposes a scalable CMOS process on-chip transmission line and inductance model. The transmission line model is designed as a single π structure, including a series branch that characterizes the metal conductor loss characteristics and a substrate loss network at two ports. The series branch consists of a series inductor (characterizing the high-frequency inductance characteristics of the metal conductor), a series resistor (characterizing the low-frequency resistance characteristics of the metal conductor), and multiple series resistor-inductor parallel structures (characterizing the skin effect and proximity effect of the metal conductor); the substrate loss network at the port consists of a parallel capacitor and multiple parallel conductor-capacitor series structures. Because the shape of this substrate network is similar to a horizontally placed ladder, the present invention refers to it as a ladder-shaped substrate loss network. The series branch and substrate loss network of the proposed model are dual structures to each other, and each resistor-inductor parallel (conductor-capacitor series) structure corresponds to a fitting frequency point. After selecting the appropriate fitting frequency point, the model can effectively fit the transmission line characteristics to the millimeter wave band.

[0062] The network proposed in existing document 1 is essentially a numerical fitting structure that can be used to fit the substrate loss characteristics of various processes. However, existing document 1 only provides a rough parameter extraction method for the network. This method can meet the needs of fitting the substrate loss characteristics of CMOS processes. However, for gallium arsenide substrates, whose loss characteristics vary more dramatically with frequency, the accuracy of this parameter extraction method is still lacking.

[0063] Existing Reference 2 proposes a network parameter-based silicon-based millimeter-wave six-port transformer model. This model introduces center taps on both the primary and secondary coils and considers electromagnetic coupling between the various coil components. This model uses the series branch structure of the transmission line model from Existing Reference 1 to characterize the coil loss characteristics, which includes a three-resistance-inductance parallel structure. The traditional CRC substrate loss model is used at all six ports to characterize the transformer substrate loss characteristics. Furthermore, the model introduces parasitic capacitance between the primary and secondary coils, which is represented by a lumped capacitor connected between the two ports. In the existing literature 2, two CMOS process low-turns-ratio stacked structure transformers were established to verify the model fit. One transformer has a turns ratio of 1:1, and the primary and secondary coil line widths are both 10um. The other transformer has a turns ratio of 1:2, and the primary and secondary coil line widths are 8um and 3um, respectively. The outer diameters of the primary and secondary coils of the two transformers are equal and both less than 50um. The primary coil is located on the M8 layer, and the secondary coil is located on the M9 layer. The established transformer model can well fit the loss characteristics of these two transformers to the millimeter wave frequency band.

[0064] The transformer model in existing literature 2 uses a traditional CRC substrate loss network. This structure effectively fits the conductance and capacitance characteristics of CMOS process substrate losses, which tend to be stable at high frequencies. However, in GaAs processes, both conductance and capacitance increase with increasing frequency, and the rate of increase is increasingly rapid. Continuing to use the traditional CRC substrate model to fit these substrate loss characteristics has significant limitations. Consequently, the overall transformer model fit results in significant errors, and these errors increase with increasing transformer dimensions (line width, line spacing, and outer diameter).

[0065] like Figure 1 As shown, this embodiment provides an on-chip semiconductor transformer model, which consists of four parts:

[0066] The first part is the series branch that characterizes the inductance and resistance characteristics of the primary and secondary coils of the transformer. Each coil contains two series branches symmetrical about the common terminal, which is the center tap of the coil. Each series branch has a series inductor L 0x , a series resistor R 0x , and three series RL parallel networks (R ix and L ix ), where x = a, b, c, d, and i = 1, 2, 3. The series inductor and series resistor represent the inductive and resistive characteristics of the metal coil at high and low frequencies, respectively. The three series RL parallel networks represent the skin effect and proximity effect of the metal coil over a wide frequency band.

[0067] The second part is the mutual inductance that characterizes the magnetic field coupling effect between the primary and secondary coils of the transformer and within the primary and secondary coils. The proposed six-port transformer model includes the magnetic field coupling between each series branch, which is represented by the mutual inductance M. 12 , M 13 , M 14 , M 23 , M 24 , M 34 express.

[0068] The third part is the parasitic capacitance that characterizes the capacitive coupling effect between the primary and secondary coils of the transformer. The proposed six-port transformer model introduces parasitic capacitance between each port of the primary and secondary coils, which are represented by C 13 , C 14 , C 16 , C 23 , C 24 , C 26 , C 35 , C 45 and C 56 A total of 9 capacitors are represented.

[0069] The fourth part is the substrate loss network that characterizes the transformer substrate loss effect. A ladder-shaped substrate loss network is connected in parallel at each port of the proposed transformer model. Each substrate loss network consists of a parallel capacitor C subi0 , a parallel conductance G subi0 , and four parallel GC series structures (G subij and C subij ), where i = 1, 2, 3, 4, 5, 6, j = 1, 2, 3, 4.

[0070] like Figure 2 As shown, this embodiment provides a Figure 1 The modeling method of the on-chip semiconductor transformer model shown in FIG. 1 includes the following steps:

[0071] S1. Create the transformer layout structure in ADS software according to the design parameters;

[0072] S2. Set a port at each of the six terminals of the transformer (including the two center taps on the primary and secondary windings), and then perform EM simulation on the structure.

[0073] S3, converting the S parameter matrix obtained by simulation into a Y parameter matrix;

[0074] S4. Based on the equivalent circuit model, establish the relationship between the Y parameter matrix and the impedance or admittance of each part of the model;

[0075] S5. According to the equivalent circuit model and the established relationship, select the appropriate fitting frequency point and extract the lumped model parameters of the mutual inductance, parasitic capacitance, series branch and substrate loss network in sequence;

[0076] S6. Establish an equivalent circuit model in ADS software based on the extracted model parameters;

[0077] S7. Verify the six-port goodness of fit of the model. The verification indicators include mutual inductance, parasitic capacitance, inductance and resistance of the series branch, and capacitance and conductance of the substrate loss network.

[0078] S8. Determine whether the six-port fit meets the requirements. If so, further verify the two-port fit of the model. Otherwise, adjust the fitting frequency point and return to S5.

[0079] S9. Verify the two-port goodness of fit of the model. The verification indicators include two-port S parameters, quality factor, and coupling coefficient. Among them, the quality factor has the advantages of high sensitivity and easy observation, and is therefore most suitable for verifying the two-port goodness of fit of the model.

[0080] The following is a detailed explanation of the parameter extraction method of the trapezoidal substrate loss network.

[0081] In S5, the three parameters of the transformer model, namely mutual inductance, parasitic capacitance, and series branch, can be extracted using existing methods, so they will not be explained here. The following describes the parameter extraction method for the trapezoidal substrate loss network:

[0082] First, the six-port Y parameter matrix extracted by simulation satisfies:

[0083] y i =Y 1i +Y 2i +Y 3i +Y 4i +Y 5i +Y 6i (1)

[0084] Where i = 1, 2, 3, 4, 5, 6, so the substrate loss characteristics at port i can be calculated using formula (1).

[0085] Secondly, considering that the substrate loss network used has a total of four parallel GC series structures, a total of four frequency points need to be selected for fitting. These four fitting frequency points can be represented by angular frequencies from small to large as ω1, ω2, ω3, and ω4.

[0086] The strategy for selecting the fitting frequency point is: 1) draw a curve of the substrate conductivity at port i as a function of frequency, i.e. Re(y i), and then select four fitting frequency points on the curve. The reason for choosing substrate conductance instead of capacitance as the fitting object is that the amplitude of substrate conductance change is much larger than that of substrate capacitance change; 2) Usually ω1 is selected as the first simulation frequency point (the starting point of the simulation is generally 1 GHz), and the selection of ω2, ω3, and ω4 should try to ensure the smoothness of the fitting curve (that is, the curve formed by connecting the four fitting frequency points in sequence with line segments) within the self-resonance frequency range, and try to satisfy (ω2-ω1)≤(ω3-ω2)≤(ω4-ω3).

[0087] Finally, the conductance and capacitance taking into account the substrate loss model can be written as:

[0088]

[0089]

[0090] According to formula (2) (3) and the selected fitting frequency points, the following equations are obtained:

[0091]

[0092] The equation group contains a total of 10 equations and 10 unknowns. Based on formulas (4)-(13), Mathematica software can be used to solve the equation group to obtain all the parameters in the substrate loss model.

[0093] In summary, based on the published silicon-based six-port transformer model, this paper adopts an improved trapezoidal substrate loss network to replace the traditional CRC substrate loss network. On this basis, an on-chip transformer model is established. The adopted trapezoidal substrate loss network can better fit the loss characteristics of the GaAs substrate. The following is analyzed in conjunction with the following examples:

[0094] Transformers used to validate model fit such as Figure 3 As shown in the figure, the transformer is a GaAs-based planar symmetrical structure transformer with the primary coil located on the outside and the secondary coil located on the inside. The turns ratio is 1:2, the line width and line spacing are both 12um, and the outer diameter is 168um. The open-circuit self-resonant frequency of the transformer is lower than 40GHz, so the fitting frequency points of the substrate loss network can be selected as 1GHz, 10GHz, 20GHz, and 40GHz. The comparison of the substrate admittance fitting effect at port 1 is shown in the figure. Figure 4As shown in FIG, the objects used for comparison include EM simulation results, the trapezoidal substrate loss model used in this embodiment, and the traditional CRC model used in existing document 2. It can be seen that the trapezoidal substrate loss model used in this embodiment can ensure effective fitting within 40 GHz (within the open circuit self-resonant frequency range), while the traditional CRC substrate model cannot be effectively fitted because its conductivity characteristics are completely different from those of the GaAs substrate. Figure 5 As shown, the calculation formula for the open circuit quality factor is

[0095]

[0096] The objects used for comparison include EM simulation results, the model proposed in this embodiment, the model in existing document 2, and the reference model. Among them, the parameters of the mutual inductance, series branch, and parasitic capacitance of the reference model are consistent with the previous two models. Only the substrate loss network is replaced by a behavioral level model. This behavioral level model can perfectly fit the loss characteristics of the GaAs substrate under the premise of basically ensuring passivity and reciprocity, such as Figure 6 As shown, the reference model can at least ensure that the best fitting effect is achieved when the mutual inductance, series branch and parasitic capacitance parameters of the model remain unchanged. It can be seen that the model proposed in this embodiment and the reference model almost overlap in the range of 1 to 40 GHz, indicating that the proposed transformer model can ensure the best fitting effect in the open-circuit self-resonant frequency range. At the same time, it is not difficult to find that the peak values ​​and zero crossing points of the model proposed in this embodiment, the reference model and the EM simulation results are almost at the same frequency point, while the peak values ​​and zero crossing points of the model proposed in the existing document 2 and the EM simulation results have a large deviation, indicating that the model proposed in this embodiment can better fit the loss characteristics of the GaAs-based transformer.

[0097] This embodiment also provides a modeling device, including:

[0098] at least one processor;

[0099] at least one memory for storing at least one program;

[0100] When the at least one program is executed by the at least one processor, the at least one processor implements the following Figure 2 The method shown.

[0101] A modeling device of this embodiment can execute a modeling method provided by the method embodiment of the present invention, can execute any combination of implementation steps of the method embodiment, and has the corresponding functions and beneficial effects of the method.

[0102] The present application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs Figure 2 The method shown.

[0103] This embodiment also provides a storage medium that stores instructions or programs that can execute a modeling method provided by an embodiment of the method of the present invention. When the instructions or program are run, any combination of implementation steps of the method embodiment can be executed, and the corresponding functions and beneficial effects of the method can be obtained.

[0104] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0105] Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise indicated, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It will also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, a person skilled in the art using ordinary skill will be able to implement the present invention set forth in the claims without undue experimentation. It will also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0106] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0107] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0108] More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0109] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0110] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0111] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0112] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. An on-chip semiconductor transformer model, characterized in that: The on-chip semiconductor transformer model is a six-port transformer model, comprising four parts; The first part is a series branch that characterizes the inductance and resistance characteristics of the primary and secondary coils of the transformer; each coil includes two series branches symmetrical about a common terminal, and the common terminal is the center tap of the coil; each of the series branches has a series inductor L 0x , a series resistor R 0x , and three series RL parallel networks; The second part is the mutual inductance that characterizes the magnetic field coupling effect between the primary and secondary coils of the transformer and within the primary and secondary coils; the six-port transformer model includes the magnetic field coupling between each series branch; The third part is the parasitic capacitance that characterizes the capacitive coupling effect between the primary and secondary windings of the transformer; A parasitic capacitance is introduced between each port of the primary and secondary coils of the six-port transformer model; The fourth part is the substrate loss network that characterizes the transformer substrate loss effect. A ladder-shaped substrate loss network is connected in parallel at each port of the transformer model. Each ladder-shaped substrate loss network consists of a parallel capacitor C subi0 , a parallel conductance G subi0 , and four parallel GC series structures, the GC series structure includes G subij and C subij , where i=1,2,3,4,5,6, j＝1,2,3,4； The parameters of the ladder substrate loss network are extracted by: After EM simulation and parameter conversion, the six-port Y parameter matrix satisfies: y i =Y 1i +Y 2i +Y 3i +Y 4i +Y 5i +Y 6i (1) Calculate the substrate loss characteristics at port i according to formula (1); Considering that the adopted ladder substrate loss network has a total of four parallel GC series structures, four frequency points need to be selected for fitting. These four fitting frequency points are represented by angular frequencies from small to large as ω1, ω2, ω3, and ω4; Considering the trapezoidal substrate loss network, the conductance and capacitance can be written as: According to formula (2) (3) and the selected fitting frequency points, the following equations are obtained: All parameters of the trapezoidal substrate loss network are obtained by solving formulas (4)-(13).

2. The on-chip semiconductor transformer model according to claim 1, characterized in that: In the first part, the series inductor and series resistor represent the inductive and resistive characteristics of the metal coil at high and low frequencies, respectively; the three series RL parallel networks represent the skin effect and proximity effect of the metal coil over a wide frequency band; In the second part, the magnetic field coupling between each series branch is expressed by mutual inductance M 12 , M 13 , M 14 , M 23 , M 24 , M 34 express; In the third part, there are 9 parasitic capacitors, represented by C 13 , C 14 , C 16 , C 23 , C 24 , C 26 , C 35 , C 45 and C 56 express.

3. A modeling method for an on-chip semiconductor transformer model according to claim 1 or 2, characterized in that: The following steps are involved: S1. Establish the transformer layout structure according to the preset design parameters; S2. Set a port at each of the six terminals of the transformer and then perform EM simulation on the structure; S3, converting the S parameter matrix obtained by EM simulation into a Y parameter matrix; S4. Based on the equivalent circuit model, establish the relationship between the Y parameter matrix and the impedance or admittance of each part of the transformer model; S5. Select fitting frequency points based on the equivalent circuit model and the relationship established in step S4, and extract lumped model parameters of the mutual inductance, parasitic capacitance, series branch, and trapezoidal substrate loss network; S6. Establish an equivalent circuit in ADS software based on the extracted lumped model parameters; S7. Verify the six-port fit of the transformer model according to the established equivalent circuit, and verify the first indicator; S8, judging whether the six-port fitting degree meets the requirements, if so, further verifying the two-port fitting degree of the model, otherwise, returning to S5 and adjusting the fitting frequency point; S9. Verify the two-port fit of the transformer model based on the established equivalent circuit and verify the second indicator.

4. A modeling method according to claim 3, characterized in that: In step S5, the parameters of the trapezoidal substrate loss network are extracted by: After EM simulation and parameter conversion, the six-port Y parameter matrix satisfies: y i =Y 1i +Y 2i +Y 3i +Y 4i +Y 5i +Y 6i (1) Calculate the substrate loss characteristics at port i according to formula (1); Considering that the adopted ladder substrate loss network has a total of four parallel GC series structures, four frequency points need to be selected for fitting. These four fitting frequency points are represented by angular frequencies from small to large as ω1, ω2, ω3, and ω4; Considering the trapezoidal substrate loss network, the conductance and capacitance can be written as: According to formula (2) (3) and the selected fitting frequency points, the following equations are obtained: All parameters of the trapezoidal substrate loss network are obtained by solving formulas (4)-(13).

5. A modeling method according to claim 4, characterized in that: The selection strategy of the fitting frequency points is as follows: 1) Obtain a curve of substrate conductivity at port i versus frequency, and select four fitting frequency points on the curve; 2) Select ω1 as the first simulation frequency point, and the selection of ω2, ω3, and ω4 should ensure that the conductivity curve of the substrate model is effectively fitted within the self-resonant frequency range and satisfies (ω2-ω1)≤(ω3-ω2)≤(ω4-ω3).

6. A modeling method according to claim 3, characterized in that: The first indicator in step S7 includes mutual inductance, parasitic capacitance, inductance and resistance of the series branch, and capacitance and conductance of the ladder substrate loss network.

7. A modeling method according to claim 3, characterized in that: The second indicators in step S9 include dual-port S parameters, quality factors, and coupling coefficients.

8. A modeling device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 3 to 7.

9. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 3 to 7 when executed by the processor.

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