Scan driving circuit and display panel

Abstract

Embodiments of the present application disclose a scanning driving circuit and a display panel. The scanning driving circuit comprises an input control module, a first mutual control module, a reverse control module, a first stabilizing module, a second stabilizing module, a first output module and a second output module. The first output module further accesses a first threshold voltage adjusting signal, the level of the first threshold voltage adjusting signal being opposite to that of the first level signal; and / or the second output module further accesses a second threshold voltage adjusting signal, the level of the second threshold voltage adjusting signal being opposite to that of the second level signal. Compared with the prior art, the present application can overcome the problem of threshold voltage drift of the transistor in the prior scanning driving circuit, so that the transistor in the scanning driving circuit can be reliably turned on or turned off, the output of the driving circuit is more stable, and thus the stability of the display panel display is improved.

Description

Technical Field

[0001] The present invention relates to display technology, and more particularly to a scanning driving circuit and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming increasingly wide, and people's requirements for display panels are also getting higher and higher. The reliable operation of the scanning drive circuit plays a crucial role in the stable display of the display panel. However, the transistors in the existing scanning drive circuit have the problem of threshold voltage drift, which can cause the transistors to fail to reliably turn on or off, resulting in unstable output of the scanning drive circuit and affecting the stability of the display panel. Summary of the Invention

[0003] This invention provides a scanning drive circuit and a display panel to improve the reliability of the output of the scanning drive circuit and enhance the stability of the display panel.

[0004] To achieve the above technical objectives, the embodiments of the present invention provide the following technical solutions:

[0005] A scanning drive circuit includes: an input control module, a first mutual control module, an inverting control module, a first stabilizing module, a second stabilizing module, a first output module, and a second output module;

[0006] The input control module is connected to the first output module and is used to control the first output module to be turned on, so that the first output module outputs a first level signal;

[0007] The first mutual control module is connected to the input control module and to the reverse control module; the reverse control module is also connected to the second output module; the first mutual control module is used to turn on under the control of the input control module and transmit control signals to the reverse control module so that the reverse control module controls the second output module to turn off.

[0008] The first stabilization module is connected to the reverse control module. The first stabilization module is used to control the reverse control module to generate a control signal when the first mutual control module is disconnected, so that the reverse control module controls the second output module to be turned on, and the second output module outputs a second level signal.

[0009] The second stabilizing module is connected to the first stabilizing module and to the first output module; the second stabilizing module is used to control the first output module to disconnect when the first mutual control module is disconnected, according to the control of the first stabilizing module.

[0010] The first output module is further connected to a first threshold voltage adjustment signal, the first threshold voltage adjustment signal being opposite in level to the first level signal; and / or, the second output module is further connected to a second threshold voltage adjustment signal, the second threshold voltage adjustment signal being opposite in level to the second level signal.

[0011] Optionally, the first output module includes:

[0012] The first dual-gate transistor has its interconnection node of the input control module, the second stabilization module, and the first mutual control module connected to its first gate. The second gate of the first dual-gate transistor is connected to a first threshold voltage adjustment signal. The first terminal of the first dual-gate transistor is connected to a first level signal. The second terminal of the first dual-gate transistor is connected to the first output terminal of the scan drive circuit.

[0013] Preferably, the first dual-gate transistor is an N-type transistor, the first level signal is a high-level signal, and the first threshold voltage adjustment signal is a low-level signal.

[0014] Optionally, the second output module includes:

[0015] The second dual-gate transistor has its first gate connected to the inverting control module and its second gate connected to a second threshold voltage adjustment signal. The first terminal of the second dual-gate transistor is connected to a second level signal and its second terminal is connected to the first output terminal of the scan drive circuit.

[0016] The first capacitor has its first plate connected to the first gate of the second dual-gate transistor, and its second plate connected to the second electrode of the second dual-gate transistor.

[0017] Preferably, the second dual-gate transistor is an N-type transistor, the second level signal is a low-level signal, and the second threshold voltage adjustment signal is a high-level signal.

[0018] Optionally, the second stabilization module is further connected to the first threshold voltage adjustment signal, and the second stabilization module includes:

[0019] The third transistor is connected to the gate of the interconnection node of the first stabilization module, the first mutual control module and the reverse control module, and the first terminal of the third transistor is connected to the second level signal.

[0020] The second capacitor has its first plate connected to the second terminal of the third transistor, and its second plate connected to the first output module.

[0021] The fourth dual-gate transistor has its interconnection node of the input control module, the first mutual control module, and the first output module connected to its first gate. The second gate of the fourth dual-gate transistor is connected to the first threshold voltage adjustment signal. The first terminal of the fourth dual-gate transistor is connected to the first clock signal. The second terminal of the fourth dual-gate transistor is connected to the first plate of the second capacitor.

[0022] Preferably, both the third transistor and the fourth dual-gate transistor are N-type transistors, and the first threshold voltage adjustment signal is a low-level signal.

[0023] Optionally, the first mutual control module is further connected to a first threshold voltage adjustment signal, and the first mutual control module includes:

[0024] The interconnection nodes of the input control module, the second stabilization module, and the first output module of the fifth dual-gate transistor are connected to the first gate of the fifth dual-gate transistor. The second gate of the fifth dual-gate transistor is connected to the first threshold voltage adjustment signal. The first terminal of the fifth dual-gate transistor is connected to the second clock signal. The interconnection nodes of the first stabilization module, the second stabilization module, and the reverse control module are connected to the second terminal of the fifth dual-gate transistor.

[0025] Preferably, the fifth dual-gate transistor is an N-type transistor, and the first threshold voltage adjustment signal is a low-level signal;

[0026] Preferably, the fifth dual-gate transistor further includes a third gate and a fourth gate, the third gate of the fifth dual-gate transistor is connected to the first gate, and the fourth gate of the fifth dual-gate transistor is connected to the second gate; the fifth dual-gate transistor is equivalent to two dual-gate transistors connected in series.

[0027] Optionally, the first stabilization module is further connected to a first threshold voltage adjustment signal, and the first stabilization module includes:

[0028] The seventh dual-gate transistor has a first gate connected to a second clock signal, a second gate connected to a first threshold voltage adjustment signal, and a first terminal connected to a first level signal. The interconnection nodes of the first mutual control module, the reverse control module, and the second stabilization module are connected to the second terminal of the seventh dual-gate transistor.

[0029] Preferably, the seventh dual-gate transistor is an N-type transistor, the first level signal is a high-level signal, and the first threshold voltage adjustment signal is a low-level signal.

[0030] Optionally, the input control module includes:

[0031] The eighth transistor has a gate connected to a second clock signal and a first terminal connected to an input signal. The interconnection nodes of the first mutual control module, the second stabilization module, and the first output module are connected to the second terminal of the eighth transistor.

[0032] Preferably, the eighth transistor is an N-type transistor, and the input signal is a high-low level pulse signal.

[0033] Optionally, the reverse control module includes:

[0034] The ninth transistor is connected to the gate of the first stabilization module, the first mutual control module and the second stabilization module. The first terminal of the ninth transistor is connected to the first clock signal, and the second terminal of the ninth transistor is connected to the second output module.

[0035] The third capacitor has its first plate connected to the gate of the ninth transistor and its second plate connected to the second terminal of the ninth transistor.

[0036] Preferably, the ninth transistor is an N-type transistor.

[0037] Optionally, the scan drive circuit further includes:

[0038] The second mutual control module is connected to the input control module, the second mutual control module is connected to the second output module, and the second mutual control module is also connected to the first threshold voltage adjustment signal; the second mutual control module is used to be turned on under the control of the input control module to control the second output module to be turned off.

[0039] Preferably, the second mutual control module includes: a sixth dual-gate transistor, the interconnection node of the input control module, the second stabilization module, the first mutual control module and the first output module is connected to the first gate of the sixth dual-gate transistor, the second gate of the sixth dual-gate transistor is connected to a first threshold voltage adjustment signal, the first terminal of the sixth dual-gate transistor is connected to a second level signal, and the interconnection node of the second output module and the reverse control module is connected to the second terminal of the sixth dual-gate transistor.

[0040] Preferably, the sixth dual-gate transistor is an N-type transistor, the second level signal is a low-level signal, and the first threshold voltage adjustment signal is a low-level signal.

[0041] Accordingly, the present invention also provides a display panel comprising a plurality of cascaded scanning drive circuits as described in any embodiment of the present invention.

[0042] In this embodiment of the invention, by connecting the first output module to a first threshold voltage adjustment signal, the threshold voltage of the transistor in the first output module can be adjusted using the first threshold voltage adjustment signal, thereby enabling the first output module to reliably turn on or off. Similarly, by connecting the second output module to a second threshold voltage adjustment signal, the threshold voltage of the transistor in the second output module can be adjusted using the second threshold voltage adjustment signal, thereby enabling the second output module to reliably turn on or off. In summary, compared to the prior art, this invention overcomes the problem of threshold voltage drift in transistors in existing scan driving circuits, enabling the transistors in the scan driving circuit to reliably turn on or off, making the output of the driving circuit more stable, and thus improving the stability of the display panel. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0053] Figures 10-21 A schematic diagram of the switching states and corresponding timing of a scanning drive circuit at each stage, provided for an embodiment of the present invention;

[0054] Figure 22 This is a schematic diagram of a cascaded scanning drive circuit provided in an embodiment of the present invention. Detailed Implementation

[0055] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the term "comprising" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] This invention provides a scanning drive circuit. Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention. See also: Figure 1 The scanning drive circuit includes: an input control module 110, a first mutual control module 120, an inverse control module 130, a first stabilization module 140, a second stabilization module 150, a first output module 160, and a second output module 170.

[0058] The input control module 110 is connected to the first output module 160 and is used to control the first output module 160 to be turned on, and the first output module 160 outputs a first level signal.

[0059] The first mutual control module 120 is connected to the input control module 110 and to the reverse control module 130; the reverse control module 130 is also connected to the second output module 170; the first mutual control module 120 is used to turn on under the control of the input control module 110 and transmit control signals to the reverse control module 130 so that the reverse control module 130 controls the second output module 170 to turn off.

[0060] The first stabilizing module 140 is connected to the reverse control module 130. The first stabilizing module 140 is used to control the reverse control module 130 to generate a control signal when the first mutual control module 120 is disconnected, so that the reverse control module 130 controls the second output module 170 to be turned on, and the second output module 170 outputs a second level signal.

[0061] The second stabilization module 150 is connected to the first stabilization module 140 and the second stabilization module 150 is connected to the first output module 160; the second stabilization module 150 is used to control the first output module 160 to disconnect when the first mutual control module 120 is disconnected according to the control of the first stabilization module 140.

[0062] The first output module 160 is also connected to a first threshold voltage adjustment signal B1, which is opposite in level to the first level signal; and / or, the second output module 170 is also connected to a second threshold voltage adjustment signal B2, which is opposite in level to the second level signal.

[0063] Specifically, during the first-level signal output period, the input control module 110 directly controls the first output module 160 to turn on, outputting the first-level signal. Simultaneously, the input control module 110 can also directly control the first interconnect module 120 to turn on, transmitting a control signal to the inverting control module 130. This causes the inverting control module 130 to control the second output module 170 to turn off, ensuring that when the first output module 160 is on, the second output module 170 can reliably turn off and cannot output the second-level signal. This ensures that the scan drive circuit reliably outputs the first-level signal.

[0064] During the second-level signal output, the first mutual control module 120 is disconnected, and the first stabilization module 140 controls the inverting control module 130 to generate a control signal, causing the inverting control module 130 to control the second output module 170 to conduct and output the second-level signal. Simultaneously, the second stabilization module 150, under the control of the first stabilization module 140, outputs a control signal, causing the second stabilization module 150 to control the first output module 160 to disconnect, thereby ensuring that the first output module 160 is reliably disconnected and unable to output the first-level signal. This ensures that the scan drive circuit reliably outputs the second-level signal.

[0065] The signal output by the scan driving circuit needs to be sent to the corresponding pixel driving circuit and the next-level scan driving circuit. For example, if the scan driving circuit outputs a second-level signal for an extended period, the first output module 160 in the scan driving circuit will be in a disconnected state for a long time, while the second output module 170 will be in a conducting state for a long time. This will cause threshold voltage drift in the transistors of the first and second output modules 160. In particular, the threshold voltage drift of the transistor in the first output module 160 will prevent the first output module 160 from reliably disconnecting, resulting in unstable output of the scan driving circuit.

[0066] To address the aforementioned issues, the first output module 160 of this solution is further connected to a first threshold voltage adjustment signal B1. By inputting the first threshold voltage adjustment signal B1 to the first output module 160, the threshold voltage of the transistor in the first output module 160 can be adjusted, thereby enabling the first output module 160 to reliably conduct under the control of the input control module 110 and to reliably disconnect under the control of the first stabilizing module 140 via the second stabilizing module 150. Similarly, the second output module 170 is further connected to a second threshold voltage adjustment signal B2. By inputting the second threshold voltage adjustment signal B2 to the second output module 170, the threshold voltage of the transistor in the second output module 170 can be adjusted, thereby enabling the second output module 170 to reliably conduct under the control of the first stabilizing module 140 via the reverse control module 130 and to reliably disconnect under the control of the input control module 110 via the first mutual control module 120.

[0067] It should be noted that the first threshold voltage adjustment signal B1 is opposite in level to the first level signal. For example, if the voltage of the first level signal output by the first output module 160 is high, then the voltage of the first threshold voltage adjustment signal B1 is low. The second threshold voltage adjustment signal B2 is opposite in level to the second level signal. For example, if the voltage of the second level signal output by the second output module 170 is low, then the voltage of the second threshold voltage adjustment signal B2 is high.

[0068] In summary, this solution, by connecting the first threshold voltage adjustment signal B1 to the first output module 160 and the second threshold voltage adjustment signal B2 to the second output module 170, can overcome the problem of threshold voltage drift in the transistors of the existing scanning drive circuit, enabling the transistors in the scanning drive circuit to reliably turn on or off, making the output of the drive circuit more stable, thereby improving the stability of the display panel.

[0069] Continue to refer to Figure 1To facilitate the description of the working principle of the scanning drive circuit, the interconnection node between the input control module 110, the first mutual control module 120, the second stabilization module 150, and the first output module 160 is defined as the first node N1; the interconnection node between the inverting control module 130 and the second output module 170 is defined as the second node N2; and the interconnection node between the first stabilization module 140, the first mutual control module 120, the second stabilization module 150, and the inverting control module 130 is defined as the third node N3. All transistors are N-type transistors, fabricated using metal-oxide-semiconductor (MODS) technology, specifically indium gallium zinc oxide (IGZO).

[0070] Based on the above embodiments, optionally, Figure 2 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 2 The first output module 160 includes a first dual-gate transistor M1. The interconnection node of the input control module, the second stabilization module, and the first mutual control module is connected to the first gate of the first dual-gate transistor M1, that is, the first gate of the first dual-gate transistor M1 is connected to the first node N1. The second gate of the first dual-gate transistor M1 is connected to a first threshold voltage adjustment signal B1, the first terminal of the first dual-gate transistor M1 is connected to a first level signal, and the second terminal of the first dual-gate transistor M1 is connected to the first output terminal Vout of the scan drive circuit.

[0071] The first gate of the first dual-gate transistor M1 can be the top gate or bottom gate (or bottom shielding metal BSM) of the first dual-gate transistor M1, and the second gate of the first dual-gate transistor M1 can be the bottom gate or top gate of the first dual-gate transistor M1. The specific top gate and bottom gate are determined according to the gate setting position.

[0072] For example, if the first dual-gate transistor M1 is an N-type transistor, then the conduction level of the first dual-gate transistor M1 is high. The first level signal is a high-level signal, and the first threshold voltage adjustment signal B1 is a low-level signal. When the first node N1 is high, the first dual-gate transistor M1 is turned on. The first dual-gate transistor M1 outputs the high level VGH of the first level signal, that is, the first output terminal Vout of the scan drive circuit outputs the high level VGH of the first level signal. When the first node N1 is low, the first dual-gate transistor M1 is turned off.

[0073] Furthermore, when the scan drive circuit outputs the second-level signal voltage for an extended period, the first dual-gate transistor M1 remains off for an extended time. Therefore, the threshold voltage of the first dual-gate transistor M1 is prone to negative bias. This causes the first dual-gate transistor M1 to fail to effectively turn off when the second output module 170 outputs the second-level signal voltage. Consequently, the voltage of the first-level signal leaks through the first terminal of the first dual-gate transistor M1 to its second terminal, i.e., to the first output terminal Vout of the scan drive circuit, resulting in an increase in the output voltage at the first output terminal Vout. In this situation, the first threshold voltage adjustment signal B1 needs to be input to the second gate of the first dual-gate transistor M1 to negatively bias it, making the threshold voltage of the first dual-gate transistor M1 positively biased to compensate for the negative bias of the threshold voltage, thereby ensuring the normal output voltage of the first output terminal Vout of the scan drive circuit.

[0074] Based on the above embodiments, optionally, Figure 3 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 3 The second output module 170 includes: a second dual-gate transistor M2 and a first capacitor C1; the first gate of the second dual-gate transistor M2 is connected to the inverting control module 130, and the second gate of the second dual-gate transistor M2 is connected to a second threshold voltage adjustment signal B2; the first terminal of the second dual-gate transistor M2 is connected to a second level signal, and the second terminal of the second dual-gate transistor M2 is connected to the first output terminal Vout of the scan driving circuit; the first plate of the first capacitor C1 is connected to the first gate of the second dual-gate transistor M2, and the second plate of the first capacitor C1 is connected to the second terminal of the second dual-gate transistor M2; optionally, the second dual-gate transistor M2 is an N-type transistor, the second level signal is a low-level signal, and the second threshold voltage adjustment signal B2 is a high-level signal.

[0075] For example, if the second dual-gate transistor M2 is an N-type transistor, then the conduction level of the second dual-gate transistor M2 is high. The voltage of the second level signal is low VGL. When the second node N2 is high, the second dual-gate transistor M2 is turned on. The conduction of the second dual-gate transistor M2 outputs the low level VGL of the second level signal, that is, the first output terminal Vout of the scan drive circuit outputs the low level VGL of the second level signal. During the high level VGL output of the second level signal, the first plate of the first capacitor C1 is high, and the second plate of the second capacitor C2 is low VGL. When the second node N2 is low, the second dual-gate transistor M2 is turned off.

[0076] Furthermore, because the scan drive circuit outputs the second-level signal voltage VGL for an extended period, the second dual-gate transistor M2 remains in a continuously conducting state. Therefore, the threshold voltage of the second dual-gate transistor M2 is prone to forward bias. This causes the second dual-gate transistor M2 to fail to effectively turn off when the first output module 160 outputs the first-level signal. Consequently, the second-level signal leaks through the first terminal of the second dual-gate transistor M2 to its second terminal, i.e., to the first output terminal Vout of the scan drive circuit, resulting in a decrease in the output voltage at the first output terminal Vout. In this case, the second threshold voltage adjustment signal B2 needs to be input to the second gate of the second dual-gate transistor M2 to adjust its threshold voltage, making it negatively biased to compensate for the forward bias and thus ensure the normal output voltage at the first output terminal Vout of the scan drive circuit.

[0077] Based on the above embodiments, optionally, Figure 4 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 4 The second stabilization module 150 is also connected to a first threshold voltage adjustment signal B1. The second stabilization module 150 includes a third transistor M3, a second capacitor C2, and a fourth dual-gate transistor M4. The interconnection node of the first stabilization module 140, the first mutual control module 120, and the reverse control module 130 is connected to the gate of the third transistor M3, that is, the gate of the third transistor M3 is connected to the third node N3. The first terminal of the third transistor M3 is connected to a second level signal; the first plate of the second capacitor C2 is connected to the second terminal of the third transistor M3, and the second plate of the second capacitor C2 is connected to the first output module 160; the interconnection node of the input control module 110, the first mutual control module 120, and the first output module 160 is connected to the first gate of the fourth dual-gate transistor M4, that is, the first gate of the fourth dual-gate transistor M4 is connected to the first node N1. The second gate of the fourth dual-gate transistor M4 is connected to the first threshold voltage adjustment signal B1, the first terminal of the fourth dual-gate transistor M4 is connected to the first clock signal ECK1, and the second terminal of the fourth dual-gate transistor M4 is connected to the first plate of the second capacitor C2.

[0078] To facilitate the description of the working principle of the scanning drive circuit, the interconnection node of the second terminal of the third transistor M3, the second terminal of the fourth dual-gate transistor M4, and the first plate of the second capacitor C2 is defined as the fourth node N4.

[0079] For example, if both the third transistor M3 and the fourth dual-gate transistor M4 are N-type transistors, then the conduction level of both the third transistor M3 and the fourth dual-gate transistor M4 is high. The first threshold voltage adjustment signal B1 is a low-level signal.

[0080] If the first node N1 in the first stage is at a low level and the third node N3 is at a high level, the third transistor M3 is turned on, and the fourth dual-gate transistor M4 is turned off. The turning on of the third transistor M3 transmits the low level VGL of the second level signal to the fourth node N4, thereby making the fourth node N4 a low level VGL.

[0081] Subsequently, in the second stage, both the first node N1 and the third node N3 are at a high level, and both the third transistor M3 and the fourth dual-gate transistor M4 are turned on. The third transistor M3 transmits the low level VGL of the second-level signal to the fourth node N4, and the fourth dual-gate transistor M4 transmits the low level of the first clock signal ECK1 to the fourth node N4. Therefore, the voltage at the fourth node N4 is low level VGL. At this time, the first plate of the second capacitor C2 is at a high level, and the second plate of the second capacitor C2 is at a low level VGL.

[0082] Subsequently, in the third stage, the first node N1 is at a high level, the third node N3 is at a low level, the third transistor M3 is off, and the fourth dual-gate transistor M4 is on. The conduction of the fourth dual-gate transistor M4 transmits the high level of the first clock signal ECK1 to the fourth node N4, thereby making the voltage of the fourth node N4 high. Due to the coupling effect of the second capacitor C2, the potential of the first node N1 increases.

[0083] Subsequently, in the fourth stage, the first node N1 is at a low level and the third node N3 is at a high level. This process is the same as in the first stage and will not be described again here.

[0084] Subsequently, in the fifth stage, the first node N1 is at a low level, the third node N3 is at a high level, the fourth dual-gate transistor M4 is turned off, and the third transistor M3 is turned on. The turn-on of the third transistor M3 transmits the low level VGL of the second level signal to the fourth node N4, so the voltage of the fourth node N4 is low level VGL.

[0085] Furthermore, when the scan drive circuit outputs the second-level signal voltage for an extended period, the fourth dual-gate transistor M4 remains off for an extended time. Therefore, the threshold voltage of the fourth dual-gate transistor M4 is prone to negative bias. This causes the fourth dual-gate transistor M4 to fail to effectively turn off when the second output module 170 outputs the second-level signal voltage VGL, resulting in an excessively high potential at the first node N1. This causes the first dual-gate transistor M1 to conduct, leading to leakage of the high voltage VGH of the first-level signal from the first terminal to the second terminal of the first dual-gate transistor M1, i.e., leakage to the first output terminal Vout of the scan drive circuit. This results in an increase in the voltage output at the first output terminal Vout of the scan drive circuit. At this point, the second gate of the fourth dual-gate transistor M4 needs to be negatively adjusted using the first threshold voltage adjustment signal B1 to compensate for the negative bias of its threshold voltage. This ensures that the fourth dual-gate transistor M4 can reliably turn off, thereby guaranteeing the normal output voltage at the first output terminal Vout of the scan drive circuit.

[0086] Based on the above embodiments, optionally, Figure 5 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 5 The first inter-control module 120 is also connected to a first threshold voltage adjustment signal B1. The first inter-control module 120 includes a fifth dual-gate transistor M5. The interconnection node of the input control module 110, the second stabilization module 150, and the first output module 160 is connected to the first gate of the fifth dual-gate transistor M5, that is, the first gate of the fifth dual-gate transistor M5 is connected to the first node N1. The second gate of the fifth dual-gate transistor M5 is connected to the first threshold voltage adjustment signal B1. The first terminal of the fifth dual-gate transistor M5 is connected to the second clock signal ECK2. The interconnection node of the first stabilization module 140, the second stabilization module 150, and the reverse control module 130 is connected to the second terminal of the fifth dual-gate transistor M5, that is, the second terminal of the fifth dual-gate transistor M5 is connected to the third node N3. The first threshold voltage adjustment signal B1 is a low-level signal.

[0087] The reverse control module 130 includes a ninth transistor M9 and a third capacitor C3. The interconnection node of the first stabilization module 140, the first mutual control module 120, and the second stabilization module 150 is connected to the gate of the ninth transistor M9, that is, the gate of the ninth transistor M9 is connected to the third node N3. The first terminal of the ninth transistor M9 is connected to the first clock signal ECK1, and the second terminal of the ninth transistor M9 is connected to the second output module 170. The first plate of the third capacitor C3 is connected to the gate of the ninth transistor M9, and the second plate of the third capacitor C3 is connected to the second terminal of the ninth transistor M9.

[0088] For example, if both the fifth dual-gate transistor M5 and the ninth transistor M9 are N-type transistors, then the conduction level of the fifth dual-gate transistor M5 and the ninth transistor M9 is high. If the first node N1 in the first stage is low, the first clock signal ECK1 is high, and the second clock signal ECK2 is low. In the previous stage, the first clock signal ECK1 was low, and the third node N3 was high. In this stage, the first clock signal ECK1 jumps from low to high. Due to the coupling effect of the parasitic capacitance in the ninth transistor M9, the third node N3 jumps to a higher voltage high level. Correspondingly, due to the coupling effect of the third capacitor C3, the potential of the second node N2 increases, jumping from low to high.

[0089] Subsequently, in the second stage, the first node N1 is high, the first clock signal ECK1 is low, the second clock signal ECK2 is high, and the fifth dual-gate transistor M5 is turned on. The fifth dual-gate transistor M5 outputs the high level of the second clock signal ECK2 to the third node N3, thus making the voltage of the third node N3 high. In response to the high level of the third node N3, the ninth transistor M9 is turned on. The ninth transistor M9, being turned on, outputs the low voltage of the first clock signal ECK1 to the second node N2.

[0090] Subsequently, in the third stage, the first node N1 is high, the first clock signal ECK1 is high, the second clock signal ECK2 is low, and the fifth dual-gate transistor M5 is turned on. The fifth dual-gate transistor M5 outputs the low level of the second clock signal ECK2 to the third node N3, thus making the voltage of the third node N3 low. In response to the low level of the third node N3, the ninth transistor M9 is turned off. Correspondingly, due to the coupling effect of the third capacitor C3, the potential of the second node N2 jumps to an even lower low level.

[0091] Subsequently, in the fourth stage, the first node N1 is low, the first clock signal ECK1 is low, the second clock signal ECK2 is high, and the fifth dual-gate transistor M5 is turned off.

[0092] Furthermore, when the scan drive circuit outputs a low voltage VGL of the second-level signal for an extended period, the fifth dual-gate transistor M5 remains off for an extended time. Therefore, the threshold voltage of the fifth dual-gate transistor M5 is prone to negative bias. This causes the fifth dual-gate transistor M5 to fail to effectively turn off when the second output module 170 outputs the low voltage VGL of the second-level signal, resulting in an excessively low potential at the second node N2. Consequently, the second dual-gate transistor M2 cannot reliably conduct, and the first output terminal Vout of the scan drive circuit cannot reliably output the low voltage VGL of the second-level signal. In this situation, the second gate of the fifth dual-gate transistor M5 needs to be negatively adjusted using the first threshold voltage adjustment signal B1 to compensate for the negative bias of its threshold voltage. This allows the fifth dual-gate transistor M5 to reliably turn off, thereby ensuring that the first output terminal Vout of the scan drive circuit reliably outputs the low voltage VGL of the second-level signal.

[0093] Based on the above embodiments, optionally, Figure 6 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 6 The fifth dual-gate transistor comprises two dual-gate transistors connected in series. The fifth dual-gate transistor M5 is a six-terminal device, comprising a first gate, a second gate, a third gate, and a fourth gate. Both the first and second gates of the fifth dual-gate transistor are connected to the first node, and both the second and fourth gates are connected to the first threshold voltage adjustment signal B1. The fifth dual-gate transistor is equivalent to two dual-gate transistors connected in series, thereby reducing leakage current and preventing leakage at the third node N3.

[0094] Based on the above embodiments, optionally, Figure 7 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 7 The scanning drive circuit also includes: a second mutual control module 180, which is connected to the input control module 110 and the second output module 170, and is also connected to a first threshold voltage adjustment signal B1; the second mutual control module is used to be turned on under the control of the input control module 110 to control the second output module 170 to be turned off.

[0095] During the first level signal output period, the input control module 110 controls the first output module 160 to conduct, so as to output the first level signal. At the same time, the first output module 160 controls the second interconnection module 180 to conduct, so as to control the second output module 170 to be disconnected, thereby avoiding the first output module 160 and the second output module 170 from conducting at the same time, which is conducive to the reliable output of the first level signal by the scan drive circuit.

[0096] In addition, the second mutual control module is also connected to the first threshold voltage adjustment signal B1. By inputting the first threshold voltage adjustment signal B1 to the second mutual control module, the threshold voltage of the transistor in the second mutual control module can be adjusted, so that the second mutual control module can be effectively turned on or off under the control of the input control module 110.

[0097] Based on the above embodiments, optionally, Figure 8 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 8 The second mutual control module includes a sixth dual-gate transistor M6. The interconnection nodes of the input control module 110, the second stabilization module 150, the first mutual control module 120, and the first output module 160 are connected to the first gate of the sixth dual-gate transistor M6, that is, the first gate of the sixth dual-gate transistor M6 is connected to the first node N1. The second gate of the sixth dual-gate transistor M6 is connected to a first threshold voltage adjustment signal B1, and the first terminal of the sixth dual-gate transistor M6 is connected to a second level signal. The interconnection nodes of the second output module 170 and the reverse control module 130 are connected to the second terminal of the sixth dual-gate transistor M6, that is, the second terminal of the sixth dual-gate transistor M6 is connected to the second node N2. The second level signal is a low-level signal, and the first threshold voltage adjustment signal B1 is a low-level signal.

[0098] For example, if the sixth dual-gate transistor M6 is an N-type transistor, then the conduction level of the sixth dual-gate transistor M6 is high. When the first node N1 is high, the sixth dual-gate transistor M6 is turned on. The conduction of the sixth dual-gate transistor M6 outputs the low voltage VGL of the second level signal to the second node N2, thereby making the voltage of the second node N2 low voltage VGL. In response to the low voltage VGL of the second node N2, the second dual-gate transistor M2 is turned off. When the first node N1 is low, the sixth dual-gate transistor M6 is turned off.

[0099] Furthermore, when the scan drive circuit outputs a low voltage VGL of the second-level signal for an extended period, the sixth dual-gate transistor M6 remains off for an extended time. Therefore, the threshold voltage of the sixth dual-gate transistor M6 is prone to negative bias. This causes the sixth dual-gate transistor M6 to fail to effectively turn off when the second output module 170 outputs the low voltage VGL of the second-level signal, resulting in an excessively low potential at the second node N2. Consequently, the second dual-gate transistor M2 cannot reliably conduct, and the first output terminal Vout of the scan drive circuit cannot reliably output. In this situation, the second gate of the sixth dual-gate transistor M6 needs to be negatively adjusted using the first threshold voltage adjustment signal B1 to compensate for the negative bias of its threshold voltage. This allows the sixth dual-gate transistor M6 to reliably turn off, thereby ensuring that the first output terminal Vout of the scan drive circuit reliably outputs the low level VGL.

[0100] Based on the above embodiments, optionally, Figure 9 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 9 The first stabilization module 140 is also connected to the first threshold voltage adjustment signal B1. The first stabilization module 140 includes a seventh dual-gate transistor M7. The first gate of the seventh dual-gate transistor M7 is connected to the second clock signal ECK2. The second gate of the seventh dual-gate transistor M7 is connected to the first threshold voltage adjustment signal B1. The first terminal of the seventh dual-gate transistor M7 is connected to the first level signal. The interconnection node of the first mutual control module 120, the reverse control module 130 and the second stabilization module 150 is connected to the second terminal of the seventh dual-gate transistor M7, that is, the second terminal of the seventh dual-gate transistor M7 is connected to the third node N3.

[0101] The input control module 110 includes an eighth transistor M8, the gate of the eighth transistor M8 is connected to the second clock signal ECK2, the first terminal of the eighth transistor M8 is connected to the input signal, and the interconnection node of the first mutual control module 120, the second stabilization module 150 and the first output module 160 is connected to the second terminal of the eighth transistor M8, that is, the second terminal of the eighth transistor M8 is connected to the first node N1.

[0102] In the above embodiments, the first gate of each transistor can be its top gate or bottom gate (or bottom shielding metal BSM), and correspondingly, the second gate can be its bottom gate or top gate, with the top gate and bottom gate specifically determined according to the gate setting position.

[0103] For example, the seventh dual-gate transistor M7 and the eighth transistor M8 are both N-type transistors, the first level signal is a high level signal, the first threshold voltage adjustment signal B1 is a low level signal, and the input signal is a high-low level pulse signal.

[0104] Due to the operating characteristics of transistors, the seventh dual-gate transistor M7 is prone to threshold voltage drift after long-term operation. Specifically, the threshold voltage of the seventh dual-gate transistor M7 becomes negatively biased. This causes the seventh dual-gate transistor M7 to fail to effectively turn off when the second output module 170 outputs a low voltage VGL for the second level signal. Consequently, the potential of the third node N3 becomes too high, causing the ninth transistor M9 to transmit the voltage of the first clock signal ECK1 to the second node N2. This affects the conduction or turn-off of the second dual-gate transistor M2, resulting in the first output terminal Vout of the scan drive circuit failing to output reliably. In this case, the second gate input of the seventh dual-gate transistor M7 needs to be negatively adjusted using the first threshold voltage adjustment signal B1 to compensate for the negative threshold voltage bias of the seventh dual-gate transistor M7. This allows the seventh dual-gate transistor M7 to be reliably turned off, thereby ensuring that the first output terminal Vout of the scan drive circuit reliably outputs a low level VGL.

[0105] Those skilled in the art will understand that, similar to the seventh dual-gate transistor M7, the eighth transistor M8 will also exhibit a negative threshold voltage bias, but this has a relatively small impact on the output signal of the scan drive circuit. Therefore, setting the seventh dual-gate transistor M7 as a dual-gate transistor and the eighth transistor M8 as a single-gate transistor helps to reduce production costs while ensuring stable output of the scan drive circuit.

[0106] In another embodiment, the eighth transistor M8 is optionally configured as a vertical dual-gate transistor, with the first gate of the eighth transistor M8 connected to the second clock signal ECK2 and the second gate of the eighth transistor M8 connected to the first threshold voltage adjustment signal B1, so as to further improve the stability of the output signal of the scan drive circuit.

[0107] In the above embodiments, optionally, each transistor is an N-type transistor, fabricated using a metal-oxide-semiconductor process, specifically indium gallium zinc oxide (IGZO).

[0108] Figures 10-21 This is a schematic diagram illustrating the switching states of a scan driving circuit at various stages and their corresponding timing, provided as an embodiment of the present invention. See also... Figures 10-21 A solid square indicates that the transistor is turned on, and a hollow square indicates that the transistor is turned off. The voltage of the first level signal is high level VGH, and the voltage of the second level signal is low level VGL. The input signal EIN of the scan drive circuit is the high and low level pulse signal output from the first output terminal Vout of the previous stage scan drive circuit. Therefore, the high voltage in the input signal EIN is high level VGH, and the low voltage in the input signal EIN is low level VGL. The conduction level of the first dual-gate transistor M1 to the ninth transistor M9 is high level. The scan drive circuit includes stages P1, P2, P3, P4, P5, and P6.

[0109] See Figure 10 and Figure 11In the first stage P1, the voltage of the input signal EIN is high (VGH), the voltage of the first clock signal ECK1 is high (VGH), and the voltage of the second clock signal ECK2 is low (VGL). Specifically, the eighth transistor M8 and the seventh dual-gate transistor M7 are disconnected under the control of the second clock signal ECK2. At this time, the first node N1 maintains the state of the previous stage, that is, the first node N1 is low (VGL). In response to the low (VGL) of the first node N1, the fifth dual-gate transistor M5, the sixth dual-gate transistor M6, the fourth dual-gate transistor M4, and the first dual-gate transistor M1 are disconnected, and the fourth node N4 maintains the low (VGL) of the previous stage. In the previous stage, the first clock signal ECK1 was low (VGL), and the third node N3 was high (VGH). In the first stage P1, the first clock signal ECK1 jumps from low (VGL) to high (VGH). Due to the coupling effect of the parasitic capacitance in the ninth transistor M9, the third node N3 jumps to a higher voltage level. Correspondingly, due to the coupling effect of the third capacitor C3, the potential of the second node N2 rises, changing from low level VGL to high level VGH, controlling the second dual-gate transistor M2 to conduct. The conduction of the second dual-gate transistor M2 outputs the low voltage VGL of the second level signal, that is, the first output terminal Vout outputs the low voltage VGL of the second level signal.

[0110] Specifically, the first dual-gate transistor M1, the second dual-gate transistor M2, the fifth dual-gate transistor M5, and the sixth dual-gate transistor M6 are configured as four-terminal devices. By inputting a second threshold voltage adjustment signal B2 to the second dual-gate transistor M2, its threshold voltage is negatively biased to compensate for the positive bias of its threshold voltage. Similarly, by inputting a first threshold voltage adjustment signal B1 to the first dual-gate transistor M1, the fifth dual-gate transistor M5, and the sixth dual-gate transistor M6, their threshold voltages are positively biased to compensate for the negative bias of their threshold voltages. Therefore, in the first stage P1, the first dual-gate transistor M1 will not be mis-turned on, causing the voltage output at the first output terminal Vout to be too high; the fifth dual-gate transistor M5 will not be mis-turned on, causing the voltage at the third node N3 to decrease and preventing the ninth transistor M9 from conducting, and the voltage at the second node N2 will decrease due to the coupling of the third capacitor C3; the sixth dual-gate transistor 6 will not be mis-turned on, causing the voltage at the second node N2 to decrease; the second dual-gate transistor M2 will not fail to conduct, preventing the first output terminal Vout from outputting the low voltage VGL of the second level signal.

[0111] See Figure 12 and Figure 13In the second stage P2, the voltage of the input signal EIN is high (VGH), the voltage of the first clock signal ECK1 is low (VGL), and the voltage of the second clock signal ECK2 is high (VGH). Specifically, the eighth transistor M8 and the seventh dual-gate transistor M7 are turned on under the control of the second clock signal ECK2. The eighth transistor M8 outputs the high-level VGH of the input signal EIN to the first node N1, thus making the first node N1 high (VGH). In response to the high-level VGH of the first node N1, the fifth dual-gate transistor M5, the sixth dual-gate transistor M6, the fourth dual-gate transistor M4, and the first dual-gate transistor M1 are turned on. The first dual-gate transistor M1 outputs the high-level VGH of the first level signal, that is, the first output terminal Vout outputs the high-level VGH of the first level signal. The seventh dual-gate transistor M7 outputs the high-level VGH of the first level signal to the third node N3, and the fifth dual-gate transistor M5 outputs the high-level VGH of the second clock signal ECK2 to the third node N3, thus making the third node N3 high (VGH). In response to the high level VGH of the third node N3, both the ninth transistor M9 and the third transistor M3 are turned on. The ninth transistor M9 outputs the low voltage VGL of the first clock signal ECK1 to the second node N2, and the sixth dual-gate transistor M6 outputs the low voltage VGL of the second level signal to the second node N2, thus making the second node N2 low level VGL. In response to the low level VGL of the second node N2, the second dual-gate transistor M2 is turned off. The third transistor M3 outputs the low voltage VGL of the second level signal to the fourth node N4, and the fourth dual-gate transistor M4 outputs the low level VGL of the first clock signal ECK1 to the fourth node N4, thus making the fourth node N4 low level VGL. At this time, the first plate of the second capacitor C2 has a low voltage VGL, and the second plate of the second capacitor C2 has a high voltage VGH.

[0112] See Figure 14 and Figure 15In the third stage P3, the voltage of the input signal EIN is high (VGH), the voltage of the first clock signal ECK1 is high (VGH), and the voltage of the second clock signal ECK2 is low (VGL). Specifically, the eighth transistor M8 and the seventh dual-gate transistor M7 are turned off under the control of the second clock signal ECK2. At this time, the first node N1 maintains the state of the previous stage, that is, the first node N1 is high (VGH). In response to the high level VGH of the first node N1, the fifth dual-gate transistor M5, the sixth dual-gate transistor M6, the fourth dual-gate transistor M4, and the first dual-gate transistor M1 are turned on. The first dual-gate transistor M1 outputs the high level VGH of the first level signal, that is, the first output terminal Vout outputs the high level VGH of the first level signal. The fifth dual-gate transistor M5 outputs the low level VGL of the second clock signal ECK2 to the third node N3, thereby making the third node N3 low (VGL). Correspondingly, due to the coupling effect of the third capacitor C3, the potential of the second node N2 jumps to a lower voltage, continuing to control the second dual-gate transistor M2 to turn off. In response to the low level VGL of the third node N3, the ninth transistor M9 and the third transistor M3 are disconnected. Furthermore, the sixth dual-gate transistor M6 turns on, outputting the low voltage VGL of the second-level signal to the second node N2, further ensuring that the second node N2 is at a low level. The fourth dual-gate transistor M4 turns on, outputting the high level VGH of the first clock signal ECK1 to the fourth node N4, thus making the fourth node N4 high. Correspondingly, due to the coupling effect of the second capacitor C2, the potential of the first node N1 rises and jumps to a higher voltage level, further ensuring that the first output terminal Vout continues to output the first-level signal VGH, thereby further improving the reliability of the scan drive circuit output. Therefore, by combining the third transistor M3 and the fourth dual-gate transistor M4, the second capacitor C2 can achieve continuous coupling to the high level of the first node N1, ensuring continuous high-level output. For example, to achieve low-frequency display, the high-level pulse width of the input signal EIN is relatively wide; this embodiment of the invention can still achieve stable output, thus facilitating the realization of low frequencies.

[0113] See Figure 16 and Figure 17In stage P4, the voltage of the input signal EIN is low (VGL), the voltage of the first clock signal ECK1 is low (VGL), and the voltage of the second clock signal ECK2 is high (VGH). Specifically, the eighth transistor M8 and the seventh dual-gate transistor M7 are turned on under the control of the second clock signal ECK2. The eighth transistor M8 outputs the low-level VGL of the input signal EIN to the first node N1, thus making the first node N1 low (VGL). In response to the low-level VGL of the first node N1, the fifth dual-gate transistor M5, the sixth dual-gate transistor M6, the fourth dual-gate transistor M4, and the first dual-gate transistor M1 are turned off. The seventh dual-gate transistor M7 is turned on, transmitting the high-level VGH to the third node N3, thus making the third node N3 high (VGH). In response to the high-level VGH of the third node N3, the ninth transistor M9 and the third transistor M3 are turned on. The ninth transistor M9 outputs the low-level VGL of the first clock signal ECK1 to the second node N2. In response to the low level VGL of the second node N2, the second dual-gate transistor M2 is turned off. The third transistor M3 turns on, outputting the low level VGL of the second level signal to the fourth node N4, thus making the fourth node N4 low level VGL. In summary, both the first dual-gate transistor M1 and the second dual-gate transistor M2 are turned off. At this time, the first output terminal Vout maintains the output state of the previous stage, that is, the first output terminal Vout continues to output the high level VGH of the first level signal.

[0114] In this configuration, the first dual-gate transistor M1 is configured as a four-terminal device. By inputting a first threshold voltage adjustment signal B1 to the first dual-gate transistor M1 to make it negatively biased, the threshold voltage of the first dual-gate transistor M1 is positively biased, thus compensating for the negative bias of its threshold voltage. Therefore, in the fourth stage P4, the first dual-gate transistor M1 will not leak current, preventing the first output terminal Vout from outputting the high level VGH of the first level signal.

[0115] See Figure 18 and Figure 19In stage P5, the input signal EIN is at a low level (VGL), the first clock signal ECK1 is at a high level (VGH), and the second clock signal ECK2 is at a low level (VGL). The eighth transistor M8 and the seventh dual-gate transistor M7 are disconnected under the control of the second clock signal ECK2. At this time, the first node N1 maintains the state of the previous stage, i.e., the first node N1 is at a low level (VGL). In response to the low level (VGL) of the first node N1, the fifth dual-gate transistor M5, the sixth dual-gate transistor M6, the fourth dual-gate transistor M4, and the first dual-gate transistor M1 are all disconnected. The fourth node N4 maintains the low level (VGL) of the previous stage. In the previous stage, the first clock signal ECK1 was at a low level (VGL), and the third node N3 was at a high level (VGH). In stage P5, the first clock signal ECK1 jumps from low level (VGL) to high level (VGH). Due to the coupling effect of the parasitic capacitance within the ninth transistor M9, the third node N3 jumps to a higher voltage level. Correspondingly, due to the coupling effect of the third capacitor C3, the potential of the second node N2 rises, changing from low level VGL to high level VGH, controlling the second dual-gate transistor M2 to conduct. The conduction of the second dual-gate transistor M2 outputs the low level VGL of the second level signal, that is, the first output terminal Vout outputs the low level VGL of the second level signal.

[0116] Specifically, the first dual-gate transistor M1, the second dual-gate transistor M2, the fifth dual-gate transistor M5, and the sixth dual-gate transistor M6 are configured as four-terminal devices. By inputting a second threshold voltage adjustment signal B2 to the second dual-gate transistor M2, its threshold voltage is negatively biased to compensate for the positive bias of its threshold voltage. Similarly, by inputting a first threshold voltage adjustment signal B1 to the first dual-gate transistor M1, the fifth dual-gate transistor M5, and the sixth dual-gate transistor M6, their threshold voltages are positively biased to compensate for the negative bias of their threshold voltages. Therefore, in the fifth stage P5, the first dual-gate transistor M1 will not be mis-turned on, causing the voltage output at the first output terminal Vout to be too high; the fifth dual-gate transistor M5 will not be mis-turned on, causing the voltage at the third node N3 to decrease and preventing the ninth transistor M9 from conducting, and the voltage at the second node N2 to decrease due to the coupling of the third capacitor C3; the sixth dual-gate transistor 6 will not be mis-turned on, causing the voltage at the second node N2 to decrease; the second dual-gate transistor M2 will not fail to conduct, preventing the first output terminal Vout from outputting the low voltage VGL of the second level signal.

[0117] See Figure 20 and Figure 21In stage P6, the voltage of the input signal EIN is low (VGL), the voltage of the first clock signal ECK1 is low (VGL), and the voltage of the second clock signal ECK2 is high (VGH). Specifically, the eighth transistor M8 and the seventh dual-gate transistor M7 are turned on under the control of the second clock signal ECK2. The eighth transistor M8 transmits the low level of the input signal EIN to the first node N1. In response to the low level VGL of the first node N1, the fifth dual-gate transistor M5, the sixth dual-gate transistor M6, the fourth dual-gate transistor M4, and the first dual-gate transistor M1 are all turned off. The seventh dual-gate transistor M7 turns on and outputs the third voltage signal VGH to the third node N3, thus making the third node N3 high. In response to the high level VGH of the third node N3, the ninth transistor M9 and the third transistor M3 are turned on. The ninth transistor M9 turns on and outputs the low level VGL of the first clock signal ECK1 to the second node N2, thus making the second node N2 low (VGL). In response to the low level VGL of the second node N2, the second dual-gate transistor M2 is turned off. The third transistor M3 turns on, outputting the low level VGL of the second level signal to the fourth node N4, thus making the fourth node N4 low. In summary, both the first dual-gate transistor M1 and the second dual-gate transistor M2 are turned off. At this time, the first output terminal Vout maintains the output state of the previous stage, that is, the first output terminal Vout continues to output the low level VGL of the second level signal.

[0118] In this configuration, the first dual-gate transistor M1 is configured as a four-terminal device. By inputting a first threshold voltage adjustment signal B1 to the first dual-gate transistor M1 to make it negatively biased, the threshold voltage of the first dual-gate transistor M1 is positively biased, thus compensating for the negative bias of the threshold voltage of the first dual-gate transistor M1. Therefore, in the sixth stage P6, the first dual-gate transistor M1 will not leak current, resulting in a higher voltage output at the first output terminal Vout.

[0119] Based on the analysis of the first stage P1, second stage P2, third stage P3, fourth stage P4, fifth stage P5, and sixth stage P6 of the scanning drive circuit, it can be seen that: 1) When the first output terminal Vout of the scanning drive circuit outputs a high-level first voltage signal VGH, the voltage of the first node N1 can be adjusted to be greater than the high voltage VGH of the first voltage signal through the capacitive coupling architecture composed of the third transistor M3, the fourth dual-gate transistor M4, and the second capacitor C2, thereby ensuring that the first output terminal Vout of the scanning drive circuit stably outputs the high voltage VGH of the first voltage signal. Furthermore, the continuous coupling of the second capacitor C2 is beneficial for achieving low frequencies. 2) When the scan drive circuit outputs a low voltage VGL of the second-level signal for an extended period, the seventh dual-gate transistor M7, the fifth dual-gate transistor M5, the fourth dual-gate transistor M4, the sixth dual-gate transistor M6, and the first dual-gate transistor M1 are in a prolonged off-state, while the second dual-gate transistor M2 is in a prolonged on-state. Therefore, the threshold voltages of the seventh dual-gate transistor M7, the fifth dual-gate transistor M5, the fourth dual-gate transistor M4, the sixth dual-gate transistor M6, and the first dual-gate transistor M1 are prone to negative bias, while the threshold voltage of the second dual-gate transistor M2 is prone to positive bias. This results in the scan drive circuit's first output terminal Vout being unable to reliably output. In this situation, the negative bias of the threshold voltages of the seventh dual-gate transistor M7, the fifth dual-gate transistor M5, the fourth dual-gate transistor M4, the sixth dual-gate transistor M6, and the second gate of the first dual-gate transistor M1 can be compensated by negatively adjusting the input of the first threshold voltage adjustment signal B1 to the second gate of the seventh dual-gate transistor M7, the fifth dual-gate transistor M5, the fourth dual-gate transistor M4, the sixth dual-gate transistor M6, and the first dual-gate transistor M1. The second gate input threshold voltage adjustment signal B2 of the second dual-gate transistor M2 is adjusted to compensate for the positive bias of the threshold voltage of the second dual-gate transistor M2. This ensures that the seventh dual-gate transistor M7, the fifth dual-gate transistor M5, the fourth dual-gate transistor M4, the sixth dual-gate transistor M6, the first dual-gate transistor M1, and the second dual-gate transistor M2 can be reliably turned on or off during each stage of operation, thereby guaranteeing the reliable output of the first output terminal Vout of the scan drive circuit.

[0120] This invention also provides a display panel, which, exemplarily, is an organic light-emitting diode (OLED) display panel, a liquid crystal display (LCD) panel, a micro light-emitting diode (Micro LED) display panel, an electrophoresis display (EPD) panel, or a quantum dot light-emitting diode (QLED) panel. The display panel includes a plurality of cascaded scanning drive circuits 10 as provided in any embodiment of this invention, possessing corresponding beneficial effects. Figure 22 This is a schematic diagram of a cascaded scanning drive circuit provided in an embodiment of the present invention. See also... Figure 22 The display panel includes N+1 level scanning drive circuits 10. The signal output from the first output terminal Vout(1) of the first level scanning drive circuit 10 is used as the input signal EIN of the second level scanning drive circuit 10, ..., and the signal output from the first output terminal Vout(N-1) of the Nth level scanning drive circuit 10 is used as the input signal EIN of the Nth level scanning drive circuit 10. This achieves signal shifting output.

[0121] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0122] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scanning drive circuit, characterized in that, include: Input control module, first mutual control module, reverse control module, first stabilization module, second stabilization module, first output module, and second output module; The input control module is connected to the first output module and is used to control the first output module to be turned on, so that the first output module outputs a first level signal; The first mutual control module is connected to the input control module and to the reverse control module; the reverse control module is also connected to the second output module; the first mutual control module is used to turn on under the control of the input control module and transmit control signals to the reverse control module so that the reverse control module controls the second output module to turn off. The first stabilization module is connected to the reverse control module. The first stabilization module is used to control the reverse control module to generate a control signal when the first mutual control module is disconnected, so that the reverse control module controls the second output module to be turned on, and the second output module outputs a second level signal. The second stabilizing module is connected to the first stabilizing module and the second stabilizing module is connected to the first output module; the second stabilizing module is used to control the first output module to disconnect when the first mutual control module is disconnected, according to the control of the first stabilizing module. The first output module is further connected to a first threshold voltage adjustment signal, the first threshold voltage adjustment signal being opposite in level to the first level signal; the second output module is further connected to a second threshold voltage adjustment signal, the second threshold voltage adjustment signal being opposite in level to the second level signal.

2. The scanning drive circuit according to claim 1, characterized in that, The first output module includes: The first dual-gate transistor is connected to the first gate of the input control module, the second stabilization module and the first mutual control module. The second gate of the first dual-gate transistor is connected to the first threshold voltage adjustment signal. The first terminal of the first dual-gate transistor is connected to the first level signal. The second terminal of the first dual-gate transistor is connected to the first output terminal of the scan drive circuit.

3. The scanning drive circuit according to claim 2, characterized in that, The first dual-gate transistor is an N-type transistor, the first level signal is a high-level signal, and the first threshold voltage adjustment signal is a low-level signal.

4. The scanning drive circuit according to claim 1, characterized in that, The second output module includes: The second dual-gate transistor has its first gate connected to the inverting control module and its second gate connected to the second threshold voltage adjustment signal; the first terminal of the second dual-gate transistor is connected to a second level signal and its second terminal is connected to the first output terminal of the scan driving circuit. A first capacitor, wherein the first plate of the first capacitor is connected to the first gate of the second dual-gate transistor, and the second plate of the first capacitor is connected to the second terminal of the second dual-gate transistor.

5. The scanning drive circuit according to claim 4, characterized in that, The second dual-gate transistor is an N-type transistor, the second level signal is a low-level signal, and the second threshold voltage adjustment signal is a high-level signal.

6. The scanning drive circuit according to claim 1, characterized in that, The second stabilization module is also connected to the first threshold voltage adjustment signal, and the second stabilization module includes: The third transistor is connected to the gate of the first stabilizing module, the first mutual control module and the reverse control module, and the first terminal of the third transistor is connected to the second level signal. The second capacitor has its first plate connected to the second terminal of the third transistor, and its second plate connected to the first output module. The fourth dual-gate transistor is connected to the first gate of the input control module, the first mutual control module and the first output module. The second gate of the fourth dual-gate transistor is connected to the first threshold voltage adjustment signal. The first terminal of the fourth dual-gate transistor is connected to the first clock signal. The second terminal of the fourth dual-gate transistor is connected to the first plate of the second capacitor.

7. The scanning drive circuit according to claim 6, characterized in that, Both the third transistor and the fourth dual-gate transistor are N-type transistors, and the first threshold voltage adjustment signal is a low-level signal.

8. The scanning drive circuit according to claim 1, characterized in that, The first mutual control module is also connected to the first threshold voltage adjustment signal, and the first mutual control module includes: The fifth dual-gate transistor has its interconnection nodes of the input control module, the second stabilization module, and the first output module connected to its first gate. The second gate of the fifth dual-gate transistor is connected to the first threshold voltage adjustment signal, and the first terminal of the fifth dual-gate transistor is connected to the second clock signal. The interconnection nodes of the first stabilization module, the second stabilization module, and the reverse control module are connected to the second terminal of the fifth dual-gate transistor.

9. The scanning drive circuit according to claim 8, characterized in that, The fifth dual-gate transistor is an N-type transistor, and the first threshold voltage adjustment signal is a low-level signal.

10. The scanning drive circuit according to claim 8, characterized in that, The fifth dual-gate transistor further includes a third gate and a fourth gate. The third gate of the fifth dual-gate transistor is connected to the first gate, and the fourth gate of the fifth dual-gate transistor is connected to the second gate. The fifth dual-gate transistor is equivalent to two dual-gate transistors connected in series.

11. The scanning drive circuit according to claim 1, characterized in that, The first stabilization module is also connected to the first threshold voltage adjustment signal, and the first stabilization module includes: The seventh dual-gate transistor has a first gate connected to a second clock signal, a second gate connected to a first threshold voltage adjustment signal, a first terminal connected to a first level signal, and the interconnection nodes of the first mutual control module, the reverse control module, and the second stabilization module are connected to the second terminal of the seventh dual-gate transistor.

12. The scanning drive circuit according to claim 11, characterized in that, The seventh dual-gate transistor is an N-type transistor, the first level signal is a high-level signal, and the first threshold voltage adjustment signal is a low-level signal.

13. The scanning drive circuit according to claim 1, characterized in that, The input control module includes: The eighth transistor has a gate connected to a second clock signal and a first terminal connected to an input signal. The interconnection node of the first mutual control module, the second stabilization module, and the first output module is connected to the second terminal of the eighth transistor.

14. The scanning drive circuit according to claim 13, characterized in that, The eighth transistor is an N-type transistor, and the input signal is a high-low level pulse signal.

15. The scanning drive circuit according to claim 1, characterized in that, The reverse control module includes: The ninth transistor has an interconnection node of the first stabilization module, the first mutual control module, and the second stabilization module connected to its gate. The first terminal of the ninth transistor is connected to a first clock signal, and the second terminal of the ninth transistor is connected to the second output module. The third capacitor has its first plate connected to the gate of the ninth transistor and its second plate connected to the second terminal of the ninth transistor.

16. The scanning drive circuit according to claim 15, characterized in that, The ninth transistor is an N-type transistor.

17. The scanning drive circuit according to any one of claims 1-16, characterized in that, Also includes: The second mutual control module is connected to the input control module and the second output module, and is also connected to the first threshold voltage adjustment signal; the second mutual control module is used to be turned on under the control of the input control module to control the second output module to be turned off.

18. The scanning drive circuit according to claim 17, characterized in that, The second mutual control module includes a sixth dual-gate transistor. The interconnection node of the input control module, the second stabilization module, the first mutual control module, and the first output module is connected to the first gate of the sixth dual-gate transistor. The second gate of the sixth dual-gate transistor is connected to the first threshold voltage adjustment signal. The first terminal of the sixth dual-gate transistor is connected to the second level signal. The interconnection node of the second output module and the reverse control module is connected to the second terminal of the sixth dual-gate transistor.

19. The scanning drive circuit according to claim 18, characterized in that, The sixth dual-gate transistor is an N-type transistor, the second level signal is a low-level signal, and the first threshold voltage adjustment signal is a low-level signal.

20. A display panel, characterized in that, It includes multiple cascaded scanning drive circuits as described in any one of claims 1-19.

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