Wafer pad structure and forming method thereof

Abstract

A wafer pad structure and a method for forming the same, wherein the wafer pad structure comprises: a first substrate; a pad structure located on the first substrate, wherein the top angle between the top surface and the side wall of the pad structure is a rounded angle; and a passivation layer located on the pad structure, wherein the passivation layer has a passivation opening, wherein the passivation opening exposes the top surface of the pad structure. The top angle between the top surface and the side wall of the pad structure is a rounded angle, and in the subsequent thermal process of packaging, the rounded structure can well disperse and reduce the stress generated by thermal expansion of the pad structure, thereby reducing the risk of cracks in the passivation layer covering the pad structure due to stress concentration. This can reduce the contact of external water vapor with the pad structure through the cracks, thereby improving the performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a wafer pad structure and a forming method thereof. Background Art

[0002] Wafer Lever BGA (WLBGA) packaging is based on BGA (Ball Grid Array) technology and is an improved and enhanced CSP packaging technology. Wafer-level BGA technology uses wafers as processing objects, packages, ages and tests multiple chips on the wafer at the same time, and then cuts the wafer into a single device, which can be directly mounted on a substrate or printed circuit board.

[0003] Wafer-level BGA technology has the advantages of small package size and supports a wide range of bonding requirements, making the application of wafer-level BGA technology more and more extensive, and the demand for products packaged with wafer-level BGA technology is also increasing.

[0004] However, the performance of the wafer pad structure formed in the packaging process of the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a wafer pad structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a wafer pad structure, comprising: a first substrate; a pad structure located on the first substrate, wherein the top angle between the top surface and the side wall of the pad structure is a rounded angle; a passivation layer located on the pad structure, wherein the passivation layer has a passivation opening, and the passivation opening exposes the top surface of the pad structure.

[0007] Optionally, the first substrate includes: a first base and a first device layer located on the first base, wherein the first device layer has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures.

[0008] Optionally, it further includes: a dielectric layer located on the first substrate, the dielectric layer having a connection layer therein, the pad structure located on the dielectric layer, and the connection layer connecting the pad structure and the electrical interconnection structure.

[0009] Optionally, the material of the passivation layer includes: silicon oxide and silicon nitride.

[0010] Optionally, the material of the dielectric layer includes: silicon oxide and silicon nitride.

[0011] Optionally, the angle between the side wall and the bottom surface of the pad structure is an acute angle, and the acute angle is 68° to 72°.

[0012] Optionally, it also includes: a buffer layer located on the surface of the passivation layer and a portion of the surface of the pad structure.

[0013] Optionally, the material of the buffer layer includes: a polyimide composite material.

[0014] Optionally, it also includes: a conductive structure, wherein the conductive structure is connected to the pad structure.

[0015] Optionally, the conductive structure includes: a conductive column or a solder ball.

[0016] Optionally, the conductive pillar includes: a seed layer and a conductive layer located on the seed layer.

[0017] Optionally, the material of the conductive layer includes: copper.

[0018] Optionally, the material of the pad structure includes: aluminum.

[0019] Correspondingly, the present invention also provides a method for forming a wafer pad structure, comprising: providing a first substrate; forming a pad structure on the first substrate, wherein the top angle between the top surface and the side wall of the pad structure is a rounded angle; forming a passivation layer on the pad structure, wherein the passivation layer has a passivation opening, and the passivation opening exposes the top surface of the pad structure.

[0020] Optionally, the first substrate includes: a first base and a first device layer located on the first base, wherein the first device layer has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures.

[0021] Optionally, before forming the pad structure, the method further includes: forming a dielectric layer on the first substrate, wherein the dielectric layer has a connection layer, the pad structure is located on the dielectric layer, and the connection layer connects the pad structure and the electrical interconnection structure.

[0022] Optionally, the method for forming the pad structure includes: forming a metal layer on the dielectric layer; performing a patterning process on the metal layer to form an initial pad structure; and performing a back etching process on the initial pad structure to form the pad structure.

[0023] Optionally, the etch-back process includes a wet etching process.

[0024] Optionally, the angle between the side wall and the bottom surface of the pad structure is an acute angle, and the acute angle is 68° to 72°.

[0025] Optionally, after forming the passivation layer, the method further includes: forming a buffer layer on a surface of the passivation layer and a portion of a surface of the pad structure.

[0026] Optionally, after forming the buffer layer, the method further includes: forming a conductive structure on the pad structure, wherein the conductive structure is connected to the pad structure.

[0027] Optionally, the conductive structure includes: a conductive column or a solder ball.

[0028] Optionally, the conductive pillar includes: a seed layer and a conductive layer located on the seed layer.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the structure of the technical solution of the present invention, the top angle between the top surface and the side wall of the pad structure is rounded, and in the subsequent thermal process of packaging, the rounded structure can well disperse and reduce the stress generated by the thermal expansion of the pad structure, thereby reducing the risk of cracks in the passivation layer covering the pad structure due to stress concentration. In addition, it can reduce the contact of external water vapor with the pad structure through the cracks, thereby improving the performance of the semiconductor structure finally formed.

[0031] Furthermore, it also includes: a buffer layer located on the surface of the passivation layer and part of the surface of the pad structure. Since the buffer layer has good elastic deformation ability, when subjected to a greater impact force, the buffer layer can also absorb part of the impact force, effectively reducing the impact force borne by the pad structure, thereby reducing the expansion force of the pad structure due to migration deformation, and can further reduce the risk of cracks in the passivation layer covering the pad structure.

[0032] In the formation method of the technical solution of the present invention, the top angle between the top surface and the side wall of the pad structure is a rounded angle. In the subsequent thermal process of packaging, the rounded angle structure can well disperse and reduce the stress generated by the thermal expansion of the pad structure, thereby reducing the risk of cracks in the passivation layer covering the pad structure due to stress concentration. In addition, it can reduce the contact of external water vapor with the pad structure through the cracks, thereby improving the performance of the semiconductor structure finally formed.

[0033] Furthermore, after forming the passivation layer, it also includes: forming a buffer layer on the passivation surface layer and part of the surface of the pad structure. Since the buffer layer has good elastic deformation ability, when subjected to a greater impact force, the buffer layer can also absorb part of the impact force, effectively reducing the impact force borne by the pad structure, thereby reducing the expansion force of the pad structure due to migration deformation, and can further reduce the risk of cracks in the passivation layer covering the pad structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0035] Figures 2 to 8 It is a schematic diagram of the structures of the steps of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, the performance of the wafer pad structure formed in the packaging process of the prior art still needs to be improved.

[0037] Please refer to Figure 1 , including: providing a first substrate 100, forming a pad structure 101 on the first substrate 100, wherein the top surface of the pad structure 101 forms an obtuse angle with the side wall; forming a passivation layer 102 on the side wall and top surface of the pad structure 101, wherein the passivation layer 102 has a passivation opening, and the passivation opening exposes the top surface of the pad structure 101.

[0038] In this embodiment, since the top surface edge of the pad structure 101 is sharp (eg Figure 1 As shown in part A in the figure, the top surface sidewalls of the pad structure 101 are at an obtuse angle. In the subsequent packaging process, there will be multiple heating and cooling processes. The pad structure 101 will expand after being heated, and more concentrated stress will be formed at the sharp corner, which will easily cause cracks in the passivation layer 102 covering the surface of the pad structure 101. Due to the existence of the cracks, external water vapor can easily contact the pad structure 101 through the cracks, thereby affecting the performance of the formed semiconductor structure.

[0039] On this basis, the present invention provides a wafer pad structure and a method for forming the same, wherein the top surface edge of the pad structure is formed into an arc-shaped structure, and in the subsequent thermal process, the arc-shaped structure can well disperse and reduce stress, and can reduce the risk of causing cracks in the second passivation layer covering the pad structure. Furthermore, it can reduce the contact of external water vapor with the pad structure through the cracks, thereby improving the performance of the semiconductor structure finally formed.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 8 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 2 , providing a first substrate.

[0043] In this embodiment, the first substrate includes: a first base 200 and a first device layer 201 located on the first base 200, wherein the first device layer 201 has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures (not shown).

[0044] In this embodiment, the material of the first substrate 200 is silicon; in other embodiments, the material of the first substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0045] In this embodiment, the device structure includes a transistor, a resistor, an inductor or a capacitor.

[0046] The material of the electrical interconnection structure includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the electrical interconnection structure is copper.

[0047] Please refer to Figure 3 , a dielectric layer 202 is formed on the first substrate, and a connecting layer 203 is provided in the dielectric layer 202 .

[0048] In this embodiment, the material of the dielectric layer 202 includes silicon oxide and silicon nitride.

[0049] In this embodiment, the method for forming the dielectric layer 202 and the connecting layer 203 includes: forming an initial dielectric layer (not shown) on the first substrate; performing patterning on the initial dielectric layer to form a dielectric layer 202, wherein the dielectric layer 202 has a dielectric layer opening; and forming the connecting layer 203 in the dielectric layer opening, wherein the bottom surface of the connecting layer 203 is connected to the electrical interconnection structure.

[0050] Please refer to Figure 4 After forming the dielectric layer 202, a pad structure 204 is formed on the first substrate, and the top angle between the top surface and the side wall of the pad structure 204 is a rounded corner.

[0051] In this embodiment, the top angle between the top surface and the side wall of the pad structure 204 is rounded, and in the subsequent thermal process of packaging, the rounded structure can well disperse and reduce the stress generated by the thermal expansion of the pad structure 204, thereby reducing the risk of cracks in the passivation layer covering the pad structure 204 due to stress concentration. In addition, it can reduce the contact between external water vapor and the pad structure 204 through the cracks, thereby improving the performance of the semiconductor structure finally formed.

[0052] In this embodiment, the method for forming the pad structure 204 includes: forming a metal layer (not shown) on the dielectric layer 202; performing a patterning process on the metal layer to form an initial pad structure; and performing a back etching process on the initial pad structure to form the pad structure 204.

[0053] In this embodiment, the top surface of the connection layer 203 is connected to the pad structure 204 .

[0054] In other embodiments, the pad structure and the connection layer may be formed simultaneously.

[0055] In this embodiment, the etch-back process includes a wet etching process.

[0056] The process parameters can ensure that the final rounded corners are moderate. If the curvature of the rounded corners is small, the stress dispersion effect is poor; if the curvature of the rounded corners is large, the pad structure 204 will be more damaged, thereby affecting the performance of the final semiconductor structure.

[0057] In this embodiment, the angle between the side wall and the bottom surface of the pad structure 204 is an acute angle, and the acute angle is 68° to 72°. This structure enables the subsequent passivation layer formed on the pad structure 204 to withstand less stress and pull, reducing the risk of damage to the passivation layer due to excessive stress.

[0058] In this embodiment, the material of the pad structure 204 is aluminum.

[0059] Please refer to Figure 5 A passivation layer 205 is formed on the pad structure 204 , and a passivation opening 206 is provided in the passivation layer 205 . The passivation opening 206 exposes the top surface of the pad structure 204 .

[0060] In this embodiment, the passivation layer 205 is formed by an atomic layer deposition process. The passivation layer 205 formed by the atomic layer deposition process has better uniformity and step coverage.

[0061] In this embodiment, the passivation layer 205 adopts a multi-layer structure, and the material of the passivation layer 205 includes silicon oxide and silicon nitride.

[0062] Please refer to Figure 6 After the passivation layer 205 is formed, a buffer layer 207 is formed on the surface of the passivation layer 205 and a portion of the surface of the pad structure 204 .

[0063] In this embodiment, the material of the buffer layer 207 is a polyimide composite material.

[0064] Since the buffer layer 207 has good elastic deformation ability, when subjected to a greater impact force, the buffer layer 207 can also absorb part of the impact force, effectively reducing the impact force borne by the pad structure 204, thereby reducing the expansion force of the pad structure 204 due to migration deformation, and can further reduce the risk of causing cracks to the passivation layer 205 covering the pad structure 204.

[0065] Please refer to Figure 7 After the buffer layer 207 is formed, a conductive structure 208 is formed on the pad structure 204 , and the conductive structure 208 is connected to the pad structure 204 .

[0066] In this embodiment, the conductive structure 208 is a conductive column, and the conductive column includes a seed layer and a conductive layer located on the seed layer. In other embodiments, the conductive structure may also be a solder ball.

[0067] In this embodiment, the method for forming the seed layer and the conductive layer includes: forming the seed layer in the passivation opening 206 and on a portion of the top surface of the buffer layer 207; and forming the conductive layer on the seed layer using a metal growth process.

[0068] In this embodiment, the process of forming the seed layer adopts an atomic layer deposition process.

[0069] In this embodiment, the conductive layer is made of copper.

[0070] Please refer to Figure 8 After forming the conductive structure 208, a second substrate 209 is provided; and the first substrate 209 and the second substrate are bonded.

[0071] In this embodiment, the second substrate 209 includes: a second base and a second device layer located on the second base, wherein the second device layer has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures (not shown).

[0072] Correspondingly, an embodiment of the present invention further provides a wafer pad structure, please continue to refer to Figure 8 , including: a first substrate; a pad structure 204 located on the first substrate, wherein the top angle between the top surface and the side wall of the pad structure 204 is rounded; a passivation layer located on the pad structure 204, wherein the passivation layer 205 has a passivation opening 206, and the passivation opening 206 exposes the top surface of the pad structure 204.

[0073] In this embodiment, the top angle between the top surface and the side wall of the pad structure 204 is rounded, and in the subsequent thermal process of packaging, the rounded structure can well disperse and reduce the stress generated by the thermal expansion of the pad structure 204, thereby reducing the risk of cracks in the passivation layer 205 covering the pad structure 204 due to stress concentration. In addition, it can reduce the contact between external water vapor and the pad structure 204 through the cracks, thereby improving the performance of the semiconductor structure finally formed.

[0074] In this embodiment, the first substrate includes: a first base 200 and a first device layer 201 located on the first base 200 , wherein the first device layer 201 has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures.

[0075] In this embodiment, it also includes: a dielectric layer 202 located on the first substrate, a connection layer 203 is provided in the dielectric layer 202, the pad structure 204 is located on the dielectric layer 202, and the connection layer 203 connects the pad structure 204 and the electrical interconnection structure.

[0076] In this embodiment, the material of the passivation layer 205 includes silicon oxide and silicon nitride.

[0077] In this embodiment, the material of the dielectric layer 202 includes silicon oxide and silicon nitride.

[0078] In this embodiment, the angle between the side wall and the bottom surface of the pad structure 204 is an acute angle, and the acute angle is 68° to 72°. This structure can form a smaller stress pull on the passivation layer 205 on the pad structure 204, reducing the risk of damage to the passivation layer 205 due to excessive stress.

[0079] In this embodiment, it further includes: a buffer layer 207 located on the surface of the passivation layer 205 and part of the surface of the pad structure 204. Since the buffer layer 207 has good elastic deformation ability, when subjected to a greater impact force, the buffer layer 207 can also absorb a part of the impact force, effectively reducing the impact force borne by the pad structure 204, thereby reducing the expansion force of the pad structure 204 due to migration deformation, and can further reduce the risk of cracks in the passivation layer 205 covering the pad structure 204.

[0080] In this embodiment, the material of the buffer layer 207 includes: a polyimide composite material.

[0081] In this embodiment, the device further includes a conductive structure 208 connected to the pad structure 204 .

[0082] In this embodiment, the conductive structure 208 includes a conductive column or a solder ball.

[0083] In this embodiment, the conductive pillar includes: a seed layer and a conductive layer located on the seed layer.

[0084] In this embodiment, the conductive layer is made of copper.

[0085] In this embodiment, the material of the pad structure 204 is aluminum.

[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A wafer pad structure, characterized in that: include: a first substrate; A pad structure located on the first substrate, wherein the top angle between the top surface and the side wall of the pad structure is a rounded angle, and the rounded angle structure is used to disperse and reduce the stress generated by the thermal expansion of the pad structure, and the angle between the side wall and the bottom surface of the pad structure is an acute angle, which is used to reduce the stress pull of the passivation layer formed on the pad structure; wherein the top angle projection of the pad structure falls on the bottom edge of the pad structure and does not overlap with its bottom angle; A passivation layer is located on the pad structure, the passivation layer is a multi-layer structure, and a passivation opening is provided in the passivation layer, and the passivation opening exposes the top surface of the pad structure.

2. The wafer pad structure according to claim 1, characterized in that: The first substrate includes: a first base and a first device layer located on the first base, wherein the first device layer has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures.

3. The wafer pad structure as claimed in claim 2, characterized in that: Also includes: A dielectric layer is located on the first substrate, wherein the dielectric layer has a connection layer therein, the pad structure is located on the dielectric layer, and the connection layer connects the pad structure and the electrical interconnection structure.

4. The wafer pad structure according to claim 1, characterized in that: The material of the passivation layer includes silicon oxide and silicon nitride.

5. The wafer pad structure as claimed in claim 3, characterized in that: The material of the dielectric layer includes silicon oxide and silicon nitride.

6. The wafer pad structure according to claim 1, wherein: The acute angle is 68° to 72°.

7. The wafer pad structure according to claim 1, characterized in that: Also includes: A buffer layer is located on the surface of the passivation layer and part of the surface of the pad structure.

8. The wafer pad structure as claimed in claim 7, characterized in that: The material of the buffer layer includes: a polyimide composite material.

9. The wafer pad structure according to claim 1, wherein: Also includes: A conductive structure is connected to the pad structure.

10. The wafer pad structure according to claim 9, characterized in that: The conductive structure includes: a conductive column or a solder ball.

11. The wafer pad structure according to claim 10, characterized in that: The conductive pillar includes a seed layer and a conductive layer located on the seed layer.

12. The wafer pad structure according to claim 11, characterized in that: The material of the conductive layer includes: copper.

13. The wafer pad structure according to claim 1, wherein: The material of the pad structure includes: aluminum.

14. A method for forming a wafer pad structure, characterized in that: include: providing a first substrate; A pad structure is formed on the first substrate, wherein the top angle between the top surface and the side wall of the pad structure is a rounded angle, and the rounded angle structure is used to disperse and reduce the stress generated by the thermal expansion of the pad structure, and the angle between the side wall and the bottom surface of the pad structure is an acute angle, which is used to reduce the stress pull of the passivation layer formed on the pad structure; wherein the top angle projection of the pad structure falls on the bottom edge of the pad structure and does not overlap with its bottom angle; A passivation layer is formed on the pad structure, wherein the passivation layer is a multi-layer structure and has a passivation opening therein, wherein the passivation opening exposes the top surface of the pad structure.

15. The method for forming a wafer pad structure according to claim 14, wherein: The first substrate includes: a first base and a first device layer located on the first base, wherein the first device layer has a plurality of device structures and a plurality of electrical interconnection structures, and the electrical interconnection structures are connected to the device structures.

16. The method for forming a wafer pad structure as claimed in claim 15, characterized in that: Before forming the pad structure, the method further includes: forming a dielectric layer on the first substrate, wherein the dielectric layer has a connection layer, the pad structure is located on the dielectric layer, and the connection layer connects the pad structure and the electrical interconnection structure.

17. The method for forming a wafer pad structure according to claim 16, wherein: The method for forming the pad structure includes: forming a metal layer on the dielectric layer; performing a patterning process on the metal layer to form an initial pad structure; and performing a back etching process on the initial pad structure to form the pad structure.

18. The method for forming a wafer pad structure according to claim 17, wherein: The etch-back process includes a wet etching process.

19. The method for forming a wafer pad structure as claimed in claim 18, characterized in that: The acute angle is 68° to 72°.

20. The method for forming a wafer pad structure according to claim 14, wherein: After forming the passivation layer, the method further includes: forming a buffer layer on the surface of the passivation layer and a portion of the surface of the pad structure.

21. The method for forming a wafer pad structure as claimed in claim 20, characterized in that: After forming the buffer layer, the method further includes: forming a conductive structure on the pad structure, wherein the conductive structure is connected to the pad structure.

22. The method for forming a wafer pad structure as claimed in claim 21, characterized in that: The conductive structure includes: a conductive column or a solder ball.

23. The method for forming a wafer pad structure as claimed in claim 22, characterized in that: The conductive pillar includes a seed layer and a conductive layer located on the seed layer.

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