SOI LDMOS device and its manufacturing method

Abstract

The present invention discloses a SOILDMOS device formed on a hybrid substrate. It includes an SOI region and a non-isolated region, and the non-isolated region is a semiconductor substrate without a dielectric buried layer. A gate structure, a channel region, and a source region are formed in the semiconductor substrate, and a drain region is formed in the semiconductor top layer of the SOI substrate. The gate structure adopts a trench gate passing through the channel region. The source region is formed on the surface of the channel region and is self-aligned with the trench gate. A drift region is formed between the channel region and the drain region, and is composed of a first drift sub-region formed in the semiconductor top layer and a second drift sub-region formed in the semiconductor substrate. The junction depth of the second drift sub-region is greater than that of the first drift sub-region, so as to expand the conduction current path and thus reduce the on-resistance. The present invention also discloses a manufacturing method of the SOILDMOS device. The present invention can expand the conduction current path, thereby reducing the on-resistance; it can also increase the current density and further reduce the on-resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a SOI LDMOS device. The present invention also relates to a method for manufacturing a SOI LDMOS device. Background Art

[0002] Semiconductor on Insulator (SOI) includes a semiconductor body layer, a buried dielectric layer, and a semiconductor top layer. Usually, the semiconductor material is silicon, so it is usually called silicon on insulator. The SOI process technology is a full dielectric isolation technology. MOS and other devices are made on the top silicon film, and there is an oxide layer, i.e., the buried dielectric layer, between the top silicon film and the silicon substrate, i.e., the semiconductor body layer, for isolation. This technology completely eliminates the latching effect of the traditional bulk silicon process, has small parasitic capacitance, and has advantages such as high speed, low power consumption, high integration, and high reliability.

[0003] However, for a Power SOI LDMOS device, its on-state conduction current is restricted in the thin silicon film, and the current conduction path is limited, resulting in a decrease in current density and an inability to improve device performance.

[0004] Currently, conventional Power LDMOS uses a planar gate distribution and a single channel, making it impossible to effectively improve the current density.

[0005] As Figure 1 shown, it is a schematic structural diagram of an existing SOI LDMOS device; the existing SOI LDMOS device is formed on a SOI substrate.

[0006] The SOI substrate is formed by superimposing a semiconductor body layer 101, a buried dielectric layer 102, and a semiconductor top layer 103. The buried dielectric layer 102 is formed on the surface of the semiconductor body layer 101, and the semiconductor top layer 103 is formed on the surface of the buried dielectric layer 102.

[0007] Usually, the materials of the semiconductor body layer 101 and the semiconductor top layer 103 are both silicon; the material of the buried dielectric layer 102 is silicon dioxide.

[0008] The gate structure is a planar gate formed by superimposing a gate dielectric layer such as a gate oxide layer 104 and a polysilicon gate 105.

[0009] The source region and the drain region are respectively self-aligned and formed in the semiconductor top layer 103 on both sides of the planar gate.

[0010] Positive metal layers 106 are respectively formed on the tops of the source region, the drain region, and the polysilicon gate 105, and the source electrode, the drain electrode, and the gate electrode are respectively led out.

[0011] Taking an N-type device as an example, when the device is turned on, the source is grounded, the gate voltage is greater than the threshold voltage, and a high voltage is applied to the drain. The conduction current path of the device is as shown by the arrow line 107. However, due to the very thin thickness of the semiconductor top layer 103, the conduction current path is restricted, such as the conduction current paths in the areas shown by the dashed circles 108a and 108b. This will increase the on-resistance.

[0012] Moreover, the planar gate structure can only form one conductive channel, so the channel density is also low. Summary of the Invention

[0013] The technical problem to be solved by the present invention is to provide a SOI LDMOS device that can expand the conduction current path, thereby reducing the on-resistance; it can also increase the current density and further reduce the on-resistance. To this end, the present invention also provides a manufacturing method of a SOI LDMOS device.

[0014] To solve the above technical problem, the SOI LDMOS device provided by the present invention is formed on a hybrid substrate.

[0015] The hybrid substrate includes a SOI region and a non-isolated region. The SOI region has a SOI substrate, and the SOI substrate is formed by stacking a semiconductor body layer, a dielectric buried layer, and a semiconductor top layer. The dielectric buried layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer.

[0016] The non-isolated region has a semiconductor substrate formed by directly stacking the semiconductor body layer and a semiconductor epitaxial layer. The semiconductor top layer and the dielectric buried layer in the non-isolated region are removed, and the semiconductor epitaxial layer and the semiconductor body layer are in direct contact.

[0017] The gate structure, channel region, and source region of the SOI LDMOS device are formed in the semiconductor substrate, and the drain region is formed in the semiconductor top layer. Both the source region and the drain region have a first conductive type heavy doping.

[0018] The channel region is composed of a well region doped with a second conductive type.

[0019] The gate structure adopts a trench gate, and the trench gate penetrates through the channel region.

[0020] The source region is formed on the surface of the channel region and is self-aligned with the trench gate.

[0021] A drift region is formed between the channel region and the drain region. The drift region is composed of a first drift sub-region and a second drift sub-region. The first drift sub-region is composed of a doping region of a first conduction type formed in the top layer of the semiconductor. The second drift sub-region is composed of a doping region of a first conduction type formed in the semiconductor substrate, and the junction depth of the second drift sub-region is greater than that of the first drift sub-region, so as to expand the conduction current path and thus reduce the on-resistance.

[0022] A further improvement is that the gate structure includes a plurality of trench gates connected electrically. The depth of the trench gate closer to the drain region is shallower. By means of the plurality of trench gates, the number of conductive channels is increased, thereby increasing the current density.

[0023] A further improvement is that the trench gates included in the gate structure are two, namely a first trench gate and a second trench gate. The first trench gate is closer to the drain region than the second trench gate. The first trench gate is formed in a first gate trench, and the second trench gate is formed in a second gate trench. The depth of the first gate trench is less than that of the second gate trench.

[0024] A further improvement is that the second trench gate includes a second polysilicon gate. There is a second gate dielectric layer between the second polysilicon gate and the first side surface and the second side surface of the second gate trench, and there is a second bottom dielectric layer between the second polysilicon gate and the bottom surface of the second gate trench.

[0025] A further improvement is that the width of the first gate trench is greater than that of the second gate trench.

[0026] The first trench gate includes a first polysilicon gate. There is a first gate dielectric layer between the first polysilicon gate and the first side surface of the first gate trench, there is a trench side dielectric layer between the first polysilicon gate and the second side surface of the first gate trench, and there is a first bottom dielectric layer between the first polysilicon gate and the bottom surface of the first gate trench.

[0027] The width of the trench side dielectric layer is greater than the thickness of the first gate dielectric layer, and the thickness of the first bottom dielectric layer is greater than the thickness of the first gate dielectric layer.

[0028] The second side surface of the first gate trench is in contact with the drift region, and the breakdown voltage of the device is increased by increasing the width of the trench side dielectric layer.

[0029] A further improvement is that a drain-end trench is formed in the formation region of the drain region. The drain region is composed of a heavily doped injection region of a first conduction type formed on the inner surface of the drain-end trench, so as to increase the drain-end conduction current area and thus reduce the on-resistance.

[0030] A further improvement is that a semi-insulating polysilicon layer is formed on the top surface of the drift region.

[0031] A further improvement is that a carrier storage layer with heavy doping of the first conductivity type is formed on the bottom surface of the channel region, and the mask for ion implantation of the carrier storage layer is the same as the mask for ion implantation of the source region.

[0032] To solve the above technical problems, the manufacturing method of the SOI LDMOS device provided by the present invention includes the following steps:

[0033] Step 1: Form a hybrid substrate including an SOI region and a non-isolated region, including:

[0034] Provide an SOI substrate, which is composed of a semiconductor body layer, a dielectric buried layer, and a semiconductor top layer stacked on top of each other. The dielectric buried layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer.

[0035] Remove the semiconductor top layer and the dielectric buried layer in the non-isolated region.

[0036] Form a semiconductor epitaxial layer in the non-isolated region. The bottom surface of the semiconductor epitaxial layer is in direct contact with the semiconductor body layer and stacked to form a semiconductor substrate. The top surface of the semiconductor epitaxial layer is flush with the top surface of the semiconductor top layer.

[0037] The SOI region outside the non-isolated region remains as the SOI substrate.

[0038] Step 2: Form a drift region, which is located between the subsequently formed channel region and the drain region. The drift region is composed of a first drift sub-region and a second drift sub-region. The first drift sub-region is composed of a doping region of the first conductivity type formed in the semiconductor top layer; the second drift sub-region is composed of a doping region of the first conductivity type formed in the semiconductor substrate, and the junction depth of the second drift sub-region is greater than the junction depth of the first drift sub-region, so as to expand the conduction current path and thus reduce the on-resistance.

[0039] Step 3: Form a channel region in the semiconductor substrate of the non-isolated region by using a well region process doped with the second conductivity type.

[0040] Step 4: Form a gate structure in the semiconductor substrate of the non-isolated region. The gate structure uses a trench gate, and the trench gate penetrates through the channel region.

[0041] Step 5: Perform source-drain implantation with heavy doping of the first conductivity type to form a source region and a drain region.

[0042] The source region is formed on the surface of the channel region and is self-aligned with the trench gate.

[0043] The drain region is formed in the semiconductor top layer.

[0044] A further improvement is that the gate structure includes a plurality of electrically connected trench gates. The depth of the trench gate closer to the drain region is shallower. The number of conductive channels is increased through the plurality of trench gates, thereby increasing the current density.

[0045] A further improvement is that the trench gates included in the gate structure are two, namely a first trench gate and a second trench gate; the first trench gate is closer to the drain region than the second trench gate; the first trench gate is formed in a first gate trench, the second trench gate is formed in a second gate trench, and the depth of the first gate trench is less than the depth of the second gate trench.

[0046] A further improvement is that step four includes the following sub-steps:

[0047] Step 41: Define the formation regions of the first gate trench and the second gate trench simultaneously, and then perform a first etching to form the top parts of the first gate trench and the second gate trench at the same time; the width of the first gate trench is greater than the width of the second gate trench.

[0048] Step 42: Form a first dielectric layer to completely fill the top parts of the first gate trench and the second gate trench.

[0049] Step 43: Perform a second etching, and the second etching etches the first dielectric layer in the first gate trench and the second gate trench.

[0050] After the second etching is completed, the first side surface of the first gate trench is exposed and the first dielectric layer remains on the second side surface and the bottom surface of the first gate trench.

[0051] The remaining first gate dielectric layer encloses a first gate sub-trench.

[0052] The first dielectric layer remaining on the bottom surface of the first gate trench serves as a first bottom dielectric layer.

[0053] The first dielectric layer remaining on the second side surface of the first gate trench above the first bottom dielectric layer serves as a trench side dielectric layer; the second side surface of the first gate trench contacts the drift region, and the breakdown voltage of the device is increased by increasing the width of the trench side dielectric layer.

[0054] The first side and the second side of the top portion of the second gate trench are both exposed, and the remaining first dielectric layer is retained on the bottom surface of the top portion of the second gate trench.

[0055] Step 44: Perform a third etching to continue etching the remaining first dielectric layer at the bottom of the top portion of the second gate trench and the semiconductor substrate at the bottom to form the second gate trench.

[0056] Step 45: Form a first gate dielectric layer on the first side of the first gate sub-trench, form a second gate dielectric layer on the first side and the second side of the second gate sub-trench, and form a second bottom dielectric layer on the bottom surface.

[0057] Step 46: Form a first polysilicon gate in the first gate sub-trench and simultaneously form a second polysilicon gate in the second gate trench.

[0058] A further improvement is that the first dielectric layer includes an oxide layer;

[0059] In step 45, the first gate dielectric layer, the first bottom dielectric layer, and the second gate dielectric layer are simultaneously formed by a thermal oxidation process.

[0060] A further improvement is that before performing the source-drain implantation in step five, it further includes:

[0061] Etch the semiconductor top layer to form a drain-end trench in the formation region of the drain region;

[0062] The source-drain implantation forms a first-conductivity-type heavily doped implantation region on the inner surface of the drain-end trench, and the drain region is composed of the first-conductivity-type heavily doped implantation region formed on the inner surface of the drain-end trench, so as to increase the drain-end conduction current area and thus reduce the conduction resistance.

[0063] A further improvement is that after step five is completed, it further includes the step of forming a semi-insulating polysilicon layer on the top surface of the drift region.

[0064] A further improvement is that after step five is completed, it further includes the step of forming a first-conductivity-type heavily doped carrier storage layer on the bottom surface of the channel region, and the photomask for ion implantation of the carrier storage layer is the same as the photomask for ion implantation of the source region.

[0065] Different from the structure of existing SOI LDMOS devices which are formed on the semiconductor top layer of an SOI substrate, the present invention uses a hybrid substrate that includes both an SOI substrate and a semiconductor substrate. The semiconductor substrate does not have a dielectric buried layer and thus is a non-isolated bulk structure. The channel region, source region, and gate structure of the SOI LDMOS are formed in the semiconductor substrate, and the drain region is formed in the semiconductor top layer of the SOI substrate. The region range of the drift region will be extended in the direction from the drain region to the channel region, enabling the range of the conduction current path to be unrestricted by the thickness of the semiconductor top layer, thereby expanding the conduction current path and reducing the on-resistance.

[0066] Since the gate structure of the present invention is formed in a non-isolated region, the depth of the gate structure is also unrestricted by the thickness of the semiconductor top layer, thus enabling the formation of multiple trench gates with gradually varying depths, which can increase the current density and further reduce the on-resistance.

[0067] The present invention can also form a drain-end trench, such that the drain region consists of a first-conductivity-type heavily doped implantation region formed on the inner surface of the drain-end trench, thereby increasing the drain-end conduction current area and further reducing the on-resistance.

[0068] The present invention can provide a trench side dielectric layer with a relatively large width on the side surface of the first gate trench of the first trench gate in contact with the drift region, which can increase the device breakdown voltage, i.e., increase the lateral breakdown voltage between the drain region and the channel region of the device.

[0069] The drain region of the present invention is located on the SOI substrate, and the vertical breakdown voltage of the device is still borne by the dielectric buried layer.

[0070] The present invention can also provide a carrier storage layer at the bottom of the channel region, thereby further reducing the on-resistance of the device.

[0071] The present invention can also use semi-insulating polycrystalline silicon (SIPOS) as a passivation layer on the device surface, which can effectively shield the external electric field and protect the surface states of the substrate, such as the surface states of the drift region, thereby improving the device breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The following further describes the present invention in detail with reference to the drawings and specific embodiments:

[0073] Figure 1 is a schematic structural diagram of an existing SOI LDMOS device;

[0074] Figure 2 is a schematic structural diagram of an SOI LDMOS device according to an embodiment of the present invention;

[0075] Figures 3A - 3KIt is a schematic diagram of the device structure in each step of the manufacturing method of the SOI LDMOS device according to the embodiment of the present invention. Detailed implementation manners

[0076] As Figure 2 shown, it is a schematic diagram of the structure of the SOI LDMOS device according to the embodiment of the present invention; the SOI LDMOS device according to the embodiment of the present invention is formed on a hybrid substrate.

[0077] The hybrid substrate includes an SOI region 302 and a non-isolated region 301. The SOI region 302 has an SOI substrate, and the SOI substrate is formed by stacking a semiconductor body layer 201, a buried dielectric layer 202, and a semiconductor top layer 203. The buried dielectric layer 202 is formed on the surface of the semiconductor body layer 201, and the semiconductor top layer 203 is formed on the surface of the buried dielectric layer 202.

[0078] In the embodiment of the present invention, the materials of the semiconductor body layer 201, the semiconductor top layer 203, and the subsequent semiconductor epitaxial layer 204 are all silicon; the material of the buried dielectric layer 202 is silicon dioxide. In other embodiments, the materials of the semiconductor body layer 201, the semiconductor top layer 203, and the subsequent semiconductor epitaxial layer 204 can also be other semiconductor materials, and the material of the buried dielectric layer 202 can also be other insulating materials.

[0079] The non-isolated region 301 has a semiconductor substrate 205 formed by directly stacking the semiconductor body layer 201 and the semiconductor epitaxial layer 204. The semiconductor top layer 203 and the buried dielectric layer 202 in the non-isolated region 301 are removed, and the semiconductor epitaxial layer 204 is in direct contact with the semiconductor body layer 201. For the formation region of the semiconductor epitaxial layer 204, please refer to Figure 3C shown.

[0080] The gate structure, channel region 206, and source region 214 of the SOI LDMOS device are formed in the semiconductor substrate 205, and the drain region 215 is formed in the semiconductor top layer 203. Both the source region 214 and the drain region 215 have a first conductive type heavy doping.

[0081] The channel region 206 is composed of a well region doped with a second conductive type.

[0082] The gate structure adopts a trench gate, and the trench gate penetrates through the channel region 206.

[0083] The source region 214 is formed on the surface of the channel region 206 and is self-aligned with the trench gate.

[0084] The drift region is formed between the channel region 206 and the drain region 215. The drift region consists of a first drift sub-region and a second drift sub-region. The first drift sub-region consists of a doping region of a first conductivity type formed in the semiconductor top layer 203; the second drift sub-region consists of a doping region of a first conductivity type formed in the semiconductor substrate 205, and the junction depth of the second drift sub-region is greater than that of the first drift sub-region, so as to expand the conduction current path and thus reduce the on-resistance. That is, since the second drift sub-region is located in the semiconductor substrate 205, the conduction current path of the second drift sub-region will not be squeezed, so the on-resistance can be significantly reduced.

[0085] In an embodiment of the present invention, the gate structure includes a plurality of trench gates electrically connected. The closer the trench gate is to the drain region 215, the shallower its depth. By means of the plurality of trench gates, the number of conductive channels is increased, thereby increasing the current density. In some embodiments, the trench gates included in the gate structure are two, namely a first trench gate and a second trench gate; the first trench gate is closer to the drain region 215 than the second trench gate; the first trench gate is formed in a first gate trench 207, the second trench gate is formed in a second gate trench 208, and the depth of the first gate trench 207 is less than that of the second gate trench 208. In an embodiment of the present invention, the two trench gates can provide two longitudinal conductive channels. Therefore, the on-resistance of current conduction can be reduced and the current density can be increased, and finally the device performance can be significantly improved.

[0086] The second trench gate includes a second polysilicon gate 212b. A second gate dielectric layer 211b is provided between the second polysilicon gate 212b and the first side and the second side of the second gate trench 208, and a second bottom dielectric layer is provided between the second polysilicon gate 212b and the bottom surface of the second gate trench 208. In some embodiments, the second gate dielectric layer 211b, the second bottom dielectric layer, and the subsequent first gate dielectric layer 211a are all thermal oxide layers and are formed simultaneously by the same thermal oxidation process.

[0087] The width of the first gate trench 207 is greater than the width of the second gate trench 208.

[0088] The first trench gate includes a first polysilicon gate 212a, a first gate dielectric layer 211a is spaced between the first polysilicon gate 212a and the first side of the first gate trench 207, a trench side dielectric layer 209 is spaced between the first polysilicon gate 212a and the second side of the first gate trench 207, and a first bottom dielectric layer 210 is spaced between the first polysilicon gate 212a and the bottom surface of the first gate trench 207. In some embodiments, the trench side dielectric layer 209 and the first bottom dielectric layer 210 are both formed of Figure 3F The first dielectric layer 304 is formed by etching and the material of the first dielectric layer 304 is an oxide layer. In other embodiments, the material of the first dielectric layer 304 can also be other insulating dielectric films.

[0089] The width of the trench side dielectric layer 209 is greater than the thickness of the first gate dielectric layer 211 a , and the thickness of the first bottom dielectric layer 210 is greater than the thickness of the first gate dielectric layer 211 a .

[0090] The second side of the first gate trench 207 is in contact with the drift region, and the device withstand voltage is increased by increasing the width of the trench side dielectric layer 209. In the embodiment of the present invention, the width of the trench side dielectric layer 209 is directly related to the withstand voltage specification of the device, and the size of the trench side dielectric layer 209 can be defined according to different device withstand voltage requirements, which is applicable to various LDMOS applications.

[0091] Most of the vertical withstand voltage of the device is borne by the dielectric buried layer 202 of the SOI substrate.

[0092] In some embodiments, a drain trench 213 is formed in the formation area of ​​the drain region 215, and the drain region 215 is composed of a first conductive type heavily doped implantation region formed on the inner surface of the drain trench 213 to increase the drain conduction current area and thereby reduce the on-resistance.

[0093] In some embodiments, a semi-insulating polysilicon layer (SIPOS) 219 is formed on the top surface of the drift region. The SIPOS passivation layer technology can effectively shield the external electric field, effectively protect the surface energy state of the hybrid substrate, and improve the device withstand voltage.

[0094] In some embodiments, a heavily doped carrier storage layer 216 of the first conductivity type is formed on the bottom surface of the channel region 206, and the ion implantation mask of the carrier storage layer 216 is the same as the ion implantation mask of the source region 214. The carrier storage layer 216 can effectively reduce the on-resistance.

[0095] The source region 214, the drain region 215, and the gate structure respectively lead out the source electrode, the drain electrode, and the gate through a metal interconnection structure. Figure 2 Only one layer of front metal layer 218 is shown. The front metal layer 218 completely fills the drain-end trench 213. At the bottom of the front metal layer 218 on top of the source region 214, a well lead-out region 217 doped heavily with the second conductive type is also formed. The junction depth of the well lead-out region 217 is greater than that of the source region 214 and realizes connecting the channel region 206 to the source electrode.

[0096] The front metal layers 218 on top of the first polysilicon gate 212a and the second polysilicon gate 212b are connected together and both are connected to the gate, realizing the parallel connection of the first polysilicon gate 212a and the second polysilicon gate 212b.

[0097] In the embodiment of the present invention, the SOI LDMOS device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. In other embodiments, it can also be that the SOI LDMOS device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0098] Different from the structure in the prior art where the SOI LDMOS device is formed on the semiconductor top layer 203 of the SOI substrate, the embodiment of the present invention adopts a hybrid substrate that includes both the SOI substrate and the semiconductor substrate 205. The semiconductor substrate 205 does not have a dielectric buried layer 202 and thus is a non-isolated bulk structure. The channel region 206, the source region 214, and the gate structure of the SOI LDMOS are formed in the semiconductor substrate 205, and the drain region 215 is formed in the semiconductor top layer 203 of the SOI substrate. The region range of the drift region is extended in the direction from the drain region 215 to the channel region 206, enabling the range of the conduction current path not to be limited by the thickness of the semiconductor top layer 203, thereby enabling the conduction current path to be extended and thus reducing the on-resistance.

[0099] Since the gate structure in the embodiment of the present invention is formed in the non-isolated region 301, the depth of the gate structure is not limited by the thickness of the semiconductor top layer 203 either, so that multiple trench gates with gradually changing depths can be formed, thereby improving the current density and further reducing the on-resistance.

[0100] The embodiment of the present invention can also form a drain-end trench 213, and the drain region 215 is composed of a first-conductive-type heavily doped injection region formed on the inner surface of the drain-end trench 213, thereby increasing the drain-end conduction current area and further reducing the on-resistance.

[0101] In the embodiment of the present invention, a trench side dielectric layer 209 with a larger width can be arranged on the side surface of the first gate trench 207 of the first trench gate in contact with the drift region, which can increase the breakdown voltage of the device, that is, increase the lateral breakdown voltage between the drain region 215 and the channel region 206 of the device.

[0102] In the embodiment of the present invention, the drain region 215 is located on the SOI substrate, and the longitudinal breakdown voltage of the device is still borne by the buried dielectric layer 202.

[0103] In the embodiment of the present invention, a carrier storage layer 216 can also be arranged at the bottom of the channel region 206, so as to further reduce the on-resistance of the device.

[0104] In the embodiment of the present invention, semi-insulating polysilicon can also be used as the passivation layer on the surface of the device, which can effectively shield the external electric field, effectively protect the surface energy states of the substrate such as the surface of the drift region, and thus improve the breakdown voltage of the device.

[0105] As Figures 3A through 3K shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the SOI LDMOS device in the embodiment of the present invention; the manufacturing method of the SOI LDMOS device in the embodiment of the present invention includes the following steps:

[0106] Step 1: Form a hybrid substrate including an SOI region 302 and a non-isolated region 301, including:

[0107] As Figure 3A shown, provide an SOI substrate, which is composed of a semiconductor body layer 201, a buried dielectric layer 202, and a semiconductor top layer 203 stacked together. The buried dielectric layer 202 is formed on the surface of the semiconductor body layer 201, and the semiconductor top layer 203 is formed on the surface of the buried dielectric layer 202.

[0108] In the method of the embodiment of the present invention, the materials of the semiconductor body layer 201, the semiconductor top layer 203, and the subsequent semiconductor epitaxial layer 204 all adopt silicon; the material of the buried dielectric layer 202 adopts silicon dioxide. In the methods of other embodiments, the materials of the semiconductor body layer 201, the semiconductor top layer 203, and the subsequent semiconductor epitaxial layer 204 can also be other semiconductor materials, and the material of the buried dielectric layer 202 can also adopt other insulating materials.

[0109] As Figure 3B shown, remove the semiconductor top layer 203 and the buried dielectric layer 202 in the non-isolated region 301, and part of the semiconductor body layer 201 will also be removed, and finally a groove 302 is formed.

[0110] As Figure 3CAs shown, a semiconductor epitaxial layer 204 is formed in the non-isolation region 301. The bottom surface of the semiconductor epitaxial layer 204 is in direct contact with and stacked on the semiconductor body layer 201 to form a semiconductor substrate 205. The semiconductor epitaxial layer 204 is formed by an epitaxial growth process. After the epitaxial growth is completed, the top surface of the semiconductor epitaxial layer 204 is higher than the top surface of the semiconductor top layer 203 outside the groove 302.

[0111] As Figure 3D shown, a chemical mechanical polishing (CMP) process is performed to make the top surface of the semiconductor epitaxial layer 204 flush with the top surface of the semiconductor top layer 203. Figure 3D In it, in the non-isolation region 301, the semiconductor substrate is directly represented by the label 205, and the semiconductor body layer 201 and the semiconductor epitaxial layer 204 are no longer separately labeled.

[0112] Outside the non-isolation region 301, the SOI region 302 remains as the SOI substrate.

[0113] Step 2: Form a drift region. The drift region is located between the subsequently formed channel region 206 and the drain region 215. The drift region is composed of a first drift sub-region and a second drift sub-region. The first drift sub-region is composed of a doping region of a first conduction type formed in the semiconductor top layer 203; the second drift sub-region is composed of a doping region of a first conduction type formed in the semiconductor substrate 205. The junction depth of the second drift sub-region is greater than the junction depth of the first drift sub-region, so as to expand the conduction current path and thus reduce the on-resistance.

[0114] In the method of the embodiment of the present invention, the semiconductor top layer 203 directly doped with a first conduction type is used. In this way, it is not necessary to perform ion implantation doping on the semiconductor top layer 203 additionally. In the methods of other embodiments, a doping region of a first conduction type required for forming the first drift sub-region can also be formed in the semiconductor top layer 203 by performing ion implantation of a first conduction type.

[0115] In the method of the embodiment of the present invention, the semiconductor epitaxial layer 204 has a doping structure of a first conduction type, and the second drift sub-region is directly realized by the doping of the semiconductor epitaxial layer 204 itself. In the methods of other embodiments, it can also be: performing ion implantation of a first conduction type on the semiconductor substrate 205 to form a doping region of a first conduction type required for the second drift sub-region.

[0116] Step 3: As Figure 3E shown, a channel region 206 is formed in the semiconductor substrate 205 of the non-isolation region 301 by using a well region process doped with a second conduction type.

[0117] Step 4: AsFigure 3E As shown, a gate structure is formed in the semiconductor substrate 205 of the non-isolation region 301. The gate structure uses a trench gate, and the trench gate penetrates through the channel region 206.

[0118] In the method of the embodiment of the present invention, the gate structure includes a plurality of electrically connected trench gates. The depth of the trench gate closer to the drain region 215 is shallower. The number of conductive channels is increased through the plurality of trench gates, thereby increasing the current density.

[0119] In the method of some preferred embodiments, the trench gates included in the gate structure are two, namely a first trench gate and a second trench gate; the first trench gate is closer to the drain region 215 than the second trench gate; the first trench gate is formed in the first gate trench 207, the second trench gate is formed in the second gate trench 208, and the depth of the first gate trench 207 is less than the depth of the second gate trench 208.

[0120] Step four includes the following sub-steps:

[0121] Step 41: As Figure 3E shown, the formation regions of the first gate trench 207 and the second gate trench 208 are defined simultaneously, and then a first etching is performed to simultaneously form the top portions 208a of the first gate trench 207 and the second gate trench 208; the width of the first gate trench 207 is greater than the width of the second gate trench 208.

[0122] Step 42: As Figure 3F shown, a first dielectric layer 304 is formed to completely fill the top portions 208a of the first gate trench 207 and the second gate trench 208.

[0123] In the method of some embodiments, the first dielectric layer 304 is an oxide layer.

[0124] Step 43: As Figure 3G shown, a second etching is performed, and the second etching etches the first dielectric layer 304 in the first gate trench 207 and the second gate trench 208.

[0125] After the second etching is completed, the first side surface of the first gate trench 207 is exposed, and the first dielectric layer 304 remains on the second side surface and the bottom surface of the first gate trench 207.

[0126] The remaining first gate dielectric layer 211a encloses the first gate sub-trench 207a.

[0127] The first dielectric layer 304 remaining on the bottom surface of the first gate trench 207 serves as the first bottom dielectric layer 210.

[0128] The first dielectric layer 304 remaining on the second side of the first gate trench 207 above the first bottom dielectric layer 210 serves as the trench side dielectric layer 209; the second side of the first gate trench 207 is in contact with the drift region, and the breakdown voltage of the device is increased by increasing the width of the trench side dielectric layer 209.

[0129] Both the first side and the second side of the top portion 208a of the second gate trench 208 are exposed, and the remaining first dielectric layer 304 is retained on the bottom surface of the top portion 208a of the second gate trench 208.

[0130] Step 44, as Figure 3H shown, perform a third etching to continue etching the remaining first dielectric layer 304 at the bottom of the top portion 208a of the second gate trench 208 and the bottom semiconductor substrate 205 to form the second gate trench 208.

[0131] Step 45, as Figure 3I shown, form a first gate dielectric layer 211a on the first side of the first gate sub-trench 207a, form a second gate dielectric layer 211b on the first side and the second side of the second gate sub-trench, and form a second bottom dielectric layer on the bottom surface.

[0132] In some embodiments of the method, the first gate dielectric layer 211a, the first bottom dielectric layer 210, and the second gate dielectric layer 211b are formed simultaneously by a thermal oxidation process.

[0133] Step 46, as Figure 3I shown, form a first polysilicon gate 212a in the first gate sub-trench 207a and simultaneously form a second polysilicon gate 212b in the second gate trench 208.

[0134] Step Five, as Figure 3K shown, perform a source / drain implantation with a first conductive type heavy doping to form a source region 214 and a drain region 215.

[0135] The source region 214 is formed on the surface of the channel region 206 and is self-aligned with the trench gate.

[0136] The drain region 215 is formed in the semiconductor top layer 203.

[0137] In the method of the embodiment of the present invention, before performing the source / drain implantation, it further includes:

[0138] AsFigure 3J As shown, etching the semiconductor top layer 203 forms a drain end trench 213 in the formation region of the drain region 215.

[0139] The source-drain implantation forms a first conductivity type heavily doped implantation region on the inner surface of the drain end trench 213, and the drain region 215 is composed of the first conductivity type heavily doped implantation region formed on the inner surface of the drain end trench 213, so as to increase the drain end conduction current area and thus reduce the on-resistance.

[0140] As Figure 2 shown, after step five is completed, it further includes the step of forming a semi-insulating polysilicon layer 219 on the top surface of the drift region.

[0141] It further includes the step of forming a first conductivity type heavily doped carrier storage layer 216 on the bottom surface of the channel region 206, and the photomask for ion implantation of the carrier storage layer 216 is the same as the photomask for ion implantation of the source region 214.

[0142] The present invention has been described in detail through specific embodiments above, but these do not constitute limitations to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. An SOI LDMOS device, characterized in that: the SOI LDMOS device is formed on a hybrid substrate; the hybrid substrate includes an SOI region and a non-isolated region. The SOI region has an SOI substrate, which is formed by superimposing a semiconductor body layer, a dielectric buried layer, and a semiconductor top layer. The dielectric buried layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer; the non-isolated region has a semiconductor substrate formed by directly superimposing the semiconductor body layer and the semiconductor epitaxial layer. The semiconductor top layer and the dielectric buried layer in the non-isolated region are removed, and the semiconductor epitaxial layer is in direct contact with the semiconductor body layer; the gate structure, channel region, and source region of the SOI LDMOS device are formed in the semiconductor substrate, and the drain region is formed in the semiconductor top layer. Both the source region and the drain region are heavily doped with the first conduction type; the channel region is composed of a well region doped with the second conduction type; the gate structure uses a trench gate, and the trench gate penetrates through the channel region; the source region is formed on the surface of the channel region and is self-aligned with the trench gate; a drift region is formed between the channel region and the drain region. The drift region is composed of a first drift sub-region and a second drift sub-region. The first drift sub-region is composed of a first conduction type doped region formed in the semiconductor top layer; the second drift sub-region is composed of a first conduction type doped region formed in the semiconductor substrate. The junction depth of the second drift sub-region is greater than that of the first drift sub-region, so as to expand the conduction current path and thus reduce the on-resistance.

2. The SOI LDMOS device according to claim 1, characterized in that: the gate structure includes a plurality of electrically connected trench gates. The closer the trench gate is to the drain region, the shallower its depth. By using a plurality of trench gates, the number of conductive channels is increased, thereby increasing the current density.

3. The SOI LDMOS device according to claim 2, characterized in that: the trench gates included in the gate structure are two, namely a first trench gate and a second trench gate; the first trench gate is closer to the drain region than the second trench gate; the first trench gate is formed in a first gate trench, and the second trench gate is formed in a second gate trench. The depth of the first gate trench is less than that of the second gate trench.

4. The SOI LDMOS device according to claim 3, characterized in that: the second trench gate includes a second polysilicon gate. There is a second gate dielectric layer between the second polysilicon gate and the first side and the second side of the second gate trench, and there is a second bottom dielectric layer between the second polysilicon gate and the bottom surface of the second gate trench.

5. The SOI LDMOS device according to claim 4, characterized in that: the width of the first gate trench is greater than the width of the second gate trench; The first trench gate includes a first polysilicon gate. There is a first gate dielectric layer between the first polysilicon gate and the first side surface of the first gate trench, a trench side dielectric layer between the first polysilicon gate and the second side surface of the first gate trench, and a first bottom dielectric layer between the first polysilicon gate and the bottom surface of the first gate trench; The width of the trench side dielectric layer is greater than the thickness of the first gate dielectric layer, and the thickness of the first bottom dielectric layer is greater than the thickness of the first gate dielectric layer; The second side surface of the first gate trench is in contact with the drift region, and the breakdown voltage of the device is increased by increasing the width of the trench side dielectric layer.

6. The SOI LDMOS device according to claim 1, characterized in that: A drain-end trench is formed in the formation region of the drain region. The drain region is composed of a first-conductivity-type heavily doped implantation region formed on the inner surface of the drain-end trench, so as to increase the drain-end conduction current area and thus reduce the on-resistance.

7. The SOI LDMOS device according to claim 1, characterized in that: A semi-insulating polysilicon layer is formed on the top surface of the drift region.

8. The SOI LDMOS device according to claim 1, characterized in that: A first-conductivity-type heavily doped carrier storage layer is formed on the bottom surface of the channel region. The photomask for ion implantation of the carrier storage layer is the same as the photomask for ion implantation of the source region.

9. A manufacturing method of an SOI LDMOS device, comprising the following steps: Step 1, form a hybrid substrate including an SOI region and a non-isolated region, including: Provide an SOI substrate, which is composed of a semiconductor body layer, a buried dielectric layer and a semiconductor top layer stacked. The buried dielectric layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the buried dielectric layer; Remove the semiconductor top layer and the buried dielectric layer in the non-isolated region; Form a semiconductor epitaxial layer in the non-isolated region. The bottom surface of the semiconductor epitaxial layer is in direct contact with the semiconductor body layer and stacked to form a semiconductor substrate. The top surface of the semiconductor epitaxial layer is flush with the top surface of the semiconductor top layer; The SOI region outside the non-isolated region remains as the SOI substrate; Step 2, form a drift region. The drift region is located between the subsequently formed channel region and the drain region. The drift region is composed of a first drift sub-region and a second drift sub-region. The first drift sub-region is composed of a first-conductivity-type doped region formed in the semiconductor top layer; the second drift sub-region is composed of a first-conductivity-type doped region formed in the semiconductor substrate. The junction depth of the second drift sub-region is greater than the junction depth of the first drift sub-region, so as to expand the on-current path and thus reduce the on-resistance; Step 3, form a channel region in the semiconductor substrate in the non-isolated region by using a well region process doped with a second conductivity type; Step 4, form a gate structure in the semiconductor substrate in the non-isolated region. The gate structure uses a trench gate, and the trench gate penetrates through the channel region; Step Five: Perform source / drain implantation with heavy doping of the first conductivity type to form a source region and a drain region; The source region is formed on the surface of the channel region and is self-aligned with the trench gate; The drain region is formed in the semiconductor top layer.

10. The manufacturing method of the SOI LDMOS device according to claim 9, characterized in that: The gate structure includes a plurality of electrically connected trench gates. The closer the trench gate is to the drain region, the shallower its depth. By means of the plurality of trench gates, the number of conductive channels is increased, thereby increasing the current density.

11. The manufacturing method of the SOI LDMOS device according to claim 10, characterized in that: The trench gates included in the gate structure are two, namely a first trench gate and a second trench gate; the first trench gate is closer to the drain region than the second trench gate; the first trench gate is formed in a first gate trench, the second trench gate is formed in a second gate trench, and the depth of the first gate trench is less than the depth of the second gate trench.

12. The manufacturing method of the SOI LDMOS device according to claim 11, characterized in that: Step Four includes the following sub-steps: Step 41: Define the formation regions of the first gate trench and the second gate trench simultaneously, and then perform a first etching to form the top portions of the first gate trench and the second gate trench simultaneously; The width of the first gate trench is greater than the width of the second gate trench; Step 42: Form a first dielectric layer to completely fill the top portions of the first gate trench and the second gate trench; Step 43: Perform a second etching, and the second etching etches the first dielectric layer in the first gate trench and the second gate trench; After the second etching is completed, the first side surface of the first gate trench is exposed, and the first dielectric layer remains on the second side surface and the bottom surface of the first gate trench; The remaining first dielectric layer encloses a first gate sub-trench; The first dielectric layer remaining on the bottom surface of the first gate trench serves as a first bottom dielectric layer; The first dielectric layer remaining on the second side surface of the first gate trench above the first bottom dielectric layer serves as a trench side dielectric layer; the second side surface of the first gate trench contacts the drift region, and the breakdown voltage of the device is increased by increasing the width of the trench side dielectric layer; The first side surface and the second side surface of the top portion of the second gate trench are both exposed, and the remaining first dielectric layer remains on the bottom surface of the top portion of the second gate trench; Step 44: Perform a third etching to continue etching the remaining first dielectric layer at the bottom of the top portion of the second gate trench and the semiconductor substrate at the bottom to form the second gate trench; Step 45: Form a first gate dielectric layer on the first side surface of the first gate sub-trench, form a second gate dielectric layer on the first side surface and the second side surface of the second gate trench, and form a second bottom dielectric layer on the bottom surface; Step 46: Form a first polysilicon gate in the first gate trench and simultaneously form a second polysilicon gate in the second gate trench.

13. The manufacturing method of the SOI LDMOS device according to claim 12, characterized in that: The first dielectric layer includes an oxide layer; In step 45, the first gate dielectric layer, the first bottom dielectric layer, and the second gate dielectric layer are simultaneously formed by a thermal oxidation process.

14. The manufacturing method of the SOI LDMOS device according to claim 9, characterized in that: Before step five, before performing the source-drain implantation, it further includes: Etching the semiconductor top layer to form a drain end trench in the formation region of the drain region; The source-drain implantation forms a first-conductivity-type heavily doped implantation region on the inner surface of the drain end trench, and the drain region is composed of the first-conductivity-type heavily doped implantation region formed on the inner surface of the drain end trench, so as to increase the drain end conduction current area and thus reduce the on-resistance.

15. The manufacturing method of the SOI LDMOS device according to claim 9, characterized in that: After step five is completed, it further includes the step of forming a semi-insulating polysilicon layer on the top surface of the drift region.

16. The manufacturing method of the SOI LDMOS device according to claim 9, characterized in that: After step five is completed, it further includes the step of forming a first-conductivity-type heavily doped carrier storage layer on the bottom surface of the channel region, and the mask for ion implantation of the carrier storage layer is the same as the mask for ion implantation of the source region.

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