Adaptive frequency adjustment circuit, method, chip, electronic device and configuration method

Abstract

The application provides an adaptive frequency adjustment circuit, method, chip, electronic device and configuration method. The adaptive frequency adjustment circuit comprises: a frequency difference acquisition module connected with a voltage-controlled oscillator, configured to acquire a difference between an oscillation frequency of the voltage-controlled oscillator and a target frequency, and generate a frequency difference signal; and a power supply module connected with the frequency difference acquisition module and the voltage-controlled oscillator, configured to provide working voltages for the voltage-controlled oscillator and a processor, adjust the working voltages according to the frequency difference signal, and provide the adjusted working voltages for the voltage-controlled oscillator and the processor, wherein a difference between the oscillation frequency generated by the voltage-controlled oscillator under the adjusted working voltages and the target frequency is within a frequency difference range. The adaptive frequency adjustment circuit can adaptively adjust the working frequency and working voltage of the chip, so as to ensure the performance of the chip and reduce unnecessary power consumption as much as possible.

Description

Technical Field

[0001] This invention belongs to the field of automatic frequency control, and relates to a frequency adjustment circuit, and particularly to an adaptive frequency adjustment circuit, method, chip, electronic device and configuration method. Background Technology

[0002] With the improvement of integrated circuit performance and process technology, issues such as circuit power consumption and process fluctuations have an increasingly significant impact on chip yield, performance consistency, and product stability.

[0003] At the chip manufacturing process level, individual chips exhibit process differences. Therefore, even at the same operating voltage, different chips will have different stable operating frequencies. Current technologies often rely on measured frequency-voltage tables to determine the operating voltage of different chips at various operating frequencies. However, obtaining these frequency-voltage tables requires stability testing on a large number of chips, necessitating long-term stability testing of the operating voltage at each frequency, which is a significant undertaking.

[0004] In terms of circuit power consumption, chip performance is affected by factors such as operating voltage and manufacturing process, resulting in performance differences between different chips in practical applications. For the same operating frequency, a lower-performing chip requires a higher operating voltage, while a higher-performing chip only needs a relatively lower operating voltage. During stability testing to obtain a frequency-voltage table, current technology requires configuring the operating voltage for each frequency point based on the lower-performing chip to ensure all chips function correctly. However, the operating voltage configured in this way is higher than the actual operating voltage required by the higher-performing chip. Therefore, setting the operating voltage of the higher-performing chip according to the frequency-voltage table leads to unnecessary power consumption increases.

[0005] Furthermore, when using power supply chips, the output voltage of these chips often exhibits deviations. In practical applications, it is necessary to consider the voltage error of the power supply chip output and increase the voltage value in the "frequency-voltage" table accordingly. Specifically, to ensure that all chips function properly, existing technology requires configuring the operating voltage corresponding to each operating frequency point based on the output voltage of the power supply chip with a negative deviation. However, configuring the operating voltage in this way leads to unnecessary power consumption increases when the power supply chip has a positive deviation.

[0006] Furthermore, the transient response performance of existing power supply chips often falls short of the requirements of high-performance chips. Specifically, when the chip load suddenly increases, the power supply chip often struggles to respond promptly. In practical applications, there is typically a period of several microseconds to tens of microseconds during which the power supply's filter capacitors need to provide energy to the chip. During this time, the voltage of the power supply chip will drop. To ensure the chip's continuous and stable operation, existing technologies need to guarantee that the power supply chip can still meet the power supply requirements after the voltage drop. Therefore, when configuring the "frequency-voltage" table, the lowest voltage point of the power supply chip during the voltage drop period is considered, thereby further increasing the operating voltage corresponding to each operating frequency point. This leads to a further increase in power consumption.

[0007] In summary, current technologies cannot adaptively adjust the chip's operating frequency based on factors such as operating voltage and manufacturing process. Therefore, they can only obtain the operating voltage of different chips at various operating frequencies based on measured frequency-voltage tables. On the one hand, obtaining these frequency-voltage tables relies on extensive stability testing, which is labor-intensive. On the other hand, to ensure that most chips meet performance requirements, the operating voltage configured based on the frequency-voltage table is often higher than the chip's actual needs, resulting in unnecessary power consumption. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an adaptive frequency adjustment circuit, method, chip, electronic device and configuration method to solve the problem that the prior art cannot adaptively adjust the chip's operating frequency according to factors such as the chip's operating voltage and process.

[0009] To achieve the above and other related objectives, a first aspect of the present invention provides an adaptive frequency adjustment circuit; the adaptive frequency adjustment circuit is applied to a chip, the chip including a processor and a voltage-controlled oscillator (VCO); the adaptive frequency adjustment circuit includes: a frequency difference acquisition module connected to the VCO, used to acquire the difference between the oscillation frequency of the VCO and a target frequency, and generate a frequency difference signal; a power supply module connected to the frequency difference acquisition module, the VCO and the processor, used to provide operating voltage to the VCO and the processor, and adjust the operating voltage according to the frequency difference signal, and provide the adjusted operating voltage to the VCO and the processor, wherein the difference between the oscillation frequency generated by the VCO under the adjusted operating voltage and the target frequency is within a frequency difference range.

[0010] In one embodiment of the first aspect, the voltage-controlled oscillator and the processor are disposed adjacent to each other on the chip.

[0011] In one embodiment of the first aspect, the voltage-controlled oscillator is a ring oscillator.

[0012] In one embodiment of the first aspect, the adaptive frequency adjustment circuit further includes a pre-configuration module; the pre-configuration module is connected to the ring oscillator and is used to pre-configure the number of cascaded inverters in the ring oscillator so that the oscillation frequency of the ring oscillator matches the critical timing path in the processor.

[0013] In one embodiment of the first aspect, the pre-configuration module includes: a pre-configuration unit connected to the ring oscillator, configured to configure the cascaded number of inverters to a preset number of stages; a cascade reduction unit connected to the ring oscillator and the pre-configuration unit, configured to reduce the cascaded number of inverters after the pre-configuration unit has configured the cascaded number of inverters to the preset number of stages, until a timing violation occurs in the processor; and a cascade increase unit connected to the ring oscillator and the cascade reduction unit, configured to increase the cascaded number of inverters by a margin number of stages after a timing violation occurs in the processor.

[0014] In one embodiment of the first aspect, the frequency difference acquisition module includes: a crystal oscillator for generating a reference clock signal; a frequency meter connected to the crystal oscillator and the voltage-controlled oscillator for acquiring the oscillation frequency of the voltage-controlled oscillator; and a comparator connected to the frequency meter for comparing the oscillation frequency of the voltage-controlled oscillator with a target frequency to acquire the frequency difference signal.

[0015] A second aspect of the present invention provides a chip comprising: a processor; a voltage-controlled oscillator; and an adaptive frequency adjustment circuit as described in any one of the first aspects of the present invention, connected to the voltage-controlled oscillator and the processor, for providing operating voltage to the voltage-controlled oscillator and the processor.

[0016] A third aspect of the present invention provides an electronic device comprising the chip described in the second aspect of the present invention.

[0017] A fourth aspect of the present invention provides an adaptive frequency adjustment method applied to a chip; the chip includes a processor and a voltage-controlled oscillator (VCO), the operating voltages of the VCO and the processor being provided by the same power supply module; the adaptive frequency adjustment method includes: obtaining the difference between the oscillation frequency of the VCO and a target frequency; adjusting the operating voltage according to the difference between the oscillation frequency of the VCO and the target frequency, and providing the adjusted operating voltage to the VCO and the processor, wherein the difference between the oscillation frequency generated by the VCO under the adjusted operating voltage and the target frequency is within a frequency difference range.

[0018] A fifth aspect of the present invention provides a pre-configuration method applied to a chip, the chip including a processor and a ring oscillator; the pre-configuration method includes: configuring the number of cascaded inverters in the ring oscillator to a preset number of stages; reducing the number of cascaded inverters until a timing violation occurs in the processor; and increasing the number of cascaded inverters by a margin number of stages.

[0019] As described above, the technical solution of the adaptive frequency adjustment circuit, method, chip, electronic device, and configuration method of the present invention has the following beneficial effects:

[0020] The adaptive frequency adjustment circuit can adaptively adjust the operating frequency and operating voltage of the chip according to the chip's manufacturing process, thereby configuring a higher operating voltage for chips with poorer manufacturing processes to meet their performance requirements, and configuring a lower operating voltage for chips with better manufacturing processes to reduce power consumption while meeting their performance requirements.

[0021] Furthermore, when the chip's operating voltage changes, the adaptive frequency adjustment circuit can adaptively adjust the chip's operating frequency and operating voltage to ensure chip performance and minimize unnecessary power consumption.

[0022] Furthermore, the adaptive frequency adjustment circuit described in this invention does not require a "frequency-voltage" table to obtain the operating voltage of the chip at each operating frequency point, thus eliminating the need for extensive stability testing and reducing workload. Attached Figure Description

[0023] Figure 1 The diagram shown is a structural schematic of the adaptive frequency adjustment circuit described in this invention in a specific embodiment.

[0024] Figure 2 The diagram shown is a structural schematic of a pre-configured module in a specific embodiment of the adaptive frequency adjustment circuit described in this invention.

[0025] Figure 3 The diagram shown is a structural schematic of the adaptive frequency adjustment circuit described in this invention in a specific embodiment.

[0026] Figure 4 The diagram shown is a structural schematic of the chip described in a specific embodiment of the present invention.

[0027] Figure 5 The flowchart shown is a specific embodiment of the adaptive frequency adjustment method described in this invention.

[0028] Figure 6 The flowchart shown is a specific embodiment of the pre-configuration method described in this invention.

[0029] Component designation explanation

[0030] 1. Adaptive frequency adjustment circuit

[0031] 11 Frequency Difference Acquisition Module

[0032] 111 Crystal Oscillator

[0033] 112 Frequency meter

[0034] 113 Comparator

[0035] 12 Power Modules

[0036] 13 Pre-configured modules

[0037] 131 Pre-configured Unit

[0038] 132 cascaded reduction units

[0039] 133 cascaded addition units

[0040] 14 Low-pass filter

[0041] 2. Voltage-controlled oscillator

[0042] 3 processors

[0043] Steps S51-S52

[0044] Steps S61 to S63 Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0046] It should be noted that the illustrations provided in the following embodiments are merely schematic representations of the basic concept of the present invention. The illustrations only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex. Furthermore, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0047] In practical applications, chip performance is affected by factors such as manufacturing process and operating voltage. Current technology cannot adaptively and dynamically adjust the chip's operating frequency based on these factors. Therefore, it is necessary to obtain the correspondence between the chip's operating frequency and operating voltage based on a measured "frequency-voltage" table. However, this approach has the following drawbacks: First, obtaining the "frequency-voltage" table requires stability testing on a large number of chips, which is labor-intensive. Second, factors such as manufacturing process, operating voltage, and temperature affect chip performance, leading to performance differences between different chips. The "frequency-voltage" table cannot reflect these performance differences. To ensure that all chips can operate normally, the operating voltage corresponding to each frequency point in the "frequency-voltage" table is often higher than the actual operating voltage required by most chips. Therefore, configuring the chip's operating voltage based on the "frequency-voltage" table increases unnecessary power consumption.

[0048] To address the aforementioned problems, this invention provides an adaptive frequency adjustment circuit. This circuit adaptively adjusts the chip's operating frequency and voltage based on the chip's manufacturing process. This allows for a higher operating voltage to be configured for chips with inferior manufacturing processes to meet their performance requirements, and a lower operating voltage to be configured for chips with better manufacturing processes to reduce power consumption while still meeting performance needs. Furthermore, when the chip's operating voltage changes, the adaptive frequency adjustment circuit can adaptively adjust both the chip's operating frequency and voltage to ensure chip performance and minimize unnecessary power consumption. Moreover, the adaptive frequency adjustment circuit of this invention does not require a frequency-voltage table to obtain the chip's operating voltage at each operating frequency point, thus eliminating the need for extensive stability testing and reducing workload.

[0049] Please see Figure 1 In one embodiment of the present invention, the adaptive frequency adjustment circuit 1 is applied to a chip. The chip includes the adaptive frequency adjustment circuit 1, a voltage-controlled oscillator 2, and a processor 3. The voltage-controlled oscillator 2 provides timing for the chip, and the oscillation frequency of the voltage-controlled oscillator 2, the operating frequency of the processor 3, and the operating frequency of the chip are the same. The oscillation frequency of the clock signal fclk is determined by the operating voltage of the voltage-controlled oscillator 2; preferably, the oscillation frequency of the clock signal fclk is proportional to the operating voltage of the voltage-controlled oscillator 2. The adaptive frequency adjustment circuit 1 includes a frequency difference acquisition module 11 and a power supply module 12.

[0050] The frequency difference acquisition module 11 is connected to the voltage-controlled oscillator 2 and is used to acquire the difference between the oscillation frequency of the voltage-controlled oscillator 2 and a target frequency Ftar, and generate a frequency difference signal Fdif. The target frequency can be pre-specified by software according to the actual application scenario and stored in a register. The level value of the frequency difference signal Fdif is used to identify the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar; for example, when the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is positive, the frequency difference signal Fdif is high; when the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is negative, the frequency difference signal Fdif is low.

[0051] The power module 12 is connected to the frequency difference acquisition module 11, the voltage-controlled oscillator 2, and the processor 3. The output voltage VDD of the power module 12 is the operating voltage of the voltage-controlled oscillator 2 and the processor 3. Since the voltage-controlled oscillator 2 and the processor 3 are all powered by the power module 12, in this embodiment, the operating voltage of the chip, the operating voltage of the voltage-controlled oscillator 2, and the operating voltage of the processor 3 can be approximately considered to be the same.

[0052] In addition, the power module 12 can also adjust its output voltage VDD according to the frequency difference signal Fdif so that the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is within a frequency difference range. At this time, it can be considered that the oscillation frequency of the voltage-controlled oscillator 2 is approximately equal to the target frequency Ftar.

[0053] It should be noted that since both the voltage-controlled oscillator 2 and the processor 3 are powered by the power module 12, when the power module 12 adjusts the operating voltage of the voltage-controlled oscillator 2, the operating voltage of the processor 3 will also be adjusted accordingly. In specific applications, the target frequency and the frequency difference range can be configured according to actual needs, so that when the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is within the frequency difference range, the operating voltage of the processor 3 is its actual required operating voltage.

[0054] Specifically, when the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is less than the lower limit of the frequency difference range, the power supply module 12 reduces the operating voltage of the voltage-controlled oscillator 2, thereby reducing the oscillation frequency of the voltage-controlled oscillator 2. When the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is greater than the upper limit of the frequency difference range, the power supply module 12 increases the operating voltage of the voltage-controlled oscillator 2, thereby increasing the oscillation frequency of the voltage-controlled oscillator 2. When the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency Ftar is within the frequency difference range, the power supply module 12 switches its output to a high-impedance state to keep the operating voltage of the voltage-controlled oscillator 2 constant. The frequency difference range and its upper and lower limits can be set according to actual needs.

[0055] The adaptive frequency adjustment circuit 1 described in this embodiment can adaptively adjust the operating frequency and operating voltage of the chip according to its process.

[0056] Specifically, the voltage-controlled oscillator 2 and the processor 3 are located on the same chip. Preferably, the logic units (e.g., MOSFETs) in the voltage-controlled oscillator 2 and the logic units (e.g., MOSFETs) in the processor 3 have the same threshold voltage, so the chip's manufacturing process, the processor 3's manufacturing process, and the voltage-controlled oscillator 2's manufacturing process can be approximated as the same. Furthermore, in practical applications, components of the same chip are often manufactured by the same manufacturer using the same or similar processes; therefore, from a practical application perspective, the chip's manufacturing process, the processor 3's manufacturing process, and the voltage-controlled oscillator 2's manufacturing process can also be approximated as the same.

[0057] For two chips with different manufacturing processes, to ensure they achieve the same performance at the same target frequency, the chip with the inferior process needs a higher operating voltage for its processor 3 to guarantee consistent performance; similarly, the chip with the inferior process needs a higher operating voltage for its voltage-controlled oscillator 2 to ensure they operate at the same target frequency. Therefore, the operating voltage of the processor 3 changes with the manufacturing process in the same way as the operating voltage of the voltage-controlled oscillator 2. In this embodiment, the voltage module 12 can adaptively adjust the output voltage VDD (i.e., the operating voltage of the voltage-controlled oscillator 2) to ensure that the oscillation frequency of the voltage-controlled oscillator 2 is the same as or close to the target frequency. The result of this adjustment is that the chip with the inferior process has a higher VDD, while the chip with the better process has a lower VDD. Therefore, the power module 12 in the adaptive frequency adjustment circuit 1 of this embodiment can adaptively adjust its output voltage VDD according to the chip's manufacturing process, thereby achieving adaptive adjustment of the operating voltage of the voltage-controlled oscillator 2 according to the chip's manufacturing process. For the voltage-controlled oscillator 2, its oscillation frequency is determined by its operating voltage. Adjusting its operating voltage will inevitably lead to an adjustment of its oscillation frequency. Therefore, the adaptive frequency adjustment circuit 1 described in this embodiment can also adaptively adjust the oscillation frequency of the voltage-controlled oscillator 2 (i.e., the operating frequency of the processor 3) according to the chip process. Furthermore, in this embodiment, the operating voltage of the voltage-controlled oscillator 2 is the same as the operating voltage of the processor 3; therefore, the operating voltage of the processor 3 will also adaptively adjust according to the chip process.

[0058] Furthermore, for chips with superior manufacturing processes, assuming a target frequency f, existing technologies use a "frequency-voltage" table to obtain its operating voltage V1. As previously described, the operating voltage V1 obtained in this way is often higher than the actual required voltage V2, leading to unnecessary power consumption. In the adaptive frequency adjustment circuit 1 of this embodiment, the operating voltage of the voltage-controlled oscillator 2 is consistent with the operating voltage of the processor 3. Even if a voltage V1 higher than the actual requirement is configured for the processor 3 in the initial stage, this voltage V1 will cause the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency to exceed the upper limit of the frequency difference range. At this time, the voltage module 12 will reduce its output voltage VDD until the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency f is within the frequency difference range. When the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency f is within the frequency difference range, the operating voltage of the processor 3 is lower than V1 and is the same as or approximately the same as V2. Therefore, the adaptive frequency adjustment circuit 1 described in this embodiment can adaptively adjust its operating frequency and operating voltage according to the chip's process technology, thereby reducing unnecessary power consumption in the circuit.

[0059] The adaptive frequency adjustment circuit 1 described in this embodiment can enable the chip's operating frequency to be adaptively adjusted according to its operating voltage.

[0060] Specifically, when the operating voltage of the chip increases and exceeds its actual requirements, the oscillation frequency of the voltage-controlled oscillator 2 will increase. In this case, to ensure that the difference between the oscillation frequency of the voltage-controlled oscillator 2 and the target frequency is within the frequency difference range, the power supply module 12 will reduce its output voltage VDD, thereby reducing the operating voltage of the voltage-controlled oscillator 2. Since the operating voltages of the voltage-controlled oscillator 2 and the processor 3 are the same, the operating voltage of the processor 3 will also decrease. Therefore, when the operating voltage of the chip increases and exceeds its actual requirements, the adaptive frequency adjustment circuit 1 in this embodiment can adaptively reduce the operating voltage of the chip to reduce unnecessary power consumption while ensuring chip performance.

[0061] Similarly, when the operating voltage of the chip decreases and fails to meet the actual needs of the chip, the adaptive frequency adjustment circuit 1 can adaptively increase the operating voltage of the chip in order to meet the performance requirements of the chip.

[0062] As described above, the adaptive frequency adjustment circuit in this embodiment can adaptively adjust the operating frequency and voltage of the chip according to its manufacturing process. This allows for a higher operating voltage to be configured for chips with inferior manufacturing processes to meet their performance requirements, and a lower operating voltage to be configured for chips with better manufacturing processes to reduce power consumption while still meeting their performance needs. Furthermore, when the chip's operating voltage changes, the adaptive frequency adjustment circuit can adaptively adjust the chip's operating frequency and voltage to ensure chip performance and minimize unnecessary power consumption.

[0063] In one embodiment of the present invention, the voltage-controlled oscillator 2 is disposed adjacent to the processor 3. In this case, the voltage-controlled oscillator 2 and the processor 3 have the same or similar temperatures. Specifically, existing chips often have very small dimensions, and with continuous technological advancements, chip dimensions may become even smaller. Because the voltage-controlled oscillator 2 and the processor 3 are arranged adjacently on the chip, there is only a small temperature difference between them when the chip temperature changes. Therefore, it can be considered that the voltage-controlled oscillator 2 and the processor 3 have the same or similar temperatures, and the oscillation frequency of the voltage-controlled oscillator 2 matches the temperature variation trend of the processor 3.

[0064] Based on this, the adaptive frequency adjustment circuit 1 described in this embodiment can realize the adaptive adjustment of the chip's operating frequency and operating voltage with temperature.

[0065] Specifically, when the temperature of the processor 3 changes, causing a decrease in the performance of its internal logic units (e.g., MOSFETs), the processor 3 requires a higher operating voltage to maintain its performance. Simultaneously, since the voltage-controlled oscillator 2 and the processor 3 have the same or similar temperatures, when the temperature of the processor 3 changes, the temperature of the voltage-controlled oscillator 2 will change in the same trend (e.g., both temperatures rise or fall simultaneously), leading to a decrease in the performance of its internal logic units (e.g., MOSFETs), and consequently, a decrease in its oscillation frequency, deviating from the target frequency. At this time, the power module 12 increases its output voltage VDD to ensure that the oscillation frequency of the voltage-controlled oscillator 2 is the same as or close to the target frequency. Therefore, the adaptive frequency adjustment circuit 1 in this embodiment can adaptively adjust the operating voltage and oscillation frequency of the voltage-controlled oscillator 2 according to temperature changes, and realize the adaptive adjustment of the operating voltage and operating frequency of the processor 3 with temperature.

[0066] To ensure proper chip operation at all temperatures, existing technologies often configure the chip's operating voltage to a relatively high level (V3). This V3 is used to guarantee normal operation even under harsh temperature conditions. However, temperature varies due to factors such as season, weather, and operating time; even the same chip may experience different temperatures at different times. If the chip's operating voltage is fixed at V3, unnecessary power consumption will occur when the chip operates at its optimal temperature. The adaptive frequency adjustment circuit 1 described in this embodiment can adaptively adjust the chip's operating voltage and frequency according to temperature. When temperature conditions are harsh, a higher operating voltage is configured to maintain chip performance; when temperature conditions are favorable, a lower operating voltage is configured to reduce power consumption while maintaining chip performance. Therefore, compared to existing technologies, the adaptive frequency adjustment circuit 1 described in this embodiment can reduce chip power consumption.

[0067] In one embodiment of the present invention, the voltage-controlled oscillator 2 is a ring oscillator. The ring oscillator is a ring-shaped oscillator formed by connecting an odd number of NOT gate outputs and inputs end-to-end. In this embodiment, the operating voltage of the ring oscillator is the same as the operating voltage of the processor 3.

[0068] Preferably, the ring oscillator and the processor 3 are disposed adjacent to each other on the chip, and the logic units in the ring oscillator include N-channel MOSFETs and P-channel MOSFETs; in this case, the oscillation frequency of the ring oscillator is... The ring oscillator described herein consists of 2×n+1 inverters, where n is a positive integer. VDD is the output voltage value of the power module 12, L is the channel length of the MOSFET in the ring oscillator, and Wn W is the channel width of the N-channel MOSFET in the ring oscillator. p V is the channel width of the P-channel MOSFET in the ring oscillator; THN (T) is the initial turn-on voltage of the N-channel MOSFET in the ring oscillator when the temperature of the processor 3 is T Kelvin, V THP (T) represents the initial turn-on voltage of the P-channel MOSFET in the ring oscillator when the temperature of the processor 3 is T Kelvin. Taking the N-channel MOSFET as an example, its initial turn-on voltage... Among them, V THN (T0) represents the initial turn-on voltage of the N-channel MOSFET at a reference temperature T0. μ n (T) represents the carrier mobility of the N-channel MOSFET in the ring oscillator at a temperature of T Kelvin in the processor 3, in μ. p (T) represents the carrier mobility of the P-channel MOSFET in the ring oscillator at a temperature of T Kelvin in the processor 3. Taking an N-channel MOSFET as an example, its carrier mobility... Where, μ n (T0) represents the carrier mobility of an N-channel MOSFET at a reference temperature T0.

[0069] As described above, the oscillation frequency of the ring oscillator in this embodiment is a function of temperature T, operating voltage VDD, and process technology (including the channel length and channel width of the MOSFET). It should be noted that the above description only uses a MOSFET as an example to illustrate the oscillation frequency of the ring oscillator. When the logic unit of the ring oscillator is another device, its oscillation frequency is also a function of temperature, operating voltage, and process technology. When the ring oscillator is used as the clock source of the chip, the chip's operating frequency is also a function of temperature, operating voltage, and process technology.

[0070] In one embodiment of the present invention, the adaptive frequency adjustment circuit further includes a pre-configuration module. The pre-configuration module is connected to the ring oscillator and is used to pre-configure the number of cascaded inverters in the ring oscillator so that the oscillation frequency of the ring oscillator matches the critical timing path in the processor 3.

[0071] Optionally, please refer to Figure 2The pre-configuration module 13 includes a pre-configuration unit 131, a cascade reduction unit 132, and a cascade increase unit 133. The pre-configuration unit 131 is connected to the ring oscillator and is used to configure the number of cascaded inverters to a preset number. The cascade reduction unit 132 is connected to both the ring oscillator and the pre-configuration unit 131 and is used to successively reduce the number of cascaded inverters after the pre-configuration unit 131 has configured the number of cascaded inverters to the preset number, until a timing violation occurs in the processor 3. The cascade increase unit 133 is connected to both the ring oscillator and the cascade reduction unit 132 and is used to increase the number of cascaded inverters by a margin number after a timing violation occurs in the processor 3.

[0072] Specifically, after power-on, the chip first sets its operating clock to a default clock and starts the ring oscillator. The pre-configuration unit 131 sets the number of inverters in the ring oscillator to a sufficiently long number to ensure that the oscillation frequency of the ring oscillator is low enough to prevent timing violations in the processor 3. Then, the operating clock of the processor 3 is switched to the ring oscillator. Based on this, the cascading reduction unit 132 gradually reduces the number of cascaded inverters in the ring oscillator to increase the oscillation frequency of the ring oscillator until the processor 3 experiences a timing violation under stress test conditions, causing errors in the program or calculation. At this point, the delay generated by the inverters in the ring oscillator can be considered to be basically consistent with the most critical timing path within the processor 3. Based on this, the cascading increase unit 133 increases the number of cascaded inverters in the ring oscillator by a margin number as a margin for the most critical timing path; wherein the margin number is a pre-set integer. In this way, the pre-configuration module 13 can pre-configure the number of inverters cascaded in the ring oscillator, so that the oscillation frequency of the ring oscillator matches the critical timing path in the processor 3. At this time, the oscillation frequency of the ring oscillator can well meet the timing of the most critical timing path in the processor 3.

[0073] Preferably, the ring oscillator is consistent with the threshold voltage of the logic unit in the processor 3. In this case, although the oscillation frequency of the ring oscillator may change under different operating voltages, the oscillation frequency of the ring oscillator can always match the key timing path in the processor 3, thereby achieving self-adaptation to the power supply voltage.

[0074] Please see Figure 3 In one embodiment of the present invention, the frequency difference acquisition module 11 includes a crystal oscillator 111, a frequency converter 112, and a comparator 113.

[0075] The crystal oscillator 111 is used to generate a high-precision reference clock signal Fref and to generate a specific, precise time window to detect the frequency of the voltage-controlled oscillator 2. The frequency of the reference clock signal Fref is, for example, 1 MHz.

[0076] The frequency counter 112 is connected to the crystal oscillator 111 and the voltage-controlled oscillator 2, and is used to obtain the oscillation frequency of the voltage-controlled oscillator 2. Specifically, the frequency counter 112 counts the number of clock cycles of the voltage-controlled oscillator 2 within a precise time window, for example, 1 microsecond, and calculates the clock frequency value of the voltage-controlled oscillator 2. In addition, the frequency counter 112 can also output the average frequency value of the voltage-controlled oscillator 2 for system query.

[0077] The comparator 113 is connected to the frequency counter 112 and is used to compare the oscillation frequency of the voltage-controlled oscillator 2 with a target frequency to obtain the frequency difference signal; wherein, the comparator 113 is a numerical comparator. For example, when the clock frequency generated by the voltage-controlled oscillator 2 is lower than the target frequency, the frequency difference signal output by the comparator 113 is low; otherwise, the frequency difference signal output by the comparator 113 is high.

[0078] Preferably, the adaptive frequency adjustment circuit 1 further includes a low-pass filter 14. The frequency difference acquisition module 11 is connected to the power supply module 12 through the low-pass filter 14. The low-pass filter 14 is used to perform low-pass filtering on the frequency difference signal to make the signal a relatively smooth DC signal Vfb. At this time, the power supply module 12 adjusts its output voltage VDD according to the DC signal Vfb. For example, the power supply module 12 can be implemented using a DC / DC conversion circuit, and the DC signal Vfb is added to the feedback circuit of the DC / DC conversion circuit in a certain proportion to achieve the purpose of adjusting the output voltage of the DC / DC conversion circuit.

[0079] Please see Figure 4 Based on the above description of the adaptive frequency adjustment circuit, the present invention also provides a chip. The chip includes a processor, a voltage-controlled oscillator, and... Figure 1 Alternatively, an adaptive frequency adjustment circuit as shown in Figure 3 may be used. In this circuit, the voltage-controlled oscillator (VCO) and the processor are powered by the same power supply module within the adaptive frequency adjustment circuit, and the VCO and the processor are preferably arranged adjacent to each other on the chip. The adaptive frequency adjustment circuit is connected to the VCO and is used to adjust the operating voltage of the VCO.

[0080] The chip includes at least a portion of the components in the adaptive frequency adjustment circuit of the present invention. For example, the chip may include the entire adaptive frequency adjustment circuit, or it may only include the frequency difference acquisition module 11 in the adaptive frequency adjustment circuit. The chip may be represented as a commercially available active device packaged from an adaptive frequency adjustment circuit manufactured on a wafer using semiconductor technology; or as a commercially available active device packaged from the adaptive frequency adjustment circuit using PCB packaging technology.

[0081] Based on the above description of the adaptive frequency adjustment circuit and the chip, the present invention also provides an electronic device. The electronic device includes... Figure 4 The chip shown.

[0082] Based on the above description of the adaptive frequency adjustment circuit, the present invention also provides an adaptive frequency adjustment method. The adaptive frequency adjustment method is applied to a chip, the chip including a processor and a voltage-controlled oscillator (VCO). The operating voltages of the VCO and the processor are provided by the same power supply module, and the VCO and the processor are preferably disposed adjacent to each other on the chip. The adaptive frequency adjustment method can be used in… Figure 1 or Figure 3 The adaptive frequency adjustment circuit is shown. For details, please refer to [link / reference]. Figure 5 The adaptive frequency adjustment method includes the following steps:

[0083] S51, obtain the difference between the oscillation frequency of the voltage-controlled oscillator and a target frequency. This step S51 can be achieved by... Figure 1 or Figure 3 The frequency difference acquisition module 11 shown is implemented.

[0084] S52, the operating voltage is adjusted based on the difference between the oscillation frequency of the voltage-controlled oscillator and a target frequency, and the adjusted operating voltage is provided to the voltage-controlled oscillator and the processor. The difference between the oscillation frequency generated by the voltage-controlled oscillator under the adjusted operating voltage and the target frequency is within a frequency difference range. This step S52 can be achieved through... Figure 1 or Figure 3 The power module 12 shown is implemented.

[0085] Based on the above description of the adaptive frequency adjustment circuit, the present invention also provides a pre-configuration method applied to a chip, the chip including a processor and a ring oscillator. For details, please refer to... Figure 6 In one embodiment of the present invention, the pre-configuration method can be achieved through... Figure 2 or Figure 3 The pre-configured module 13 shown is implemented, including:

[0086] S61, configure the number of cascaded inverters in the ring oscillator to a preset number of stages. The preset number of stages needs to be long enough to ensure that the oscillation frequency of the ring oscillator is low enough to guarantee that no timing violations occur in the processor.

[0087] S62, gradually reduce the number of cascaded inverters until a timing violation occurs in the processor. Specifically, as the number of cascaded inverters decreases, the oscillation frequency of the ring oscillator increases, and the operating frequency of the processor also increases. Step S62 gradually reduces the number of cascaded inverters until a timing violation occurs in the processor under stress test conditions, causing errors in the program or calculation. At this point, it can be considered that the delay generated by the inverters in the ring oscillator is basically consistent with the most critical timing path inside the processor.

[0088] S63, increase the number of cascaded inverters by a margin level as a margin for the most critical timing path; wherein, the margin level is a pre-set integer.

[0089] Through the above steps S61 to S63, the pre-configuration method can pre-configure the number of inverters cascaded in the ring oscillator, so that the oscillation frequency of the ring oscillator matches the critical timing path in the processor. At this time, the oscillation frequency of the ring oscillator can well meet the timing of the most critical timing path in the processor.

[0090] The scope of protection for the adaptive frequency adjustment method and the pre-configuration method described in this invention is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this invention is included within the scope of protection of this invention.

[0091] As described above, the adaptive frequency adjustment circuit of this invention can adaptively adjust the operating frequency and voltage of the chip according to the chip's manufacturing process. This allows for a higher operating voltage to be configured for chips with inferior manufacturing processes to meet their performance requirements, and a lower operating voltage to be configured for chips with better manufacturing processes to reduce power consumption while still meeting their performance needs. Furthermore, when the chip's operating voltage changes, the adaptive frequency adjustment circuit can adaptively adjust the chip's operating frequency and voltage to ensure chip performance and minimize unnecessary power consumption. Moreover, the adaptive frequency adjustment circuit of this invention does not require a frequency-voltage table to obtain the operating voltage of the chip at each operating frequency point, thus eliminating the need for extensive stability testing and reducing workload.

[0092] Furthermore, the adaptive frequency adjustment circuit of this invention is applied to a chip, which includes a processor and a voltage-controlled oscillator (VCO). The VCO and the processor are in the same power domain, and the processor and the VCO can be placed adjacent to each other on the chip. Therefore, the differences in operating voltage, process technology, and temperature between the VCO and the processor are small. When the operating voltage, process technology, and temperature of the processor change, the power module in the adaptive frequency adjustment circuit can adaptively adjust its output voltage, and the oscillation frequency of the VCO changes accordingly. The changed oscillation frequency always meets the timing requirements of the most critical timing path in the processor, preventing timing violations and logic errors in the processor. Therefore, the adaptive frequency adjustment circuit of this invention can achieve adaptive control of the chip's operating frequency, process technology, operating voltage, and temperature. Using this adaptive frequency adjustment circuit improves the chip's consistency, stability, and other performance characteristics.

[0093] Furthermore, the adaptive frequency adjustment circuit of the present invention automatically adjusts the operating voltage and oscillation frequency of the voltage-controlled oscillator by hardware without the need for software intervention. Therefore, the adjustment speed is fast, and it can follow the changes in operating voltage well and achieve a response speed at the single clock level—that is, a response time at the nanosecond or even picosecond level.

[0094] In summary, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An adaptive frequency adjustment circuit, characterized in that, Applied to a chip, the chip including a processor and a voltage-controlled oscillator (VCO), the VCO being a ring oscillator; the adaptive frequency adjustment circuit includes: A frequency difference acquisition module, connected to the voltage-controlled oscillator, is used to acquire the difference between the oscillation frequency of the voltage-controlled oscillator and a target frequency, and generate a frequency difference signal. A power supply module, connected to the frequency difference acquisition module, the voltage-controlled oscillator (VCO), and the processor, provides operating voltage to the VCO and the processor, adjusts the operating voltage according to the frequency difference signal, and provides the adjusted operating voltage to the VCO and the processor. The difference between the oscillation frequency generated by the VCO under the adjusted operating voltage and the target frequency is within a frequency difference range. A pre-configuration module, connected to the ring oscillator, is used to pre-configure the number of cascaded inverters in the ring oscillator so that the oscillation frequency of the ring oscillator matches the critical timing paths in the processor. The pre-configuration module includes: A pre-configuration unit, connected to the ring oscillator, is used to configure the number of cascaded inverters to a preset number of stages; A cascading reduction unit, connected to the ring oscillator and the pre-configuration unit, is configured to reduce the number of cascaded inverters after the pre-configuration unit has configured the number of cascaded inverters to the preset number of stages, until a timing violation occurs in the processor; and A cascade increase unit, connected to the ring oscillator and the cascade decrease unit, is used to increase the number of cascaded inverters by a margin number after a timing violation occurs in the processor.

2. The adaptive frequency adjustment circuit according to claim 1, characterized in that: The voltage-controlled oscillator and the processor are disposed adjacent to each other on the chip.

3. The adaptive frequency adjustment circuit according to claim 1, characterized in that, The frequency difference acquisition module includes: A crystal oscillator is used to generate a reference clock signal; A frequency meter, connected to the crystal oscillator and the voltage-controlled oscillator, is used to obtain the oscillation frequency of the voltage-controlled oscillator; A comparator, connected to the frequency meter, is used to compare the oscillation frequency of the voltage-controlled oscillator with a target frequency to obtain the frequency difference signal.

4. A chip, characterized in that, The chip includes: processor; Voltage-controlled oscillator; The adaptive frequency adjustment circuit according to any one of claims 1-3 is connected to the voltage-controlled oscillator and the processor, and is used to provide operating voltage for the voltage-controlled oscillator and the processor.

5. An electronic device, characterized in that: The electronic device includes the chip described in claim 4.

6. An adaptive frequency adjustment method, characterized in that, The method is applied to a chip, the chip including a processor and a voltage-controlled oscillator (VCO), the VCO being a ring oscillator, and the operating voltage of the VCO and the processor being provided by the same power supply module; the adaptive frequency adjustment method includes: The number of cascaded inverters in the ring oscillator is pre-configured to match the oscillation frequency of the ring oscillator with the critical timing paths in the processor. Obtain the difference between the oscillation frequency of the voltage-controlled oscillator and a target frequency; The operating voltage is adjusted based on the difference between the oscillation frequency of the voltage-controlled oscillator and the target frequency, and the adjusted operating voltage is provided to the voltage-controlled oscillator and the processor. The difference between the oscillation frequency generated by the voltage-controlled oscillator under the adjusted operating voltage and the target frequency is within a frequency difference range. Pre-configuring the number of cascaded inverters in the ring oscillator to match the oscillation frequency of the ring oscillator with the critical timing paths in the processor includes: The number of cascaded inverters in the ring oscillator is configured to a preset number of stages; Reduce the number of inverters cascaded until a timing violation occurs in the processor; and Increase the number of cascaded inverters by a margin number of stages.

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