Data packet processing method, communication chip and computer equipment

Abstract

The present application discloses a data packet processing method, a communication chip and a computer device, and belongs to the field of computer technology. The method is executed by a communication chip, and the communication chip includes a modem and a hardware accelerator. The method includes: determining the data type corresponding to the received data packet through the modem, storing the data packet in a first queue that matches the priority of the data type among multiple first queues, wherein the priorities of the multiple first queues are different; and processing the data packets in the multiple first queues in order from high to low priority through the hardware accelerator. The above method enables data packets with higher priority of the corresponding data type to be processed earlier, improves the flexibility of processing data packets, and reduces the processing delay of data packets corresponding to high-priority data types.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a data packet processing method, a communication chip, and a computer device. Background Art

[0002] The communication chip can receive data packets sent by other communication chips and process the data packets. In the related art, the communication chip processes data packets according to the reception time of the data packets. The earlier the reception time, the earlier the data packet is processed. The processing method is relatively simple. However, as the number and types of data packets increase, it is urgent to provide a more flexible data packet processing method. Summary of the invention

[0003] The embodiment of the present application provides a data packet processing method, a communication chip and a computer device, which can improve the flexibility of processing data packets. The technical solution is as follows:

[0004] According to one aspect of an embodiment of the present application, a method for processing a data packet is provided, the method being executed by a communication chip, the communication chip comprising a modem and a hardware accelerator; the method comprising:

[0005] Determining, by the modem, a data type corresponding to the received data packet, and storing the data packet in a first queue among a plurality of first queues that matches a priority of the data type, wherein the plurality of first queues have different priorities;

[0006] The data packets in the plurality of first queues are processed in sequence according to the order of priority from high to low through the hardware accelerator.

[0007] According to another aspect of an embodiment of the present application, a communication chip is provided, the communication chip comprising a modem and a hardware accelerator;

[0008] The modem is configured to determine a data type corresponding to a received data packet, and store the data packet in a first queue among a plurality of first queues that matches a priority of the data type, wherein the priorities of the plurality of first queues are different;

[0009] The hardware accelerator is used to process the data packets in the multiple first queues in order from high to low priority.

[0010] According to another aspect of an embodiment of the present application, a data packet processing method is provided, which is executed by a computer device, wherein the computer device includes a communication chip and an application processing chip, and the application processing chip includes a plurality of target memories; the method includes:

[0011] Determine, by means of the communication chip, a data type corresponding to the received data packet, store the data packet in a first queue among a plurality of first queues that matches the priority of the data type, and process the data packets in the plurality of first queues in descending order of priority, wherein the plurality of first queues have different priorities;

[0012] By means of the communication chip, a label of the allocated target memory is added to the processed data packet, and the labeled data packet is stored in the second queue, wherein the target memory allocated to the data packets corresponding to the same data type is the same, and the target memory allocated to the data packets corresponding to different data types is different, and the data packets corresponding to the data types with higher priority have higher priority allocated to the target memory;

[0013] By means of the communication chip, the data packets in the second queue are stored in a target memory corresponding to the carried label;

[0014] The data packets in the multiple target memories are processed by the application processing chip based on the priorities of the multiple target memories.

[0015] According to another aspect of an embodiment of the present application, a computer device is provided, the computer device comprising a communication chip and an application processing chip, the application processing chip comprising a plurality of target memories;

[0016] The communication chip is used to determine the data type corresponding to the received data packet, store the data packet in a first queue among a plurality of first queues that matches the priority of the data type, and process the data packets in the plurality of first queues in order from high to low priority, wherein the plurality of first queues have different priorities;

[0017] The communication chip is further used to add a label of the allocated target memory to the processed data packet, and store the labeled data packet in the second queue, wherein the target memory allocated to the data packets corresponding to the same data type is the same, and the target memory allocated to the data packets corresponding to different data types is different, and the data packets corresponding to the data types with higher priority have higher priority allocated to the target memory;

[0018] The communication chip is further used to store the data packets in the second queue into a target memory corresponding to the carried label;

[0019] The application processing chip is used to process the data packets in the multiple target memories based on the priorities of the multiple target memories.

[0020] In an embodiment of the present application, the modem in the communication chip determines the queue for storing the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the higher the priority of the queue for storing the data packet. The hardware accelerator in the communication chip gives priority to processing data packets in the high-priority queue to determine the processing order of the data packets based on the data type corresponding to the data packet, so that data packets with higher priority of the corresponding data type are processed earlier, thereby improving the flexibility of processing data packets and reducing the processing delay of data packets corresponding to high-priority data types. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of the structure of a communication chip provided by an exemplary embodiment of the present application is shown;

[0023] Figure 2 A flowchart of a data packet processing method provided by an exemplary embodiment of the present application is shown;

[0024] Figure 3 A flowchart of another data packet processing method provided by an exemplary embodiment of the present application is shown;

[0025] Figure 4 A flowchart of another data packet processing method provided by an exemplary embodiment of the present application is shown;

[0026] Figure 5 A schematic diagram showing a data packet processing process provided by an exemplary embodiment of the present application is shown;

[0027] Figure 6 A schematic diagram of the structure of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] In this article, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0030] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned figure descriptions are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0031] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the data packets involved in this application are all obtained with full authorization.

[0032] Figure 1 1 is a schematic diagram of the structure of a communication chip 100 provided in an embodiment of the present application. Figure 1 The communication chip 100 includes a modem 101 and a hardware accelerator 102, wherein the modem 101 is used to determine the data type corresponding to the received data packet, and store the data packet in a first queue among multiple first queues that matches the priority of the data type, and the hardware accelerator 102 is used to process the data packets in the multiple first queues in order from high to low priority.

[0033] Among them, the communication chip 100 can be run on any computer device to implement the data packet processing method provided in this application. Optionally, the computer device is a terminal or a server, wherein the terminal includes various types of terminals such as mobile phones, desktop computers, laptops, tablet computers, wearable devices, vehicle-mounted terminals, household appliances, and intelligent robots. Optionally, the communication chip 100 is connected to an application processing chip to send the processed data packets to the application processing chip for further processing.

[0034] The data packet processing method provided in the embodiment of the present application can be applied in the scenario of autonomous driving. For example, a communication chip and an application processing chip are configured in an autonomous driving vehicle. In addition to the autonomous driving function, the autonomous driving vehicle also has other functions, such as an audio playback function. Accordingly, the autonomous driving vehicle will receive a variety of data packets corresponding to different data types during driving. For example, a data packet containing autonomous driving data and a data packet containing audio data, wherein the autonomous driving data refers to data related to the autonomous driving of the vehicle, such as the control data of the vehicle or the environmental data around the vehicle. Since the data type to which the autonomous driving data belongs is "delay sensitive", and the data type to which the audio data belongs is "non-delay sensitive", and the priority of "delay sensitive" is higher than that of "non-delay sensitive", therefore, after the modem in the communication chip receives the data packet containing the autonomous driving data, the data packet is stored in the first queue of high priority, and after receiving the data packet containing the audio data, the data packet is stored in the first queue of low priority, so that the hardware accelerator in the communication chip can process the data packets in the first queue in the order of priority from high to low, and the data packet containing the autonomous driving data can be processed first, thereby reducing the processing delay of the data packet. The hardware accelerator sends the processed data packets to the application processing chip. After processing the data packets containing the autonomous driving data, the application processing chip controls the driving of the autonomous driving vehicle based on the autonomous driving data. After processing the data packets containing the audio data, the application processing chip plays the audio data.

[0035] The data packet processing method provided in the embodiment of the present application can also be applied in other scenarios, and the embodiment of the present application does not limit this.

[0036] Figure 2 A flowchart of a data packet processing method provided by an exemplary embodiment of the present application is shown. Figure 2 The method is performed by a communication chip, the communication chip includes a modem and a hardware accelerator, and the method includes:

[0037] 201. The communication chip determines the data type corresponding to the received data packet through the modem, and stores the data packet into a first queue among multiple first queues that matches the priority of the data type, wherein the priorities of the multiple first queues are different.

[0038] Among them, the data type corresponding to the data packet is the data type to which the data packet belongs. Optionally, the data types include "delay sensitive" and "non-delay sensitive". "Delay sensitive" data packets have strict requirements on delay, that is, the processing of the data packet must meet low delay conditions. If the delay in processing the data packet is high, it may cause serious impact. However, "non-delay sensitive" data packets do not have strict requirements on delay, that is, the data packet does not need to meet low delay conditions. Even if the delay in processing the data packet is high, it will not cause serious impact. Among them, the priority of "delay sensitive" is higher than that of "non-delay sensitive".

[0039] Optionally, "delay-sensitive" data packets include data packets corresponding to URLLC (Ultra Reliable Low Latency Communication) data. Among them, URLLC data includes data related to application scenarios such as Internet of Vehicles, industrial control, and telemedicine. Optionally, "non-delay-sensitive" data packets include data packets corresponding to eMBB (Enhanced Mobile Broadband) data. Among them, eMBB data includes data related to application scenarios such as ultra-high-definition video, virtual reality, and augmented reality. Among them, the priority of URLLC data is higher than the priority of eMBB data.

[0040] Optionally, the first queue is a FIFO (First Input First Output) memory, which is a first-in-first-out dual-port buffer including an input port and an output port, and the first data to enter the FIFO memory is removed first. Optionally, the first queue is set at any position of the communication chip, for example, in a modem, or in a hardware accelerator, which is not limited in the embodiments of the present application. The priorities of the multiple first queues in the communication chip are different, wherein the higher the priority of the first queue, the higher the priority of the data type corresponding to the stored data packet.

[0041] Optionally, the data packet carries a corresponding data type, and the modem calls MAC (Medium Access Control), RLC (Radio Link Control) and PDCP (Packet Data Convergence Protocol) units to parse the received data packet in sequence to obtain the data type corresponding to the data packet.

[0042] Optionally, the communication chip stores the priorities corresponding to each data type and the priorities corresponding to each first queue. Accordingly, after the modem determines the data type corresponding to the received data packet, it stores the data packet in a first queue among multiple first queues that matches the priority of the data type, including: the modem determines the priority of the data type, and then determines a first queue among multiple first queues that is consistent with the priority, and stores the data packet in the first queue. For example, if the priority of the data type corresponding to the data packet is the first priority, then determine the first queue with the first priority from the multiple first queues, and store the data packet in the first queue. Among them, the priority corresponding to each data type can be set as needed, and the embodiment of the present application does not limit this.

[0043] In a possible implementation, the multiple first queues include a third queue and a fourth queue, the third queue matches the priority of URLLC data, and the fourth queue matches the priority of eMBB data. Accordingly, the communication chip stores the data packet in the first queue that matches the priority of the data type among the multiple first queues through the modem, including: the communication chip stores the data packet in the third queue through the modem when the data packet belongs to URLLC data; or, when the data packet belongs to eMBB data, stores the data packet in the fourth queue.

[0044] For example, the third queue and the fourth queue are the URLLC queue and the eMBB queue, respectively, wherein the priority of the URLLC queue is higher than the priority of the eMBB queue, the eMBB queue is used to store data packets corresponding to eMBB data, and the URLLC queue is used to store data packets corresponding to URLLC data with higher priority.

[0045] In an embodiment of the present application, since URLLC data is more sensitive to latency than eMBB data, the priority of URLLC data is set higher than that of eMBB data, and a fourth queue with a lower priority is used to store data packets corresponding to eMBB data, and a third queue with a higher priority is used to store data packets corresponding to URLLC data. When the data packets are subsequently processed according to the priority of the queue, the data packets corresponding to the URLLC data can be processed earlier, thereby reducing the processing delay of the URLLC data.

[0046] 202. The communication chip processes the data packets in the plurality of first queues in order from high to low priority through a hardware accelerator.

[0047] Among them, the hardware accelerator is used to perform any processing operation on the data packet, for example, parsing the packet header of the data packet, verifying the data packet, filtering the data packet to discard the data packet containing the target data, etc., and the embodiments of the present application do not limit this.

[0048] Each time the modem in the communication chip receives a data packet, it stores the data packet in the corresponding first queue, and the hardware accelerator in the communication chip monitors multiple first queues. As long as there are data packets to be processed stored in multiple first queues, the hardware accelerator will process the data packets in the multiple first queues in order from high to low priority. That is, when there are data packets in the first queue with the highest priority, the hardware accelerator processes the data packets in the first queue, and when there are no data packets in the first queue, the hardware accelerator processes the data packets in the first queue with the next priority, and so on.

[0049] Among them, for any first queue, the hardware accelerator processes the data packets in the first queue according to the first-in-first-out principle, that is, the data packets first stored in the first queue are processed first. Since the data packets in any first queue correspond to the same data type, and the earlier the data packet is received, the earlier it is stored in the first queue, therefore, the data packets in the first queue are processed according to the first-in-first-out principle, so that for multiple data packets corresponding to the same data type, the earlier the data packet is received, the earlier it is processed.

[0050] In an embodiment of the present application, the modem in the communication chip determines the queue for storing the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the higher the priority of the queue for storing the data packet. The hardware accelerator in the communication chip gives priority to processing data packets in the high-priority queue to determine the processing order of the data packets based on the data type corresponding to the data packet, so that data packets with higher priority of the corresponding data type are processed earlier, thereby improving the flexibility of processing data packets and reducing the processing delay of data packets corresponding to high-priority data types.

[0051] exist Figure 2 Based on the shown embodiment, Figure 3 A flowchart of a data packet processing method provided by an exemplary embodiment of the present application is shown. Figure 3 The method is executed by a communication chip, which includes a modem, a hardware accelerator, and a DMA (Direct Memory Access) controller. In this embodiment, the communication chip also stores the processed data packets in a target memory in the application processing chip, so that the application processing chip can continue to process the data packets in the target memory. The method includes:

[0052] 301. The communication chip determines the data type corresponding to the received data packet through the modem, and stores the data packet into a first queue among multiple first queues that matches the priority of the data type, wherein the priorities of the multiple first queues are different.

[0053] For the implementation of the above step 301, please refer to the above step 201, which will not be repeated here.

[0054] 302. The communication chip processes the data packets in the first queue in sequence according to the priority from high to low through the hardware accelerator.

[0055] In one possible implementation, a hardware accelerator is used to verify data packets of a target type, and accordingly, the communication chip processes the data packets in a plurality of first queues in order of priority from high to low through the hardware accelerator, including: the communication chip determines the packet type of each data packet in a plurality of first queues in order of priority from high to low through the hardware accelerator, and verifies the current data packet when the currently determined packet type is the target type. Optionally, the hardware accelerator is specifically used to verify data packets of the target type, and therefore, the verification efficiency of the hardware accelerator is very high. Then, the hardware accelerator is used to verify the data packet of the target type, and the data packet is subsequently sent to the application processing chip, and the application processing chip does not need to verify the data packet, thereby improving the overall processing efficiency of the data packet.

[0056] Optionally, the verification includes accuracy verification, validity verification, etc., wherein the accuracy verification refers to verifying whether an error occurs in the data packet during transmission, and the validity verification refers to verifying whether the data packet is valid, for example, verifying whether the data packet is within the validity period. Optionally, the verification also includes other types of verification, which are not limited in the embodiments of the present application.

[0057] Among them, the target type can be set to any type as needed, for example, IP (Internet Protocol) data packets, UDP (User Datagram Protocol) data packets, TCP (Transmission Control Protocol) data packets, etc., and the embodiments of the present application do not limit this.

[0058] 303. The communication chip adds a tag of the allocated target memory to the processed data packet through the hardware accelerator, and stores the tagged data packet into the second queue.

[0059] Among them, the target memories allocated to data packets corresponding to the same data type are the same, and the target memories allocated to data packets corresponding to different data types are different. In addition, each target memory has a corresponding priority. The higher the priority of the data packet corresponding to the data type, the higher the priority of the target memory allocated to the data packet.

[0060] For example, the target memories allocated to URLLC data packets (i.e., data packets containing URLLC data) are the same, but the target memories allocated to URLLC data packets and eMBB data packets (i.e., data packets containing eMBB data) are different. Moreover, since the priority of URLLC data is higher than that of eMBB data, the priority of the target memory allocated to the URLLC data packet is higher than that of the target memory allocated to the eMBB data packet.

[0061] Optionally, the second queue is a FIFO memory, for example, the second queue is a PCIE (a high-speed serial computer expansion bus standard) FIFO memory. Optionally, the second queue is set at any position of the communication chip, for example, in a hardware accelerator, and the embodiment of the present application does not limit this.

[0062] In a possible implementation, the communication chip adds a tag of the allocated target memory to the processed data packet through a hardware accelerator, including: the communication chip determines the target field in the packet header of the processed data packet through the hardware accelerator; when the target field satisfies the field condition corresponding to any data type, adding a tag of the target memory corresponding to the data type to the processed data packet.

[0063] The target field can be set to any field as required. Optionally, the target field includes a source address, a destination address, a source port, and a destination port. The field condition corresponding to any data type is used to filter data packets corresponding to the data type, that is, if the target field in the header of any data packet meets the field condition corresponding to the data type, it means that the data packet corresponds to the data type.

[0064] Optionally, the hardware accelerator stores field conditions corresponding to each data type and a label of a corresponding target memory, which is the target memory allocated to the data packet corresponding to the data type. Optionally, the field conditions corresponding to each data type and the label of the corresponding target memory are sent to the hardware accelerator by the modem. For example, after determining the data type corresponding to the data packet, the modem sends the field conditions corresponding to the data type and the label of the target memory corresponding to the data type to the hardware accelerator.

[0065] In an embodiment of the present application, the target field in the packet header of the processed data packet satisfies the field condition corresponding to any data type, indicating that the data packet corresponds to the data type. In this case, a label of the target memory corresponding to the data type is added to the processed data packet to ensure the accuracy of the added label.

[0066] Optionally, when the hardware accelerator determines the packet type of each data packet in the plurality of first queues in order of priority from high to low, if the currently determined packet type is other than the target type, the label of the allocated target memory is directly added to the data packet. That is, the hardware accelerator is only used to verify the data packets of the target type, but not to verify the data packets of other types, which can reduce the complexity of the hardware accelerator structure and ensure the processing efficiency of the hardware accelerator.

[0067] 304. The communication chip calls the DMA controller through the hardware accelerator to store the data packets in the second queue into the target memory corresponding to the carried tags.

[0068] Optionally, the communication chip stores the data packets in the second queue in sequence to the target memory, that is, the data packets that enter the second queue first are first stored in the target memory.

[0069] In an embodiment of the present application, data packets corresponding to the same data type are stored in the same target memory through a hardware accelerator, and data packets corresponding to different data types are stored in different target memories. The higher the priority of the target memory, the higher the priority of the data type corresponding to the data packet stored in it. This facilitates the subsequent differentiated processing of the data packets in each target memory according to the priority of the target memory, so as to achieve differentiated processing of data packets corresponding to data types of different priorities, thereby improving the flexibility of processing data packets.

[0070] Since the DMA controller can perform data transmission without occupying the processing resources of the central processing unit in the communication chip, it will not affect the work of the central processing unit. Moreover, since the data transmission efficiency of the DMA controller is high, the hardware accelerator calls the DMA controller to transfer the data packet from the second queue to the target memory, thereby improving the efficiency of storing the data packet in the target memory.

[0071] Optionally, the target memory is a memory in the application processing chip, and after the communication chip stores the data packet in the target memory through the hardware accelerator, the application processing chip continues to process the data packet in the target memory.

[0072] 305. The communication chip determines the timing duration of the current target timer each time a data packet is stored in the corresponding target memory through the hardware accelerator. When the timing duration reaches the target timing duration, an interrupt signal is sent to the application processing chip, and the target timer is restarted.

[0073] The target timer is a timer corresponding to the data type corresponding to the data packet, and the target timing duration of the timer corresponding to the data type with a higher priority is shorter.

[0074] Among them, the interrupt signal is used to request the application processing chip to process the data packet in the target memory, that is, to request the application processing chip to stop the currently executed operation and process the data packet in the target memory instead. Since frequent interruptions will affect the processing efficiency of the application processing chip and increase the load of the application processing chip, the hardware accelerator uses a timer to control the frequency of interrupting the application processing chip. Only when the timing duration of the target timer reaches the target timing duration, that is, when the interval between the time when the data packet is stored in the target memory and the time when the interrupt signal was last sent reaches the target timing duration, the interrupt signal is sent to the application processing chip, instead of sending the interrupt signal to the application processing chip as long as the data packet is stored in the target memory, which effectively reduces the frequency of interrupting the application processing chip. In addition, the target timing duration of the timer corresponding to the data type with higher priority is shorter, so that for the data packet corresponding to the data type with higher priority, the hardware accelerator can send an interrupt signal to the application processing chip as soon as possible, so that the application processing chip can process the data packet corresponding to the data type with higher priority as soon as possible, and reduce the processing delay of the data packet corresponding to the data type with higher priority.

[0075] Optionally, the application processing chip includes a central processing unit, and the interrupt signal is used to request the central processing unit in the application processing chip to process a data packet in the target memory.

[0076] In an embodiment of the present application, data packets of different corresponding data types are stored separately, and data packets corresponding to data types with higher priority are processed preferentially in multiple processing links on the data path (from the modem in the communication chip to the central processing unit in the application processing chip), thereby reducing the processing delay of data packets corresponding to high-priority data types.

[0077] In an embodiment of the present application, the modem in the communication chip determines the queue for storing the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the higher the priority of the queue for storing the data packet. The hardware accelerator in the communication chip gives priority to processing data packets in the high-priority queue to determine the processing order of the data packets based on the data type corresponding to the data packet, so that data packets with higher priority of the corresponding data type are processed earlier, thereby improving the flexibility of processing data packets and reducing the processing delay of data packets corresponding to high-priority data types.

[0078] In the embodiment of the present application, since the efficiency of the hardware accelerator in packet verification is very high, the hardware accelerator is used to verify the target type of data packet, and then the data packet is sent to the application processing chip. The application processing chip does not need to verify the data packet, which improves the overall data packet processing efficiency.

[0079] In an embodiment of the present application, the target field in the packet header of the processed data packet satisfies the field condition corresponding to any data type, indicating that the data packet corresponds to the data type. In this case, a label of the target memory corresponding to the data type is added to the processed data packet to ensure the accuracy of the added label.

[0080] In an embodiment of the present application, data packets corresponding to the same data type are stored in the same target memory through a hardware accelerator, and data packets corresponding to different data types are stored in different target memories. The higher the priority of the target memory, the higher the priority of the data type corresponding to the data packet stored in it. This facilitates the subsequent differentiated processing of the data packets in each target memory according to the priority of the target memory, so as to achieve differentiated processing of data packets corresponding to data types of different priorities, thereby improving the flexibility of processing data packets.

[0081] Figure 4 A flowchart of a data packet processing method provided by an exemplary embodiment of the present application is shown. Figure 4 The method is executed by a computer device, the computer device includes a communication chip and an application processing chip, the application processing chip includes a plurality of target memories, and the method includes:

[0082] 401. The computer device determines the data type corresponding to the received data packet through the communication chip, stores the data packet in a first queue among multiple first queues that matches the priority of the data type, and processes the data packets in the multiple first queues in order from high to low priority.

[0083] Among them, the priorities of the multiple first queues are different.

[0084] 402. The computer device adds a tag of the allocated target memory to the processed data packet through the communication chip, and stores the tagged data packet into the second queue.

[0085] The target memories allocated to data packets corresponding to the same data type are the same, and the target memories allocated to data packets corresponding to different data types are different. Moreover, the target memory allocated to the data packet corresponding to the data type with a higher priority has a higher priority.

[0086] 403. The computer device stores the data packets in the second queue into a target memory corresponding to the carried label through the communication chip.

[0087] For the implementation of steps 401-403, please refer to the above Figure 2 and Figure 3 The embodiments shown will not be described in detail here.

[0088] 404. The computer device processes the data packets in the multiple target memories based on the priorities of the multiple target memories through the application processing chip.

[0089] In one possible implementation, the application processing chip includes a central processing unit (CPU), and the central processing unit includes a processing core. Accordingly, the computer device processes data packets in multiple target memories based on the priorities of the multiple target memories through the application processing chip, including: the computer device processes the data packets in the multiple target memories in order from high to low priority through the processing core. That is, the computer device first processes the data packets in the target memory with the highest priority through the processing core, and then processes the data packets in the next target memory, and so on. Since the data packets stored in the target memory with higher priority have higher priority, the data packets corresponding to the data packets are stored in the target memory with higher priority. Therefore, the processing core processes the data packets in the multiple target memories in order from high to low priority, so that the data packets corresponding to the data types with higher priority are processed earlier, which can reduce the processing delay of the data packets corresponding to the high-priority data types.

[0090] In another possible implementation, the application processing chip includes a central processing unit, the central processing unit includes multiple processing cores with different processing performances, each processing core is associated with a target memory, and the stronger the processing performance of the processing core, the higher the priority of the associated target memory. Accordingly, the computer device processes data packets in multiple target memories based on the priorities of the multiple target memories through the application processing chip, including: the computer device processes the data packets in the associated target memories respectively through the multiple processing cores.

[0091] The multiple processing cores process the data packets in the associated target memory in parallel, that is, the processing cores have no influence on each other and process the data packets in the associated target memory respectively.

[0092] In an embodiment of the present application, the higher the priority of the data packet stored in the target memory, the higher the priority of the data packet, and the stronger the processing performance of the processing core, the higher the priority of the associated target memory, so that the data packet corresponding to the higher priority data type can be processed by the processing core with stronger processing performance, thereby improving the processing efficiency of the data packet corresponding to the high priority data type and reducing the processing delay of the data packet corresponding to the high priority data type.

[0093] Figure 5 A schematic diagram of a data packet processing process provided in an embodiment of the present application, referring to Figure 5 The communication chip includes a modem, a first queue A, a first queue B, a hardware accelerator, and a second queue, wherein the priority of the first queue A is higher than the priority of the first queue B. The application processing chip includes a target memory A, a target memory B, a processing core A, and a processing core B. The priority of the target memory A is higher than the priority of the target memory B, the processing performance of the processing core A is stronger than the processing performance of the processing core B, and the processing core A is associated with the target memory A, and the processing core B is associated with the target memory B. Accordingly, the data packet processing process includes the following steps:

[0094] 1. The modem stores the received data packet in the first queue that matches the priority of the data type, that is, the first queue A or the first queue B, according to the data type corresponding to the received data packet.

[0095] 2. The hardware accelerator first processes the data packets in the first queue A, adds a tag of the allocated target memory A to the processed data packets, and then stores the tagged data packets in the second queue. After the data packets in the first queue A are processed, the data packets in the first queue B are processed, and adds a tag of the allocated target memory B to the processed data packets, and then stores the tagged data packets in the second queue.

[0096] 3. The hardware accelerator calls the DMA controller to transfer the data packets in the second queue to the target memory corresponding to the tag carried, that is, the data packets carrying the tag of target memory A are transferred to target memory A, and the data packets carrying the tag of target memory B are transferred to target memory B.

[0097] 4. The processing core A in the application processing chip processes the data packets in the associated target memory A, and the processing core B processes the data packets in the associated target memory B.

[0098] For the specific implementation of each step, please refer to the above embodiment and will not be repeated here.

[0099] In an embodiment of the present application, the communication chip determines the queue for storing the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the higher the priority of the queue for storing the data packet, and the data packets in the high-priority queue are processed first, so as to determine the processing order of the data packets based on the data type corresponding to the data packet, so that the data packets with higher priority of the corresponding data type are processed earlier, which improves the flexibility of processing data packets and reduces the processing delay of the data packets corresponding to the high-priority data type. In addition, the communication chip stores the processed data packets corresponding to the same data type into the same target memory, and stores the data packets corresponding to different data types into different target memories, and the data type corresponding to the data packets stored in the target memory with higher priority has higher priority, so that the application processing chip processes the data packets in each target memory according to the priority of the target memory, so as to realize the different processing of data packets corresponding to data types with different priorities, and improve the flexibility of data packet processing.

[0100] Figure 6 A schematic diagram of the structure of a computer device 600 provided by an exemplary embodiment of the present application is shown. Figure 6 The computer device 600 includes a communication chip 601 and an application processing chip 602. The application processing chip 602 includes a plurality of target memories 603 ( Figure 6 (In the figure, two target memories 603 are taken as an example).

[0101] The communication chip 601 is used to determine the data type corresponding to the received data packet, store the data packet in a first queue among multiple first queues that matches the priority of the data type, and process the data packets in the multiple first queues in order from high to low priority, wherein the priorities of the multiple first queues are different.

[0102] The communication chip 601 is also used to add a label of the allocated target memory 603 to the processed data packets, and store the labeled data packets in the second queue, wherein the target memories 603 allocated to data packets corresponding to the same data type are the same, and the target memories 603 allocated to data packets corresponding to different data types are different, and the target memories 603 allocated to the data packets corresponding to the higher priority data types have higher priority.

[0103] The communication chip 601 is further used to store the data packets in the second queue into the target memory 603 corresponding to the carried labels.

[0104] The application processing chip 602 is used to process data packets in the multiple target memories 603 based on the priorities of the multiple target memories 603 .

[0105] Among them, the specific way in which the communication chip 601 and the application processing chip 602 implement various functions can be found in the above method embodiment, which will not be repeated here.

[0106] The computer device 600 further includes a central processing unit. Optionally, the central processing unit includes one or more processing cores.

[0107] Optionally, the target memory includes a random access memory (RAM), optionally, the target memory includes a read-only memory (ROM), and optionally, the target memory includes a non-transitory computer-readable storage medium.

[0108] Optionally, the computer device 600 further includes a display screen. The display screen is a display component for displaying a user interface.

[0109] In addition, those skilled in the art will appreciate that the structure of the computer device 600 shown in the above figures does not limit the computer device 600, and the computer device 600 includes more or fewer components than shown, or combines certain components, or arranges components differently. For example, the computer device 600 also includes components such as a microphone, a speaker, an input unit, a sensor, an audio circuit, a power supply, and a Bluetooth module, which will not be described in detail here.

[0110] The serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data packet processing method, characterized in that: The method is performed by a communication chip, wherein the communication chip includes a modem, a hardware accelerator, and a direct memory access (DMA) controller; the method includes: Determining, by the modem, a data type corresponding to the received data packet; In the case where the data packet belongs to ultra-reliable low-latency communication (URLLC) data, storing the data packet in a third queue among a plurality of first queues that matches the priority of the URLLC data through the modem, wherein the priorities of the plurality of first queues are different; In a case where the data packet belongs to enhanced mobile broadband eMBB data, storing, by the modem, the data packet in a fourth queue among the multiple first queues that matches the priority of the eMBB data, the priority of the URLLC data being higher than the priority of the eMBB data; Determine, by the hardware accelerator, the packet type of each data packet in the plurality of first queues in order from high to low priority, and verify the current data packet when the packet type of the current data packet is the target type; In the case where the packet type of the current data packet is other than the target type, or in the case where the current data packet verification is completed, the hardware accelerator adds a tag of the allocated target memory to the current data packet, and stores the tagged data packet in the second queue, wherein the data packet corresponding to the data type with a higher priority has a higher priority of the target memory allocated thereto, and the priority of the target memory is used to indicate the priority of the application processing chip in processing the data packet in the target memory; The DMA controller is called through the hardware accelerator to store the data packets in the second queue into a target memory corresponding to the carried tag.

2. The method according to claim 1, characterized in that: The target memories allocated to data packets corresponding to the same data type are the same, and the target memories allocated to data packets corresponding to different data types are different.

3. The method according to claim 1, characterized in that The communication chip is connected to the application processing chip, the target memory is located in the application processing chip, and the method further includes: By means of the hardware accelerator, each time a data packet is stored in a corresponding target memory, a timing duration of a current target timer is determined, and when the timing duration has reached a target timing duration, an interrupt signal is sent to the application processing chip, and the target timer is restarted; Among them, the target timer is the timer corresponding to the data type corresponding to the data packet, and the higher the priority of the data type, the shorter the target timing duration of the timer corresponding to the data packet. The interrupt signal is used to request the application processing chip to process the data packet in the target memory.

4. The method according to claim 1, characterized in that The step of adding a label of the allocated target memory to the current data packet comprises: Determine a target field in a packet header of the current data packet; In the case that the target field meets the field condition corresponding to any data type, a label of the target memory corresponding to the data type is added to the current data packet.

5. A communication chip, characterized in that: The communication chip includes a modem, a hardware accelerator and a direct memory access DMA controller; The modem is used to determine the data type corresponding to the received data packet; In the case where the data packet belongs to ultra-reliable low-latency communication URLLC data, storing the data packet in a third queue among a plurality of first queues that matches the priority of the URLLC data, wherein the priorities of the plurality of first queues are different; In a case where the data packet belongs to enhanced mobile broadband eMBB data, storing the data packet in a fourth queue among the multiple first queues that matches the priority of the eMBB data, and the priority of the URLLC data is higher than the priority of the eMBB data; The hardware accelerator is used to determine the packet type of each data packet in the plurality of first queues in order from high to low priority, and verify the current data packet when the packet type of the current data packet is the target type; The hardware accelerator is further used to add a label of the allocated target memory to the current data packet when the packet type of the current data packet is other than the target type or when the current data packet verification is completed, store the data packet with the label added to the second queue, call the DMA controller, and store the data packets in the second queue to the target memory corresponding to the carried label, wherein the target memories allocated to data packets corresponding to the same data type are the same, and the target memories allocated to data packets corresponding to different data types are different, and the target memory allocated to the data packet corresponding to a data type with a higher priority has a higher priority, and the priority of the target memory is used to indicate the priority of the application processing chip in processing the data packet in the target memory.

6. A data packet processing method, characterized in that: The method is executed by a computer device, the computer device includes a communication chip and an application processing chip, the application processing chip includes a plurality of target memories; the method includes: Determine, by means of the communication chip, the data type corresponding to the received data packet; if the data packet belongs to ultra-reliable low-latency communication URLLC data, store the data packet in a third queue among multiple first queues that matches the priority of the URLLC data, wherein the priorities of the multiple first queues are different; if the data packet belongs to enhanced mobile broadband eMBB data, store the data packet in a fourth queue among the multiple first queues that matches the priority of the eMBB data, and the priority of the URLLC data is higher than the priority of the eMBB data; determine the packet type of each data packet in the multiple first queues in descending order of priority, and verify the current data packet if the packet type of the current data packet is the target type; By means of the communication chip, when the packet type of the current data packet is other than the target type, or when the current data packet verification is completed, a label of the allocated target memory is added to the current data packet, and the labeled data packet is stored in the second queue, wherein the target memories allocated to data packets corresponding to the same data type are the same, and the target memories allocated to data packets corresponding to different data types are different, and the data packets corresponding to the data types with higher priority have higher priority allocated to the target memory; By means of the communication chip, the data packets in the second queue are stored in a target memory corresponding to the carried label; The data packets in the multiple target memories are processed by the application processing chip based on the priorities of the multiple target memories.

7. The method according to claim 6, characterized in that The application processing chip includes a central processing unit, and the central processing unit includes a processing core; The step of processing the data packets in the plurality of target memories by the application processing chip based on the priorities of the plurality of target memories comprises: The data packets in the plurality of target memories are processed in sequence by the processing core in order of priority from high to low.

8. The method according to claim 6, characterized in that The application processing chip includes a central processing unit, and the central processing unit includes a plurality of processing cores with different processing performances, each of the processing cores is associated with one of the target memories, and the stronger the processing performance of the processing core, the higher the priority of the associated target memory; The step of processing the data packets in the plurality of target memories by the application processing chip based on the priorities of the plurality of target memories comprises: The data packets in the associated target memory are processed respectively by the multiple processing cores.

9. A computer device, characterized in that: The computer device includes a communication chip and an application processing chip, and the application processing chip includes a plurality of target memories; The communication chip is used to determine the data type corresponding to the received data packet; In the case where the data packet belongs to ultra-reliable low-latency communication URLLC data, the data packet is stored in a third queue among multiple first queues that matches the priority of the URLLC data, wherein the priorities of the multiple first queues are different; in the case where the data packet belongs to enhanced mobile broadband eMBB data, the data packet is stored in a fourth queue among the multiple first queues that matches the priority of the eMBB data, and the priority of the URLLC data is higher than the priority of the eMBB data; the packet type of each data packet in the multiple first queues is determined in descending order of priority, and the current data packet is verified if the packet type of the current data packet is the target type; The communication chip is further used for, when the packet type of the current data packet is other than the target type, or when the current data packet verification is completed, adding a label of the allocated target memory to the current data packet, and storing the labeled data packet in the second queue, wherein the target memories allocated to data packets corresponding to the same data type are the same, and the target memories allocated to data packets corresponding to different data types are different, and the data packets corresponding to data types with higher priority have higher priority allocated to the target memory; The communication chip is further used to store the data packets in the second queue into a target memory corresponding to the carried label; The application processing chip is used to process the data packets in the multiple target memories based on the priorities of the multiple target memories.

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