Circuit board manufacturing methods and circuit boards

Abstract

A method for manufacturing a circuit board includes the following steps: providing a metal layer, the metal layer including a first surface; laminating a first shielding layer onto the first surface, patterning the first shielding layer to form a first insulating layer and exposing a portion of the first surface spaced apart; forming a first circuit layer on the first surface, the first circuit layer including a first sub-circuit and a second sub-circuit spaced apart; removing the metal layer corresponding to the first sub-circuit, electroplating the second sub-circuit to form a second circuit layer on the surface of the second sub-circuit; removing the remaining metal layer; covering the two opposite surfaces of the first circuit layer with a first solder resist layer and a second solder resist layer, the first solder resist layer further covering the first insulating layer and the second circuit layer, the second solder resist layer further covering the first insulating layer, to obtain the circuit board. This application also provides a circuit board.

Description

Technical Field

[0001] This application relates to the field of circuit boards, and more particularly to a method for manufacturing a circuit board and the circuit board itself. Background Technology

[0002] With the trend towards miniaturization in electronic products, there is a need to connect several products with similar functions on the same circuit board. To ensure signal integrity and power efficiency, the thickness of the circuit layers on the circuit board usually has different requirements.

[0003] Conventional circuit board manufacturing processes use partial copper plating or partial copper reduction to create circuits of varying thicknesses. However, both methods require at least two pattern transfers of the photosensitive layer, which can easily lead to misalignment between the circuit layers formed during different pattern transfer processes, resulting in a stepped morphology for the thickened circuit layer. In addition, due to the limitations of alignment tolerances, the linewidth requirement for the thickened circuit layer using these methods is generally greater than 200μm, making it unsuitable for small-size packages, high-density fine lines, and thin designs. Furthermore, masking etching is not suitable for thicker metal layers, as it can lead to etching defects. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for manufacturing high-precision circuit boards.

[0005] Additionally, it is necessary to provide a circuit board.

[0006] A method for manufacturing a circuit board includes the following steps:

[0007] A metal layer is provided, the metal layer including a first surface;

[0008] A first shielding layer is pressed onto the first surface, and a first insulating layer is formed by patterning the first shielding layer, exposing a portion of the first surface that is spaced apart.

[0009] A first circuit layer is formed on the first surface, the first circuit layer including a first sub-circuit and a second sub-circuit spaced apart;

[0010] Remove the metal layer corresponding to the first sub-circuit and electroplate the second sub-circuit to form a second circuit layer on the surface of the second sub-circuit;

[0011] Remove the remaining metal layer;

[0012] A first solder resist layer and a second solder resist layer are respectively covered on the two opposite surfaces of the first circuit layer. The first solder resist layer also covers the first insulating layer and the second circuit layer, and the second solder resist layer also covers the first insulating layer to obtain the circuit board.

[0013] In some embodiments, the metal layer further includes a second surface disposed opposite to the first surface; prior to the step of forming the first circuit layer on the first surface, the second shielding layer is further laminated on the second surface, and the second shielding layer is patterned to form a second insulating layer.

[0014] In some embodiments, the thickness of the first shielding layer is greater than the thickness of the second shielding layer along the stacking direction of the first shielding layer, the metal layer, and the second shielding layer.

[0015] In some embodiments, prior to forming the first circuit layer, the fabrication method further includes: removing the unpatterned second masking layer to expose a portion of the second surface; and during the step of forming the first circuit layer, also forming a copper plating layer on the exposed second surface.

[0016] In some embodiments, prior to the step of forming the second circuit layer, the metal layer corresponding to the first sub-circuit is removed; in the step of forming the second circuit layer, the current flowing through the metal layer corresponding to the second sub-circuit is used to electroplate the second sub-circuit to form the second circuit layer on the surface of the second sub-circuit.

[0017] In some embodiments, prior to the step of forming the second circuit layer, the metal layers corresponding to the first sub-circuit and the second sub-circuit are removed; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to electroplate the second sub-circuit to form the second circuit layer.

[0018] In some embodiments, the copper plating layer is removed before the step of forming the second solder resist layer.

[0019] In some embodiments, prior to the step of forming the first circuit layer, the fabrication method further includes covering a resist film on the surface of the second insulating layer opposite to the metal layer, the resist film also covering an unpatterned second masking layer.

[0020] In some embodiments, prior to the step of forming the second circuit layer, the process further includes removing the resist film and the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, the current flowing through the metal layer corresponding to the second sub-circuit is used to electroplate the second sub-circuit to form the second circuit layer on the surface of the second sub-circuit.

[0021] In some embodiments, prior to the step of forming the second circuit layer, the process further includes removing the resist film and the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to electroplate the second sub-circuit to form the second circuit layer.

[0022] A circuit board includes a first insulating layer, a circuit layer, a first solder resist layer, and a second solder resist layer. The circuit layer is embedded in the first insulating layer. The first solder resist layer and the second solder resist layer respectively cover two opposite surfaces of the first insulating layer and also cover two opposite surfaces of the circuit layer. The circuit layer includes a thin copper region and a thick copper region. The thickness of the circuit layer located in the thin copper region is less than the thickness of the circuit layer located in the thick copper region.

[0023] The method for fabricating circuit layers provided in this application involves selectively patterning different areas of the metal layer to create a first circuit layer, and then selectively forming a second circuit layer on the surface of the first circuit layer, thereby achieving the fabrication of locally thick copper circuits. In other words, this method can be achieved through a single pattern transfer, avoiding misalignment between circuit layers caused by multiple different pattern transfer processes. Furthermore, this method requires fewer etching steps and is suitable for high-precision circuit fabrication. Attached Figure Description

[0024] Figure 1 This is a cross-sectional schematic diagram of a first shielding layer and a second shielding layer pressed onto the two surfaces of a metal layer, as provided in an embodiment of this application.

[0025] Figure 2 This is a cross-sectional schematic diagram of the patterned first and second masking layers shown in the figure.

[0026] Figure 3 To remove Figure 2 The diagram shows a cross-sectional view of the first and second masking layers without patterning.

[0027] Figure 4 In order to be in Figure 3 The diagram shows a cross-section of the exposed metal layer after the first surface forms the first circuit layer and the exposed second surface forms the copper plating layer.

[0028] Figure 5 To remove Figure 4 A cross-sectional schematic diagram of the formed copper plating layer and the metal layer corresponding to the first sub-line of the first circuit layer.

[0029] Figure 6 In order to be in Figure 5 The diagram shows a cross-sectional view of the second sub-line surface of the first line layer after the second line layer is formed.

[0030] Figure 7 In order to be in Figure 6 A cross-sectional diagram of the first and second circuit layers after the first solder mask layer has been applied to their surfaces.

[0031] Figure 8 To remove in Figure 7 The diagram shows a cross-section after the metal layer is applied and covered with a second solder resist layer.

[0032] Figure 9 To remove Figure 8 A schematic diagram of the cross-section of the circuit board obtained after the waste area is shown.

[0033] Figure 10 For another embodiment of this application Figure 1 A cross-sectional schematic diagram of the first and second masking layers after patterning.

[0034] Figure 11 In order to be in Figure 10 The diagram shows a cross-section of the second insulating layer surface after it has been covered with an anti-coating film.

[0035] Figure 12 To remove Figure 11 The diagram shows a cross-sectional view of the unpatterned first shielding layer exposing a portion of the metal layer.

[0036] Figure 13 In order to be in Figure 12 A cross-sectional schematic diagram of the exposed metal layer surface after the first circuit layer has been formed.

[0037] Figure 14 To remove Figure 13 The diagram shows a cross-section of the anti-coating film, the unpatterned second masking layer, and the metal layer corresponding to the unpatterned second masking layer.

[0038] Figure 15 In order to be in Figure 14 The diagram shown is a cross-sectional view of the surface of the first circuit layer after the second circuit layer has been formed.

[0039] Figure 16 In order to be in Figure 15 The diagram shows a cross-sectional view of the first circuit layer and the second circuit layer after the first solder resist layer has been applied.

[0040] Figure 17 This is a cross-sectional view of a second sub-line formed on the surface of the second sub-line after removing the metal layers corresponding to the first sub-line and the second sub-line of the first circuit layer in another embodiment of this application.

[0041] Figure 18 for Figure 17The image shown is a top view after the second circuit layer is formed by connecting leads.

[0042] Explanation of main component symbols

[0043] Detailed Implementation

[0044] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Many specific details are set forth in the following description to provide a thorough understanding of this application; the described embodiments are merely some, not all, of the embodiments described in this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0046] Please see Figures 1 to 9 This application provides a method for manufacturing a circuit board 100, including steps S101-S109.

[0047] Step S101: Please refer to Figure 1 A metal layer 10 is provided, the metal layer 10 including a first surface 12 and a second surface 14 disposed opposite to each other, a first shielding layer 20 is pressed onto the first surface 12, and a second shielding layer 30 is pressed onto the second surface 14.

[0048] The metal layer 10 serves to conduct electricity during subsequent electroplating and to support the circuit layer during subsequent circuit layer formation processes. The metal layer 10 can be made of copper, silver, nickel, or other materials.

[0049] The metal layer 10 is removed in the final process. The thickness of the metal can be set according to the capabilities of the equipment. In this embodiment, taking copper foil as an example, the thickness of the copper foil is 9μm-18μm. In other embodiments, this is not a limitation.

[0050] Along the stacking direction L of the first masking layer 20, the metal layer 10, and the second masking layer 30, the thickness of the first masking layer 20 is greater than the thickness of the second masking layer 30. Because the portion of the first masking layer 20 that is selectively copper-plated and exposed / developed on the first surface 12 after subsequent exposure and development processes remains in the final manufactured circuit board 100, the thickness of the first masking layer 20 is relatively large. The second masking layer 30 is used for the subsequent selective etching of the metal layer 10, and it needs to be completely removed in subsequent processes. To avoid excessive thickness increasing the difficulty of removal and damaging other parts of the circuit board 100 that do not need to be removed, the thickness of the second masking layer 30 is relatively small.

[0051] In some embodiments, the thickness of the first shielding layer 20 is greater than 50 μm, and the thickness of the second shielding layer 30 is less than 30 μm.

[0052] The material of the first shielding layer 20 can be a photosensitive film, such as photosensitive polyimide or dry film, or it can be selected from resin materials, such as ABF. Among them, photosensitive polyimide and dry film can form circuit patterns by exposure and development, while resin materials can form circuit patterns by plasma etching.

[0053] In some embodiments, when both the first masking layer 20 and the second masking layer 30 are dry films, the difficulty of removing the first masking layer 20 and the second masking layer 30 differs because the thickness of the first masking layer 20 is greater than the thickness of the second masking layer 30. Specifically, in some embodiments, the first masking layer 20 can be removed by ultrasonic vibration in a special organic stripping solution for a processing time greater than 8 minutes; the second masking layer 30 can be removed using a NaOH solution for a processing time of less than 2 minutes.

[0054] Step S102: Please refer to Figure 2 The first shielding layer 20 is patterned to form a first insulating layer 22, and the second shielding layer 30 is patterned to form a second insulating layer 32.

[0055] In this embodiment, the first masking layer 20, which does not require the formation of a circuit layer, is exposed to transform the exposed portion of the first masking layer 20 into a first insulating layer 22, which ultimately remains in the formed circuit board 100. The first insulating layer 22 includes a first region 22a and a second region 22b, wherein the pattern located in the first region 22a is subsequently used to form a thin copper circuit layer, and the pattern located in the second region 22b is subsequently used to form a thick copper circuit layer.

[0056] The second masking layer 30 is exposed, and the exposed area of ​​the second masking layer 30 includes at least the portion corresponding to the first region 22a, so that in subsequent processes, it is convenient to remove the metal layer 10 corresponding to the first region 22a, thereby facilitating the adjustment of the thickness of the circuit layer formed between the first region 22a and the second region 22b.

[0057] Step S103: Please refer to Figure 3 Remove the unpatterned first masking layer 20 to expose a portion of the first surface 12, and remove the unpatterned second masking layer 30 to expose a portion of the second surface 14.

[0058] In this embodiment, the unpatterned first masking layer 20 and the unpatterned second masking layer 30 are removed by developing. After the first masking layer 20 is removed, a portion of the first surface 12 is exposed for subsequent formation of the circuit layer. The first insulating layer 22 partially masks the first surface 12, and the second insulating layer 32 partially masks the second surface 14.

[0059] Step S104: Please refer to Figure 4 A first circuit layer 50 is formed on the first surface 12, and a copper plating layer 57 is formed on the second surface 14. The first circuit layer 50 includes a first sub-circuit 52 and a second sub-circuit 55.

[0060] In this embodiment, the metal layer 10 is electroplated to form the first circuit layer 50 on the exposed first surface 12. The first circuit layer 50 formed in the first region 22a is a first sub-circuit 52, and the first circuit layer 50 formed in the second region 22b is a second sub-circuit 55. That is, the first circuit layer 50 includes the first sub-circuit 52 and the second sub-circuit 55, which are spaced apart by the first insulating layer 22.

[0061] During the electroplating process, the copper plating layer 57 is formed on the exposed second surface 14.

[0062] Step S105: Please refer to Figure 5 Remove the second insulating layer 32 to expose the second surface 14 corresponding to the first region 22a; remove the copper plating layer 57 and the metal layer 10 corresponding to the first sub-circuit 52.

[0063] In this embodiment, the copper plating layer 57 and the metal layer 10 corresponding to the first sub-circuit 52 are removed by etching. Removing the metal layer 10 corresponding to the first sub-circuit 52 blocks the current flowing through the first sub-circuit 52 during subsequent electroplating, thereby allowing a circuit layer to continue forming on the surface of the first sub-circuit 52.

[0064] In some implementations, to ensure that the metal layer 10 corresponding to the first sub-line 52 is fully removed, the etching intensity is increased so that part of the first sub-line 52 is removed.

[0065] Step S106: Please refer to Figure 6 A second circuit layer 60 is formed on the surface of the second sub-circuit 55.

[0066] In this embodiment, the second circuit layer 60 is formed by electroplating. The second sub-circuit 55 is electroplated by passing current through the metal layer 10 corresponding to the second sub-circuit 55 to form the second circuit layer 60 on the surface of the second sub-circuit 55.

[0067] The first sub-line 52 of the first circuit layer 50 forms a thin copper region I, and the second sub-line 55 of the first circuit layer 50 and the second circuit layer 60 formed on the surface of the second sub-line 55 together form a thick copper region II. In some embodiments, the thickness of the circuit layer located in the thin copper region I is 12μm-20μm, and the thickness of the circuit layer located in the thick copper region II is 40μm-60μm; the circuit layer is formed by an additive method, and the linewidth perpendicular to the stacking direction L is easier to control than the linewidth formed by a subtractive method, and can be less than 30μm.

[0068] Step S107: Please refer to Figure 7 The first solder resist layer 72 covers the surface of the first circuit layer 50 opposite to the metal layer 10, and the first solder resist layer 72 also covers the second circuit layer 60 and the first insulating layer 22.

[0069] Step S108: Please refer to Figure 8 Remove the metal layer 10; cover the surface of the first circuit layer 50 opposite to the first solder resist layer 72 with a second solder resist layer 75, the second solder resist layer 75 also covering the first insulating layer 22.

[0070] The metal layer 10 can be removed by etching to expose the surface of the first circuit layer 50.

[0071] In some embodiments, the step of removing the copper plating layer 57 occurs before the step of covering the second solder resist layer 75.

[0072] Step S109: Please refer to Figure 9 Remove the waste area 85, excluding the product area 82, to obtain the circuit board 100.

[0073] The thin copper region I and the thick copper region II are located within the product region 82. The unnecessary first insulating layer 22, first solder resist layer 72 and second solder resist layer 75 are removed to obtain the circuit board 100.

[0074] In some embodiments, the step of removing the waste zone 85 may be omitted.

[0075] Please see Figure 1 as well as Figures 8 to 16 The method for manufacturing a circuit board 100 provided in another embodiment of this application includes steps S201-S210.

[0076] Step S201: Please refer to again Figure 1 A metal layer 10 is provided, the metal layer 10 including a first surface 12 and a second surface 14 disposed opposite to each other, a first shielding layer 20 is pressed onto the first surface 12, and a second shielding layer 30 is pressed onto the second surface 14.

[0077] That is, step S201 and step S101 can be the same, and will not be described again here.

[0078] Step S202: Please refer to Figure 10 The first shielding layer 20 is patterned to form a first insulating layer 22, and the second shielding layer 30 is patterned to form a second insulating layer 32.

[0079] In this embodiment, the unpatterned second masking layer 30 can be the area corresponding to the subsequent formation of thin copper region I. In other embodiments, the unpatterned second masking layer 30 may also include the area corresponding to the subsequent formation of thick copper region II.

[0080] Step S203: Please refer to Figure 11 An anti-plating film 90 is covered on the surface of the second insulating layer 32, and the anti-plating film 90 is also covered with an unpatterned second masking layer 30.

[0081] The anti-coating film 90 can be made of black opaque material and is laminated under low temperature and low pressure.

[0082] The anti-plating film 90 is used to prevent the formation of a copper plating layer 57 on the second surface 14 of the metal layer 10 during subsequent electroplating processes, thereby reducing the steps required to remove the copper plating layer 57.

[0083] Step S204: Please refer to Figure 12 Remove the unpatterned first masking layer 20 to expose part of the first surface 12.

[0084] Step S205: Please refer to Figure 13The metal layer 10 is electroplated to form a first circuit layer 50 on the first surface 12, wherein the first circuit layer 50 includes a first sub-circuit 52 and a second sub-circuit 55.

[0085] Step S206: Please refer to Figure 14 Remove the anti-coating film 90; remove the unpatterned second masking layer 30 and the metal layer 10 corresponding to the unpatterned second masking layer 30.

[0086] Step S207: Please refer to Figure 15 The second sub-circuit 55 is electroplated to form the second circuit layer 60.

[0087] In this embodiment, the lead wire (not shown) used for electroplating can be directly connected to the metal layer 10 corresponding to the second sub-line 55 for electroplating.

[0088] Step S208: Please refer to Figure 16 The first solder resist layer 72 covers the surface of the first circuit layer 50 opposite to the metal layer 10, and the first solder resist layer 72 also covers the second circuit layer 60 and the first insulating layer 22.

[0089] Step S209: Please refer again Figure 8 Remove the second insulating layer 32 and the metal layer 10; cover the surface of the first circuit layer 50 opposite to the first solder resist layer 72 with a second solder resist layer 75, which also covers the first insulating layer 22.

[0090] Step S210: Please refer to again Figure 9 Remove the waste area 85 to obtain the circuit board 100.

[0091] Please see Figure 17 and Figure 18 In some embodiments, in step S102 or step S202, the area exposed to the second shielding layer 30 may further include a portion corresponding to the second region 22b. In the step of forming the second circuit layer 60, conductive leads may be selectively connected to the first circuit layer 50 formed in the second region 22b, thereby electroplating the second region 22b to form the second circuit layer 60. The leads may be additional connections or conductive leads reserved during the etching process. In this embodiment, electroplating is performed by connecting the second sub-circuit 55 and the metal layer 10 corresponding to the waste area 85. Electroplating by connecting leads avoids alignment errors caused by selective etching during the shielding of the second shielding layer 30, and can reduce the distance d between the thin copper region I and the thick copper region II. The distance d can be less than 50 μm, making this method suitable for higher precision product designs.

[0092] In this embodiment, since the lead is also connected to the metal layer 10 located in the waste area 85, a copper plating layer is formed on the surface of the second sub-line 55 in the waste area 85.

[0093] Please see Figure 9 This application also provides a circuit board 100, which includes a first insulating layer 22, a circuit layer, a first solder resist layer 72, and a second solder resist layer 75. The circuit layer is embedded in the first insulating layer 22. The first solder resist layer 72 and the second solder resist layer 75 respectively cover two opposite surfaces of the first insulating layer 22 and also cover two opposite surfaces of the circuit layer. The circuit layer includes a thin copper region I and a thick copper region II, and the thickness of the circuit layer located in the thin copper region I is less than the thickness of the circuit layer located in the thick copper region II.

[0094] In some embodiments, the first insulating layer 22 is formed by the transformation of the photosensitive first shielding layer 20 under light conditions.

[0095] The distance d between thin copper region I and thick copper region II is less than 50 μm.

[0096] The circuit board 100 manufacturing method provided in this application involves selectively patterning different areas of the metal layer 10 to create a first circuit layer 50, and then selectively forming a second circuit layer 60 on the surface of the first circuit layer 50, thereby achieving the fabrication of locally thick copper circuits. In other words, this manufacturing method can achieve the desired effect with only one pattern transfer, avoiding misalignment between circuit layers caused by multiple different pattern transfer processes. Furthermore, this method requires fewer etching steps and is suitable for high-precision circuit fabrication.

[0097] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, Includes the following steps: A metal layer is provided, the metal layer including a first surface; A first shielding layer is pressed onto the first surface, and a first insulating layer is formed by patterning the first shielding layer, exposing a portion of the first surface that is spaced apart. A first circuit layer is formed on the first surface, the first circuit layer including a first sub-circuit and a second sub-circuit spaced apart; Remove the metal layer corresponding to the first sub-circuit and electroplate the second sub-circuit to form a second circuit layer on the surface of the second sub-circuit; Remove the remaining metal layer; as well as A first solder resist layer and a second solder resist layer are respectively covered on the two opposite surfaces of the first circuit layer. The first solder resist layer also covers the first insulating layer and the second circuit layer, and the second solder resist layer also covers the first insulating layer to obtain the circuit board.

2. The method for manufacturing a circuit board according to claim 1, characterized in that, The metal layer further includes a second surface disposed opposite to the first surface; prior to the step of forming the first circuit layer on the first surface, the second shielding layer is further laminated on the second surface, and the second shielding layer is patterned to form a second insulating layer.

3. The method for manufacturing a circuit board according to claim 2, characterized in that, Along the stacking direction of the first shielding layer, the metal layer, and the second shielding layer, the thickness of the first shielding layer is greater than the thickness of the second shielding layer.

4. The method for manufacturing a circuit board according to claim 2, characterized in that, Prior to the step of forming the first circuit layer, the fabrication method further includes: removing the unpatterned second masking layer to expose a portion of the second surface; and in the step of forming the first circuit layer, also forming a copper plating layer on the exposed second surface.

5. The method for manufacturing a circuit board according to claim 4, characterized in that, Before the step of forming the second circuit layer, the method further includes removing the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, the current flowing through the metal layer corresponding to the second sub-circuit is used to electroplate the second sub-circuit to form the second circuit layer on the surface of the second sub-circuit.

6. The method for manufacturing a circuit board according to claim 4, characterized in that, Before the step of forming the second circuit layer, the metal layers corresponding to the first sub-circuit and the second sub-circuit are removed; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to electroplate the second sub-circuit to form the second circuit layer.

7. The method for manufacturing a circuit board according to claim 4, characterized in that, Prior to the step of forming the second solder resist layer, the step of removing the copper plating layer is also included.

8. The method for manufacturing a circuit board according to claim 2, characterized in that, Prior to the step of forming the first circuit layer, the fabrication method further includes: covering the surface of the second insulating layer opposite to the metal layer with a resist film, the resist film also covering an unpatterned second masking layer.

9. The method for manufacturing a circuit board according to claim 8, characterized in that, Before the step of forming the second circuit layer, the process further includes removing the anti-plating film and the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, the current flowing through the metal layer corresponding to the second sub-circuit is used to electroplate the second sub-circuit to form the second circuit layer on the surface of the second sub-circuit.

10. The method for manufacturing a circuit board according to claim 8, characterized in that, Before the step of forming the second circuit layer, the method further includes removing the anti-plating film and the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to electroplate the second sub-circuit to form the second circuit layer.

11. A circuit board, characterized in that, The circuit board includes a first insulating layer, a circuit layer, a first solder resist layer, and a second solder resist layer. The circuit layer is embedded in the first insulating layer. The first solder resist layer and the second solder resist layer respectively cover two opposite surfaces of the first insulating layer and also cover two opposite surfaces of the circuit layer. The circuit layer includes a thin copper region and a thick copper region. The thickness of the circuit layer located in the thin copper region is less than the thickness of the circuit layer located in the thick copper region. The first insulating layer is formed by transforming a photosensitive first shielding layer under light conditions. The distance between the thin copper region and the thick copper region is less than 50 μm. The circuit layer includes a first circuit layer and a second circuit layer. The first circuit layer is located in the thin copper region and the thick copper region, and the second circuit layer is located in the thick copper region and is located on the surface of the first circuit layer.

Images