A method for preparing a Si-based GaN-HEMT device

Abstract

A method for preparing a Si-based GaN-HEMT device. It relates to the field of semiconductor technology. It includes the following steps: S100, preparing a U-shaped groove on an epitaxial wafer; S200, preparing P-type Si and N-type Si in the U-shaped groove from bottom to top; S300, preparing a SiO2 film in the U-shaped groove; S400, preparing polycrystalline silicon in the U-shaped groove; S500, preparing a gate electrode above the polycrystalline silicon; S600, etching the drain electrode area and preparing the drain electrode; S700, back processing, and preparing the source electrode. Further, in step S100, the epitaxial wafer includes a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer formed in sequence on a Si substrate. The present invention saves the area of ​​the source PAD region on the chip surface; avoids the interface state problem and high-frequency current collapse effect caused by the etching of the current mainstream P-GaN enhanced device, thereby promoting the development and application of Si-based GaN HEMT in the field of power electronics.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a Si-based GaN-HEMT device. Background Art

[0002] In the field of power electronic device technology, as the current mainstream Si devices are getting closer and closer to the performance limit determined by their material properties, third-generation semiconductors represented by GaN and SiC are increasingly valued. GaN has the advantages of large bandgap width, critical breakdown field strength and high electron mobility, and has great application potential in power device markets such as fast charging, data centers, OBCs, and solar inverters.

[0003] Currently, the main application form of GaN in power devices is GaN HEMT devices. Since Khan et al. produced the first AlGaN / GaN high electron mobility transistor (HEMT) in 1993, horizontally structured GaN HEMT devices have attracted widespread attention for their superior electrical performance and lower energy consumption than Si devices. In 2005, Nitronex launched the first commercial depletion-mode RF GaN HEMT device grown on a Si substrate, and in 2009, EPC launched the first enhancement-mode Si-based GaN HEMT device.

[0004] Although GaN HEMT devices have better performance than traditional Si devices, there are still some problems that restrict the application of GaN HEMT devices. For example, the current mainstream P GaN enhancement mode devices require etching of the P GaN layer above the AlGaN. The interface state problems caused by etching will seriously affect the performance of the device at high frequencies and cause serious current collapse effects. Other devices such as F ion implantation enhancement mode GaN HEMT and common source and common gate hybrid enhancement mode GaN HEMT also have disadvantages such as difficult to control process conditions. Summary of the invention

[0005] In view of the above problems, the present invention provides a method for preparing a Si-based GaN-HEMT device, which effectively reduces the interface state problem caused by etching P GaN and improves the heat dissipation performance of the device.

[0006] The technical solution of the present invention is: a method for preparing a Si-based GaN-HEMT device, comprising the following steps:

[0007] S100, preparing a U-shaped groove on the epitaxial wafer;

[0008] S200, preparing P-type Si and N-type Si in sequence from bottom to top in the U-shaped groove;

[0009] S300, preparing SiO2 film in a U-shaped groove;

[0010] S400, preparing polycrystalline silicon in a U-shaped groove;

[0011] S500, preparing a gate electrode on the polysilicon;

[0012] S600, etching the drain electrode region and preparing the drain electrode;

[0013] S700: back side processing and preparation of source electrode.

[0014] Further, in step S100, the epitaxial wafer includes a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer which are sequentially formed on a Si substrate.

[0015] Further, the U-shaped groove preparation method in step S100 includes:

[0016] The epitaxial wafer is sequentially cleaned, coated with photoresist, photolithographed and developed. Then, ICP dry etching is used to etch a U-shaped groove of designed depth on the epitaxial wafer, and finally the photoresist is cleaned off.

[0017] Furthermore, the method for preparing the gate electrode in step S500 includes:

[0018] S510, protecting the area where the gate electrode is located with a photoresist through a coating, photolithography and development process;

[0019] S520, using a metal ion sputtering deposition process to prepare a gate electrode in a designed area on the polysilicon, and then cleaning off the photoresist.

[0020] Furthermore, the preparation method of the drain electrode in step S600 includes:

[0021] S610, protecting the region where the drain removal electrode is located with a photoresist through a coating, photolithography and development process;

[0022] S620, etching a drain electrode groove of a designed depth on the epitaxial wafer using ICP dry etching;

[0023] S630, after cleaning the photoresist in step S610, re-coating, photolithography and development processes are performed to protect the area where the drain electrode is located with photoresist;

[0024] S640, a drain electrode is prepared in the drain electrode groove region by using a metal ion sputtering deposition process, and then the photoresist is cleaned off.

[0025] Further, the method for preparing the source electrode in step S700 includes:

[0026] S710, use UV film to protect the front of the chip;

[0027] S720, thinning the back side of the chip through grinding and polishing processes;

[0028] S730, using a metal ion sputtering deposition process to prepare a source electrode on the back of the chip, and then removing the UV film to complete the preparation.

[0029] The gate structure proposed in the present invention is a U-groove composite gate structure. The composite gate structure is located in the U-groove and forms a MOS-like structure with the n-type Si in the substrate. The on-off of the GaN HEMT is controlled by controlling the on-off of the MOS-like structure channel. The invention has the following advantages: the source of the device is placed at the bottom, saving the area of ​​the source PAD region on the chip surface; the interface state problem and high-frequency current collapse effect caused by etching of the current mainstream P-GaN enhancement mode device are avoided, thereby promoting the development and application of Si-based GaN HEMT in the field of power electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a process flow chart of the present invention,

[0031] Figure 2 is a schematic diagram of step S100,

[0032] Figure 3 is a schematic diagram of step S200,

[0033] Figure 4 is a schematic diagram of step S300,

[0034] Figure 5 is a schematic diagram of step S400,

[0035] Figure 6 is a schematic diagram of step S500,

[0036] Figure 7 is a schematic diagram of step S600,

[0037] Figure 8 is a schematic diagram of step S700,

[0038] Fig. 9 This is the test result of the ratio of the actual current to the saturation current of Sample 1, Sample 2 and the device in this case after the current collapse effect occurs at high frequency.

[0039] Fig.10 This is the thermal resistance test result from junction to case of sample 1, sample 2 and the device in this case under 100% duty cycle condition;

[0040] In the figure, 1 is the source electrode, 2 is the Si substrate, 3 is the buffer layer, 4 is the GaN intrinsic layer, 5 is the drain electrode, 6 is the AlGaN barrier layer, 7 is N-type Si, 8 is the gate electrode, 9 is polysilicon, 10 is SiO2 film, and 11 is P-type Si. DETAILED DESCRIPTION

[0041] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0042] The present invention Figure 1-10 As shown; A method for preparing a Si-based GaN-HEMT device comprises the following steps:

[0043] S100, preparing a U-shaped groove on the epitaxial wafer; Figure 2 As shown;

[0044] Further, in step S100 , the epitaxial wafer includes a buffer layer 3 , a GaN intrinsic layer 4 and an AlGaN barrier layer 6 which are sequentially formed on a Si substrate 2 .

[0045] Further, the U-shaped groove preparation method in step S100 includes:

[0046] The epitaxial wafer is sequentially cleaned, coated with photoresist, photolithographed and developed. Then, ICP dry etching is used to etch a U-shaped groove of designed depth on the epitaxial wafer, and finally the photoresist is cleaned off.

[0047] S200, prepare P-type Si11 and N-type Si7 in the U-shaped groove from bottom to top; Figure 3 As shown;

[0048] S300, preparing SiO2 film 10 in the U-shaped groove; Figure 4 As shown;

[0049] S400, preparing polysilicon 9 in a U-shaped groove; Figure 5 As shown;

[0050] S500, preparing a gate electrode 8 on the polysilicon 9; Figure 6 As shown;

[0051] Furthermore, the method for preparing the gate electrode 8 in step S500 includes:

[0052] S510, protecting the area where the gate electrode 8 is located with photoresist through coating, photolithography and development processes;

[0053] S520, using a metal ion sputtering deposition process to prepare a gate electrode 8 in a designed area on the polysilicon 9, and then cleaning off the photoresist. Figure 6 The device morphology after the gate electrode 8 is prepared in the U-shaped groove.

[0054] S600, etching the drain electrode region and preparing the drain electrode 5; Figure 7 As shown;

[0055] Furthermore, the preparation method of the drain electrode 5 in step S600 includes:

[0056] S610, protecting the area where the drain removal electrode 5 is located with a photoresist through a coating, photolithography and development process;

[0057] S620, etching a drain electrode groove of a designed depth on the epitaxial wafer using ICP dry etching;

[0058] S630, after cleaning the photoresist in step S610, re-coating, photolithography and development processes are performed to protect the area where the drain electrode 5 is located with photoresist;

[0059] S640, using a metal ion sputtering deposition process to prepare a drain electrode 5 in the drain electrode groove region, and then cleaning off the photoresist, Figure 7 The device morphology after etching the drain electrode region and preparing the drain electrode 5 is shown.

[0060] S700, back surface treatment and preparation of source electrode 1; Figure 8 shown.

[0061] Furthermore, the method for preparing the source electrode 1 in step S700 includes:

[0062] S710, use UV film to protect the front of the chip;

[0063] S720, thinning the back side of the chip through grinding and polishing processes;

[0064] S730, using a metal ion sputtering deposition process to prepare a source electrode 1 on the back of the chip, and then removing the UV film, the preparation of the Si-based GaN HEMT new gate structure device proposed by the present invention is completed. Figure 8 The device morphology after back-side processing and preparation of source electrode 1 is shown.

[0065] Reference Figure 8 As shown, the Si-based GaN-HEMT device includes a source electrode 1, a Si substrate 2, a buffer layer 3, a GaN intrinsic layer 4 and an AlGaN barrier layer 6 connected in sequence from bottom to top;

[0066] The drain electrode 5 is located at the end of the device, and extends into the GaN intrinsic layer 4 after passing through the AlGaN barrier layer 6 from top to bottom, ensuring a good connection with the two-dimensional electron gas;

[0067] A U-shaped groove extending from the AlGaN barrier layer 6 to the substrate 2 is provided in the middle of the device;

[0068] A SiO2 film 10 is provided in the U-shaped groove;

[0069] Between the SiO2 film 10 and the inner wall of the U-shaped groove, a P-type Si 11 and an N-type Si 7 are arranged in sequence from bottom to top;

[0070] The middle part of the SiO2 film 10 is provided with polysilicon 9;

[0071] The top of the polysilicon 9 is provided with a gate electrode 8 extending upward. The gate electrode 8 is located above the polysilicon 9, and its lower surface contacts the upper surface of the polysilicon 9 to form an ohmic contact. The gate electrode can be any material that can form an ohmic contact with the polysilicon. The gate electrode 8 is a Ti / Ni metal layer to ensure that the gate electrode 8 forms a good ohmic contact with the polysilicon 9.

[0072] In this case, the U-shaped groove and the composite gate in the groove (including polysilicon 9, SiO2 film 10 and P-type Si 11) constitute the gate structure of the device. The U-shaped groove is formed by etching to provide a vertical conductive channel for the device. The U-shaped groove is deeply etched to the Si substrate layer of the epitaxial wafer and over-etched, and the composite gate structure is located in the groove gate.

[0073] The U-shaped groove needs to be etched into the Si substrate layer of the epitaxial wafer. The bottom of the U-shaped groove can be located at any horizontal plane of the Si substrate layer according to the actual process conditions and electrical parameter design. The width of the U-shaped groove is 100nm-5um, which can be determined according to specific process conditions and machine accuracy.

[0074] Further define P-type Si 11;

[0075] The P-type Si 11 is connected to the inner side wall of the U-shaped groove, has a lower surface flush with the bottom of the U-shaped groove, and an upper surface lower than the upper surface of the GaN intrinsic layer 4 .

[0076] by Figure 8 The direction is the reference direction, and the horizontal thickness of the P-type Si11 from the inner wall of the U-shaped groove to the SiO2 film 10 is 10nm-1um. The P-type Si11 close to the surface of the SiO2 film can form an inversion layer under the condition of a positive gate voltage. The thickness of the inversion layer can generally only reach 10nm. To ensure that the inversion layer can be fully developed inside the P-type Si11, the horizontal thickness of the P-type Si11 is set to 10nm-1um.

[0077] Further define N-type Si 7;

[0078] The lower surface of the N-type Si 7 is in contact with the upper surface of the P-type Si 11 , and the upper surface is flush with the AlGaN barrier layer 6 .

[0079] The thickness of the N-type Si 7 in the horizontal direction is the same as that of the P-type Si 11 .

[0080] The horizontal thickness of P-type Si11 and N-type Si7 is 10nm-1um respectively, ensuring that P-type Si11 can form a saturated current channel under the gate forward bias condition. The sum of the vertical heights of P-type Si11 and N-type Si7 is the U-shaped groove etching depth. The upper surface of P-type Si11 is lower than the horizontal plane where the two-dimensional electron gas of the GaN HEMT device is located, and the upper surface of N-type Si7 is flush with the upper surface of the AlGaN barrier layer 6.

[0081] Further defining the SiO2 film 10;

[0082] The lower surface of the SiO2 film 10 is flush with the lower surface of the P-type Si 11, and the upper surface is flush with the AlGaN barrier layer 6, with a thickness of 5nm-100nm, ensuring that the gate leakage current is less than 1A / cm 2 .

[0083] Further defining polysilicon 9;

[0084] The polysilicon 9 is filled inside the SiO 2 film 10 , and the upper surface is flush with the AlGaN barrier layer 6 .

[0085] The polysilicon 9 is located inside the groove surrounded by the SiO2 film 10, that is, there is no gap or obvious defect inside the polysilicon 9, thus ensuring good electrical conductivity.

[0086] The present invention proposes a novel Si-based GaN HEMT novel gate structure, which avoids the P GaN etching step required for P GaN enhancement mode devices, effectively reduces the interface state problem caused by etching P GaN, which will seriously affect the performance of the device at high frequencies and cause serious current collapse effect. Fig. 9 As shown (the vertical coordinate in the figure represents the percentage of actual current and saturation current after the current collapse effect occurs at high frequency), the current of P GaN enhanced devices on the market (sample 1 and sample 2 in the figure) under high frequency is generally 50%-85% of that under static conditions. The new Si-based GaN HEMT new gate structure device proposed in the present invention (The device in the figure) has an extremely low current collapse effect, and the current under high frequency can reach 95% of that under static conditions. In addition, the gate adopts a vertical conductive structure, the source is located below the chip, and is directly connected to the packaging frame, which enhances the heat dissipation capacity of the device and solves the problem that most of the current mainstream GaN HEMT devices are horizontal structure devices, which are prone to self-heating under high power conditions and the heat cannot be dissipated well. Refer to Fig.10As shown in the figure, under the same power and the same packaging conditions (DFN5*6), the thermal resistance Rthjc from the junction to the packaging surface of the new Si-based GaN HEMT new gate structure device proposed in the present invention is typically 0.5℃ / W, and the thermal resistance Rthjc of the P GaN enhanced device on the market is between 1.1-1.6. The thermal resistance Rthjc of the new Si-based GaN HEMT new gate structure device proposed in the present invention is significantly improved.

[0087] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0088] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0089] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;

[0090] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a Si-based GaN-HEMT device, characterized in that: The following steps are involved: S100, preparing a U-shaped groove on the epitaxial wafer; In step S100, the epitaxial wafer comprises a buffer layer (3), a GaN intrinsic layer (4) and an AlGaN barrier layer (6) which are sequentially formed on a Si substrate (2); S200, preparing P-type Si (11) and N-type Si (7) in sequence from bottom to top in the U-shaped groove; S300, preparing SiO2 film in the U-shaped groove (10); S400, preparing polycrystalline silicon (9) in a U-shaped groove; S500, preparing a gate electrode (8) on the polysilicon (9); S600, etching the drain electrode region and preparing the drain electrode (5); S700, back surface processing and preparation of source electrode (1); The horizontal thickness of the P-type Si (11) from the inner wall of the U-shaped groove to the SiO2 film (10) is 10nm-1um; The horizontal thicknesses of the P-type Si (11) and the N-type Si (7) are 10nm-1um respectively, ensuring that the P-type Si (11) forms a saturated current channel under the gate forward bias condition, the upper surface of the P-type Si (11) is lower than the horizontal plane of the two-dimensional electron gas of the GaN HEMT device, and the upper surface of the N-type Si (7) is flush with the upper surface of the AlGaN barrier layer (6).

2. The method for preparing a Si-based GaN-HEMT device according to claim 1, characterized in that: The U-shaped groove preparation method in step S100 includes: The epitaxial wafer is sequentially cleaned, coated with photoresist, photolithographed and developed. Then, ICP dry etching is used to etch a U-shaped groove of designed depth on the epitaxial wafer, and finally the photoresist is cleaned off.

3. The method for preparing a Si-based GaN-HEMT device according to claim 1, characterized in that: The method for preparing the gate electrode (8) in step S500 includes: S510, protecting the area where the gate electrode (8) is located with photoresist through a coating, photolithography and development process; S520, using a metal ion sputtering deposition process to prepare a gate electrode (8) in a designed area on the polysilicon (9), and then cleaning off the photoresist.

4. The method for preparing a Si-based GaN-HEMT device according to claim 1, characterized in that: The method for preparing the drain electrode (5) in step S600 includes: S610, protecting the area where the drain removal electrode (5) is located with a photoresist through a coating, photolithography and development process; S620, etching a drain electrode groove of a designed depth on the epitaxial wafer using ICP dry etching; S630, after cleaning the photoresist in step S610, re-performing the coating, photolithography and development processes to protect the area where the drain electrode (5) is located with the photoresist; S640, using a metal ion sputtering deposition process to prepare a drain electrode (5) in the drain electrode groove region, and then cleaning off the photoresist.

5. The method for preparing a Si-based GaN-HEMT device according to claim 1, characterized in that: The method for preparing the source electrode (1) in step S700 includes: S710, use UV film to protect the front of the chip; S720, thinning the back side of the chip through grinding and polishing processes; S730, using a metal ion sputtering deposition process to prepare a source electrode (1) on the back side of the chip, and then removing the UV film to complete the preparation.

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