Preparation method of HfO2-based memristor compatible with CMOS backend process and memristor

Abstract

The present application discloses a preparation method of an HfO2-based memristor compatible with CMOS back-end process and a memristor. The preparation method is as follows: select a Si / SiO2 substrate and clean it; form a bottom electrode pattern on the substrate; generate a Ti layer and a Pt layer on the substrate as the bottom electrode; generate an HfO2 layer on the bottom electrode as the dielectric layer; form a top electrode pattern on the HfO2 layer; generate a Ti layer and a Pt layer on the HfO2 layer as the top electrode; form a bottom electrode etching region pattern on the top electrode; etch the bottom electrode etching region to etch away the HfO2 layer; keep the device at a temperature of 250-300 °C in an N2 environment for 60-90 s of metallization annealing to obtain the finished product of the HfO2-based memristor with the structure of Ti / Pt / HfO2 / Ti / Pt. The process of the present application has a low process temperature, small thermal stress, is compatible with the CMOS back-end process, has a 100% yield rate, and helps to realize mass production of devices.

Description

Technical Field

[0001] The present application relates to the field of memristors, and in particular to a preparation method of an HfO2-based memristor and a memristor that is compatible with a CMOS back-end process. Background Art

[0002] At present, the information age is developing rapidly. With the rise of the Internet of Everything, the demand for huge information storage capacity and fast data processing capabilities is becoming increasingly urgent. Semiconductor device technology has been developing in accordance with Moore's Law until 2015, but as the process gradually decreases, Moore's Law is limited by various physical problems and has no market value. The computing paradigm of information processing systems has also entered the eve of change. The traditional computing system is a storage-computation separation system based on the "von Neumann" architecture. The system generates a lot of energy consumption due to data transmission between the central processing unit (CPU) and the memory, which is not conducive to the development of the information age. Take machine learning as an example. Machine learning has a unique way of working. It iterates simple calculations and a large amount of data. There is a huge data flow between the processor and the memory subsystem. If the traditional von Neumann computing architecture is used, the von Neumann bottleneck will be further amplified. In contrast, the neuromorphic computing system consists of multiple neurons and synapses that calculate and store data, and a neural network that communicates with them. The computing system can effectively calculate simple iterations and fundamentally solve the von Neumann bottleneck. In order to build such a system, a new type of component that can imitate biological "synapses" in working mode is urgently needed.

[0003] Common ones include static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory. Among them, SRAM always needs to be connected to a power source, DRAM has a short data retention time, and Flash has low cycle durability. Memristors happen to have similar characteristics to biological synapses. Based on their unique working principles, memristors can realize the functions of a single synapse on a one-to-one basis. Neural networks built based on memristors can imitate the functions of biological nervous systems at the hardware level. Therefore, memristors have been widely studied in recent years. Memristors have the advantages of non-volatility, fast response, and ultra-high integration, providing a reliable solution for storage and computing technology. Based on these superior properties, memristors are considered to be the most promising non-volatile devices for manufacturing new artificial intelligence chips.

[0004] The most common structure of a memristor is a metal / insulator / metal stacking structure, which includes two layers of electrode materials and a layer of functional memristor material. The resistive switching characteristics of the device are closely related to the functional layer materials and electrode materials. In order to be compatible with the CMOS back-end process, binary metal oxides such as TiO are currently used. x , HfO x 、AlO x 、TaOx and ZrO x etc. Among them, more research has been done on HfO x , HfO2 belongs to a dielectric material with a high dielectric constant, the band gap is 5.68 eV, and it has excellent resistive switching performance. Based on HfO x -based memristors can exhibit fast switching speed (<10 ns), large switching ratio (>100), high erasable write times (10 8 times), etc., and have great potential in data storage and brain-inspired computing.

[0005] However, at present, the manufacturing process of HfO x -based memristors is still not perfect, the device reliability is poor, the yield rate is low, it does not meet the commercial standard, and it is difficult to mass-produce. Summary of the Invention

[0006] In order to improve the problems of poor device reliability and low yield rate during the manufacture of HfO x -based memristors, this application provides a preparation method and a memristor of an HfO2-based memristor compatible with the CMOS back-end process.

[0007] First, the memristor and its resistive switching phenomenon are described. The memristor is mainly composed of a three-layer structure similar to a metal-dielectric-metal capacitor. Generally speaking, the resistive switching phenomenon refers to the reversible change between two or more resistance states of the dielectric material in the middle of the three-layer structure by changing the voltage applied to the metal layer. When the voltage applied to the metal layer is removed, this resistance state does not change. First, a large voltage needs to be applied to the top electrode for the Forming operation (the threshold voltage required for the device resistance to jump is called the Forming voltage) to make the device in a soft breakdown state. At this time, oxygen atoms in the oxide layer gather towards the top electrode under the action of the electric field, and oxygen vacancies in the oxide layer form stable conductive filaments, connecting the two end electrodes, converting the high resistance state (HRS) to the low resistance state (LRS). This process can be called the Set process. Then, a negative voltage is applied at the top electrode, and oxygen ions return to their original positions, canceling out the oxygen vacancies, promoting the movement of the defects that make up the conductive filaments, so that the conductive filaments break, and the device changes from the low resistance state (LRS) to the high resistance state (HRS). This process is called the Reset process.

[0008] In the first aspect, this application provides a preparation method of an HfO2-based memristor compatible with the CMOS back-end process, adopting the following technical solution:

[0009] A preparation method of an HfO2-based memristor compatible with the CMOS back-end process, including the following steps:

[0010] Select a Si / SiO2 substrate and clean the Si / SiO2 substrate to remove impurities;

[0011] The bottom electrode pattern is formed on the Si / SiO2 substrate by using ultraviolet lithography technology;

[0012] The Ti layer and the Pt layer are deposited on the Si / SiO2 substrate by using electron beam evaporation technology as the bottom electrode, and the Ti layer is located between the SiO2 layer and the Pt layer;

[0013] The HfO2 layer is deposited on the bottom electrode by using atomic layer deposition technology as the dielectric layer;

[0014] The top electrode pattern is formed on the HfO2 layer by using ultraviolet lithography technology;

[0015] The Ti layer and the Pt layer are deposited on the HfO2 layer by using electron beam evaporation technology as the top electrode, and the Ti layer is located between the HfO2 layer and the Pt layer;

[0016] The bottom electrode etching area pattern is formed on the top electrode by using ultraviolet lithography technology;

[0017] The bottom electrode etching area is etched to remove the HfO2 layer to expose the bottom electrode, and the HfO2-based memristor semi-finished product is obtained;

[0018] The HfO2-based memristor semi-finished product is annealed for 60 - 90 s at a temperature of 250 - 300 °C in an N2 environment to obtain the HfO2-based memristor finished product with the structure of Ti / Pt / HfO2 / Ti / Pt.

[0019] In the preparation method of this application, the annealing temperature of the device is controlled at 250 - 300 °C, which is compatible with the CMOS back-end process. During preparation, the thermal stress on the device is low, greatly reducing the possibility of device damage or failure, and the yield rate is high, up to 100%. It helps to realize the mass production of the device, the uniformity and stability of the device performance are good, and good synaptic performance can be obtained subsequently, promoting the development of the hardware implementation of low-bit neural networks. And the V reset and V set are small and uniform, which is beneficial to reducing power consumption. In addition, the prepared device is a Forming-Free device, and no subsequent Forming treatment is required, reducing the device test cost. A Forming-Free device is considered to be a device that does not require a Forming operation.

[0020] In this application, the Pt layer is in contact with the HfO2 layer at the interface of the bottom electrode, and the Ti layer is in contact with the HfO2 layer at the interface of the top electrode. For the device treated by metallization annealing, the Ti layer will absorb oxygen atoms from the oxide layer (i.e., the HfO2 layer) to form TiO x layer, and a large number of oxygen vacancies are formed inside the HfO2 layer. The high concentration of oxygen vacancy content is beneficial to the formation of conductive filaments.

[0021] Preferably, the metallization annealing step of the HfO₂-based memristor semi-finished product includes:

[0022] Heat the HfO₂-based memristor semi-finished product to 200 °C at a heating rate of 50 °C / s;

[0023] Maintain the temperature at 200 °C and introduce N₂ until the N₂ atmosphere is stable;

[0024] Heat to 250 - 300 °C at a heating rate of 20 °C / s, hold for 60 - 90 s, and then cool to room temperature to complete annealing.

[0025] Preferably, the cleaning step of the Si / SiO₂ substrate includes:

[0026] First, put the Si / SiO₂ substrate into deionized water and ultrasonically clean it for 3 - 5 min;

[0027] Then, put the Si / SiO₂ substrate into acetone and ultrasonically clean it for 3 - 5 min;

[0028] Next, put the Si / SiO₂ substrate into isopropyl alcohol and ultrasonically clean it for 3 - 5 min;

[0029] Finally, dry the Si / SiO₂ substrate with nitrogen.

[0030] Preferably, the thickness of the SiO₂ layer in the Si / SiO₂ substrate is not less than 300 nm.

[0031] Through experiments, when the thickness of the SiO₂ layer in the Si / SiO₂ substrate is less than 300 nm, its insulation performance is poor, which affects the subsequent testing and application of the memristor.

[0032] Preferably, the thickness of the Ti layer is 10 nm, the thickness of the Pt layer is 20 nm, and the thickness of the HfO₂ layer is 5 nm.

[0033] Through experiments, the memristor prepared with the Ti layer, Pt layer, and HfO₂ layer of this thickness selection has better performance.

[0034] In a second aspect, the present application provides a memristor, adopting the following technical solution:

[0035] A memristor is prepared by the preparation method of the HfO₂-based memristor in the above technical solution.

[0036] By adopting the above technical solution, the number of internal conductive filaments of the manufactured device increases, the Forming voltage is reduced, the Forming process of the device can be omitted, it is a Forming-Free device, the testing cost is reduced, and the uniformity and stability of the device are high.

[0037] In summary, the present application includes at least one of the following beneficial technical effects:

[0038] 1. The process temperature of the present application is low, the thermal stress is small, it is compatible with the CMOS back-end process, and has a 100% yield rate, which helps to realize mass production of devices; the prepared device is a Forming-Free device, and no Forming treatment is required, reducing the test cost. The V of the device reset and V set are small, which is beneficial to reducing power consumption. In addition, the stability and uniformity of the device performance are good, and good synaptic performance can be obtained subsequently, which is beneficial to promoting the development of low-bit neural network hardware.

[0039] 2. The internal conductive filaments of the device prepared in the present application increase, reducing the Forming voltage, eliminating the Forming process of the device, being a Forming-Free device, reducing the test cost, and having high uniformity and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a flowchart of the preparation method of the HfO2-based memristor in the embodiment of the present application;

[0041] Figure 2 is a schematic diagram of the preparation of the HfO2-based memristor in the embodiment of the present application;

[0042] Figure 3 is a schematic diagram of the principle of the formation of conductive filaments of the HfO2-based memristor in the embodiment of the present application;

[0043] Figure 4 is a graph of the Forming test of the HfO2-based memristor prepared in Examples 1-2 and Comparative Examples 1-2 of the present application;

[0044] Figure 5 is the resistance conversion curve of the HfO2-based memristor prepared in Example 1 of the present application;

[0045] Figure 6 is the resistance conversion curve of the HfO2-based memristor prepared in Example 2 of the present application;

[0046] Figure 7 is a schematic diagram of the LTP / LTD test scheme of the HfO2-based memristor prepared in Example 2 of the present application;

[0047] Figure 8 is a schematic diagram of the single-pulse test scheme of the HfO2-based memristor prepared in Example 2 of the present application;

[0048] Figure 9 is the LTD graph measured for the HfO2-based memristor prepared in Example 2 of the present application;

[0049] Figure 10 It is a schematic diagram of the layer structure of the HfO2-based memristor according to an embodiment of the present application;

[0050] Explanation of reference numerals: 1, bottom electrode; 2, dielectric layer; 3, top electrode. Detailed implementation manners

[0051] To more conveniently understand the technical solution of the present application, the present application will be further described in detail below in combination with tables, drawings and embodiments, but it does not constitute the scope of protection defined by the present application.

[0052] Embodiment

[0053] Embodiment 1

[0054] This embodiment discloses a preparation method of an HfO2-based memristor compatible with the CMOS back-end process. Referring to Figure 1 and Figure 2 , the method includes the following steps:

[0055] Select a Si / SiO2 substrate. The Si / SiO2 substrate is composed of a Si layer and a SiO2 layer. The SiO2 layer is the upper layer and has a thickness of 300 nm. Clean the Si / SiO2 substrate to remove impurities. The specific steps are as follows: Put the Si / SiO2 substrate into deionized water and ultrasonically clean it for 3 minutes, then put the Si / SiO2 substrate into acetone and ultrasonically clean it for 3 minutes, then put the Si / SiO2 substrate into isopropyl alcohol and ultrasonically clean it for 3 minutes, and finally dry the Si / SiO2 substrate with a nitrogen gun;

[0056] Use ultraviolet lithography technology to form a bottom electrode pattern on the Si / SiO2 substrate, and generate a Ti layer and a Pt layer on the Si / SiO2 substrate as the bottom electrode through an electron beam evaporation system. The specific steps are as follows: First deposit a Ti layer with a thickness of 10 nm on the SiO2 layer, and then deposit a Pt layer with a thickness of 20 nm on the Ti layer. The Ti layer is located between the SiO2 layer and the Pt layer;

[0057] Generate an HfO2 layer on the bottom electrode through an atomic layer deposition system (ALD). The thickness of the HfO2 layer is 5 nm, and the layer in contact with the interface between the bottom electrode and the HfO2 layer is the Pt layer;

[0058] Use ultraviolet lithography technology to form a top electrode pattern on the HfO2 layer, and generate a Ti layer and a Pt layer on the HfO2 layer as the top electrode through an electron beam evaporation system. The layer in contact with the interface between the top electrode and the HfO2 layer is the Ti layer, and the Ti layer is located between the HfO2 layer and the Pt layer;

[0059] The pattern of the bottom electrode etching region is formed on the top electrode by using the ultraviolet lithography process. The bottom electrode etching region is etched by using the inductively coupled plasma (ICP) etching method to etch away the HfO2 layer, exposing the bottom electrode, and obtaining a semi-finished HfO2-based memristor;

[0060] The semi-finished HfO2-based memristor is annealed for 60 s after metallization at a temperature of 250 °C in an N2 environment by using a rapid thermal processing (RTP) furnace. The specific steps are as follows: the semi-finished HfO2-based memristor is heated to 200 °C at a heating rate of 50 °C / s, the temperature is maintained at 200 °C, N2 is introduced until the N2 atmosphere is stable, then it is heated to 250 °C at a heating rate of 20 °C / s, kept at 250 °C for 60 s, and then cooled to room temperature to complete the annealing, obtaining a finished HfO2-based memristor with the structure of Ti / Pt / HfO2 / Ti / Pt.

[0061] Refer to Figure 3 , for the HfO2-based memristor treated by annealing after metallization, the Ti layer will absorb oxygen atoms from the HfO2 layer to form a TiO x layer, and a large number of oxygen vacancies are formed inside the HfO2 layer. The high concentration of oxygen vacancy content is beneficial to the formation of conductive filaments.

[0062] Example 2

[0063] The difference from Example 1 is that the annealing temperature of the semi-finished HfO2-based memristor is 300 °C.

[0064] Comparative example

[0065] Comparative example 1

[0066] The difference from Example 1 is that the semi-finished HfO2-based memristor is not annealed.

[0067] Comparative example 2

[0068] The difference from Example 1 is that the annealing temperature of the semi-finished HfO2-based memristor is 200 °C.

[0069] Comparative example 3

[0070] The difference from Example 1 is that the annealing temperature of the semi-finished HfO2-based memristor is 400 °C.

[0071] Performance detection test

[0072] Forming test: Ground the bottom electrode, apply a positive voltage that increases from 0 V to a specific value +V Forming and finally decreases to 0 V to the top electrode, set a current limiting value of 10 μA to protect the device, and the test results are as Figure 4 shown. Since the voltage at which the mutation occurs is uncertain during the Forming test, in the present invention, when no annealing treatment is performed, the specific value +VForming Set to +3V. During normal I-V testing, a specific value +V Forming Set to +1.5V. The purpose of the Forming operation is to activate the device and allow the device to form conductive filaments.

[0073] From Figure 4 As can be seen from the curve graph of, the V of the unannealed device, the device annealed at 200 °C, and the device annealed at 250 °C Forming are +2.6V, +1.85V, and +1.45V respectively. The Forming voltage gradually decreases with the increase of the annealing temperature. When unannealed, there is an obvious sudden increase in current at +2.6V on the curve. At this time, conductive filaments are formed inside the device, and the voltage at this point is called V Forming , when the annealing temperature is 250 °C, there is no sudden increase in current on the curve, which can correspond to the Set part in the I-V curve and can also be considered a Forming-Free device. A Forming-Free device is considered a device that does not require the Forming operation. When the annealing temperature is 300 °C and 400 °C, the device also shows Forming-Free characteristics. However, when the annealing temperature is 400 °C, it is found that the device is short-circuited during the test, so it is not shown in the figure.

[0074] Among them, the devices annealed at 250 °C, 300 °C, and 400 °C do not require the Forming process and are Forming-Free devices, which reduces the test cost. At the same time, this result proves that the method of this application helps the generation of the TiO x layer, promotes the increase of conductive filaments, and thus reduces the Forming voltage.

[0075] Yield test: According to the change of the biological synaptic weight from +100% to -50%, with a 4-fold dynamic switching ratio, the yield is defined as the proportion of devices in which the test device is successfully Formed and the first Reset has a switching ratio of more than 4 times.

[0076] Take 106 finished HfO2-based memristors prepared in Examples 1-2, 106 finished HfO2-based memristors prepared in Comparative Example 1, 74 finished HfO2-based memristors prepared in Comparative Example 2, and 97 finished HfO2-based memristors prepared in Comparative Example 3 for testing. Among them, some devices are tested as single devices, and some devices are tested as array devices (such as 2×2, 3×3, 4×4, etc.); the test results are shown in Table 1.

[0077] Table 1: Yield of finished HfO2-based memristors prepared in Examples 1-2 and Comparative Examples 1-3

[0078]

[0079] As can be seen from the results in Table 1, when the annealing temperature is 250 °C and 300 °C, the yield rate of the devices is 100%. When the devices are not annealed, the yield rate of the devices is 50.9%, which does not meet the industrial standard. When the annealing temperature is 200 °C, the qualified rate of the devices is 93.4%, but it is found that the device performance is unstable during testing, manifested as unstable and irregular switching ratio, poor repeatability, and the I-V test can only be carried out up to 20 cycles at most. When the annealing temperature is 400 °C, the qualified rate of the devices is only 4.1% because the too high annealing temperature destroys the internal structure of the devices, resulting in abnormal short connections and breaks of the conductive filaments. Therefore, the HfO₂-based memristors prepared at the annealing temperatures of 250 °C and 300 °C have a higher yield rate and more stable performance.

[0080] DC resistive switching characteristics and switching ratio: Twenty HfO₂-based memristors prepared in Examples 1 and 2 were selected for 50-cycle I-V tests. The device specifications were 8 μm × 8 μm. The bottom electrode was grounded, and voltages of 0 V to -1.5 V to 0 V and 0 V to +1.5 V to 0 V were applied to the top electrode, with a limited current of 500 μA. The test was carried out for 50 cycles, and the test results are as Figure 5 and Figure 6 shown. Since the yield rates of the HfO₂-based memristors prepared in Comparative Examples 1 and 3 are low, and the performance of the HfO₂-based memristor prepared in Comparative Example 2 is unstable, only the HfO₂-based memristors prepared in Examples 1 and 2 were tested.

[0081] From Figure 5 and Figure 6 it can be seen that the resistance conversion of the HfO₂-based memristors prepared in Example 1 and Example 2 is relatively uniform and stable. When a positive scanning voltage was applied to the top electrode of the device at 0 to +1.5 V, with the limited current set to 500 μA, the voltage corresponding to the current mutation point during the scanning process was the Set voltage. When a negative scanning voltage of 0 to -1.5 V was applied to the top electrode of the device, it was found that the Reset process of the device was of a slow change type. As Figure 5 , the V set of the HfO₂-based memristor prepared in Example 1 was about 0.6 V, and the V reset was about -0.9 V; as Figure 6 , the V set of the HfO₂-based memristor prepared in Example 2 was about 0.8 V, and the V reset was about -0.75 V. Reading the switching ratio (I on / I off ) of the HfO₂-based memristor prepared in Example 1 and the HfO₂-based memristor prepared in Example 2 from -0.2 V, it was found that for the HfO₂-based memristor when the annealing temperature was 250 °C, the Ion / I off is about 150, and the I of the HfO2-based memristor when the annealing temperature is 300 °C on / I off is about 48. When applied in a neural computing system, the larger the switching ratio is not necessarily better. A switching ratio of 10-20 times is more suitable for the application of neural computing systems.

[0082] Synaptic characteristics and conductance regulation: First, apply a wide pulse of +1.5V, 300 μs to completely Set the device to the highest conductance state, then apply a single narrow pulse of -1.5V, 50 ns to inhibit the device, and then use a +0.2V pulse to read the conductance of the device.

[0083] Since the HfO2 memristor after annealing treatment at 300 °C has a lower switching ratio, pulse tests were performed on the HfO2 memristor after annealing treatment at 300 °C. First, long-term potentiation / long-term depression (LTD / LTP) tests were carried out. The test scheme of LTP / LTD is as Figure 7 shown.

[0084] Select a range of conductance values with better linearity from 100 μS to 1000 μS and divide it into 10 stages, and then conduct conductance regulation tests with single-pulse tests. The tests use the same pulse amplitude. For each conductance value obtained within a range, a 1000s retention test is carried out, and so on, to obtain 10 states, while recording the number of pulses. The single-pulse test scheme is shown in Figure 8 .

[0085] The specific test scheme is as follows: First, apply a wide pulse of +1.5V, 200 μs to the device to make the device in a completely low-resistance state. Then use a narrow pulse of -1.5V, 50 ns to write to the device, and use 0.2V to read the conductance value. The conductive filaments of the memristor will be weakened under the reset pulse respectively, resulting in long-term depression behavior, and finally obtaining multi-level conductance states from 77.5 μS to 1280 μS.

[0086] Refer to Figure 9 , the 10 conductance states are 77.5 μS, 183 μS, 372 μS, 455 μS, 557 μS, 654 μS, 722 μS, 816 μS, 925 μS, 1050 μS respectively. The test results show that the device has 10 stable and adjustable conductance states, which are suitable for the calculation of 3-bit neural networks.

[0087] This embodiment of the application also discloses an HfO2-based memristor, which is prepared by the preparation method of the HfO2-based memristor compatible with the CMOS back-end process in the above embodiment. Refer to Figure 10, the HfO2-based memristor includes a bottom electrode 1 composed of a Ti layer and a Pt layer, a dielectric layer 2 composed of HfO2, and a top electrode 3 composed of a Ti layer and a Pt layer. The layer in contact with the HfO2 dielectric layer 2 at the interface of the bottom electrode 1 is the Pt layer, and the layer in contact with the HfO2 dielectric layer 2 at the interface of the top electrode 3 is the Ti layer.

[0088] This specific embodiment is only an interpretation of the present application and does not limit the present application. After reading this specification, those skilled in the art can make modifications to this embodiment that do not contribute creatively as needed, but as long as it is within the scope of the claims of the present application, it is protected by the patent law.

Claims

1. A preparation method of an HfO2-based memristor compatible with CMOS back-end process, characterized in that, It includes the following steps: Select a Si / SiO2 substrate and clean the Si / SiO2 substrate to remove impurities; Use ultraviolet lithography to form a bottom electrode pattern on the Si / SiO2 substrate; Use electron beam evaporation to deposit a Ti layer and a Pt layer on the Si / SiO2 substrate as the bottom electrode, and the Ti layer of the bottom electrode is located between the SiO2 layer and the Pt layer; Use atomic layer deposition to deposit a HfO2 layer on the bottom electrode as the dielectric layer; Use ultraviolet lithography to form a top electrode pattern on the HfO2 layer; Use electron beam evaporation to deposit a Ti layer and a Pt layer on the HfO2 layer as the top electrode, and the Ti layer of the top electrode is located between the HfO2 layer and the Pt layer; Use ultraviolet lithography to form a bottom electrode etching area pattern on the top electrode; Etch the bottom electrode etching area to etch away the HfO2 layer and expose the bottom electrode to obtain a HfO2-based memristor semi-finished product; Keep the temperature of the HfO2-based memristor semi-finished product at 250 - 300 °C in an N2 environment and anneal it metallurgically for 60 - 90 s to obtain a HfO2-based memristor finished product with a structure of Ti / Pt / HfO2 / Ti / Pt.

2. The preparation method of an HfO2-based memristor compatible with CMOS back-end process according to claim 1, characterized in that, The metallurgical annealing step of the HfO2-based memristor semi-finished product includes: Heat the HfO2-based memristor semi-finished product to 200 °C at a heating rate of 50 °C / s; Keep the temperature at 200 °C and introduce N2 until the N2 atmosphere is stable; Heat to 250 - 300 °C at a heating rate of 20 °C / s, keep it for 60 - 90 s, and then cool to room temperature to complete annealing.

3. The preparation method of an HfO2-based memristor compatible with CMOS back-end process according to claim 1, characterized in that, The cleaning step of the Si / SiO2 substrate includes: First, put the Si / SiO2 substrate into deionized water and ultrasonically clean it for 3 - 5 min; Then, put the Si / SiO2 substrate into acetone and ultrasonically clean it for 3 - 5 min; Next, put the Si / SiO2 substrate into isopropyl alcohol and ultrasonically clean it for 3 - 5 min; Finally, dry the Si / SiO2 substrate with nitrogen.

4. The preparation method of an HfO2-based memristor compatible with CMOS back-end process according to claim 1, characterized in that: The thickness of the SiO2 layer in the Si / SiO2 substrate is not less than 300 nm.

5. The preparation method of an HfO2-based memristor compatible with CMOS back-end process according to claim 1, characterized in that: The thickness of the Ti layer is 10 nm, the thickness of the Pt layer is 20 nm, and the thickness of the HfO2 layer is 5 nm.

6. A memristor, characterized in that: It is obtained by the preparation method of a HfO2-based memristor compatible with CMOS backend process according to any one of claims 1 to 5.

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