A low noise low offset voltage dynamic comparator circuit and electronic device

Abstract

The application provides a low-noise low-offset voltage dynamic comparator circuit, comprising a preamplifier and a dynamic comparator, and further comprising: a new MOS transistor arranged between a target MOS transistor in the dynamic comparator and a ground terminal; the target MOS transistor is a MOS transistor for adjusting the driving voltage of an input MOS transistor of the dynamic comparator; the gate terminal and the drain terminal of the new MOS transistor are connected with the source terminal of the target MOS transistor, and the source terminal of the new MOS transistor is grounded. The scheme changes the working process of the dynamic comparator by adding the new MOS transistor, can generate a larger voltage difference at the source of the corresponding MOS transistor when the dynamic comparator starts to establish the output through positive feedback, and thus can significantly inhibit the damage of thermal noise and MOS transistor mismatch to the comparison accuracy of the dynamic comparator.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically to a low-noise, low-offset voltage dynamic comparator circuit and electronic device. Background Technology

[0002] Successive approximation analog-to-digital converters (ADCs) have the advantage of low power consumption and can make a good trade-off between speed and accuracy, so they are widely used in fields such as microcontrollers.

[0003] As the core module in successive approximation analog-to-digital converters, most existing comparator circuits consist of a preamplifier and a dynamic comparator. Dynamic comparators have the advantages of fast comparison speed, no static power consumption, and rail-to-rail output, but their offset voltage and input equivalent noise are usually large, which will degrade the overall performance of the analog-to-digital converter.

[0004] See Figure 1 The figure shows a schematic diagram of a comparator circuit in the prior art. It consists of MOS transistors M1 to M7 forming a preamplifier, which is also the most commonly used structure currently, and MOS transistors M8 to M18 forming a dynamic comparator.

[0005] Figure 1 The comparator shown works as follows: The preamplifier amplifies the input differential voltages VIP and VIN, and the amplified voltages are then input to the gates of M9 and M10. When the clock signal CLK is low, the dynamic comparator is in a reset state, and the VOP, VON, X, and Y nodes of the dynamic comparator are all reset to the power supply voltage. After CLK is pulled up, MOSFETs M9 and M10 pull down the X and Y node voltages with different currents according to the gate voltage difference, until one of the MOSFETs M11 and M12 turns on. At this point, the dynamic amplifier enters the positive feedback stage and begins to establish an output.

[0006] Assume there is a small voltage difference VI between the gate terminals of M9 and M10, the average current of M9 and M10 pulling down nodes X and Y is IS, the parasitic capacitance at points X and Y is CL, the transconductance of M9 and M10 pulling down nodes X and Y is gm, and the threshold voltage of M11 and M12 is VTH. Then, what is the voltage difference V when one of the two MOSFETs M11 and M12 is turned on after pulling down from points X and Y? XY It can be represented as:

[0007]

[0008]

[0009] V XY / V I This is the input gain of the dynamic comparator.

[0010] Due to gm / I S It is proportional to the reciprocal of the overdrive voltages of M9 and M10. Therefore, the lower the gate common-mode level of M9 and M10, the higher the dynamic comparator input gain V. XY / V I The larger.

[0011] However, the gate common-mode levels of M9 and M10 are determined by the preamplifier. If the preamplifier uses... Figure 1 The most common structure in [the system], this value is usually only slightly higher than the supply voltage V. DD The gate-source voltage V of M4 to M7 is lower. GSP In the existing structure, after CLK is pulled up, M8 is turned on, and the sources of M9 and M10 are pulled low to GND. The overdrive voltage of M9 and M10 is V. DD -V GSP -V TH9,10 When V DD At relatively high voltages (e.g., 5V), the overdrive voltages of M9 and M10 are high, because the input gain V of the dynamic comparator is high at this time. XY / V I The dynamic comparator is relatively small, and is greatly affected by thermal noise and MOSFET mismatch. When the preamplifier gain cannot be very high, the effects of thermal noise and MOSFET mismatch on the dynamic comparator will lead to an increase in the overall comparator's input noise and offset voltage. Summary of the Invention

[0012] In view of this, embodiments of the present invention provide a low-noise, low-offset voltage dynamic comparator circuit, comparator, and electronic device to reduce noise and the impact of MOSFET mismatch on the dynamic comparator.

[0013] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0014] A low-noise, low-offset voltage dynamic comparator circuit includes a preamplifier and a dynamic comparator, and further includes:

[0015] A new MOS transistor is placed between the target MOS transistor and the ground terminal in the dynamic comparator;

[0016] The target MOS transistor is a MOS transistor used to adjust the drive voltage of the input MOS transistor of the dynamic comparator;

[0017] The gate and drain terminals of the newly added MOS transistor are connected to the source terminal of the target MOS transistor, and the source terminal of the newly added MOS transistor is grounded.

[0018] Optionally, in the above-mentioned low-noise, low-offset voltage dynamic comparator circuit, the newly added MOS transistor is an NMOS transistor.

[0019] Optionally, in the above-described low-noise, low-offset voltage dynamic comparator circuit, the preamplifier includes:

[0020] First MOSFET to Seventh MOSFET;

[0021] The gate terminal of the first MOS transistor is used to acquire the reference signal, and the source terminal of the first MOS transistor is grounded.

[0022] The source terminals of the second MOSFET and the third MOSFET are connected to the drain terminal of the first MOSFET. The gate terminal of the second MOSFET is used to acquire the first differential voltage signal, and the gate terminal of the third MOSFET is used to acquire the second differential voltage signal.

[0023] The source terminals of the fourth, fifth, sixth, and seventh MOSFETs are connected to the power supply.

[0024] The drain terminal of the fourth MOS transistor, the gate terminal of the fourth MOS transistor, the drain terminal of the sixth MOS transistor, and the gate terminal of the seventh MOS transistor are connected to the drain terminal of the second MOS transistor.

[0025] The drain terminal of the fifth MOS transistor, the gate terminal of the fifth MOS transistor, the drain terminal of the seventh MOS transistor, and the gate terminal of the sixth MOS transistor are connected to the drain terminal of the third MOS transistor.

[0026] The drain terminals of the second MOS transistor and the third MOS transistor serve as the output terminals of the preamplifier, respectively.

[0027] Optionally, in the above-described low-noise, low-offset voltage dynamic comparator circuit, the dynamic comparator includes:

[0028] Eighth MOSFET to eighteenth MOSFET;

[0029] The eighth MOS transistor serves as the target MOS transistor, with its gate terminal used to acquire a clock signal and its source terminal grounded through the newly added MOS transistor.

[0030] The source terminals of the ninth and tenth MOS transistors are connected to the drain terminal of the eighth MOS transistor, and the gate terminals of the ninth and tenth MOS transistors are respectively used as the input terminals of the dynamic comparator.

[0031] The drain of the fifteenth MOS transistor and the source of the eleventh MOS transistor are connected to the drain of the ninth MOS transistor. The gate of the fifteenth MOS transistor is used to obtain the clock signal. The source of the fifteenth MOS transistor is connected to the power supply. The drain of the eleventh MOS transistor is connected to the first output node of the dynamic comparator. The gate of the eleventh MOS transistor is connected to the second output node of the dynamic comparator.

[0032] The source terminal of the twelfth MOS transistor and the drain terminal of the sixteenth MOS transistor are connected to the source terminal of the tenth MOS transistor. The gate terminal of the sixteenth MOS transistor is used to obtain the clock signal. The source terminal of the sixteenth MOS transistor is connected to the power supply. The drain terminal of the twelfth MOS transistor is connected to the second output node of the dynamic comparator. The gate terminal of the twelfth MOS transistor is connected to the first output node of the dynamic comparator.

[0033] The drain terminals of the seventeenth and thirteenth MOSFETs are connected to the first output node, the source terminals of the seventeenth and thirteenth MOSFETs are connected to the power supply, the seventeenth MOSFET is used to acquire the clock signal, and the gate terminal of the thirteenth MOSFET is connected to the second output node.

[0034] The drain terminals of the fourteenth and eighteenth MOS transistors are connected to the second output node, the source terminals of the fourteenth and eighteenth MOS transistors are connected to the power supply, the eighteenth MOS transistor is used to acquire the clock signal, and the gate terminal of the fourteenth MOS transistor is connected to the first output node.

[0035] Optionally, in the above-mentioned low-noise, low-offset voltage dynamic comparator circuit, the fourth, fifth, sixth, and seventh MOS transistors are PMOS transistors, and the first, second, and third MOS transistors are NMOS transistors.

[0036] Optionally, in the above-mentioned low-noise, low-offset voltage dynamic comparator circuit, the thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are PMOS transistors, and the eighth, ninth, tenth, eleventh, and twelfth MOS transistors are NMOS transistors.

[0037] A comparator employing the low-noise, low-offset voltage dynamic comparator circuit described in any one of the above.

[0038] An electronic device that uses the low-noise, low-offset voltage dynamic comparator circuit described in any one of the above claims.

[0039] Optionally, the electronic device is a mobile phone or a computer.

[0040] Based on the above technical solution, the solution provided in this embodiment of the invention changes the working process of the dynamic comparator by adding a new MOS transistor M19. When the dynamic comparator starts positive feedback to establish the output, a larger voltage difference is generated at the source of the corresponding MOS transistor, thereby significantly suppressing thermal noise and the damage to the comparison accuracy of the dynamic comparator caused by MOS transistor mismatch. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of a comparator circuit disclosed in the prior art;

[0043] Figure 2 This is a schematic diagram of the comparison circuit disclosed in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the structure of a comparison circuit disclosed in another embodiment of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "an," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the embodiments of this application, "one or more" refers to one, two, or more; "and / or" describes the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0046] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0047] The "multiple" mentioned in the embodiments of this application refers to two or more. It should be noted that in the description of the embodiments of this application, terms such as "first" and "second" are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0048] This application adds a MOSFET to the dynamic comparator in the comparator circuit. This MOSFET regulates the overdrive voltage of the input MOSFET of the dynamic comparator, significantly increasing the input gain of the dynamic comparator and enhancing its resistance to thermal noise and MOSFET mismatch. At higher power supply voltages, it also allows for a more ideal match between the dynamic comparator and common comparator preamplifiers, thereby improving the comparator's accuracy performance.

[0049] This invention improves the dynamic comparator based on the original structure. At the instant CLK is pulled up, the overdrive voltage of M9 and M10 is reduced to increase the input gain V of the dynamic comparator in formula (2). XY / V I This improves the dynamic comparator's resistance to thermal noise and MOSFET mismatch. When the preamplifier needs to prioritize setup speed over gain in a trade-off, the design in this invention significantly optimizes the overall comparator's noise and offset performance.

[0050] Specifically, this application discloses a low-noise, low-offset voltage dynamic comparator circuit, see [link to relevant documentation]. Figure 2 The comparison circuit includes a preamplifier and a dynamic comparator, and further includes a newly added MOS transistor M19;

[0051] See Figure 2 The newly added MOS transistor M19 is disposed between the target MOS transistor in the dynamic comparator and the ground terminal. That is, the target MOS transistor is grounded through the newly added MOS transistor M19. In this scheme, the target MOS transistor can be understood as a MOS transistor used to adjust the drive voltage of the input MOS transistor of the dynamic comparator. In the existing scheme, the drain terminal of the MOS transistor is connected to the drain terminal of the input MOS transistor of the dynamic comparator, the source terminal of the MOS transistor is grounded, and its gate terminal is used to obtain the clock signal.

[0052] Specifically, the gate and drain terminals of the newly added MOS transistor M19 are connected to the source terminal of the target MOS transistor, and the source terminal of the newly added MOS transistor is grounded.

[0053] The newly added MOS transistor is preferably an NMOS transistor. Of course, the newly added MOS transistor can also be an electronic circuit composed of multiple components with the same function as the NMOS transistor.

[0054] The above-mentioned solution provided by the present invention changes the working process of the dynamic comparator by adding a new MOS transistor M19 to the original circuit. When the dynamic comparator starts to establish positive feedback and output, a larger voltage difference is generated at the source of the corresponding MOS transistor, thereby significantly suppressing thermal noise and the damage to the comparison accuracy of the dynamic comparator caused by MOS transistor mismatch.

[0055] In this solution, the structure of the preamplifier can be customized according to user requirements; for example, see [reference needed]. Figure 2 The preamplifier may include:

[0056] First MOSFET M1 to seventh MOSFET M7;

[0057] The gate terminal of the first MOS transistor M1 is used to acquire the reference signal VB, and the source terminal of the first MOS transistor M1 is grounded.

[0058] The source terminals of the second MOSFET M2 and the third MOSFET M3 are connected to the drain terminal of the first MOSFET M1. The gate terminal of the second MOSFET M2 is used to acquire the first differential voltage signal VIP, and the gate terminal of the third MOSFET M3 is used to acquire the second differential voltage signal VIN.

[0059] The source terminals of the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 are connected to the power supply VDD.

[0060] The drain terminal of the fourth MOS transistor M4, the gate terminal of the fourth MOS transistor M4, the drain terminal of the sixth MOS transistor M6, and the gate terminal of the seventh MOS transistor M7 are connected to the drain terminal of the second MOS transistor M2.

[0061] The drain terminal of the fifth MOS transistor M5, the gate terminal of the fifth MOS transistor M5, the drain terminal of the seventh MOS transistor M7, and the gate terminal of the sixth MOS transistor M6 are connected to the drain terminal of the third MOS transistor M3.

[0062] The drain terminals of the second MOS transistor M2 and the third MOS transistor M3 serve as the output terminals of the preamplifier, respectively.

[0063] See Figure 2 The dynamic comparator may include:

[0064] The eighth MOSFET M8 to the eighteenth MOSFET M18;

[0065] The eighth MOS transistor M8 serves as the target MOS transistor. The gate terminal of the eighth MOS transistor M8 is used to acquire the clock signal, and the source terminal of the eighth MOS transistor M8 is grounded through the newly added MOS transistor.

[0066] The source terminals of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the drain terminal of the eighth MOS transistor M8, and the gate terminals of the ninth MOS transistor M9 and the tenth MOS transistor M10 are respectively used as the input terminals of the dynamic comparator.

[0067] The drain of the fifteenth MOSFET M15 and the source of the eleventh MOSFET M11 are connected to the drain of the ninth MOSFET M9. The gate of the fifteenth MOSFET M15 is used to acquire the clock signal. The source of the fifteenth MOSFET M15 is connected to the power supply. The drain of the eleventh MOSFET M11 is connected to the first output node VON of the dynamic comparator. The gate of the eleventh MOSFET M11 is connected to the second output node VOP of the dynamic comparator.

[0068] The source terminal of the twelfth MOSFET M12 and the drain terminal of the sixteenth MOSFET M16 are connected to the drain terminal of the tenth MOSFET M10. The gate terminal of the sixteenth MOSFET M16 is used to obtain the clock signal. The source terminal of the sixteenth MOSFET M16 is connected to the power supply. The drain terminal of the twelfth MOSFET M12 is connected to the second output node VOP of the dynamic comparator. The gate terminal of the twelfth MOSFET M12 is connected to the first output node VON of the dynamic comparator.

[0069] The drain terminals of the seventeenth MOSFET M17 and the thirteenth MOSFET M13 are connected to the first output node VON. The source terminals of the seventeenth MOSFET M17 and the thirteenth MOSFET M13 are connected to the power supply. The seventeenth MOSFET M17 is used to acquire the clock signal. The gate terminal of the thirteenth MOSFET M13 is connected to the second output node VOP.

[0070] The drain terminals of the fourteenth MOSFET M17 and the eighteenth MOSFET M18 are connected to the second output node VOP. The source terminals of the fourteenth MOSFET M14 and the eighteenth MOSFET M18 are connected to the power supply. The eighteenth MOSFET M18 is used to acquire the clock signal. The gate terminal of the fourteenth MOSFET M14 is connected to the first output node VON.

[0071] In the above circuit, the types of each MOS transistor in the preamplifier can be selected according to user needs. For example, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 can be PMOS transistors, and the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 can be NMOS transistors.

[0072] In the above circuit, the type of each MOS transistor in the dynamic comparator can be selected according to user needs. For example, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 can be PMOS transistors, while the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 can be NMOS transistors.

[0073] The above-mentioned solution provided by the present invention modifies the operation of the dynamic comparator by adding a new MOS transistor M19, specifically an NMOS transistor, to the original circuit. Specifically, when CLK is pulled up, the target MOS transistor M8 is turned on. When the input MOS transistors M9 and M10 pull down the voltages of the X and Y nodes in the dynamic comparator, a large transient current flows through the new MOS transistor M19. At this time, the source voltages of MOS transistors M9 and M10 are raised to the gate-source voltage V of M19. GS19 At this time, the overdrive voltages of MOSFETs M9 and M10 are: V DD -V GSP -V GS19 -V TH9,10 .and Figure 1 Compared to existing structures, the input transistors M9 and M10 of the dynamic comparator in this invention have lower overdrive voltages and can generate a larger dynamic comparator input gain V. XY / V I Therefore, this means that the dynamic comparator in this invention can generate a larger voltage difference at its source when the positive feedback of MOSFETs M11 and M12 begins to establish the output, thereby significantly suppressing thermal noise and the degradation of the dynamic comparator's comparison accuracy due to MOSFET mismatch. It significantly increases the input gain of the dynamic comparator, strengthens its own resistance to thermal noise and MOSFET mismatch, and allows for more ideal matching between the dynamic comparator and common comparator preamplifiers at higher power supply voltages. This improves the comparator's accuracy performance.

[0074] To verify the effectiveness of this solution, the applicant used SMIC40 process 5V devices to simulate both the existing comparator circuit and the comparator circuit provided in this application. Simulation results show that:

[0075] With a power supply voltage of 5V, a common-mode input level of 4V for MOSFETs M9 and M10, and a differential voltage of 1mV, using nodes X and Y pulled down to 4V as the comparison reference, it can be seen that after CLK is pulled up, the dynamic comparator in this invention exhibits a 4mV voltage difference between nodes X and Y when pulled down to 4V, whereas in existing structures, this value is only 2.3mV. Monte Carlo simulations of the two dynamic comparators show that the offset voltage of the dynamic comparator proposed in this invention is reduced by 30% compared to existing structures. Transient noise simulations of the two dynamic comparators show that the dynamic comparator proposed in this invention is less affected by thermal noise by 40% compared to existing structures.

[0076] It can be seen that the dynamic comparator proposed in this invention increases the input gain V of the dynamic comparator compared to existing structures. XY / V I This represents a 74% improvement, significantly reducing thermal noise and the impact of MOSFET mismatch on the accuracy of the dynamic comparator. The trade-off is only a slight increase in the dynamic comparator's setup delay of less than 500 ps, ​​which is negligible in low-to-medium speed successive approximation ADCs.

[0077] As can be seen from the simulation results above, this invention utilizes a newly added MOSFET to adjust the overdrive voltage of the input MOSFET of the dynamic comparator, thereby significantly increasing the input gain of the dynamic comparator and enhancing its resistance to thermal noise and MOSFET mismatch. At higher power supply voltages, it also allows for a more ideal match between the dynamic comparator and common comparator preamplifiers, thus improving the comparator's accuracy performance.

[0078] Furthermore, this application also discloses a comparator that can be applied to the low-noise, low-offset voltage dynamic comparator circuit described in any of the above embodiments. The preamplifier and dynamic comparator in the comparator can be packaged as a whole or packaged separately.

[0079] This application also discloses an electronic device that can utilize the low-noise, low-offset voltage dynamic comparator circuit described in any of the above-described embodiments. The electronic device in this disclosure may include, but is not limited to, mobile terminals such as mobile phones, computers, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0081] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-noise, low-offset voltage dynamic comparator circuit, comprising a preamplifier and a dynamic comparator, characterized in that, Also includes: A new MOS transistor is placed between the target MOS transistor and the ground terminal in the dynamic comparator; The target MOS transistor is a MOS transistor used to adjust the drive voltage of the input MOS transistor of the dynamic comparator. The drain terminal of the target MOS transistor is connected to the drain terminal of the input MOS transistor of the dynamic comparator, and the gate terminal of the target MOS transistor is used to acquire the clock signal. The gate and drain terminals of the newly added MOS transistor are connected to the source terminal of the target MOS transistor, and the source terminal of the newly added MOS transistor is grounded.

2. The low-noise, low-offset voltage dynamic comparator circuit according to claim 1, characterized in that, The newly added MOS transistor is an NMOS transistor.

3. The low-noise, low-offset voltage dynamic comparator circuit according to claim 1, characterized in that, The preamplifier includes: First MOSFET to Seventh MOSFET; The gate terminal of the first MOS transistor is used to acquire the reference signal, and the source terminal of the first MOS transistor is grounded. The source terminals of the second MOSFET and the third MOSFET are connected to the drain terminal of the first MOSFET. The gate terminal of the second MOSFET is used to acquire the first differential voltage signal, and the gate terminal of the third MOSFET is used to acquire the second differential voltage signal. The source terminals of the fourth, fifth, sixth, and seventh MOSFETs are connected to the power supply. The drain terminal of the fourth MOS transistor, the gate terminal of the fourth MOS transistor, the drain terminal of the sixth MOS transistor, and the gate terminal of the seventh MOS transistor are connected to the drain terminal of the second MOS transistor. The drain terminal of the fifth MOS transistor, the gate terminal of the fifth MOS transistor, the drain terminal of the seventh MOS transistor, and the gate terminal of the sixth MOS transistor are connected to the drain terminal of the third MOS transistor. The drain terminals of the second MOS transistor and the third MOS transistor serve as the output terminals of the preamplifier, respectively.

4. The low-noise, low-offset voltage dynamic comparator circuit according to claim 1, characterized in that, The dynamic comparator includes: Eighth MOSFET to eighteenth MOSFET; The eighth MOS transistor serves as the target MOS transistor, with its gate terminal used to acquire a clock signal and its source terminal grounded through the newly added MOS transistor. The source terminals of the ninth and tenth MOS transistors are connected to the drain terminal of the eighth MOS transistor, and the gate terminals of the ninth and tenth MOS transistors are respectively used as the input terminals of the dynamic comparator. The drain of the fifteenth MOS transistor and the source of the eleventh MOS transistor are connected to the drain of the ninth MOS transistor. The gate of the fifteenth MOS transistor is used to obtain the clock signal. The source of the fifteenth MOS transistor is connected to the power supply. The drain of the eleventh MOS transistor is connected to the first output node of the dynamic comparator. The gate of the eleventh MOS transistor is connected to the second output node of the dynamic comparator. The source terminal of the twelfth MOS transistor and the drain terminal of the sixteenth MOS transistor are connected to the source terminal of the tenth MOS transistor. The gate terminal of the sixteenth MOS transistor is used to obtain the clock signal. The source terminal of the sixteenth MOS transistor is connected to the power supply. The drain terminal of the twelfth MOS transistor is connected to the second output node of the dynamic comparator. The gate terminal of the twelfth MOS transistor is connected to the first output node of the dynamic comparator. The drain terminals of the seventeenth and thirteenth MOSFETs are connected to the first output node, the source terminals of the seventeenth and thirteenth MOSFETs are connected to the power supply, the seventeenth MOSFET is used to acquire the clock signal, and the gate terminal of the thirteenth MOSFET is connected to the second output node. The drain terminals of the fourteenth and eighteenth MOS transistors are connected to the second output node, the source terminals of the fourteenth and eighteenth MOS transistors are connected to the power supply, the eighteenth MOS transistor is used to acquire the clock signal, and the gate terminal of the fourteenth MOS transistor is connected to the first output node.

5. The low-noise, low-offset voltage dynamic comparator circuit according to claim 3, characterized in that, The fourth, fifth, sixth, and seventh MOS transistors are PMOS transistors, while the first, second, and third MOS transistors are NMOS transistors.

6. The low-noise, low-offset voltage dynamic comparator circuit according to claim 4, characterized in that, The thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are PMOS transistors, while the eighth, ninth, tenth, eleventh, and twelfth MOS transistors are NMOS transistors.

7. A comparator, characterized in that, The application has the low-noise, low-offset voltage dynamic comparator circuit as described in any one of claims 1-6.

8. An electronic device, characterized in that, The application has the low-noise, low-offset voltage dynamic comparator circuit as described in any one of claims 1-6.

9. The electronic device according to claim 8, characterized in that, The electronic device is a mobile phone or a computer.

Images