High speed peripheral component interconnect interface device and method of operation thereof

Abstract

This disclosure provides a high-speed peripheral component interconnect (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic level controller. The performance analyzer may be configured to measure the throughput of multiple functions operating on one or more direct memory access (DMA) devices. The traffic level controller may be configured to assign traffic level values ​​to transaction layer packets received from the multiple functions based on their throughput.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0037503, filed with the Korean Intellectual Property Office on March 23, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure generally relate to an electronic device, and more specifically, to a PCIe interface device and a method of operating the PCIe interface device. Background Technology

[0004] High-speed peripheral component interconnect (PCIe) is an interface with a serial structure for data communication. PCIe-based storage devices support multi-port and multi-functional architectures. PCIe-based storage devices can be virtualized or non-virtualized and can implement Quality of Service (QoS) for host input / output (I / O) commands through one or more PCIe functions.

[0005] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0006] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is interrupted. Examples of volatile memory devices can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0007] Non-volatile memory devices are memory devices that retain stored data even when power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0008] Various embodiments of this disclosure relate to a PCIe interface device and a method of operating the PCIe interface device, which provides a uniform Quality of Service (QoS) for various functions.

[0009] Embodiments of this disclosure may provide a high-speed peripheral component interconnect (PCIe) interface device. The PCIe interface device may include a performance analyzer and a traffic level controller. The performance analyzer may be configured to measure the throughput of multiple functions operating on one or more direct memory access (DMA) devices. The traffic level controller may be configured to assign traffic level values ​​to transaction layer packets received from the multiple functions based on the throughput of the multiple functions.

[0010] Embodiments of this disclosure may provide a method for operating a high-speed peripheral component interconnect (PCIe) interface device. The method may include measuring the throughput of multiple functions operating on one or more direct memory access (DMA) devices, and assigning traffic level values ​​to transaction layer packets received from the multiple functions based on the throughput of the multiple functions. Attached Figure Description

[0011] Figure 1 The communication structure between a host system and a PCIe endpoint according to an embodiment of this disclosure is shown.

[0012] Figure 2 The configuration and operation of a PCIe device according to an embodiment of this disclosure are illustrated.

[0013] Figure 3 The virtual channel in the PCIe link is shown.

[0014] Figure 4 It shows Figure 3 Virtual channels in a switch.

[0015] Figure 5 A mapping table between virtual channels and traffic levels according to an embodiment of this disclosure is shown.

[0016] Figure 6 It shows that according to Figure 5 The mapping structure between virtual channels and traffic levels described in the mapping table.

[0017] Figure 7 A method for allocating traffic level values ​​based on throughput of various functions according to embodiments of this disclosure is illustrated.

[0018] Figure 8 This is a flowchart illustrating the operation of a PCIe interface device according to an embodiment of the present disclosure.

[0019] Figure 9 This is a flowchart illustrating a method for allocating traffic level values ​​according to an embodiment of the present disclosure.

[0020] Figure 10 This is a flowchart illustrating a method for allocating traffic level values ​​according to an embodiment of the present disclosure. Detailed Implementation

[0021] The specific structural or functional descriptions of embodiments of this disclosure incorporated herein by reference are used as examples to illustrate embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in the specification or this application.

[0022] Figure 1 The communication structure between a host system and a plurality of PCIe endpoints (EPs) according to an embodiment of the present disclosure is illustrated.

[0023] Reference Figure 1 The host system 200 may include a root consortium 210, a switch 220, a central processing unit (CPU) 230, and a memory 240.

[0024] Root union 210 can connect CPU 230 and memory 240 to the input / output (I / O) hierarchy. Root union 210 may include at least one host bridge and at least one root port. Root union 210 may support one or more PCIe ports.

[0025] Root union 210 can support input / output (I / O) requests. Root union 210 must support generating configuration requests. Root union 210, as a completer, must not support locking semantics. Root union 210 can, as a requester, request the generation of lock requests.

[0026] Switch 220 can connect at least two ports to each other to route transaction layer packets. Switch 220 can be a group of virtual PCI-PCI bridge devices. Switch 220 can consist of two or more logical PCI-PCI bridges. Switch 220 can use PCI bridge mechanisms (i.e., address-based multicast) to route transactions. Switch 220 must route all types of transaction layer packets between all ports. Switch 220 must support locking requests. Each enabled port of switch 220 must support flow control. When contention occurs on the same virtual channel, switch 220 can arbitrate contention using round-robin or weighted round-robin.

[0027] Each PCIe endpoint (EP) can act as either a requester or a completer of a PCIe transaction.

[0028] exist Figure 1 In this configuration, the first PCIe endpoint (PCIe EP 1) can transmit transaction layer packets to and receive transaction layer packets from the root union 210. The second and third PCIe endpoints (PCIe EP 2 and PCIe EP 3) can transmit transaction layer packets to and receive transaction layer packets from the switch 220.

[0029] Switch 220 can route transaction layer packets received from the second and third PCIe endpoints (PCIe EP 2 and PCIe EP 3) to the root federation 210. Switch 220 can route transaction layer packets received from the root federation 210 to the second and third PCIe endpoints (PCIe EP 2 and PCIe EP 3).

[0030] Therefore, root association 210 can directly transmit and receive transaction layer packets to and from the first PCIe endpoint (PCIe EP 1). Root association 210 can transmit and receive transaction layer packets to and from the second and third PCIe endpoints (PCIe EP 2 and PCIe EP 3) via switch 220. Root association 210 can forward transaction layer packets received from the first to third PCIe endpoints (PCIe EP 1 to PCIe EP 3) to CPU 230 or memory 240.

[0031] Figure 2 The configuration and operation of a PCIe device according to an embodiment of this disclosure are illustrated.

[0032] Reference Figure 2 The PCIe device 100 may include a PCIe interface (I / F) device 110 and one or more direct memory access (DMA) devices, such as 120_1 to 120_4. The PCIe device 100 may be as described above. Figure 1 Describes the PCIe endpoint. Similar to the reference. Figure 1 As described above, host system 200 may include root union 210, switch 220, CPU (not shown), and memory (not shown).

[0033] PCIe interface device 110 can receive transaction layer packets from multiple functions (functions 1 to 4) running on DMA devices 120_1 to 120_4, respectively. PCIe interface device 110 can route the received transaction layer packets to switch 220 of host system 200. PCIe interface device 110 can dynamically assign traffic level values ​​to the received transaction layer packets based on the throughput of each function. The traffic level can be a label for transaction layer packets routed between unmodified endpoints.

[0034] PCIe interface device 110 may include performance analyzer 111 and flow class (TC) controller 112.

[0035] Performance analyzer 111 can measure the throughput of multiple functions running on DMA devices 120_1 to 120_4 respectively. These multiple functions can share the data path connecting DMA devices 120_1 to 120_4 to PCIe interface device 110. Performance analyzer 111 can calculate the throughput of the multiple functions based on the occupancy of the data path. Performance analyzer 111 can also calculate the occupancy of a function based on the number of transaction layer packets corresponding to that function processed per unit time through the data path.

[0036] The traffic level controller 112 can dynamically assign traffic level values ​​to transaction layer packets received from multiple functions based on the throughput of multiple functions. Whenever the ranking of the throughput of multiple functions changes, the traffic level controller 112 can reallocate traffic level values ​​to transaction layer packets based on the changed ranking.

[0037] The traffic level controller 112 can assign preset default values ​​as the initial values ​​for the traffic level of transaction layer packets received from multiple functions.

[0038] Traffic level controller 112 can assign different traffic level values ​​to transaction layer packets based on the result of comparing the throughput of multiple functions with a threshold. Traffic level controller 112 can assign a default value as the traffic level value for transaction layer packets received from functions whose throughput is greater than the threshold. Traffic level controller 112 can also determine the ranking of traffic level values ​​for transaction layer packets received from functions whose throughput is less than or equal to the threshold, in descending order of the throughput ranking of the multiple functions. See below for further details. Figure 7 A detailed description of an embodiment for assigning traffic level values ​​is provided. In this embodiment, the preset default value may be the same as the default value.

[0039] The flow level controller 112 can assign default values ​​as flow level values ​​for transaction layer packets received from the interrupt function among multiple functions.

[0040] As will be referred to later Figure 6 As described, switch 220 or root association 210 can determine the virtual channels to be mapped to transaction layer packets based on the assigned traffic level values. Switch 220 or root association 210 can determine the order in which transaction layer packets are output to the outside based on the virtual channels mapped to the transaction layer packets.

[0041] DMA devices 120_1 to 120_4 may include one or more of the following: high-speed non-volatile memory (NVMe) devices, solid-state drive (SSD) devices, artificial intelligence central processing units (AI CPUs), artificial intelligence system-on-a-chip (AI SoCs), Ethernet devices, sound cards, graphics cards, etc. However, DMA devices 120_1 to 120_4 are not limited to these, and may include other types of electronic devices employing a PCIe interface. Functions can run on DMA devices 120_1 to 120_4, and these functions may be software or firmware that processes transactions within transaction layer packets.

[0042] For each of DMA devices 120_1 to 120_4, one or more functions can be run. Figure 2 In this context, a function can run on each of the DMA devices 120_1 to 120_4.

[0043] For example, a first function (function 1) can be run on the first DMA device 120_1. A second function (function 2) can be run on the second DMA device 120_2. A third function (function 3) can be run on the third DMA device 120_3. A fourth function (function 4) can be run on the fourth DMA device 120_4.

[0044] However, the number of functions running on each DMA device is not limited to this embodiment. For example, the PCIe device 100 may generate physical or virtual functions in response to a virtualization request received from the host system 200. The PCIe device 100 may assign the generated functions to various DMA devices. The number of functions assigned to each DMA device and running on each DMA device can be set individually. Therefore, one or more functions may be assigned to a DMA device, and each of the one or more functions may operate as an independent unit of operation.

[0045] Figure 3 The virtual channel (VC) in a PCIe link is shown.

[0046] Reference Figure 3 The upstream port UP of a PCIe endpoint (PCIe EP 1 to PCIe EP 5) can be connected to the downstream port DP of root federation 210 or the downstream port DP of switch 220. The upstream port UP of switch 220 can be connected to the downstream port DP of root federation 210.

[0047] exist Figure 3In this configuration, the upstream port UP of the first PCIe endpoint (PCIe EP 1) can be connected to the second downstream port DP2 of the root union 210. The upstream port UP of the second PCIe endpoint (PCIe EP 2) can be connected to the third downstream port DP3 of the root union 210.

[0048] The first PCIe endpoint (PCIe EP 1) can establish a single link with the root union 210 through a single virtual channel. The virtual channel can be set as the default channel VC0.

[0049] The second PCIe endpoint (PCIe EP 2) can communicate with the root union 210 via a single link that establishes two virtual channels. These two virtual channels may include the default channel VCO and another virtual channel. The number of virtual channels that can be established using a single link is not limited to this embodiment.

[0050] The upstream port UP of the third PCIe endpoint (PCIe EP 3) can be connected to the first downstream port DP1 of switch 220. The upstream port UP of the fourth PCIe endpoint (PCIe EP 4) can be connected to the second downstream port DP2 of switch 220. The upstream port UP of the fifth PCIe endpoint (PCIe EP 5) can be connected to the third downstream port DP3 of switch 220. The upstream port UP of switch 220 can be connected to the first downstream port DP1 of root federation 210.

[0051] The third to fifth PCIe endpoints (PCIe EP 3 to PCIe EP 5) can communicate with the root union 210 via switch 220.

[0052] The third PCIe endpoint (PCIe EP 3) can establish a single link with switch 220 through a virtual channel. The virtual channel can be set to the default channel VC0. The fourth PCIe endpoint (PCIe EP 4) can establish a single link with switch 220 through two virtual channels. These two virtual channels can include the default channel VC0 and another virtual channel. The fifth PCIe endpoint (PCIe EP 5) can establish a single link with switch 220 through two virtual channels. These two virtual channels can include the default channel VC0 and another virtual channel.

[0053] Switch 220 can communicate with root federation 210 through a single link that establishes two virtual channels. These two virtual channels may include the default channel VC0 and another virtual channel.

[0054] Figure 4 It shows Figure 3 Virtual channels in a switch.

[0055] Reference Figure 4 The switch may include first to third downstream ports DP1 to DP3 and upstream port UP.

[0056] Transaction layer packets received from the first downstream port DP1 can be forwarded to the upstream port UP through the default channel VC0. Transaction layer packets received from the second downstream port DP2 can be forwarded to the upstream port UP through the default channel VC0 and the additional virtual channel VCn (where n is a natural number). Transaction layer packets received from the third downstream port DP3 can be forwarded to the upstream port UP through the default channel VC0 and the additional virtual channel VCn.

[0057] Based on the switch's internal configuration information, the order in which transaction layer packets received via the default channel VC0 and the additional virtual channel VCn are output to the outside via the upstream port UP can be determined. For example, before outputting transaction layer packets received via the default channel VC0 to the outside, transaction layer packets received via the additional virtual channel VCn can be output to the outside of the switch via the upstream port UP.

[0058] Figure 5 A mapping table between virtual channels and traffic classes according to an embodiment is shown. (See also...) Figure 5 Virtual channel mechanisms can use different traffic levels to provide different traffic to the entire structure. This is to prevent bottlenecks caused by using a single type of traffic.

[0059] In one embodiment, a traffic class can be mapped to one virtual channel. In another embodiment, multiple traffic classes can be mapped to a single virtual channel. In yet another embodiment, a traffic class can be mapped to only one virtual channel. That is, a single traffic class cannot be mapped to two or more virtual channels. The default value for a traffic class can be TC0, and the default channel for a virtual channel can be VC0.

[0060] exist Figure 5 In this context, all traffic levels TC0 to TC7 can be mapped to the default channel VC0.

[0061] When traffic levels TC0 to TC7 are mapped to virtual channels VC0 and VC1, traffic levels TC0 to TC6 can be mapped to the default channel VC0, and traffic level TC7 can be mapped to the virtual channel VC1.

[0062] When traffic levels TC0 to TC7 are mapped to virtual channels VC0 to VC3, traffic levels TC0 and TC1 can be mapped to the default channel VC0, traffic levels TC2 to TC4 can be mapped to the virtual channel VC1, traffic levels TC5 and TC6 can be mapped to the virtual channel VC2, and traffic level TC7 can be mapped to the virtual channel VC3.

[0063] Traffic levels TC0 to TC7 can be mapped to virtual channels VC0 to VC7 in a one-to-one correspondence.

[0064] The number of virtual channels and traffic levels are not limited to Figure 5 The example shown.

[0065] Figure 6 It shows that according to Figure 5 The mapping structure between virtual channels and traffic levels described in the mapping table.

[0066] Reference Figure 6 Based on the traffic level value assigned to a transaction layer packet, the packets are routed via virtual channels mapped to that traffic level, thus enabling transactions between components. Here, a switch or root federation can perform the ordering of transaction layer packets based on the traffic level value.

[0067] Virtual channels can provide independent logical data streams from specific physical resources. For example, when multiple virtual channels are established in a single physical link, independent logical data streams can be provided for each virtual channel.

[0068] A switch can route transaction layer packets received over a link to the root federation. Switches can include a mapping table between traffic levels and virtual channels as configuration information. The switch configuration information can be changed in response to requests from host systems. Mapping tables can be configured differently for each switch. A switch can allocate virtual channels for transmitting transaction layer packets based on the traffic level value assigned to the packet.

[0069] For example, the first switch (switch 1) can map traffic class TC[0:6] to virtual channel VC0, and can map traffic class TC7 to virtual channel VC1. Therefore, transaction layer packets with traffic class TC[0:6] can be routed to the root union through virtual channel VC0. Transaction layer packets with traffic class TC7 can be routed to the root union through virtual channel VC1. Based on the configuration information of the first switch (switch 1), the priority or output order of transaction layer packets to be routed to the root union through virtual channels VC0 and VC1 can be determined.

[0070] The second switch (switch 2) can map traffic level TC[0:1] to virtual channel VC0, traffic level TC[2:4] to virtual channel VC1, traffic level TC[5:6] to virtual channel VC2, and traffic level TC7 to virtual channel VC3.

[0071] As described above regarding the process of routing transaction layer packets by the first switch, the transaction layer packets can be routed to the root federation through virtual channels mapped to the traffic level, based on the traffic level value. Based on the configuration information of the second switch (switch 2), the priority or output order of the transaction layer packets to be routed to the root federation through virtual channels VC0 to VC3 can be determined.

[0072] Figure 7 A method for allocating traffic level values ​​based on throughput of various functions according to embodiments of this disclosure is illustrated.

[0073] Reference Figure 7 The throughput of each function can be determined based on the number of transaction layer packets processed through the data path per unit of time. The ranking of the throughput of each function can indicate the ranking of the data path occupancy of each function.

[0074] The number of traffic level values ​​to be assigned can be the same as the number of functions. Figure 7 In this embodiment, traffic level values ​​TC0 to TC3 can be assigned to transaction layer packets received from the first function F1 to the fourth function F4. The larger the traffic level value, the higher the priority of the corresponding transaction layer packet. In another embodiment, the smaller the traffic level value, the higher the priority of the corresponding transaction layer packet.

[0075] At time t1, the default traffic level value TC0 can be assigned as the traffic level value for all transaction layer packets received from each function. Time t1 can be the point in time when a PCIe link is established (linkup).

[0076] At time t2, the throughput of functions F1 through F4 can be less than the threshold TH. The throughput can be ranked in descending order as follows: function F1, function F2, function F3, and function F4.

[0077] In this embodiment, when the throughput of functions F1 to F4 is less than the threshold TH, traffic level values ​​can be allocated in descending order of their throughput ranking. Therefore, the lowest traffic level value TC0 can be mapped to the transaction layer packet of function F1, which has the highest throughput ranking. A traffic level value TC1, which is greater than TC0, can be mapped to the transaction layer packet of function F2. A traffic level value TC2, which is greater than TC1, can be mapped to the transaction layer packet of function F3. The highest traffic level value TC3, which is greater than TC2, can be mapped to the transaction layer packet of function F4, which has the lowest throughput ranking.

[0078] At time t3, the throughput of the second function F2 can exceed the threshold TH.

[0079] In this embodiment, when the throughput of a function is greater than the threshold TH, a default value TC0 can be assigned as a traffic level value to the transaction layer packets received from the corresponding function. Therefore, the traffic level value TC0, as the default value, can be assigned to the transaction layer packets of the second function F2, whose throughput is greater than the threshold TH.

[0080] At this point, the throughput of the first function F1, the third function F3, and the fourth function F4 may be less than the threshold TH. Therefore, the unassigned traffic level values ​​TC1 to TC3 can be assigned to transaction layer packets in reverse order of the throughput ranking of the first function F1, the third function F3, and the fourth function F4.

[0081] For example, the lowest traffic level value TC1 among the unassigned traffic level values ​​TC1 to TC3 can be assigned to the transaction layer packet of the first function F1, which has the highest throughput ranking among the first function F1, third function F3, and fourth function F4. Traffic level value TC2 can be assigned to the transaction layer packet of the third function F3. Traffic level value TC3 can be assigned to the transaction layer packet of the fourth function F4.

[0082] At time t4, the throughput of functions F1 through F4 can be less than the threshold TH. The throughput can be ranked in descending order as follows: function F1, function F2, function F3, and function F4. However, at this point, function F4 may be an interrupt function.

[0083] In this embodiment, the default value TC0 can be assigned to the transaction layer packet received from the interrupt function. Therefore, the default value TC0 can be assigned to the transaction layer packet of the fourth function F4.

[0084] Since the throughput of the first function F1, the second function F2, and the third function F3 is less than the threshold TH, the unassigned traffic level values ​​TC1 to TC3 can be assigned to the transaction layer packets in reverse order of the throughput ranking of the first function F1, the second function F2, and the third function F3.

[0085] For example, the lowest traffic level value TC1 among the unassigned traffic level values ​​TC1 to TC3 can be assigned to the transaction layer packet of the first function F1, which has the highest throughput ranking among the first function F1, second function F2, and third function F3. Traffic level value TC2 can be assigned to the transaction layer packet of the second function F2. Traffic level value TC3 can be assigned to the transaction layer packet of the third function F3.

[0086] As shown above (refer to the reference) Figure 7 As described, when the throughput ranking of a function changes or when an interruption occurs, the traffic level value can be reassigned to the transaction layer packet.

[0087] In embodiments of this disclosure, a switch or root federation may perform the sorting of transaction layer packets based on the traffic level value assigned to the transaction layer packet. For example, assigning a high traffic level value to a transaction layer packet can improve the ranking of that transaction layer packet in the switch or root federation compared to assigning a low traffic level value to the corresponding transaction layer packet.

[0088] According to embodiments of this disclosure, when the throughput of a function exceeds a threshold, the PCIe interface device can allocate a traffic level value TC0, which is the lowest default value, to the transaction layer packets of that function. When the throughput of a function is less than or equal to the threshold, the PCIe interface device can allocate traffic level values ​​in descending order of the functions' throughput. In this way, since the utilization rate of a function is low when its throughput is not greater than the threshold, a higher traffic level value can be allocated to the transaction layer packets of that function, thereby achieving equal utilization of each function. Therefore, the PCIe interface device can implement unified QoS for each function in a multi-functional environment.

[0089] Figure 8 This is a flowchart illustrating the operation of a PCIe interface device according to an embodiment of the present disclosure.

[0090] Reference Figure 8 In S801, the PCIe interface device can receive transaction layer packets from multiple functions of the DMA device.

[0091] In S803, PCIe interface devices can measure the throughput of individual functions. The throughput of each function can be determined based on the number of transaction layer packets processed through the data path per unit time.

[0092] In S805, PCIe interface devices can dynamically assign traffic level values ​​to transaction layer packets received from multiple functions based on measured throughput. The following will refer to... Figure 9 and Figure 10 Additionally, describe the method for assigning traffic level values.

[0093] Figure 9 This is a flowchart illustrating a method for allocating traffic level values ​​according to an embodiment.

[0094] Reference Figure 9 In S901, the PCIe interface device can determine whether the function of the received transaction layer packet has been interrupted, i.e., whether an interrupt function exists. If an interrupt function exists, the PCIe interface device proceeds to S905. If an interrupt function does not exist, the PCIe interface device proceeds to S903.

[0095] In S905, PCIe interface devices can assign default values ​​as traffic level values ​​to transaction layer packets received from interrupt functions.

[0096] Subsequently, in S907, PCIe interface devices can dynamically allocate remaining traffic level values ​​to transaction layer packets received from other functions based on the throughput of functions other than interrupt functions.

[0097] When the interrupt function is not available, in S903, the PCIe interface device can dynamically assign traffic level values ​​to transaction layer packets received from multiple functions based on the throughput of multiple functions.

[0098] Figure 10 This is a flowchart illustrating a method for allocating traffic level values ​​according to an embodiment.

[0099] Reference Figure 10 In S1001, the PCIe interface device can assign a default value as the initial value for the traffic level of the received transaction layer packets.

[0100] In S1003, the PCIe interface device can determine whether the throughput of each function is greater than a threshold. When the throughput of a function is greater than the threshold, the PCIe interface device proceeds to S1009; when the throughput of a function is less than or equal to the threshold, the PCIe interface device proceeds to S1005.

[0101] In S1005, when the throughput is less than or equal to the threshold, the PCIe interface device can dynamically assign traffic level values ​​to transaction layer packets in reverse order of throughput ranking of multiple functions.

[0102] In S1007, the PCIe interface device can determine whether the ranking of throughput for multiple functions has changed. When the ranking of throughput changes, the PCIe interface device returns to S1003, and when the ranking of throughput does not change, the PCIe interface device terminates the operation.

[0103] In S1009, PCIe interface devices can assign default values ​​as traffic level values ​​for transaction layer packets received from functions with throughput greater than a threshold.

[0104] Subsequently, in S1011, the PCIe interface device can dynamically allocate the remaining traffic level values ​​to transaction layer packets received from other functions based on the throughput of functions other than those with throughput exceeding a threshold. Then, the PCIe interface device proceeds to S1007.

[0105] According to this disclosure, a PCIe interface device and a method of operating the PCIe interface device are provided, the PCIe interface device providing a uniform Quality of Service (QoS) for various functions.

[0106] While this disclosure has been shown and described with reference to certain exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

Claims

1. A high-speed peripheral component interconnect interface device, namely a PCIe interface device, comprising: The performance analyzer measures the throughput of multiple functions running on one or more DMA devices by counting the number of transaction layer packets transferred between one or more direct memory access devices, i.e., DMA devices, and the host system per unit time. as well as The traffic level controller assigns traffic level values ​​to transaction layer packets received from the multiple functions based on the throughput of those functions. Whenever the ranking of the throughput of the multiple functions changes, the traffic level controller reallocates traffic level values ​​to the transaction layer packets based on the changed ranking.

2. The PCIe interface device of claim 1, wherein the performance analyzer calculates the throughput of the plurality of functions based on the occupancy of the data path of the plurality of functions, the data path connecting the one or more DMA devices to the PCIe interface device.

3. The PCIe interface device of claim 2, wherein the performance analyzer calculates the utilization rate of each of the plurality of functions based on the number of transaction layer packets transmitted through the data path per unit time.

4. The PCIe interface apparatus of claim 1, wherein the traffic level controller assigns a default value as an initial value for the traffic level of transaction layer packets received from the plurality of functions.

5. The PCIe interface device of claim 4, wherein the traffic level controller assigns different traffic level values ​​to the transaction layer packets based on a comparison of the throughput of the plurality of functions with a threshold.

6. The PCIe interface apparatus of claim 5, wherein the traffic level controller assigns the default value as the traffic level value for transaction layer packets received from one of the plurality of functions whose throughput is greater than the threshold.

7. The PCIe interface device of claim 5, wherein the traffic level controller assigns traffic level values ​​to transaction layer packets received from the plurality of functions whose throughput is less than or equal to the threshold in descending order of the throughput ranking of the plurality of functions.

8. The PCIe interface device of claim 4, wherein the traffic level controller assigns the default value as the traffic level value of a transaction layer packet received from an interrupt function among the plurality of functions.

9. The PCIe interface device of claim 1, wherein the virtual channel to be mapped to the transaction layer packet is determined by the switch or root association based on the traffic level value allocated to the transaction layer packet.

10. The PCIe interface device of claim 9, wherein the order in which the transaction layer packets are to be output is determined by the switch or the root association based on a virtual channel mapped to the transaction layer packets.

11. The PCIe interface device of claim 1, wherein the one or more DMA devices include one or more of the following: a high-speed non-volatile memory device, i.e., an NVMe device; a solid-state drive device, i.e., an SSD device; an artificial intelligence central processing unit, i.e., an AICPU; an artificial intelligence system-on-a-chip, i.e., an AISoC; an Ethernet device; a sound card; and a graphics card.

12. A method for operating a high-speed peripheral component interconnect interface device, i.e., a PCIe interface device, the method comprising: The throughput of the multiple functions is measured by counting the number of transaction layer packets transferred between the multiple functions running on one or more direct memory access devices (DMA devices) and the host system per unit time. as well as Traffic level values ​​are assigned to transaction layer packets received from the multiple functions based on the throughput of the multiple functions. Whenever the throughput ranking of the multiple functions changes, the traffic level value is reassigned to the transaction layer packet based on the changed ranking.

13. The method of claim 12, wherein measuring the throughput of the plurality of functions comprises: The throughput of the multiple functions is calculated based on the occupancy rate of the data path, wherein the data path connects the one or more DMA devices to the PCIe interface device.

14. The method of claim 13, wherein the occupancy rate of each of the plurality of functions is calculated based on the number of transaction layer packets transmitted per unit time through the data path.

15. The method of claim 12, wherein assigning the traffic level value to the transaction layer packet comprises: Assign default values ​​as initial values ​​for the traffic levels of transaction layer packets received from the multiple functions; and Based on the comparison of the throughput of the multiple functions with thresholds, different traffic level values ​​are assigned to the transaction layer packets.

16. The method of claim 15, wherein assigning different traffic level values ​​to the transaction layer packets comprises: The default value is assigned as the traffic level value for transaction layer packets received from the plurality of functions that have a throughput greater than the threshold or the interrupt function.

17. The method of claim 15, wherein assigning different traffic level values ​​to the transaction layer packets comprises: According to the reverse order of the throughput ranking of the multiple functions, the traffic level value is assigned to the transaction layer packets received from the functions whose throughput is less than or equal to the threshold.

18. The method of claim 12, wherein the switch or the root association determines the virtual channel to be mapped to the transaction layer packet based on the traffic level value assigned to the transaction layer packet, and the switch or the root association determines the order in which the transaction layer packets are to be output based on the virtual channel mapped to the transaction layer packet.

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