Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a layer to be etched, the layer to be etched comprising a first region and a second region; forming a plurality of discrete core layers on the first region and the second region; forming a first sidewall on the sidewall surface of the core layer; after forming the first sidewall, removing the core layer and retaining the first sidewall; forming a covering layer on the sidewall surface and top surface of the first sidewall on the first region; forming a second sidewall on the sidewall of the covering layer on the first region and the sidewall of the first sidewall on the second region; after forming the second sidewall, removing the first sidewall on the second region and retaining the second sidewall; after removing the first sidewall on the second region, removing the second sidewall on the sidewall of the covering layer; after removing the second sidewall on the sidewall of the covering layer, removing the covering layer, forming an etching pattern of the first sidewall on the first region, and forming an etching pattern of the second sidewall on the second region. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the field of semiconductor technology, transistors are currently being widely used as the most basic semiconductor devices. Fin field effect transistors are a new type of complementary metal oxide semiconductor (CMOS) transistor that can improve circuit control and reduce leakage current, shorten the gate length of transistors, greatly increase chip processing speed and significantly reduce power consumption. They are now widely used in circuits of various semiconductor devices.

[0003] As the manufacturing of integrated circuits develops towards very large-scale integrated circuits, the circuit density inside them is getting higher and higher. As the technology nodes are reduced, the size of the formed semiconductor structure is getting smaller and smaller, and the process difficulty of forming fin field-effect transistors of various sizes is also increasing.

[0004] The performance of the fin field effect transistor formed using the existing technology needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve transistor performance.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, the layer to be etched comprising a first region and a second region; forming a plurality of discrete core layers on the first region and the second region; forming a first sidewall on the sidewall surface of the core layer; after forming the first sidewall, removing the core layer and retaining the first sidewall; forming a covering layer on the sidewall surface and the top surface of the first sidewall on the first region; forming a second sidewall by the sidewall of the covering layer on the first region and the sidewall of the first sidewall on the second region; after forming the second sidewall, removing the first sidewall on the second region and retaining the second sidewall; after removing the first sidewall on the second region, removing the second sidewall of the covering layer sidewall; after removing the second sidewall of the covering layer sidewall, removing the covering layer, forming an etching pattern of the first sidewall on the first region, and forming an etching pattern of the second sidewall on the second region.

[0007] Optionally, the method for forming the covering layer includes: forming a covering material layer on the layer to be etched and on the top surface and side wall surface of the first side wall; forming a first mask layer on the covering material layer, wherein the first mask layer exposes the surface of the covering material layer on the second area; etching the covering material layer on the second area using the first mask layer as a mask to form a covering layer on the first area.

[0008] Optionally, the material of the cover layer includes an organic material, and the organic material includes amorphous carbon or a bottom anti-reflection material.

[0009] Optionally, the process of forming the covering material layer includes a spin coating process or a spray coating process.

[0010] Optionally, the process of removing the covering layer includes an ashing process.

[0011] Optionally, the method for removing the second side wall of the covering layer side wall includes: forming a sacrificial material layer on the top surface and side wall surface of the second side wall, and the top surface of the covering layer; forming a second mask layer on the sacrificial material layer, the second mask layer exposing the sacrificial material layer on the second side wall of the covering layer side wall; etching the sacrificial material layer using the second mask layer as a mask until the surface to be etched is exposed, forming a sacrificial layer on the top surface and side wall surface of the second side wall on the top surface of the covering layer and the second region, the sacrificial layer exposing the top surface and side wall surface of the second side wall of the covering layer side wall; using the sacrificial layer as a mask, removing the second side wall of the covering layer side wall.

[0012] Optionally, the process of removing the second sidewall spacer of the cover layer sidewall includes a dry etching process.

[0013] Optionally, the material of the sacrificial layer includes an amorphous material, and the amorphous material includes amorphous carbon.

[0014] Optionally, after removing the second sidewall spacer of the cover layer sidewall, the method further includes: removing the sacrificial layer.

[0015] Optionally, the process of removing the sacrificial layer includes an ashing process.

[0016] Optionally, after forming the covering layer and before forming the second sidewall, the method further includes: thinning the first sidewall on the second region; the thinning process includes an isotropic dry etching process.

[0017] Optionally, after removing the first sidewall on the second region and before removing the second sidewall of the cover layer sidewall, the method further includes: thinning the second sidewall; the thinning process includes an isotropic dry etching process.

[0018] Optionally, the method for forming the first side wall includes: forming a side wall material layer on the side wall surface and the top surface of the core layer; etching back the side wall material layer until the core layer surface and the surface of the layer to be etched are exposed, and forming the first side wall on the side wall of the core layer.

[0019] Optionally, the material of the core layer is different from the material of the first sidewall; the material of the core layer is different from the material of the surface of the layer to be etched.

[0020] Optionally, the material of the core layer includes: silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

[0021] Optionally, a material of the first spacer includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

[0022] Optionally, in the process of removing the core layer, an etching rate of the core layer is greater than an etching rate of the first sidewall.

[0023] Optionally, the material of the first sidewall is different from the material of the second sidewall.

[0024] Optionally, the material of the second side wall includes:

[0025] Optionally, in the process of removing the first sidewall spacer on the second region, an etching rate of the first sidewall spacer is greater than an etching rate of the second sidewall spacer.

[0026] Optionally, the layer to be etched includes: a substrate, a fin material layer located on the substrate, and a hard mask material layer located on the fin material layer.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] The technical solution of the present invention forms a plurality of discrete first sidewalls on the first region and the second region, then forms a covering layer on the sidewall surface and the top surface of the first sidewall on the first region, then forms a second sidewall on the sidewall of the first sidewall and the sidewall of the covering layer, then removes the first sidewall on the second region, then removes the second sidewall on the sidewall of the covering layer, and finally removes the covering layer, so that the first sidewall on the first region and the second sidewall on the second region form a mask pattern for etching the layer to be etched. The method first covers the first sidewall on the first region with a covering layer, so that when the first sidewall on the second region is removed, the first sidewall on the first region is retained, and then removes the second sidewall on the sidewall of the covering layer, so that the first sidewall on the first region and the second sidewall on the second region formed subsequently have different spacings. The method is not limited by the accuracy of photolithography and can achieve the purpose of forming semiconductor structures with different spacings.

[0029] Furthermore, the material of the cover layer includes an organic material; the organic material includes amorphous carbon or a bottom anti-reflection material. The amorphous carbon or the bottom anti-reflection material is an ashing material, and the process of removing the amorphous carbon or the bottom anti-reflection material includes an ashing process. Therefore, when removing the cover layer, the cover layer is easy to remove, and the ashing process can remove the cover layer completely, avoiding the situation where the cover layer remains and affects the morphology of the first sidewall on the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 4 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0031] Figures 5 to 15 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the performance of existing fin field effect transistors needs to be improved.

[0033] Figures 1 to 4 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0034] Please refer to Figure 1 , comprising: providing a substrate 100, the substrate comprising a base (not shown) and a fin material layer (not shown) located on the base; forming a plurality of discrete core layers 101 on the substrate 100, with a first opening 102 and a second opening 103 between adjacent core layers 101, the first opening 102 having a first size along the arrangement direction of the core layers 101, the second opening 103 having a second size along the arrangement direction of the core layers 101, and the second size being smaller than the first size.

[0035] Please refer to Figure 2 A first sidewall 104 is formed on the sidewall surface of the first opening 102 , and a second sidewall 105 is formed in the second opening 103 , and the second sidewall 105 fills up the second opening 103 .

[0036] Please refer to Figure 3 , remove the core layer 101 , and form a third sidewall 106 on the sidewalls of the first sidewall 104 and the second sidewall 105 .

[0037] Please refer to Figure 4 , remove the first sidewall 104 and the second sidewall 105 , and etch the substrate 100 using the third sidewall 106 as a mask.

[0038] During the formation process of the semiconductor structure, the second side wall 105 in the second opening 103 is the merged first side wall 104, and then the third side wall 106 is formed on the side wall of the first side wall 104 and the side wall of the second side wall 105. The formed third side walls 106 have different spacings between adjacent third side walls 106, so that fin structures with different spacings can be formed when the substrate is subsequently etched.

[0039] However, as the size of semiconductors further decreases, the size of the fin structure to be formed also becomes smaller and smaller. The existing photolithography technology cannot form the second opening 103 with the same size reduction to meet the requirements of finally forming the third sidewall spacer 106 with reduced size and spacing.

[0040] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by first forming a plurality of discrete first sidewalls on a first region and a second region, then forming a covering layer on the sidewall surface and the top surface of the first sidewall on the first region, then forming a second sidewall on the sidewall of the first sidewall and the sidewall of the covering layer, then removing the first sidewall on the second region, then removing the second sidewall on the sidewall of the covering layer, and finally removing the covering layer, the first sidewall on the first region and the second sidewall on the sidewall of the covering layer form a mask pattern for etching the layer to be etched. The method first covers the first sidewall on the first region with a covering layer, so that when the first sidewall on the second region is removed, the first sidewall on the first region is retained, and then by removing the second sidewall on the sidewall of the covering layer, the first sidewall on the first region and the second sidewall on the sidewall of the covering layer formed subsequently have different spacings, the method is not limited by the accuracy of photolithography, and can achieve the purpose of forming semiconductor structures with different spacings.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 5 to 15 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0043] Please refer to Figure 5 , providing a layer 200 to be etched, wherein the layer 200 to be etched includes a first region I and a second region II.

[0044] In this embodiment, the layer to be etched 200 includes: a substrate (not shown), a fin material layer (not shown) located on the substrate, and a hard mask material layer (not shown) located on the fin material layer.

[0045] In this embodiment, the material of the substrate is silicon, and the material of the fin material layer includes silicon.

[0046] In other embodiments, the materials of the substrate and the fin material layer include silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0047] The material of the hard mask material layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbide, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, silicon carbonitride, and silicon oxynitride.

[0048] In this embodiment, the material of the hard mask material layer includes silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride.

[0049] Next, a plurality of separate first spacers 202 are formed on the first region I and the second region II. The formation process of the first spacers 202 can be found in Figures 5 to 7 .

[0050] Please continue to refer to Figure 5 , a plurality of discrete core layers 201 are formed on the layer to be etched 200 .

[0051] The method for forming the core layer 201 includes: forming a core material layer (not shown) on the layer to be etched 200; forming a patterned mask layer (not shown) on the core material layer, wherein the patterned mask layer exposes a portion of the surface of the core layer; etching the core material layer using the patterned mask layer as a mask until the surface of the layer to be etched 200 is exposed, thereby forming the core layer 201.

[0052] The material of the core layer 201 is different from the material of the surface of the layer to be etched 200 , that is, the material of the core layer 201 is different from the material of the hard mask material layer, so that the process of etching the core material layer can stop at the surface of the layer to be etched 200 .

[0053] The material of the core layer 201 includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

[0054] In this embodiment, the material of the core layer 201 includes silicon.

[0055] Please refer to Figure 6 , a first sidewall 202 is formed on the sidewall of the core layer 201 .

[0056] The method for forming the first sidewall 202 includes: forming a sidewall material layer (not shown) on the sidewall surface and top surface of the core layer 201; etching back the sidewall material layer until the surface of the core layer 201 and the surface of the layer to be etched 200 are exposed, and forming the first sidewall 202 on the sidewall of the core layer 201.

[0057] The material of the first sidewall 202 is different from that of the core layer 201, and the material of the first sidewall 202 is different from that of the surface of the layer to be etched 200, that is, the material of the first sidewall 202 is different from that of the hard mask material layer. Therefore, the process of etching back the sidewall material layer can cause less damage to the core layer 201 and the surface of the layer to be etched 200.

[0058] The material of the first spacer 202 includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

[0059] In this embodiment, the material of the first spacer 202 includes silicon oxide.

[0060] Please refer to Figure 7 After forming the first sidewall 202, the core layer 201 is removed.

[0061] The process of removing the core layer 201 includes a dry etching process or a wet etching process. The etching rate of the core layer 201 in the removal process is greater than the etching rate of the first sidewall 202 , and the etching rate of the core layer 201 in the removal process is greater than the etching rate of the surface of the layer 200 to be etched.

[0062] Please refer to Figure 8 A covering layer 203 is formed on the sidewall surface and the top surface of the first spacer 202 on the first region I.

[0063] The method for forming the covering layer 203 includes: forming a covering material layer (not shown) on the layer to be etched 200 and the top surface and side wall surface of the first side wall 202; forming a first mask layer (not shown) on the covering material layer, wherein the first mask layer exposes the surface of the covering material layer on the second region II; etching the covering material layer on the second region II using the first mask layer as a mask to form a covering layer 203 on the first region I.

[0064] The material of the cover layer 203 is an organic material; the organic material includes amorphous carbon or a bottom anti-reflection material. The amorphous carbon or the bottom anti-reflection material is an ashing material, and the process of removing the amorphous carbon or the bottom anti-reflection material includes an ashing process. Therefore, when the cover layer 203 is removed later, the cover layer 203 is easy to be removed, and the ashing process can remove the cover layer 203 completely, avoiding the situation where the cover layer 203 is left and affects the morphology of the first sidewall 202 on the first region I.

[0065] The process of forming the covering material layer includes: a spin coating process or a spray coating process.

[0066] Please refer to Fig. 9After forming the covering layer 203, the method further includes: thinning the first sidewall 202 on the second region II.

[0067] The thinning process includes an isotropic dry etching process. The thinning process can further reduce the size of the first sidewall 202 exposed by the cover layer 203.

[0068] In other embodiments, the first sidewall spacer on the second region may not be thinned.

[0069] Please refer to Fig.10 The sidewall of the first spacer 202 on the second region II and the sidewall of the covering layer 203 on the first region I form a second spacer 204 .

[0070] The method for forming the second sidewall 204 includes: forming a sidewall material layer (not shown) on the sidewall surface and top surface of the first sidewall 202 and the sidewall surface and top surface of the covering layer 203; etching back the sidewall material layer until the top surface of the first sidewall 202 and the surface of the layer to be etched 200 are exposed to form the second sidewall 204.

[0071] The material of the second sidewall spacer 204 is different from that of the first sidewall spacer 202, the material of the second sidewall spacer 204 is different from that of the cover layer 203, and the material of the second sidewall spacer 204 is different from that of the surface of the to-be-etched layer 200. Therefore, when the sidewall material layer is etched back, the etch-back process can cause less damage to the first sidewall spacer 202, the cover layer 203, and the to-be-etched layer 200.

[0072] The material of the second spacer 204 includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

[0073] In this embodiment, the material of the second sidewall spacer 204 includes silicon carbide.

[0074] Please refer to Fig.11 After forming the second sidewall spacer 204, the first sidewall spacer 202 on the second region II is removed, and the second sidewall spacer 204 is retained.

[0075] The process of removing the first spacer 202 on the second region II includes a dry etching process or a wet etching process. The etching rate of the first spacer 202 in the removal process is greater than the etching rate of the second spacer 204 .

[0076] Please refer to Fig.12 After removing the first sidewall 202 on the second region II, the second sidewall 204 is also thinned.

[0077] The thinning process includes an isotropic dry etching process. The thinning process can further reduce the size of the second sidewall spacer 204 exposed by the cover layer 203 .

[0078] In other embodiments, the second sidewall may not be thinned.

[0079] Next, the second sidewall 204 of the sidewall of the cover layer 203 is removed. For the process of removing the second sidewall 204 of the sidewall of the cover layer 203, please refer to Fig.13 and Fig.14 .

[0080] Please refer to Fig.13 A sacrificial layer 205 is formed on the top surface of the covering layer 203 and the top surface and side wall surface of the second spacer 204 on the second region II, and the sacrificial layer 205 exposes the top surface and side wall surface of the second spacer 204 on the side wall of the covering layer 203 .

[0081] The method for forming the sacrificial layer 205 includes: forming a sacrificial material layer (not shown) on the top surface and side wall surface of the second side wall 204 and the top surface of the covering layer 203; forming a second mask layer (not shown) on the sacrificial material layer, the second mask layer exposes the sacrificial material layer on the second side wall 204 of the side wall of the covering layer 203; etching the sacrificial material layer using the second mask layer as a mask until the surface of the layer to be etched 200 is exposed, forming a sacrificial layer 205 on the top surface of the covering layer 203 and the top surface and side wall surface of the second side wall 204 on the second region II, the sacrificial layer 205 exposing the top surface and side wall surface of the second side wall 204 of the side wall of the covering layer 203.

[0082] The material of the sacrificial layer 205 includes an amorphous material, and the amorphous material includes amorphous carbon.

[0083] The amorphous carbon material is easily removed, thereby avoiding a situation where residues are left when the sacrificial layer is subsequently removed, thereby affecting the morphology of the second sidewall spacer 204 on the second region II.

[0084] Please refer to Fig.14 , using the sacrificial layer 205 as a mask, removing the second sidewall 204 of the sidewall of the cover layer 203 .

[0085] In this embodiment, the process of removing the second spacer 204 on the sidewall of the cover layer 203 includes a dry etching process.

[0086] Please refer to Fig.15 After removing the second sidewall spacer 204 on the sidewall of the cover layer 203 , the sacrificial layer 205 is removed.

[0087] In this embodiment, the material of the sacrificial layer 205 includes amorphous carbon. The process of removing the sacrificial layer 205 includes an ashing process.

[0088] Please continue to refer to Fig.15 , further comprising: removing the covering layer 203, forming an etching pattern of a first sidewall 202 on the first region I, and forming an etching pattern of a second sidewall 204 on the second region II.

[0089] The material of the cover layer 203 is an organic material, and the organic material includes amorphous carbon or a bottom anti-reflection material. The amorphous carbon or the bottom anti-reflection material is an ashing material, and the process of removing the amorphous carbon or the bottom anti-reflection material includes an ashing process. The cover layer 203 is easy to remove, and the ashing process can remove the cover layer 203 completely, thereby avoiding the situation where the cover layer 203 remains and affects the morphology of the first sidewall 202 on the first region I.

[0090] Next, the to-be-etched layer 200 is etched using the first sidewall spacer 202 on the first region I and the second sidewall spacer 204 on the second region II as masks. This process is a common process in semiconductor manufacturing and will not be described in detail herein.

[0091] At this point, the first sidewall spacer 202 and the second sidewall spacer 204 formed have different pitches, and the first sidewall spacer 202 on the first region I and the second sidewall spacer 204 on the second region II form a mask pattern for etching the to-be-etched layer 200. When the to-be-etched layer 200 is etched using the first sidewall spacer 202 and the second sidewall spacer 204 as a mask, semiconductor structures with different pitch sizes can be formed.

[0092] The formation method of the present invention first covers the first sidewall 202 on the first area I with a covering layer 203, so that when the first sidewall 202 on the second area II is removed, the first sidewall 202 on the first area I is retained, and then the second sidewall 204 on the sidewall of the covering layer 203 is removed, so that the first sidewall 202 on the first area I and the second sidewall 204 on the second area II formed subsequently have different spacings. The method is not limited by the accuracy of photolithography and can achieve the purpose of forming semiconductor structures with different spacings.

[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein the layer to be etched includes a first area and a second area; forming a plurality of discrete core layers on the first region and the second region; forming a first side wall on the side wall surface of the core layer; After forming the first sidewall, removing the core layer and retaining the first sidewall; forming a capping layer on the sidewall surface and the top surface of the first spacer on the first region; The second spacer is formed on the sidewall of the cover layer on the first region and the sidewall of the first spacer on the second region; After forming the second sidewall spacer, removing the first sidewall spacer on the second region and retaining the second sidewall spacer; After removing the first sidewall spacer on the second region, removing the second sidewall spacer on the sidewall of the covering layer; After removing the second sidewall spacer of the cover layer sidewall, the cover layer is removed, an etching pattern of the first sidewall spacer is formed on the first region, and an etching pattern of the second sidewall spacer is formed on the second region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the covering layer includes: forming a covering material layer on the layer to be etched and on the top surface and side wall surface of the first sidewall; forming a first mask layer on the covering material layer, wherein the first mask layer exposes the surface of the covering material layer on the second area; etching the covering material layer on the second area using the first mask layer as a mask to form a covering layer on the first area.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the cover layer includes an organic material; the organic material includes amorphous carbon or a bottom anti-reflection material.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process of forming the covering material layer includes a spin coating process or a spray coating process.

5. The method for forming a semiconductor structure according to claim 3, wherein: The process of removing the cover layer includes an ashing process.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the second sidewall of the sidewall of the covering layer comprises: forming a sacrificial material layer on the top surface and the sidewall surface of the second sidewall and the top surface of the covering layer; forming a second mask layer on the sacrificial material layer, the second mask layer exposing the sacrificial material layer on the second sidewall of the sidewall of the covering layer; etching the sacrificial material layer using the second mask layer as a mask until the surface to be etched is exposed, forming a sacrificial layer on the top surface and the sidewall surface of the second sidewall on the top surface of the covering layer and the second region, the sacrificial layer exposing the top surface and the sidewall surface of the second sidewall of the sidewall of the covering layer; removing the second sidewall of the sidewall of the covering layer using the sacrificial layer as a mask.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the second sidewall spacer of the cover layer sidewall includes a dry etching process.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the sacrificial layer includes an amorphous material, and the amorphous material includes amorphous carbon.

9. The method for forming a semiconductor structure according to claim 8, wherein: After removing the second spacer of the sidewall of the cover layer, the method further includes: removing the sacrificial layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the sacrificial layer includes an ashing process.

11. The method for forming a semiconductor structure according to claim 1, wherein: After forming the cover layer and before forming the second sidewall, the method further includes: thinning the first sidewall on the second region; the thinning process includes an isotropic dry etching process.

12. The method for forming a semiconductor structure according to claim 1, wherein: After removing the first sidewall spacer on the second region and before removing the second sidewall spacer of the cover layer sidewall, the method further includes: thinning the second sidewall spacer; the thinning process includes an isotropic dry etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first sidewall includes: forming a sidewall material layer on the sidewall surface and the top surface of the core layer; etching back the sidewall material layer until the surface of the core layer and the surface of the layer to be etched are exposed, and forming the first sidewall on the sidewall of the core layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the core layer is different from the material of the first sidewall; the material of the core layer is different from the material of the surface of the layer to be etched.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the core layer includes: silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

16. The method for forming a semiconductor structure according to claim 14, wherein: The material of the first spacer includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

17. The method for forming a semiconductor structure according to claim 14, wherein: In the process of removing the core layer, the etching rate of the core layer is greater than the etching rate of the first sidewall.

18. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer is different from that of the second spacer.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the second spacer includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or amorphous carbon.

20. The method for forming a semiconductor structure according to claim 18, wherein: In the process of removing the first spacer on the second region, an etching rate of the first spacer is greater than an etching rate of the second spacer.

21. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate, a fin material layer located on the substrate, and a hard mask material layer located on the fin material layer.

Images