Bump packaging structure and method for manufacturing bump packaging structure

Abstract

Embodiments of the present application provide a bump packaging structure and a preparation method thereof, and relate to the technical field of semiconductor packaging. The bump packaging structure comprises a chip, a solder pad, a protective layer, a substrate conductive layer, a first combined conductive layer, a conductive column and a solder cap. The substrate conductive layer comprises a multilayer graphene structure. Compared with the prior art, the bump packaging structure and the preparation method thereof provided by the present application can avoid the undercut opening formed by excessive corrosion, and the structure is more stable, the problem of electrode stress cracking is avoided, and the heat dissipation and conductivity are better, effectively alleviating the failure hidden danger caused by electromigration and thermal migration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically, to a bump packaging structure and a method for preparing the bump packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, flip-chip packaging structures are widely used. Flip-chip packaging utilizes bumps to electrically connect the chip and the substrate. The bumps consist of copper pillars, a metal layer (UBM: underbump metalization), a protective layer (polyimide), and a tin cap (Sn Cap). After fabricating the UBM, excess metal needs to be etched away. Because polyimide is extremely hygroscopic, etchant residue on the UBM sidewalls at the bottom of the copper pillars can lead to excessive corrosion and undercutting at the bottom of the copper pillar bumps. This can cause the copper pillar bumps to fall off during reliability testing. Using existing technology, the bottom of the copper pillar bumps is completely connected to the chip electrodes, causing stress on the copper pillar bumps to act directly on the chip electrodes, potentially leading to electrode cracking. Furthermore, under current, due to the Joule heating effect, the metal atoms at the connection point at the bottom of the copper pillar are simultaneously affected by both electric and thermal fields. The abnormally active electromigration and thermal migration at the interconnect interface can significantly reduce its lifespan, creating potential failure hazards. Summary of the Invention

[0003] The objectives of this invention include, for example, providing a bump encapsulation structure and a method for preparing the bump encapsulation structure, which can avoid the undercut opening formed by excessive corrosion, while the structure is more stable, avoiding the problem of electrode cracking under stress, and has better heat dissipation and conductivity, effectively mitigating the failure risks caused by electromigration and thermal migration.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a bump packaging structure, comprising:

[0006] A chip, wherein a solder pad is provided on one side of the chip;

[0007] A protective layer is disposed on one side of the chip, and the protective layer has protective openings corresponding to the solder pads;

[0008] A base conductive layer disposed in the protective opening;

[0009] A first combined conductive layer disposed on the substrate conductive layer;

[0010] Conductive pillars disposed on the first combined conductive layer;

[0011] And the solder cap disposed on the conductive post;

[0012] The conductive substrate layer comprises a multilayer graphene structure.

[0013] In an optional embodiment, the height of the substrate conductive layer is greater than the depth of the protective opening, and a shielding portion is provided on the top of the substrate conductive layer. The shielding portion extends outward from the center of the protective opening to the surface of the protective layer and covers the edge of the protective opening.

[0014] In an optional embodiment, the thickness of the shielding portion is 4-8 μm.

[0015] In an optional embodiment, the first combined conductive layer includes an adhesive layer, a barrier layer, and a wetting layer. The adhesive layer is disposed on the side of the substrate conductive layer away from the chip, the barrier layer is disposed on the side of the adhesive layer away from the chip, the wetting layer is disposed on the side of the barrier layer away from the chip, and the conductive pillar is disposed on the side of the wetting layer away from the chip. The adhesive layer is in contact with both the barrier layer and the substrate conductive layer to improve the adhesion between the barrier layer and the substrate conductive layer, and the wetting layer is in contact with both the barrier layer and the conductive pillar to improve the wettability between the barrier layer and the conductive pillar.

[0016] In an optional embodiment, the surface of the substrate conductive layer away from the chip is a flat surface, the adhesive layer covers the surface of the substrate conductive layer, the barrier layer covers the surface of the substrate conductive layer, the wetting layer covers the surface of the barrier layer, and the surface of the adhesive layer away from the chip is at least partially convex arc-shaped, so that the adhesive layer forms an arc-shaped bump structure.

[0017] In an optional embodiment, at least part of the surface of the substrate conductive layer away from the chip is an outwardly convex arc surface, so that the substrate conductive layer forms an arc-shaped bump structure, the adhesive layer is disposed at the periphery of the substrate conductive layer, the barrier layer covers the surfaces of the substrate conductive layer and the adhesive layer, and the wetting layer covers the surface of the barrier layer.

[0018] In an optional embodiment, a receiving groove is provided around the periphery of the substrate conductive layer, the adhesive layer is disposed within the receiving groove, and the thickness of the adhesive layer is the same as the depth of the receiving groove.

[0019] In an optional embodiment, at least part of the surface of the substrate conductive layer away from the chip is an outwardly convex arc surface, so that the substrate conductive layer forms an arc-shaped bump structure, the adhesive layer covers the surface of the substrate conductive layer, the barrier layer covers the surface of the adhesive layer, and the wetting layer covers the surface of the barrier layer.

[0020] In an optional embodiment, the surface of the adhesive layer away from the chip is a flat plane to planarize the barrier layer and the wetting layer.

[0021] In an optional embodiment, the substrate conductive layer includes a first substrate layer, a second substrate layer, and a third substrate layer. The first substrate layer is disposed within the protective opening, the second substrate layer is disposed on the first substrate layer, and the third substrate layer is disposed on the second substrate layer. At least a portion of the surface of the first substrate layer away from the chip is a convex arc surface, the surface of the second substrate layer away from the chip is a flat plane, and at least a portion of the surface of the third substrate layer away from the chip is a convex arc surface. The first combined conductive layer is disposed on the third substrate layer.

[0022] In an optional embodiment, both the first substrate layer and the third substrate layer comprise a multilayer graphene structure, the second substrate layer comprises a titanium layer, and titanium carbide layers are formed at both interfaces of the second substrate layer.

[0023] In an optional embodiment, both the first substrate layer and the third substrate layer include titanium layers, the second substrate layer includes a multilayer graphene structure, and titanium carbide layers are formed at both interfaces of the second substrate layer.

[0024] In an optional embodiment, a second combined conductive layer is further provided on the side of the conductive post away from the chip, and the second combined conductive layer is disposed between the conductive post and the solder cap.

[0025] In an optional embodiment, the second combined conductive layer includes a first conductive layer and a second conductive layer. The first conductive layer covers the surface of the conductive pillar, the second conductive layer covers the first conductive layer, the solder cap covers the second conductive layer, the second conductive layer is used to block atomic diffusion between the solder cap and the conductive pillar, and the first conductive layer is used to improve the adhesion between the second conductive layer and the conductive pillar.

[0026] In an optional embodiment, the surface of the conductive post away from the chip is at least partially convex arc-shaped, so that the conductive post forms an arc-shaped bump structure.

[0027] In a second aspect, the present invention provides a method for preparing a bump encapsulation structure, used to prepare a bump encapsulation structure as described in any of the foregoing embodiments, the preparation method comprising:

[0028] Provide a chip with solder pads;

[0029] A protective layer is formed on the side of the chip with solder pads;

[0030] Grooves are cut into the protective layer to form protective openings corresponding to the solder pads;

[0031] A substrate conductive layer is formed in the protective opening;

[0032] A first combined conductive layer is formed on the substrate conductive layer;

[0033] Conductive pillars are formed on the first combined conductive layer;

[0034] A solder cap is formed on the conductive post;

[0035] The conductive substrate layer comprises a multilayer graphene structure.

[0036] The beneficial effects of the embodiments of the present invention include, for example:

[0037] The bump packaging structure and its fabrication method provided by this invention first form a protective opening on a protective layer, then deposit a base conductive layer within the protective opening, and subsequently deposit a first combined conductive layer, conductive pillars, and solder caps in sequence. The base conductive layer comprises a multi-layered graphene structure. Because the graphene fills and covers the protective opening, the multi-layered graphene structure enhances the stability and hydrophobicity of the bottom structure. During micro-etching processes, regardless of whether chemical or plasma etching is used, the base conductive layer avoids the undercutting problems associated with traditional micro-etching processes when removing the UBM layer. Furthermore, the coefficient of thermal expansion (CTE) of graphene is only 1 / 10 to 1 / 20 that of copper and aluminum, which better prevents deformation of the UBM layer at the bottom of the conductive pillars, protecting the solder pads and the metal structure at the bottom of the conductive pillars. Graphene exhibits significantly higher electrical conductivity than metals and superior thermal conductivity. The multilayer graphene structure, formed by increasing graphene volume, further enhances its thermal conductivity and heat dissipation, greatly improving both. This avoids the problem of abnormally active electromigration and thermal migration significantly reducing the lifespan of copper pillar bumps and causing potential failure hazards. Simultaneously, the stability of graphene addresses the issue in traditional technologies where copper pillars cause significant stress within the package, leading to damage to brittle material layers, such as cracking of the chip pads at the bottom of the copper pillars, delamination of the UBM metal layer, or reduced solder joint fatigue life, thus ensuring structural stability. Compared to existing technologies, the bump packaging structure and its fabrication method provided by this invention avoid undercut openings caused by excessive corrosion, resulting in a more stable structure that prevents electrode cracking under stress. Furthermore, it offers superior heat dissipation and electrical conductivity, effectively mitigating the failure hazards caused by electromigration and thermal migration. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is an overall schematic diagram of the bump packaging structure provided in the first embodiment of the present invention;

[0040] Figure 2 This is a partial schematic diagram of the bump packaging structure provided in the first embodiment of the present invention;

[0041] Figures 3 to 8 A process flow diagram of the method for fabricating the bump packaging structure provided in the first embodiment of the present invention;

[0042] Figure 9This is an overall schematic diagram of the bump packaging structure provided in the second embodiment of the present invention;

[0043] Figure 10 for Figure 9 A magnified view of part of XI;

[0044] Figure 11 This is an overall schematic diagram of the bump packaging structure provided in the third embodiment of the present invention;

[0045] Figure 12 This is an overall schematic diagram of the bump packaging structure provided in the fourth embodiment of the present invention;

[0046] Figure 13 for Figure 12 A magnified view of part of Ⅻ;

[0047] Figure 14 This is an overall schematic diagram of the bump packaging structure provided in the fifth embodiment of the present invention.

[0048] Icons: 100 - Bump package structure; 110 - Chip; 120 - Solder pad; 130 - Protective layer; 131 - Protective opening; 140 - Base conductive layer; 141 - First base layer; 143 - Second base layer; 145 - Third base layer; 150 - First combined conductive layer; 151 - Adhesive layer; 153 - Barrier layer; 155 - Wetting layer; 157 - Receiving groove; 160 - Conductive post; 170 - Solder cap; 180 - Second combined conductive layer; 181 - First conductive layer; 183 - Second conductive layer. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0051] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0052] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0053] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0054] As disclosed in the background section, in existing technologies, during the formation of the metal layer UBM, the protective layer material is prone to water absorption, leading to etching solution residue on the sidewalls of the UBM at the bottom of the metal pillars. Excessive etching can cause undercutting at the bottom of the copper pillar bumps, affecting the structural strength and making them prone to detachment. Furthermore, in existing technologies, the bottom of the copper pillar bumps is completely connected to the chip electrodes, with the contact interface often being a metal-to-metal contact. This causes the stress on the copper pillar bumps to act directly on the chip electrodes, potentially leading to chip electrode cracking. Moreover, when the copper pillar bumps are subjected to current, due to the Joule heating effect, the metal atoms at the bottom connection point are simultaneously affected by both electric and thermal fields. The abnormally active electromigration and thermal migration at the interconnect interface significantly reduce its lifetime, creating potential failure hazards.

[0055] To address the aforementioned problems, this invention provides a bump encapsulation structure and a method for preparing the bump encapsulation structure. It should be noted that, unless otherwise specified, the features in the embodiments of this invention can be combined with each other.

[0056] First Embodiment

[0057] See Figure 1 and Figure 2 This embodiment provides a bump encapsulation structure 100, which can avoid the undercut opening formed by excessive corrosion. At the same time, the structure is more stable, avoiding the problem of electrode cracking under stress. It also has better heat dissipation and conductivity, effectively mitigating the failure risks caused by electromigration and thermal migration.

[0058] The bump package structure 100 provided in this embodiment includes a chip 110, a solder pad 120, a protective layer 130, a base conductive layer 140, a first combined conductive layer 150, a conductive pillar 160, and a solder cap 170. The solder pad 120 is disposed on one side of the chip 110 and electrically connected to the internal circuit layer of the chip 110. The protective layer 130 is disposed on the side of the chip 110 with the solder pad 120 and has a protective opening 131 corresponding to the solder pad 120. The size of the protective opening 131 is slightly smaller than the size of the solder pad 120, so that the solder pad 120 is partially exposed to the protective layer 130. The base conductive layer 140 is disposed in the opening and covers the protective opening 131. The first combined conductive layer 150 is disposed on the base conductive layer 140, the conductive pillar 160 is disposed on the first combined conductive layer 150, and the solder cap 170 is disposed on the conductive pillar 160. The base conductive layer 140 includes a multilayer graphene structure.

[0059] The bump encapsulation structure 100 provided in this embodiment first forms a protective opening 131 on a protective layer 130, then a base conductive layer 140 is disposed in the protective opening 131, followed by a first combined conductive layer 150, a conductive pillar 160, and a solder cap 170. The base conductive layer 140 includes a multi-layered graphene structure. Since the graphene fills and covers the protective opening 131, the multi-layered graphene structure enhances the stability and hydrophobicity of the bottom structure. During micro-etching processes, whether chemical etching or plasma etching is used, the base conductive layer 140 avoids the undercutting problems caused by traditional micro-etching processes when removing the UBM layer. Furthermore, the coefficient of thermal expansion (CTE) of graphene is only 1 / 10 to 1 / 20 that of copper and aluminum, which better prevents deformation of the UBM layer at the bottom of the conductive pillar 160, protecting the solder pad 120 and the metal structure at the bottom of the conductive pillar 160. Graphene exhibits significantly higher electrical conductivity than metals and superior thermal conductivity. The multilayered graphene structure, formed by increasing graphene volume, further enhances its thermal conductivity and heat dissipation, greatly improving both. This avoids the problem of abnormally active electromigration and thermal migration that could significantly reduce the lifespan of copper pillar bumps and cause potential failures. Simultaneously, the stability of graphene addresses the issue in traditional technologies where copper pillars can induce significant stress within the package, leading to damage to brittle material layers, such as cracking of the chip's 110 pad at the bottom of the copper pillar, delamination of the UBM metal layer, or reduced solder joint fatigue life, thus ensuring structural stability.

[0060] In this embodiment, the solder pad 120 is an aluminum solder pad 120, the height of the base conductive layer 140 is greater than the depth of the protective opening 131, and a shielding portion is provided on the top of the base conductive layer 140. The shielding portion extends outward from the center of the protective opening 131 to the surface of the protective layer 130 and covers the edge of the protective opening 131. Specifically, the shielding portion is integrally provided on the top edge of the base conductive layer 140 and extends outward to the surface of the protective layer 130, so that the base conductive layer 140 can completely cover the protective opening 131. By providing the shielding portion, the base conductive layer 140 can completely cover the protective opening 131 and cover the gap between the protective opening 131 and the base conductive layer 140. When etching the base conductive layer 140, the etching solution can be prevented from remaining at the edge of the protective opening 131, thereby avoiding the undercutting phenomenon of the base conductive layer 140 and its upper metal layer, improving the connection strength of the overall structure. Furthermore, the base conductive layer 140 is made of graphene material, which can further prevent corrosion by the etching solution.

[0061] In this embodiment, the thickness of the shielding portion is 4-8 μm. For example, the thickness of the shielding portion is 6 μm, meaning that the height of the substrate conductive layer 140 is greater than the depth of the protective opening 131, and the difference is 6 μm. Meanwhile, the width of the shielding portion can be between 4-10 μm, thereby ensuring that the shielding portion can completely block the protective opening 131.

[0062] In this embodiment, the first combined conductive layer 150 includes an adhesive layer 151, a barrier layer 153, and a wetting layer 155. The adhesive layer 151 is disposed on the side of the substrate conductive layer 140 away from the chip 110, the barrier layer 153 is disposed on the side of the adhesive layer 151 away from the chip 110, the wetting layer 155 is disposed on the side of the barrier layer 153 away from the chip 110, and the conductive pillar 160 is disposed on the side of the wetting layer 155 away from the chip 110. The adhesive layer 151 is in contact with both the barrier layer 153 and the substrate conductive layer 140 to improve the adhesion between the barrier layer 153 and the substrate conductive layer 140. The wetting layer 155 is in contact with both the barrier layer 153 and the conductive pillar 160 to improve the wettability between the barrier layer 153 and the conductive pillar 160. Specifically, the barrier layer 153 is used to block diffusion atoms between adjacent layers. Furthermore, the adhesive layer 151, the barrier layer 153, and the wetting layer 155 are all made of conductive metal materials, thereby achieving good electrical connection characteristics.

[0063] In this embodiment, the adhesive layer 151 is a titanium layer, and the conductive substrate layer 140 is a graphene layer. Therefore, when the adhesive layer 151 and the conductive substrate layer 140 are combined, titanium carbide (TiC) is generated at the interface. TiC is insoluble in water, has high chemical stability, and hardly reacts with hydrochloric acid or sulfuric acid. Carbon atoms and titanium atoms are equivalent in their crystal lattice positions. TiC atoms are bonded together by strong covalent bonds, exhibiting several metal-like properties, such as high melting point, boiling point, and hardness, second only to diamond in hardness. Simultaneously, TiC has good thermal and electrical conductivity, even exhibiting superconductivity at extremely low temperatures. By adding titanium metal, the bonding force between the metals is improved, solving the problem of poor bonding between graphene structures and metal layers in traditional technologies.

[0064] In this embodiment, the surface of the substrate conductive layer 140 away from the chip 110 is a flat surface. An adhesive layer 151 covers the surface of the substrate conductive layer 140, a barrier layer 153 covers the surface of the substrate conductive layer 140, and a wetting layer 155 covers the surface of the barrier layer 153. At least a portion of the surface of the adhesive layer 151 away from the chip 110 is a convex arc surface, forming an arc-shaped bump structure. Specifically, the planar structure of the substrate conductive layer 140 increases the bottom force-bearing area of ​​the first combined conductive layer 150, thereby improving structural strength. Simultaneously, the arc-shaped bump structure of the adhesive layer 151 further increases the contact area between the adhesive layer 151 and the barrier layer 153, thus improving the adhesive properties of the adhesive layer 151 and also enhancing its conductivity, resulting in better conductivity.

[0065] In this embodiment, both the barrier layer 153 and the wetting layer 155 are layers of equal thickness. The barrier layer 153 covers the convex adhesive layer 151, and the wetting layer 155 covers the barrier layer 153. Preferably, the adhesive layer 151 is a titanium layer with an edge thickness between 4-6 μm. The barrier layer 153 can be made of at least one of nickel, vanadium, and chromium, and its thickness is 4-6 μm. Meanwhile, the wetting layer 155 is made of copper, and the conductive pillar 160 can also be a copper pillar. The wetting layer 155 has a thickness of 2-4 μm. The convex adhesive layer 151 and the arc-shaped barrier layer 153 can enhance the structural strength of the intermediate layer of the combined conductive layer.

[0066] In this embodiment, a second combined conductive layer 180 is further disposed on the side of the conductive post 160 away from the chip 110, and the second combined conductive layer 180 is disposed between the conductive post 160 and the solder cap 170. Specifically, the second combined conductive layer 180 is made of a conductive metal material.

[0067] In this embodiment, the second combined conductive layer 180 includes a first conductive layer 181 and a second conductive layer 183. The first conductive layer 181 covers the surface of the conductive post 160, the second conductive layer 183 covers the first conductive layer 181, and the solder cap 170 covers the second conductive layer 183. The second conductive layer 183 is used to block atomic diffusion between the solder cap 170 and the conductive post 160, and the first conductive layer 181 is used to improve the adhesion between the second conductive layer 183 and the conductive post 160. Specifically, the first conductive layer 181 is a titanium layer, which can improve the adhesion between the second conductive layer 183 and the conductive post 160. The second conductive layer 183 is a nickel-vanadium alloy, which can play a blocking role, preventing atoms in the top solder cap 170 from diffusing to the conductive post 160. Of course, the first conductive layer 181 can also be made of graphene material to improve heat dissipation and conductivity.

[0068] In this embodiment, at least a portion of the surface of the conductive post 160 away from the chip 110 is a convex arc surface, so that the conductive post 160 forms an arc-shaped bump structure. Specifically, the conductive post 160 is a copper post, and the end of the conductive post 160 away from the chip 110 is convex arc-shaped, thereby increasing the contact area of ​​the first conductive layer 181 and thus improving adhesion.

[0069] It is worth noting that in this embodiment, the conductive post 160 also has stop platforms formed on both sides of the convex arc surface. The surface of the stop platforms is set upward along the horizontal plane or from the inside out, so that the height of the edge of the conductive post 160 is greater than or equal to the height of the edge of the convex arc surface. By setting the stop platforms, a flow-stopping buffering effect can be achieved, reducing the phenomenon of the welding cap 170 climbing along the side of the conductive post 160.

[0070] This embodiment also provides a method for fabricating a bump encapsulation structure 100, which is used to fabricate the aforementioned bump encapsulation structure 100. The fabrication method includes:

[0071] S1: Provide a chip 110 with solder pads 120.

[0072] See Figure 3 Specifically, a chip 110 with solder pads 120 is first provided. The chip 110 has a circuit layer inside, and the solder pads 120 are electrically connected to the circuit layer.

[0073] S2: A protective layer 130 is formed on the side of the chip 110 with the solder pad 120.

[0074] See Figure 4 Specifically, a coating machine is used to uniformly coat a liquid protective material, such as polyimide, onto the surface of the chip 110 using a spin coating method, and then the film is formed by soft baking on a hot plate.

[0075] S3: A groove is cut in the protective layer 130 to form a protective opening 131 corresponding to the solder pad 120.

[0076] See Figure 5 Specifically, through exposure and development technology, holes are made at predetermined positions to expose the solder pads 120 and create a slope. Then, the protective layer 130 is accelerated to a stable state by heating in an oven. Finally, a residue remover is used to remove contaminants or residues from the surface of the protective layer 130. The protective layer 130 can also be made of materials such as silicon nitride.

[0077] S4: A substrate conductive layer 140 is formed in the protective opening 131.

[0078] See Figure 6 Specifically, a multilayer graphene structure is formed again on the surface of the protective layer 130 by coating or other means, wherein the graphene material fills the protective openings 131 and covers the surface of the protective layer 130 with a thickness between 4 and 8 μm, and then the substrate conductive layer 140 is cured again using an oven. The substrate conductive layer 140 comprises a multilayer graphene structure.

[0079] S5: A first combined conductive layer 150 is formed on the substrate conductive layer 140.

[0080] See Figure 7 Specifically, an adhesive layer 151 is electroplated on the surface of the conductive substrate 140. The adhesive layer 151 can be a titanium layer with a thickness between 4 and 6 μm. The titanium layer has extremely high metal adhesion properties. Then, a convex arc surface is formed on the adhesive layer 151 by plasma etching or chemical etching. Then, a barrier layer 153 and a wetting layer 155 are electroplated on the adhesive layer 151 in sequence.

[0081] S6: A conductive pillar 160 is formed on the first combined conductive layer 150;

[0082] See Figure 8 A protective adhesive is coated on the surface of the first conductive layer 150, and the width of the conductive pillar 160 is opened using a photolithography process. Then, a copper layer is electroplated to form the conductive pillar 160.

[0083] After the conductive pillar 160 is formed, a convex arc surface can be formed at the end of the pillar by plasma etching or chemical etching. Then, an electrolytic descaling machine (Descum) can be used to remove excess protective adhesive, forming a copper pillar structure with arc-shaped bumps.

[0084] Then, a second combined conductive layer 180 is formed at the end of the conductive post 160. The formation process of the second combined conductive layer 180 is the same as that of the first combined conductive layer 150, and will not be described again here.

[0085] S7: Form a solder cap 170 on the conductive post 160.

[0086] See also Figure 1 Specifically, after forming the second conductive layer 180, a solder cap 170 is formed using steps such as applying protective adhesive, opening, printing / electroplating, and then the protective adhesive is removed. The solder cap 170 can be a tin cap, and the process is completed after reflow.

[0087] In summary, the bump package structure 100 provided in this embodiment has a multi-layer graphene structure for its base conductive layer 140. The base conductive layer 140 fills the opening of the protective layer 130 and extends beyond the surface of the protective layer 130 by 4-6 μm. By increasing the volume of graphene, a multi-layer graphene structure is formed, enhancing the stability and hydrophobicity of the bottom structure. Since graphene is a mesh and multi-layer graphene structure, the multi-layer graphene structure exhibits excellent hydrophobicity and stability. The base conductive layer 140 is designed at the bottom of the conductive pillars 160. During micro-etching processes, whether chemical etching or plasma etching is used, the base conductive layer 140 can avoid the undercutting problem that occurs when removing the UBM layer in traditional micro-etching processes. Furthermore, the coefficient of thermal expansion (CTE) of graphene is only 1 / 10 to 1 / 20 that of copper and aluminum, which can better prevent deformation of the UBM layer at the bottom of the conductive pillars 160, while also protecting the bonding pads 120 of the chip 110 and the bottom structure from stress. Furthermore, graphene's conductivity is 100 times higher than other metals. As the volume of graphene increases, forming a multi-layered graphene structure (possessing excellent stability), its thermal conductivity and electrical conductivity are further improved, solving the problem of poor heat dissipation and conductivity in the UBM layer at the bottom of the bumps in traditional technologies. Meanwhile, in conventional technologies, under current loading, the metal atoms at the bottom connection of the conductive pillar 160 are simultaneously affected by both electric and thermal fields due to the Joule heating effect. The abnormally active electromigration and thermal migration at the interconnect interface significantly reduce the lifespan of the conductive pillar 160, creating potential failure hazards. This technology effectively utilizes graphene's stability, high thermal conductivity, and high electrical conductivity to solve these problems. It also addresses the issue in traditional technologies where the conductive pillar 160 causes significant stress within the package, leading to damage to brittle material layers, such as cracking of the chip 110 pads at the bottom of the copper pillars, delamination of the UBM metal layer, or reduced solder joint fatigue life.

[0088] The bump encapsulation structure 100 provided in this embodiment adopts an arc-shaped bump structure for the adhesive layer 151, which allows the barrier layer 153 and the wetting layer 155 to be arc-shaped. This can improve the bonding force and the structural strength at the same time, and avoid the phenomenon that the metal layer is prone to breakage when subjected to mechanical force due to the thin wetting layer, barrier layer 153 and adhesive layer 151 in the traditional technology.

[0089] Second Embodiment

[0090] See Figure 9 and Figure 10 This embodiment provides a bump encapsulation structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0091] In this embodiment, at least a portion of the surface of the substrate conductive layer 140 away from the chip 110 is a convex arc surface, so that the substrate conductive layer 140 forms an arc-shaped bump structure. The adhesive layer 151 is disposed around the periphery of the substrate conductive layer 140, the barrier layer 153 covers the surfaces of the substrate conductive layer 140 and the adhesive layer 151, and the wetting layer 155 covers the surface of the barrier layer 153. Specifically, the substrate conductive layer 140 itself is designed to convex outward from the protective layer 130, and the convex portion is an outward arc shape. The adhesive layer 151, the barrier layer 153, and the wetting layer 155 cover the substrate conductive layer 140.

[0092] In this embodiment, the substrate conductive layer 140 is also a graphene layer. By employing a bump structure, the contact area can be increased, thereby improving the bonding force and structural strength. Furthermore, compared to the first embodiment, the graphene layer in this embodiment has a larger volume, resulting in better overall conductivity and heat dissipation.

[0093] In this embodiment, a receiving groove 157 is provided around the periphery of the substrate conductive layer 140, and an adhesive layer 151 is disposed within the receiving groove 157, with the thickness of the adhesive layer 151 being the same as the depth of the receiving groove 157. Specifically, the receiving groove 157 is located around the convex arc surface of the substrate conductive layer 140, thereby enabling the adhesive layer 151 to simultaneously contact the edge of the substrate conductive layer 140 and the edge of the barrier layer 153, improving their adhesion.

[0094] It is worth noting that in this embodiment, the depth of the receiving groove 157 is comparable to the thickness of the adhesive layer 151, allowing the adhesive layer 151 to be smoothly embedded on the edge of the substrate conductive layer 140. The barrier layer 153 simultaneously covers the outer convex arc surface of both the adhesive layer 151 and the substrate conductive layer 140, significantly improving its structural strength. Furthermore, in this embodiment, the adhesive layer 151 is a titanium layer, and the bump edge of the substrate conductive layer 140 is flattened, thereby generating titanium carbide (TiC) at the edge, further preventing undercutting. At the same time, placing the adhesive layer 151 within the receiving groove 157 reduces the overall thickness of the first conductive composite layer, thereby reducing the bump height.

[0095] Third Embodiment

[0096] See Figure 11This embodiment provides a bump encapsulation structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0097] In this embodiment, at least a portion of the surface of the substrate conductive layer 140 away from the chip 110 is a convex arc surface, so that the substrate conductive layer 140 forms an arc-shaped bump structure. The adhesive layer 151 covers the surface of the substrate conductive layer 140, the barrier layer 153 covers the surface of the adhesive layer 151, and the wetting layer 155 covers the surface of the barrier layer 153. Specifically, the substrate conductive layer 140 itself is designed to convex outward from the protective layer 130, and the convex portion is in the shape of a convex arc. The adhesive layer 151, the barrier layer 153, and the wetting layer 155 cover the substrate conductive layer 140.

[0098] In this embodiment, the adhesive layer 151 completely covers the surface of the substrate conductive layer 140, and the side of the adhesive layer 151 away from the chip 110 is a flat plane to planarize the barrier layer 153 and the wetting layer 155. Specifically, the adhesive layer 151 has an inverted concave structure, with one side of its surface adhering to the convex arc surface of the substrate conductive layer 140, and the other side of its surface being planar, so that both the barrier layer 153 and the wetting layer 155 are planar.

[0099] The bump encapsulation structure 100 provided in this embodiment has a multi-layer graphene structure for the substrate conductive layer 140 and a titanium layer for the adhesive layer 151. The substrate conductive layer 140 has an outwardly convex arc surface structure, which can increase the contact area between the adhesive layer 151 and the substrate conductive layer 140, thereby improving the bonding force. Furthermore, the arc surface is fully fitted, which can generate more titanium carbide (TiC), thereby improving the overall heat dissipation capacity and conductivity.

[0100] Fourth embodiment

[0101] See Figure 12 and Figure 13 This embodiment provides a bump encapsulation structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment, the second embodiment or the third embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding contents of the first embodiment, the second embodiment or the third embodiment.

[0102] In this embodiment, the substrate conductive layer 140 includes a first substrate layer 141, a second substrate layer 143, and a third substrate layer 145. The first substrate layer 141 is disposed within the protective opening 131, the second substrate layer 143 is disposed on the first substrate layer 141, and the third substrate layer 145 is disposed on the second substrate layer 143. The surface of the first substrate layer 141 away from the chip 110 is at least partially convex arc-shaped, the surface of the second substrate layer 143 away from the chip 110 is flat, and the surface of the third substrate layer 145 away from the chip 110 is at least partially convex arc-shaped. The first combined conductive layer 150 is disposed on the third substrate layer 145.

[0103] Specifically, in this embodiment, the first base layer 141 is provided to protrude outward from the protective opening 131, the second base layer 143 and the third base layer 145 are both located outside the protective opening 131, the second base layer 143 completely covers the first base layer 141, the third base layer 145 completely covers the second base layer 143, and the surface of the third base layer 145 away from the chip 110 is also convex arc-shaped.

[0104] It is worth noting that the adhesive layer 151 can completely cover the surface of the third base layer 145, and the side of the adhesive layer 151 away from the chip 110 is a flat plane, so as to planarize the barrier layer 153 and the wetting layer 155. Specifically, the adhesive layer 151 has an inverted concave structure, with one side of its surface adhering to the convex arc surface of the third base layer 145, and the other side of its surface being planar, so that both the barrier layer 153 and the wetting layer 155 are planar.

[0105] Alternatively, the adhesive layer 151 can also be disposed on the periphery of the third base layer 145. As disclosed in the second embodiment, a receiving groove 157 is formed on the periphery of the third base layer 145, and the adhesive layer 151 is disposed within the receiving groove 157. The thickness of the adhesive layer 151 is the same as the depth of the receiving groove 157. Then, a barrier layer 153 and a wetting layer 155 are formed on the adhesive layer 151 and the third base layer 145. The side of the barrier layer 153 away from the chip 110 can be a flat plane.

[0106] In this embodiment, both the first substrate layer 141 and the third substrate layer 145 comprise multilayer graphene structures, and the second substrate layer 143 comprises a titanium layer. Titanium carbide layers are formed at both interfaces of the second substrate layer 143. Specifically, the second substrate layer 143 is an intermediate layer, which is a titanium layer. The upper and lower third substrate layers 145 and the second substrate layer 143 are graphene layers. The adhesive layer 151 also uses a titanium layer, thereby generating a multilayer TiC structure, improving the structural bonding force, and further preventing undercutting.

[0107] The bump encapsulation structure 100 provided in this embodiment improves the overall conductivity, thermal conductivity and structural strength by interleaving multiple layers of titanium and graphene layers, and generates a multi-layered TiC structure, which enhances the bonding force of the overall structure and further prevents undercutting.

[0108] Fifth Embodiment

[0109] See Figure 14 This embodiment provides a bump encapsulation structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment, the second embodiment or the third embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding contents of the first embodiment, the second embodiment or the third embodiment.

[0110] In this embodiment, the substrate conductive layer 140 includes a first substrate layer 141, a second substrate layer 143, and a third substrate layer 145. The first substrate layer 141 is disposed within the protective opening 131, the second substrate layer 143 is disposed on the first substrate layer 141, and the third substrate layer 145 is disposed on the second substrate layer 143. The surface of the first substrate layer 141 away from the chip 110 is at least partially convex arc-shaped, the surface of the second substrate layer 143 away from the chip 110 is flat, and the surface of the third substrate layer 145 away from the chip 110 is at least partially convex arc-shaped. The first combined conductive layer 150 is disposed on the third substrate layer 145.

[0111] In this embodiment, the first combined conductive layer 150 is disposed on the third base layer 145. Specifically, the first combined conductive layer 150 may consist only of a barrier layer 153 and a wetting layer 155. The barrier layer 153 is disposed on the third base layer 145, and the wetting layer 155 is disposed on the barrier layer 153, with the barrier layer 153 completely covering the third base layer 145. Furthermore, the surface of the barrier layer 153 away from the chip 110 is flat, which allows the bottom of the wetting layer 155 and the conductive pillar 160 to be flattened.

[0112] It should be noted that in this embodiment, both the first substrate layer 141 and the third substrate layer 145 include titanium layers, and the second substrate layer 143 includes a multilayer graphene structure. Titanium carbide layers are formed at both interfaces of the second substrate layer 143. Specifically, the first substrate layer 141 and the third substrate layer 145 both serve to conduct electricity and adhere, while the second substrate layer 143 serves to improve conductivity and heat dissipation.

[0113] In this embodiment, the first base layer 141 is made of titanium and protrudes outward from the protective opening 131. The edge of the first base layer 141 completely covers the protective opening 131 and protrudes by 4-6 μm. The titanium layer covering the protective opening 131 is thicker than the traditional structure, which improves the bonding force between the bottom of the conductive post 160 and the solder pad 120. At the same time, the second base layer 143 is made of graphene, which can compensate for the poor conductivity and thermal conductivity of the titanium layer, ensuring sufficient heat dissipation and conductivity.

[0114] The bump encapsulation structure 100 provided in this embodiment has a first base layer 141, a second base layer 143 and a third base layer 145 stacked sequentially. The second base layer 143 is an intermediate layer, which adopts a multi-layer graphene structure. At the same time, the third base layer 145 on the upper and lower sides and the first base layer 141 are both titanium layers, thereby generating a TiC structure in the intermediate layer, which improves the structural bonding force and prevents undercutting.

[0115] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A bump encapsulation structure, characterized in that, include: A chip, wherein a solder pad is provided on one side of the chip; A protective layer is disposed on one side of the chip, and the protective layer has protective openings corresponding to the solder pads; It is disposed in the protective opening and covers the base conductive layer of the protective opening; A first combined conductive layer disposed on the substrate conductive layer; Conductive pillars disposed on the first combined conductive layer; And the solder cap disposed on the conductive post; The conductive substrate layer comprises a multilayer graphene structure. The height of the substrate conductive layer is greater than the depth of the protective opening, and a shielding portion is provided on the top of the substrate conductive layer. The shielding portion extends outward from the center of the protective opening to the surface of the protective layer and covers the edge of the protective opening. The shielding portion is integrally provided on the top edge of the substrate conductive layer, and the width of the shielding portion is between 4-10 μm. The conductive substrate layer includes a first substrate layer, a second substrate layer, and a third substrate layer. The first substrate layer is disposed within the protective opening, the second substrate layer is disposed on the first substrate layer, and the third substrate layer is disposed on the second substrate layer. At least a portion of the surface of the first substrate layer away from the chip is a convex arc surface, the surface of the second substrate layer away from the chip is a flat plane, and at least a portion of the surface of the third substrate layer away from the chip is a convex arc surface. The first combined conductive layer is disposed on the third substrate layer. Both the first substrate layer and the third substrate layer include a multilayer graphene structure, the second substrate layer includes a titanium layer, and titanium carbide layers are formed at both interfaces of the second substrate layer. Alternatively, both the first and third substrate layers may include titanium layers, the second substrate layer may include a multilayer graphene structure, and titanium carbide layers may be formed at both interfaces of the second substrate layer.

2. The bump encapsulation structure according to claim 1, characterized in that, The thickness of the shielding part is 4-8 μm.

3. The bump encapsulation structure according to claim 1, characterized in that, The first combined conductive layer includes an adhesive layer, a barrier layer, and a wetting layer. The adhesive layer is disposed on the side of the substrate conductive layer away from the chip. The barrier layer is disposed on the side of the adhesive layer away from the chip. The wetting layer is disposed on the side of the barrier layer away from the chip. The conductive pillar is disposed on the side of the wetting layer away from the chip. The adhesive layer is in contact with both the barrier layer and the substrate conductive layer to improve the adhesion between the barrier layer and the substrate conductive layer. The wetting layer is in contact with both the barrier layer and the conductive pillar to improve the wettability between the barrier layer and the conductive pillar.

4. The bump encapsulation structure according to claim 3, characterized in that, The surface of the substrate conductive layer away from the chip is a flat surface. The adhesive layer covers the surface of the substrate conductive layer, the barrier layer covers the surface of the substrate conductive layer, the wetting layer covers the surface of the barrier layer, and the surface of the adhesive layer away from the chip is at least partially convex arc-shaped, so that the adhesive layer forms an arc-shaped bump structure.

5. The bump encapsulation structure according to claim 3, characterized in that, The surface of the conductive substrate away from the chip is at least partially convex arc-shaped to form an arc-shaped bump structure. The adhesive layer is disposed around the periphery of the conductive substrate. The barrier layer covers the surfaces of the conductive substrate and the adhesive layer. The wetting layer covers the surface of the barrier layer.

6. The bump encapsulation structure according to claim 5, characterized in that, The peripheral edge of the conductive substrate layer is provided with a receiving groove, the adhesive layer is disposed in the receiving groove, and the thickness of the adhesive layer is the same as the depth of the receiving groove.

7. The bump encapsulation structure according to claim 3, characterized in that, The surface of the conductive substrate away from the chip is at least partially convex arc-shaped to form an arc-shaped bump structure. The adhesive layer covers the surface of the conductive substrate, the barrier layer covers the surface of the adhesive layer, and the wetting layer covers the surface of the barrier layer.

8. The bump encapsulation structure according to claim 7, characterized in that, The adhesive layer has a flat surface on the side away from the chip to planarize the barrier layer and the wetting layer.

9. The bump encapsulation structure according to claim 1, characterized in that, A second combined conductive layer is also provided on the side of the conductive post away from the chip, and the second combined conductive layer is disposed between the conductive post and the solder cap.

10. The bump encapsulation structure according to claim 9, characterized in that, The second combined conductive layer includes a first conductive layer and a second conductive layer. The first conductive layer covers the surface of the conductive pillar, the second conductive layer covers the first conductive layer, and the solder cap covers the second conductive layer. The second conductive layer is used to block atomic diffusion between the solder cap and the conductive pillar, and the first conductive layer is used to improve the adhesion between the second conductive layer and the conductive pillar.

11. The bump encapsulation structure according to claim 10, characterized in that, The conductive post has at least a convex arc surface on the side of its surface away from the chip, so that the conductive post forms an arc-shaped bump structure.

12. A method for fabricating a bump encapsulation structure, used to fabricate the bump encapsulation structure as described in any one of claims 1-11, characterized in that, The preparation method includes: Provide a chip with solder pads; A protective layer is formed on the side of the chip with solder pads; Grooves are cut into the protective layer to form protective openings corresponding to the solder pads; A substrate conductive layer is formed in the protective opening; A first combined conductive layer is formed on the substrate conductive layer; Conductive pillars are formed on the first combined conductive layer; A solder cap is formed on the conductive post; The conductive substrate layer comprises a multilayer graphene structure.

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