Method for bonding a semiconductor device

Abstract

The method includes: determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer with a third alignment mark on a first side of a second wafer, including detecting the position of the second alignment mark of the first wafer; determining the position of the first alignment mark of the first wafer based on the first offset and the position of the second alignment mark of the first wafer; and repositioning the first wafer based on the determined position of the first alignment mark to align the first alignment mark with the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure. Embodiments of the present invention also relate to a method for bonding semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for bonding semiconductor devices. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the increase in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. With the growing demand for smaller electronic devices, there is a need for smaller and more innovative packaging technologies for semiconductor chips. For example, many integrated circuits can be fabricated on a single semiconductor wafer. The chips of the wafer can be processed and packaged at the wafer level, and various technologies for wafer-level packaging have been developed. Summary of the Invention

[0003] Embodiments of the present invention provide a method for bonding semiconductor devices, including: determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer with a third alignment mark on a first side of a second wafer, including: detecting the position of the second alignment mark of the first wafer; determining the position of the first alignment mark of the first wafer based on the first offset and the position of the second alignment mark of the first wafer; and repositioning the first wafer based on the determined position of the first alignment mark to align the first alignment mark with the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonding structure.

[0004] Another embodiment of the present invention provides a method for bonding semiconductor devices, including: positioning a first semiconductor device above a second semiconductor device, wherein a front side of the first semiconductor device faces a front side of the second semiconductor device, wherein the front side of the first semiconductor device includes a first alignment component, and the front side of the second semiconductor device includes a second alignment component; detecting a position of the second alignment component using a first microscope, wherein the first microscope faces the front side of the second semiconductor device; after detecting the position of the second alignment component using the first microscope, forming a third alignment component on a back side of the second semiconductor device using a first marking tool, wherein a position of the third alignment component is based on the position of the second alignment component; detecting a position of the first alignment component using a second microscope, wherein the second microscope faces the front side of the first semiconductor device; after detecting the position of the first alignment component using the second microscope, forming a fourth alignment component on a back side of the first semiconductor device using a second marking tool, wherein a position of the fourth alignment component is based on the position of the first alignment component; repositioning the first semiconductor device and the second semiconductor device to align the first alignment component with the second alignment component, wherein the repositioning is based on the position of the third alignment component and the position of the fourth alignment component; and bonding the first semiconductor device to the second semiconductor device.

[0005] Yet another embodiment of the present invention provides a method for bonding semiconductor devices, including: placing a first device wafer on an upper holder, wherein the first device wafer includes: a first front-side alignment mark; a first back-side alignment mark; a first interconnect structure; a first surface dielectric layer located above the first interconnect structure; and a first contact pad located in the first surface dielectric layer, wherein the first contact pad is connected to the first interconnect structure; placing a second device wafer on a lower holder, wherein the second device wafer includes: a second front-side alignment mark; a second back-side alignment mark; a second interconnect structure; a second surface dielectric layer located above the second interconnect structure; and a second contact pad located in the second surface dielectric layer, wherein the second contact pad is connected to the second interconnect structure; detecting positions of the first front-side alignment mark and the second back-side alignment mark using a lower microscope; detecting positions of the second front-side alignment mark and the first back-side alignment mark using an upper microscope; determining a first alignment offset between the first front-side alignment mark and the second front-side alignment mark based on positions of the first back-side alignment mark and the second back-side alignment mark; aligning the first front-side alignment mark with the second front-side alignment mark based on the first alignment offset; and bonding the first contact pad to the second contact pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view of an integrated circuit die in accordance with some embodiments is shown.

[0008] Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 Cross-sectional views of intermediate steps during a process for forming a bonding structure in accordance with some embodiments are shown.

[0009] Figure 8 and Figure 9 Cross-sectional views of intermediate steps during a process for forming a bonding structure in accordance with some embodiments are shown.

[0010] Figure 10 、 Figure 11 and Figure 12 Cross-sectional views of intermediate steps during a process for forming a bonding structure in accordance with some embodiments are shown.

[0011] Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 and Figure 19 Cross-sectional views of intermediate steps during a process for forming a bonding structure in accordance with some embodiments are shown.

[0012] Figure 20 and Figure 21 Cross-sectional views of intermediate steps during a process for forming a bonding structure in accordance with some embodiments are shown.

[0013] Figure 22 、 Figure 23 and Figure 24 Cross-sectional views of intermediate steps during a process for forming a bonding structure in accordance with some embodiments are shown.

[0014] Figure 25 A process flow for forming a bonding structure in accordance with some embodiments is shown.

[0015] Figure 26Shows a process flow for forming a bonding structure according to some embodiments. Detailed Description

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0018] A bonding structure and a method of manufacturing a bonding structure are provided according to various exemplary embodiments. In some embodiments, the bonding structure may be a semiconductor package or the like formed by bonding a first bonding component to a second bonding component using direct bonding or the like. The bonding components may be wafers, chips, dies, substrates, etc. Alignment marks may be formed on the front side and the back side of the bonding components, and a spatial offset is determined between the alignment marks on the front side and the alignment marks on the back side. This offset allows the position of the front-side alignment marks to be determined by detecting the position of the back-side alignment marks. In this way, the position of the front-side alignment marks can be determined even when the front-side alignment marks are not directly visible. In this way, the bonding components can be aligned based on their front-side alignment marks, which can improve alignment. Additionally, the use of a predetermined offset allows any misalignment of the front-side alignment marks to be measured after bonding by detecting the relative position of the back-side alignment marks. This can improve the efficiency of identifying bonding structures that are aligned within tolerances.

[0019] Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that although the formation of the bonding structure is used as an example to illustrate the concepts of the embodiments of the present invention, the embodiments of the present invention are readily applicable to packaging structures and packaging methods, where an offset between alignment marks on both sides of a bonding component can be used during alignment.

[0020] Figure 1 A cross-sectional view of a semiconductor device 50 according to some embodiments is shown. The semiconductor device 50 can be, for example, an integrated circuit die, a CMOS die, a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an input / output (IO), a baseband (BB), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. In some cases, the semiconductor device 50 can be considered a packaging component, etc. The semiconductor device 50 can be similar to the semiconductor devices 410A - 410B described below for Figure 20 description.

[0021] In some embodiments, the semiconductor device 50 can be formed in a wafer. For example, the wafer can be a semiconductor substrate, a device wafer, an interposer wafer, a packaging substrate, etc. Although Figure 1 only one semiconductor device 50 is shown, it should be understood that the wafer can include multiple semiconductor devices 50, and the multiple semiconductor devices 50 can be separated from each other by scribe regions. For example, the wafer can include different device regions that are divided in subsequent steps to form multiple semiconductor devices 50. In this way, Figure 1 the semiconductor device 50 shown in can be a part of the wafer, etc.

[0022] The semiconductor device 50 can be processed according to applicable manufacturing processes, such as those used to form integrated circuits. For example, the semiconductor device 50 includes a semiconductor substrate 52, which can be a wafer. The semiconductor substrate 52 can be a semiconductor material, such as doped or undoped silicon, the active layer of a semiconductor-on-insulator (SOI) substrate, the active layer of a semiconductor-on-sapphire substrate, etc. The semiconductor substrate 52 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates can also be used, such as multi-layer or gradient substrates. The semiconductor substrate 52 has an active surface (e.g., Figure 1 the upward-facing surface in Figure 1 ), sometimes referred to as the front side, and a non-active surface (e.g.,

[0023] the downward-facing surface in Figure 1 ), sometimes referred to as the back side.

[0024] The device 54 (represented by the Figure 1 transistors in

[0024] ) can be formed at the front surface of the semiconductor substrate 52. The device 54 can be, for example, an integrated circuit device, etc., including active devices and / or passive devices. The device 54 can include one or more active devices, such as diodes, photodiodes, fuse devices, complementary metal-oxide-semiconductor (CMOS) transistors, fin field-effect transistors (FinFETs), nanostructure (e.g., nanosheets, nanowires, all-around-gate, etc.) field-effect transistors (NSFETs), etc., or combinations thereof. The device 54 can include one or more passive devices, such as capacitors, resistors, inductors, etc., or combinations thereof. In some embodiments, the semiconductor device 50 does not have active devices. In other embodiments, the semiconductor device 50 does not have passive devices.An interlayer dielectric (ILD) 56 is located above the front surface of a semiconductor substrate 52. The ILD 56 surrounds and may cover the device 54. The ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), undoped silicate glass (USG), etc. In some embodiments, the ILD 56 may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc. A conductive plug 58 extends at least partially through the ILD 56 to electrically couple and physically couple to the device 54. For example, when the device 54 is a transistor, the conductive plug 58 may couple to the gate and / or source / drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof.

[0025] In some embodiments, an interconnect structure 60 is formed above the ILD 56 and the conductive plug 58. The interconnect structure 60 interconnects the devices 54 to form an integrated circuit and may include, for example, one or more metallization patterns in one or more dielectric layers located on the ILD 56. In some embodiments, the dielectric layer may be an intermetal dielectric (IMD), and the one or more dielectric layers may be formed of a low-k dielectric material. For example, the dielectric layer may be formed of Black (a registered trademark of Applied Materials, Inc.), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present invention, some or all of the dielectric layers are formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), etc.

[0026] The metallization pattern of the interconnect structure 60 is electrically coupled to the device 54 through the conductive plug 58. The metallization pattern of the interconnect structure 60 may include conductive components that are interconnected with each other and embedded in one or more dielectric layers. The conductive components may include multi-layer wires, conductive vias, and / or conductive contacts. Conductive vias may be formed in the dielectric layer to electrically connect wires in different layers. The conductive components of the metallization pattern may be formed of one or more metals, metal alloys, or a combination thereof. For example, the conductive components may include copper, copper alloy, aluminum, aluminum alloy, tantalum, TaN, titanium, TiN, cobalt, tungsten, CoW, ruthenium, etc. or a combination thereof. In some embodiments, some of the conductive components may include pads. The pads may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof. In some embodiments, the topmost conductive component of the metallization pattern has a top surface that is substantially coplanar (e.g., within process variations) with the top surface of the dielectric structure.

[0027] In some embodiments, semiconductor device 50 further includes a conductive pad 62, such as a metal pad, for making external connections. In some embodiments, conductive pad 62 may be a conductive component of interconnect structure 60. In some embodiments, conductive pad 62 may be formed in surface dielectric layer 64 above interconnect structure 60. Surface dielectric layer 64 may be formed at the surface of semiconductor device 50. In some embodiments, surface dielectric layer 64 is a silicon-containing dielectric layer, which may include silicon oxide, silicon oxynitride, silicon nitride, etc., but other materials are possible. The material of surface dielectric layer 64 may be selected to facilitate bonding at surface dielectric layer 64 to form a bonding structure, such as bonding structure 150 shown in more detail below Figures 6 to 7 The bonding structure 150 shown in. For example, the bonding may be a bonding process including dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). Conductive pad 62 may be formed using suitable techniques, such as using damascene process, dual damascene process, etc. In some embodiments, conductive pad 62 has a top surface that is substantially coplanar with the top surface of surface dielectric layer 64.

[0028] In some embodiments, semiconductor device 50 includes a front-side alignment mark 70 and / or a back-side alignment mark 72 (collectively referred to herein as "alignment marks 70 / 72"). Alignment marks 70 / 72 may provide features for alignment during bonding, lithographic processing, device testing, inspection, measurement, etc. For example, alignment marks 70 / 72 may allow alignment of semiconductor device 50 during a bonding process, such as one or more of the bonding processes described below for Figures 2 to 7 described. Front-side alignment mark 70 may be formed at or near the front side of semiconductor device 50, and back-side alignment mark 72 may be formed at or near the back side of semiconductor device 50. In some embodiments, front-side alignment mark 70 is a dummy structure that is electrically isolated from interconnect structure 60 or conductive pad 62. In some embodiments, front-side alignment mark 70 is electrically coupled to interconnect structure 60 or conductive pad 62. In some embodiments, alignment marks 70 / 72 may be grounded. Alignment marks 70 / 72 may include, for example, optical alignment marks, scanning electron microscope (SEM) marks, laser marks, or other types of alignment marks.

[0029] In some embodiments, alignment marks 70 / 72 may be formed in one or more semiconductor devices 50 on the same wafer. Figure 1Shown are a front-side alignment mark 70 and a back-side alignment mark 72 formed in the semiconductor device 50, but in other embodiments, one or more front-side alignment marks 70 and / or back-side alignment marks 72 are formed in the scribe region. In some embodiments, the front-side alignment mark 70 is formed before performing the bonding process, and as part of the bonding process, the back-side alignment mark 72 is formed, which is described in more detail below for Figures 13 to 19 In Figure 1 , the front-side alignment mark 70 is shown as being formed in the surface dielectric layer 64, and the back-side alignment mark 72 is shown as being formed in the semiconductor substrate 52, but the alignment marks 70 / 72 can be formed in any suitable layer of the semiconductor device 50, such as the dielectric layer of the interconnect structure 60, the ILD 56, etc.

[0030] The alignment marks 70 / 72 can be formed using suitable techniques, such as using a laser drilling process, using a lithography and etching process, etc. For example, a lithography and etching process can be used to pattern openings in the layer corresponding to the alignment marks 70 / 72, and then one or more materials (e.g., dielectric, conductive material, etc.) can be deposited in the openings to form the alignment marks 70 / 72. In other embodiments, the alignment marks 70 / 72 are unfilled openings or grooves. In some embodiments, the alignment marks 70 / 72 are formed using one or more of the same processing steps used to form the components of the semiconductor device 50. For example, the alignment marks 70 / 72 can be formed of a conductive material using the same processing steps as those used to form the conductive pads 62 or the metallization pattern of the interconnect structure 60. The alignment marks 70 / 72 can be formed using other processing steps different from these examples. In some embodiments, the front-side alignment mark 70 can be formed using a technique different from that of the back-side alignment mark 72. Other techniques for forming the alignment marks 70 / 72 are possible and are considered to be within the scope of the present invention.

[0031] Figures 2 to 7 Shown is a schematic diagram of a bonding system 100 and a bonding process for forming a bonding structure 150 (see Figures 6 to 7 ) according to some embodiments. For example, the bonding process can be used to form a bonding structure 150 by bonding a first semiconductor device 110A to a second semiconductor device 110B. The first semiconductor device 110A and the second semiconductor device 110B (collectively referred to herein as "semiconductor devices 110A-110B") can be, for example, integrated circuit dies, wafers, packaged components, etc., and are described in more detail below. In some embodiments, one or both of the semiconductor devices 110A-110B are similar to those for Figure 1The described semiconductor device 50. The bonding structure 150 can be, for example, a package, a system-on-chip (SoC), a system-on-integrated circuit (SoIC), a three-dimensional integrated circuit (3DIC), etc. In some embodiments, the bonding structure 150 can subsequently be divided to form separate packages, etc.

[0032] Figure 2 A schematic diagram of a bonding system 100 according to some embodiments is shown. The bonding system 100 can be used to bond wafers, devices, package components, etc. using bonding techniques such as silicon-on-silicon bonding, direct bonding, semiconductor-on-insulator (SOI) bonding, fusion bonding (e.g., hydrophilic bonding or hydrophobic bonding), hybrid bonding, etc. The bonding system 100 can be used, for example, to perform a bonding process that bonds a first semiconductor device 110A and a second semiconductor device 110B to form a bonding structure 150. Figures 2 to 7 The bonding system 100 shown in is a representative example of a bonding system for illustrating a bonding process, and the techniques described in the present invention should not be considered limited to any particular type of bonding system or bonding structure.

[0033] In some embodiments, the bonding system 100 includes a first holder 120A, a second holder 120B, a first microscope 130A, a second microscope 130B, and a controller 140. The first holder 120A and the second holder 120B (collectively referred to herein as "holders 120A-120B") can be chucks, supports, worktables, etc. configured to hold the semiconductor devices 110A-110B during the bonding process. For example, the first holder 120A can hold the first semiconductor device 110A, and the second holder 120B can hold the second semiconductor device 110B. As Figure 2 shown, in some embodiments, the second holder 120B can be located generally above the first holder 120A, and in this way, the first holder 120A can be considered the lower holder, and the second holder 120B can be considered the upper holder.

[0034] The retainers 120A - 120B may include actuators that allow adjustment of the position of the semiconductor devices 110A - 110B. For example, the retainers 120A - 120B may adjust their positions along the x - axis, y - axis, and / or z - axis or may adjust the orientation, rotation angle, tilt angle, etc. For example, the actuator of the first retainer 120A may adjust the position of the first semiconductor device 110A, and the actuator of the second retainer 120B may adjust the position of the second semiconductor device 110B. The positions of the first semiconductor device 110A and the second semiconductor device 110B may be adjusted relative to each other or relative to a reference position. For example, the semiconductor devices 110A - 110B may be moved to positions corresponding to specific (x, y, z) coordinates. The actuators may include, for example, stepper motors, piezoelectric motors, linear motors, another type of motor, etc.

[0035] In some embodiments, the first microscope 130A and the second microscope 130B of the bonding system 100 (collectively referred to herein as "microscopes 130A - 130B") may be configured to detect or image alignment marks (e.g., alignment marks 70A - 70B or 72A - 72B, described below) of the semiconductor devices 110A - 110B. As Figure 2 shown, the first microscope 130A may be located on one side of the semiconductor devices 110A - 110B, and the second microscope 130B may be located on the opposite side of the semiconductor devices 110A - 110B. For example, the first microscope 130A may be located below the first semiconductor device 110A, and the second microscope 130B may be located above the second semiconductor device 110B. In some embodiments, in this way, the first microscope 130A may be considered the lower microscope, and the second microscope 130B may be considered the upper microscope. The microscopes 130A - 130B may include optical microscopes, infrared microscopes, scanning electron microscopes (SEM), etc. In some embodiments, the microscopes 130A - 130B may be configured to generate digital images. In some embodiments, the microscopes 130A - 130B may include actuators configured to adjust the position of the microscopes 130A - 130B. For example, the microscopes 130A - 130B may be adjusted along the x - axis, y - axis, or z - axis, or the microscopes 130A - 130B may be moved to positions corresponding to specific (x, y, z) coordinates.

[0036] In some embodiments, the bonding system 100 includes a controller 140 that is communicatively coupled to a first holder 120A, a second holder 120B, a first microscope 130A, and a second microscope 130B. The controller 140 may be configured to send signals to these coupled components and may be configured to receive signals from these coupled components. For example, in some embodiments, the controller 140 may send a signal to one of the holders 120A-120B that instructs the holder to adjust its position. In some embodiments, the controller 140 is configured to receive a signal indicating position from one of the holders 120A-120B. In some embodiments, the controller 140 is configured to store the positions received from the holders 120A-120B and subsequently send a signal that instructs the holders 120A-120B to move to the stored positions. In some embodiments, the controller 140 may send signals to the microscopes 130A-130B to control their operations, such as focusing, position adjustment, image capture, etc. In some embodiments, the controller 140 may receive signals corresponding to, for example, captured images, detection of alignment marks, positions, etc., from one of the microscopes 130A-130B.

[0037] Reference Figure 2 , one or both of the semiconductor devices 110A-110B may be similar to the semiconductor device 50 described for Figure 1 . For example, the first semiconductor device 110A and / or the second semiconductor device 110B may be an integrated circuit die (divided or undivided), a wafer, a packaged component, etc. In some embodiments, the first semiconductor device 110A may be a different type of device than the second semiconductor device 110B. For example, in some embodiments, one of the semiconductor devices 110A-110B may be a digital circuit die and the other may be an analog circuit die. In other embodiments, the first semiconductor device 110A may include a logic die while the second semiconductor device 110B may include a memory die. These are examples, and other combinations of device types are possible. One or both of the semiconductor devices 110A-110B may be similar to the semiconductor devices 410A-410B (see Figure 20 ), the semiconductor device 510 (see Figure 22 ) or the substrate 511 (see Figure 22 ). Partitioning the functions and circuitry of the bonding structure 150 into different semiconductor devices may improve device operation, increase manufacturing efficiency, or reduce manufacturing costs.

[0038] In some embodiments, the semiconductor devices 110A-110B may include Figure 1Those similar components as described for the semiconductor device 50 shown. For example, in some embodiments, the first semiconductor device 110A may have a surface dielectric layer 64A and a conductive pad 62A formed on the front side, and the second semiconductor device 110B may have a surface dielectric layer 64B and a conductive pad 62B formed on the front side. The surface dielectric layers 64A - 64B and the conductive pads 62A - 62B may be similar to the surface dielectric layer 64 and the conductive pad 62 described for the semiconductor device 50. In some embodiments, the first semiconductor device 110A may have a semiconductor substrate 52A, and the second semiconductor device 110B may have a semiconductor substrate 52B. The semiconductor substrates 52A - 52B may be similar to the semiconductor substrate 50 described for the semiconductor device 50. In some embodiments, the first semiconductor device 110A may have one or more front - side alignment marks 70A and may have one or more back - side alignment marks 72A, and the second semiconductor device 110B may have one or more front - side alignment marks 70B and may have one or more back - side alignment marks 72B. In some embodiments, the front - side alignment marks 70A - 70B and the back - side alignment marks 72A - 72B may be similar to the alignment marks 70 / 72 of the semiconductor device 50. For clarity, the semiconductor devices 110A - 110B in other figures may not be shown Figure 1 Some components of the semiconductor device 50 shown in

[0039] In some embodiments, the semiconductor devices 110A - 110B may be placed in the bonding system 100 such that the back side of the first semiconductor device 110A faces the first microscope 130A, and the back side of the second semiconductor device 110B faces the second microscope 130B. In this way, the front side of the first semiconductor device 110A is bonded to the front side of the second semiconductor device 110B. In other embodiments, the front side of the first semiconductor device 110A may face the first microscope 130A, and / or the front side of the second semiconductor device 110B may face the second microscope 130B.

[0040] Figures 3A to 7 Intermediate steps of bonding the first semiconductor device 110A to the second semiconductor device 110B to form a bonding structure 150 according to some embodiments are shown. Figures 3A to 7 Some of the steps shown in correspond to the steps of the process flow 600 shown below Figure 25 shown in

[0041] In Figure 3A the first microscope 130A detects the position of the back - side alignment mark 72A of the first semiconductor device 110A, and the second microscope 130B detects the position of the front - side alignment mark 70A of the first semiconductor device 110A. This corresponds to Figure 25Steps 602 and 604 of the process flow 600 shown in. In some embodiments, the second semiconductor device 110B can be retracted by the second holder 120B to allow the second microscope 130B to detect the front-side alignment mark 70A without being blocked by the second semiconductor device 110B, as Figure 3A shown. The position of the alignment marks 70A / 72A can correspond to, for example, (x, y, z) coordinates, the position of the holders 120A-120B, the position of the microscopes 130A-130B (e.g., when the alignment marks 70A / 72A are being detected or imaged), etc. The position of the alignment marks 70A / 72A can be an absolute position or can be a position relative to another position. In some cases, the position of the alignment marks 70A / 72A can be determined at least in part based on the position of the first holder 120A, the position of the first microscope 130A, and / or the position of the second microscope 130B. In some embodiments, the controller 140 determines the position of the alignment marks 70A / 72A based on signals received from the first holder 120A, the first microscope 130A, and / or the second microscope 130B. In some embodiments, as Figures 8 to 9 described in more detail, the position of device components at or near the front side of the first semiconductor device 110A is detected, rather than the position of the front-side alignment mark 70A.

[0042] In some embodiments, a first offset 80A is determined between the position of the front-side alignment mark 70A and the position of the back-side alignment mark 72A of the first semiconductor device 110A. This corresponds to Figure 25 step 606 of the process flow 600 shown in. The first offset 80A can correspond to the difference between the detected position of the front-side alignment mark 70A and the detected position of the back-side alignment mark 72A. For example, the first offset 80A can indicate the position of the front-side alignment mark 70A relative to the back-side alignment mark 72A, or indicate the position of the back-side alignment mark 72A relative to the front-side alignment mark 70A.

[0043] Figure 3B shows an enlarged portion of the first semiconductor device 110A according to some embodiments, and shows a schematic representation of the first offset 80A between the front-side alignment mark 70A and the back-side alignment mark 72A. As Figure 3B shown, the first offset 80A represents the positional difference between the front-side alignment mark 70A and the back-side alignment mark 72A. The first offset 80A can be represented as a vector, differential (x, y, z) coordinates, etc. For example, the first offset 80A can be represented as (Δx, Δy, Δz), where Δx represents the difference along the x-axis, Δy represents the difference along the y-axis, and Δz represents the difference along the z-axis. In this way, the first offset 80A can include a lateral offset (Δx, Δy) and / or a vertical offset (Δz).

[0044] Since the first offset 80A represents the relative position of the alignment marks 70A / 72A, the position of one of the alignment marks 70A / 72A can be determined from the other of the alignment marks 70A / 72A and the first offset 80A. As an example, if the position of the dorsal alignment mark 72A is detected at coordinates (x, y, z) and the first offset 80A is determined to be (Δx, Δy, Δz), then the position of the ventral alignment mark 70A can be determined at coordinates (x + Δx, y + Δy, z + Δz). This is an illustrative example, and in other embodiments, the first offset 80A can be represented in a different manner, or the position of the alignment marks 70A / 72A can be determined in a different manner. Accordingly, the position of the ventral alignment mark 70A can be determined from the detected position of the dorsal alignment mark 72A and the predetermined first offset 80A. Similarly, the position of the dorsal alignment mark 72A can be determined from the detected position of the ventral alignment mark 70A and the predetermined first offset 80A. In some embodiments, the first offset 80A or the position of the alignment marks 70A / 72A can be determined by the controller 140.

[0045] In Figure 4 this, the first microscope 130A detects the position of the ventral alignment mark 70B of the second semiconductor device 110B, and the second microscope 130B detects the position of the dorsal alignment mark 72B of the second semiconductor device 110B. This corresponds to Figure 25 steps 608 and 610 of the process flow 600 shown in Figure 4 this. In some embodiments, as shown in Figure 25 this, the first semiconductor device 110A can be retracted by the first holder 120A to allow the first microscope 130A to detect the ventral alignment mark 70B without being blocked by the first semiconductor device 110A. In some embodiments, a second offset 80B between the ventral alignment mark 70B and the dorsal alignment mark 72B is determined based on the detected positions of the alignment marks 70B / 72B. This corresponds to Figures 8 to 9 step 612 of the process flow 600 shown in

[0046] In Figure 5In accordance with some embodiments, the first semiconductor device 110A and the second semiconductor device 110B are aligned for subsequent bonding. This corresponds to Figure 25 step 614 of the process flow 600 shown in Figure 25 . In some embodiments, the semiconductor devices 110A-110B are aligned by aligning the front-side alignment marks 70A-70B. For example, the semiconductor devices 110A-110B can be aligned such that the front-side alignment mark 70A of the first semiconductor device 110A is aligned with the corresponding front-side alignment mark 70B of the second semiconductor device 110B. In some embodiments, the semiconductor devices 110A-110B are aligned such that the conductive pads 62A of the first semiconductor device 110A are aligned with the corresponding conductive pads 62B of the second semiconductor device 110B. In some cases, aligning the front-side alignment marks 70A-70B can result in the alignment of the conductive pads 62A-62B. As described in more detail below, the front-side alignment marks 70A-70B can be aligned using the first offset 80A and the second offset 80B.

[0047] The alignment of the semiconductor devices 110A-110B includes controlling the holders 120A-120B to adjust the positions of the semiconductor devices 110A-110B. For example, the controller 140 can send signals to the holders 120A-120B that instruct the holders 120A-120B to move the semiconductor devices 110A-110B to a specific position. One or both of the semiconductor devices 110A-110B can be repositioned during the alignment process. In some cases, the first semiconductor device 110A can be held substantially stationary (e.g., in a fixed position), while the second semiconductor device 110B is moved into alignment, and in other cases, the second semiconductor device 110B can be held substantially stationary, while the first semiconductor device 110A is moved into alignment. In some cases, the semiconductor devices 110A-110B move (e.g., continuously or intermittently) during the alignment process.

[0048] In some embodiments, the semiconductor devices 110A - 110B are aligned by determining the positions of the front - side alignment marks 70A - 70B based on the positions of the back - side alignment marks 72A - 72B. For example, during alignment, the positions of the back - side alignment marks 72A - 72B can be detected (e.g., once, periodically, or continuously) by microscopes 130A - 130B, and using the offsets 80A - 80B, the positions of the front - side alignment marks 70A - 70B can be determined as described above. In this way, the position of the front - side alignment mark 70A can be determined from the detected position of the back - side alignment mark 72A, and the position of the front - side alignment mark 70B can be determined from the detected position of the back - side alignment mark 72B. Then, the semiconductor devices 110A - 110B can be re - positioned based on the detected positions of the back - side alignment marks 72A - 72B such that the front - side alignment marks 70A - 70B are aligned. In other words, the front - side alignment marks 70A - 70B can be aligned by re - positioning the semiconductor devices 110A - 110B such that the back - side alignment marks 72A - 72B are located at positions corresponding to alignment with the front - side alignment marks 70A - 70B.

[0049] By aligning the front - side alignment marks 70A - 70B using the detected positions of the back - side alignment marks 72 as described herein, the alignment of the semiconductor devices 110A - 110B can be improved during the fabrication of the bonding structure 150 (see Figures 6 to 7 ). For example, the overlay offset between the semiconductor devices 110A - 110B can be reduced. In some cases, the techniques described herein may allow alignment tolerances within about ±100 nm. Other tolerances (including smaller tolerances) are possible. In this way, due to the improved bonding, the techniques described herein can allow improved yield and device performance.

[0050] Turning to Figure 6 , according to some embodiments, a bonding process is performed to bond the second semiconductor device 110B to the first semiconductor device 110A. This corresponds to Figure 25Step 616 of the process flow 600 shown in. The bonding process can be, for example, chip-to-chip bonding, wafer-to-wafer bonding, chip-to-wafer bonding, substrate-to-substrate bonding, or other types of bonding processes. In some embodiments, the bonding process can include metal-to-metal bonding, such as metal-to-metal direct bonding, copper-to-copper bonding, etc. For example, the conductive pad 62A of the first semiconductor device 110A can be bonded to the corresponding conductive pad 62B of the second semiconductor device 110B. In some embodiments, the bonding process can include direct surface bonding, such as fusion bonding, dielectric-to-dielectric bonding, oxide-to-oxide bonding, substrate-to-substrate bonding, non-metal-to-non-metal bonding, polymer-to-polymer bonding, flexible substrate-to-flexible substrate bonding, etc. For example, the surface dielectric layer 64A of the first semiconductor device 110A can be bonded to the surface dielectric layer 64B of the second semiconductor device 110B. In some embodiments, the bonding process is a hybrid bonding process that includes at least two types of bonding, such as metal-to-metal bonding and non-metal-to-non-metal bonding, etc. For example, the surface dielectric layers 64A-64B can be bonded together, and the conductive pads 62A-62B can be bonded together.

[0051] In some embodiments, before performing the bonding process, a surface treatment is performed on the first semiconductor device 110A and / or the second semiconductor device 110B. In some embodiments, the surface treatment includes performing an activation process on the bonding surfaces of the semiconductor devices 110A-110B (e.g., the surface dielectric layers 64A-64B and / or the conductive pads 62A-62B). The activation process can include, for example, dry treatment, wet treatment, plasma treatment, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, etc., or a combination thereof. However, any suitable activation process can be utilized. After the activation process, the first semiconductor device 110A and / or the second semiconductor device 110B can be cleaned using, for example, a chemical rinse.

[0052] Once aligned, the first semiconductor device 110A and the second semiconductor device 110B are brought into contact using the first retainer 120A and / or the second retainer 120B. In some embodiments, as the semiconductor devices 110A - 110B come into contact, the microscopes 130A - 130B continuously or repeatedly detect the positions of the backside alignment marks 72A - 72B, and the positions of the semiconductor devices 110A - 110B can be adjusted based on the detected positions of the backside alignment marks 72A - 72B. In this way, the alignment of the semiconductor devices 110A - 110B can be monitored and adjusted during the bonding process to reduce overlay shift and improve yield. For example, by monitoring the alignment of the semiconductor devices 110A - 110B, offsets caused by movement of the retainers 120A - 120B can be detected, and the semiconductor devices 110A - 110B can be repositioned to correct for the movement. This can improve the alignment of the semiconductor devices 110A - 110B during the bonding process.

[0053] In some embodiments, the semiconductor devices 110A - 110B can then be subjected to heat treatment and / or pressed against each other (e.g., by applying contact pressure). For example, the semiconductor devices 110A - 110B can be subjected to a pressure of about 200 kPa or less and a temperature between about 200°C and about 400°C. The semiconductor devices 110A - 110B can then be subjected to a temperature equal to or higher than the eutectic point of the material of the conductive pads 62A - 62B (e.g., between about 150°C and about 650°C) to melt the conductive pad 62A. In this way, dielectric - to - dielectric bonding and / or metal - to - metal bonding of the semiconductor devices 110A - 110B forms the bonding structure 150. In some embodiments, the bonding structure 150 is baked, annealed, pressed, or otherwise treated to strengthen or complete the bond.

[0054] In some embodiments, after performing the bonding process, the alignment of the semiconductor devices 110A - 110B of the bonding structure 150 can be measured using the bonding system 100. This corresponds to Figure 25Optional step 618 of the illustrated process flow 600. For example, the bonding structure 150 can be inspected to measure any misalignment or overlay offset of the semiconductor devices 110A-110B. In some embodiments, the positions of the backside alignment marks 72A-72B on the bonding structure 150 can be measured by microscopes 130A-130B, and the misalignment can be determined from the relative positions of the backside alignment marks 72A-72B. For example, the positions of the frontside alignment marks 70A-70B within the bonding structure 150 can be determined from the measured positions of the backside alignment marks 72A-72B, and the misalignment of the semiconductor devices 110A-110B can be determined from the misalignment of the frontside alignment marks 70A-70B. Other techniques are possible. In some embodiments, by measuring alignment after forming the bonding structure 150, good devices can be identified with higher efficiency. For example, after measuring the misalignment, the bonding structure 150 or a portion of the bonding structure 150 (e.g., the area to be diced) within the alignment tolerance can then be processed or tested. This can reduce the amount of additional testing or inspection performed to identify known good dies (KGDs), good bonding structures 150, etc. Identifying good devices more efficiently can reduce manufacturing time and manufacturing cost.

[0055] Figure 7 A cross-sectional view of a bonding structure 150 according to some embodiments is shown. The bonding structure 150 can subsequently be processed using suitable techniques. For example, in some embodiments, a dicing process can be performed to dice the multiple devices formed in the bonding structure 150 into individual devices. The dicing process can include a sawing process, a laser process, etc.

[0056] Figure 8 and Figure 9 An intermediate step of bonding semiconductor devices 210A-210B to form a bonding structure 250 according to some embodiments is shown. Figure 8 A first semiconductor device 210A and a second semiconductor device 210B in a bonding system 100 according to some embodiments are shown. The bonding system 100 can be similar to the bonding system 100 described for Figure 2 The semiconductor devices 210A-210B are similar to the previously described semiconductor devices 110A-110B, except that the semiconductor devices 210A-210B do not include frontside alignment marks for alignment during the bonding process. In other embodiments, one of the semiconductor devices 210A-210B can include frontside alignment marks (e.g., similar to the frontside alignment marks 70A-70B) for alignment during the bonding process. In some embodiments, the semiconductor devices 210A-210B include backside alignment marks 72A-72B, which can be similar to the previously described backside alignment marks 72A-72B.

[0057] In some embodiments, semiconductor devices 210A - 210B further include device components 270A - 70B. The device components 270A - 70B can be functional or dummy components of the semiconductor devices 210A - 210B and can be located at or near the front side of the semiconductor devices 210A - 210B. For example, the device components 270A - 70B can include conductive components (e.g., wires, vias, etc.), conductive pads, passive devices, active devices, isolation structures, combinations thereof, etc., which can include components or structures previously described for Figure 1 the semiconductor device 50 shown.

[0058] Figure 8 An intermediate step of a bonding process according to some embodiments is shown. Figure 8 The steps shown can be similar to Figure 3A the steps shown. For example, Figure 8 a first microscope 130A is shown detecting the position of a backside alignment mark 72A of the first semiconductor device 210A. However, as Figure 8 shown, a second microscope 130B detects the position of the device component 270A of the first semiconductor device 210A instead of the position of the front - side alignment mark of the first semiconductor device 210A. Accordingly, a first offset 280A is determined between the position of the device component 270A and the position of the backside alignment mark 72A of the first semiconductor device 210A. The first offset 280A can correspond to the difference between the detected position of the device component 270A and the detected position of the backside alignment mark 72A. In this way, the first offset 280A can be similar to the first offset 80A described for Figures 3A to 3B but for the offset between the backside alignment mark 72A and the device component 270A. For example, the position of the backside alignment mark 72A and the first offset 280A can be used to determine the position of the device component 270A.

[0059] In some embodiments, the position of a backside alignment mark 72B of the second semiconductor device 210B can be detected using the second microscope 130B, and the position of the device component 270B of the second semiconductor device 210B can be detected using the first microscope 130A. This can be similar to the steps previously shown in Figure 4 In addition, a second offset 280B can be determined between the position of the device component 270B and the position of the backside alignment mark 72B of the second semiconductor device 210B.

[0060] According to some embodiments, after determining the positions of the backside alignment marks 72A - 72B, the device components 270A - 70B, and the offsets 280A - 80B, the semiconductor devices 210A - 210B can be bonded using a bonding process to form a bonded structure 250. The bonded structure 250 is shown in Figure 9is shown and can be similar to the previously described bonding structure 150. The bonding process can be similar to the bonding process described for Figure 6 , except that the semiconductor devices 210A-210B are aligned according to the positions of the device components 270A-70B rather than according to the positions of the front-side alignment marks 70A-70B. For example, the positions of the device components 270A-70B can be determined based on the measured positions of the back-side alignment marks 72A-72B and the offsets 280A-80B, and the semiconductor devices 210A-210B can be repositioned to achieve proper alignment of the device components 270A-70B. For example, in some cases, the semiconductor devices 210A-210B can be aligned such that the device components 270A-70B are bonded together during the bonding process. In other cases, the device components 270A-70B are not bonded together, as shown in the embodiment of Figures 8 to 9 . In some cases, using device components for alignment instead of front-side alignment marks can increase the available area of the semiconductor devices that can be used to form the device components. In this way, the density of the components formed in the semiconductor devices can be increased, and the design of the semiconductor devices can have greater flexibility.

[0061] Figure 10 , Figure 11 and Figure 12 show intermediate steps of bonding the semiconductor devices 110A-110B according to some embodiments to form the bonding structure 150. Figures 10 to 12 The bonding process shown in Figures 3A to 7 is similar to the bonding process shown in

[0062] In some embodiments, the carrier substrates 82A - 82B are formed of a material that is at least partially transparent to visible light. In some embodiments, the carrier substrates 82A - 82B can be materials that are at least partially transparent to other wavelengths of light, such as infrared or ultraviolet light. The carrier substrates 82A - 82B can include, for example, glass materials, silicon oxides, plastics, other transparent materials, etc., or combinations thereof. In some embodiments, the carrier substrates 82A - 82B can be panel structures, which can include, for example, a support substrate formed of a suitable dielectric material, such as a glass material, a plastic material, or an organic material. The panel structure can be, for example, a rectangular panel. In some cases, the use of the carrier substrates 82A - 82B can provide structural support for the semiconductor devices 110A - 110B, improve the flatness of the semiconductor devices 110A - 110B, or reduce the warpage of the semiconductor devices 110A - 110B.

[0063] In some embodiments, each semiconductor device 110A - 110B can be attached to the corresponding carrier substrate 82A - 82B by an adhesive or the like (not shown in the figures). In some embodiments, the adhesive can be a release layer that facilitates subsequent removal of the carrier substrate 82A - 82B. The release layer can be formed of a polymer - based material, and it can be removed together with the carrier substrate 82A - 82B. In some embodiments, the release layer is an epoxy - based thermal release material that loses its adhesive properties when heated, such as a light - to - heat conversion (LTHC) release coating. In other embodiments, the release layer can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer can be dispensed as a liquid and cured, or can be a laminated film laminated onto each carrier substrate 82A - 82B.

[0064] Figure 10 A first microscope 130A and a second microscope 130B are shown according to some embodiments. The first microscope 130A detects the position of the back - side alignment mark 72A of the first semiconductor device 110A, and the second microscope 130B detects the position of the front - side alignment mark 70A of the first semiconductor device 110A. Since the carrier substrate 82A is transparent, the first microscope 130A can detect the position of the back - side alignment mark 72A even when the carrier substrate 82A is located between the first microscope 130A and the back - side alignment mark 72A. Techniques similar to those described previously for Figures 3A to 3B determining the first offset 80A between the front - side alignment mark 70A and the back - side alignment mark 72A can be used.

[0065] In a similar manner, the position of the backside alignment marks 72B of the second semiconductor device 110B can be detected through the carrier substrate 82B by the second microscope 130B, and the position of the frontside alignment marks 70B of the second semiconductor device 110B can be detected by the first microscope 130A. Techniques similar to those described previously for Figure 4 can be used to determine the second offset 80B.

[0066] Turning Figure 11 , according to some embodiments, after determining the positions of the frontside alignment marks 70A - 70B, the positions of the backside alignment marks 72A - 72B, and the offsets 80A - 80B, the semiconductor devices 110A - 110B can be joined using a bonding process to form a bonded structure 250. The bonding process can be similar to the bonding process described for Figure 6 . For example, by detecting the positions of the backside alignment marks 72A - 72B, using the offsets 80A - 80B to determine the positions of the frontside alignment marks 70A - 70B, and then repositioning the semiconductor devices 110A - 110B as needed to align the frontside alignment marks 70A - 70B to align the semiconductor devices 110A - 110B. Once aligned, the semiconductor devices 110A - 110B can be brought into physical contact to bond the semiconductor devices 110A - 110B, as described previously. The bonded structure 150 is shown in Figure 11 and can be similar to the previously described bonded structure 150.

[0067] In Figure 12 , the carrier substrates 82A - 82B are separated (e.g., "debonded") from the bonded structure 150. According to some embodiments, debonding includes projecting light (such as laser or ultraviolet light) onto the release layer such that the release layer decomposes under the heat of the light, and the carrier substrates 82A - 82B can be removed. Other techniques for removing the carrier substrates 82A - 82B are possible. This corresponds to Figure 25 the optional step 620 of the process flow 600 shown in

[0068] Figures 13 to 19 shows an intermediate step of bonding semiconductor devices 310A - 310B to form a bonded structure 350 according to some embodiments. Figure 13 shows the first semiconductor device 310A and the second semiconductor device 310B in a bonding system 300 according to some embodiments. The bonding system 300 can be similar to that described for Figure 2The described bonding system 100, except that the bonding system 300 includes a first marking tool 330A and a second marking tool 330B described in more detail below. The semiconductor devices 310A - 310B may be similar to the previously described semiconductor devices 110A - 110B, except that the semiconductor devices 310A - 310B do not include backside alignment marks formed prior to the bonding process for alignment during the bonding process. In other embodiments, one of the semiconductor devices 310A - 310B may include backside alignment marks (e.g., similar to the backside alignment marks 72A - 72B) for alignment during the bonding process. Figures 13 to 19 Some of the steps shown in Figure 26 correspond to the steps of the process flow 700 shown below.

[0069] As described above, except for including the marking tools 330A - 330B, the bonding system 300 may be similar to the bonding system 100 described for Figure 2 The marking tools 330A - 330B may be devices configured to make alignment marks on semiconductor devices. For example, the first marking tool 330A may be configured to make alignment marks (e.g., Figure 15 the first alignment mark 372A in Figure 17 on the backside of the first semiconductor device 310A (e.g., on the semiconductor substrate 52A). Similarly, the second marking tool 330B may be configured to make alignment marks (e.g.,

[0070] in Figure 14 the second alignment mark 372B in Figure 26 on the backside of the second semiconductor device 310B (e.g., on the semiconductor substrate 52B). The marking tools 330A - 330B may use, for example, lasers, electron beams, another technique, etc. to make alignment marks. The marking tools 330A - 330B of the bonding system 300 are shown as devices separated from the microscopes 130A - 130B, but in other embodiments, the marking tools 330A - 330B may be incorporated into the microscopes 130A - 130B. The marking tools 330A - 330B may be connected to the controller 140 and may be configured to send signals to or receive signals from the controller 140. Figure 15 Figure 26 Figure 26Step 704 of the process flow 700 as shown. For example, the first alignment mark 372A may be fabricated at or near the backside surface of the semiconductor substrate 52A. In some embodiments, a first offset 380A may be determined between the front-side alignment mark 70A and the first alignment mark 372A. In some embodiments, the first offset 380A is determined before forming the first alignment mark 372A, and in other embodiments, the first offset 380A is determined after forming the first alignment mark 372A. In some embodiments, techniques similar to those previously described for the first offset 80A may be used to determine the first offset 380A.

[0071] In some embodiments, the first alignment mark 372A is fabricated at a location based on the measured position of the front-side alignment mark 70A. In some embodiments, the first alignment mark 372A may be fabricated at a location approximately directly opposite the front-side alignment mark 70A. For example, the lateral offset of the first offset 380A may be approximately zero. In other embodiments, the position of the first alignment mark 372A may have a non-zero lateral offset from the front-side alignment mark 70A. In some embodiments, the first offset 380A may be predetermined, and the first alignment mark 372A is fabricated at a location approximately the first offset 380A from the measured position of the front-side alignment mark 70A. In some embodiments, the position of the first alignment mark 372A is detected (e.g., using the first microscope 130A) after forming the first alignment mark 372A, and the first offset 380A is determined from the detected position of the first alignment mark 372A. In some cases, forming the first alignment mark 372A based on the position of the front-side alignment mark 70A as described herein may allow for a more precise determination of the first offset 380A, and thus may allow for improved alignment of the semiconductor devices 310A - 310B during the bonding process. For example, forming the alignment mark 372A within the bonding system 300 as described may reduce the chance of misalignment increased due to mechanical movement of the first semiconductor device 310A before or during the bonding process.

[0072] In Figure 16 accordance with some embodiments, the first microscope 130A detects the position of the front-side alignment mark 70B of the second semiconductor device 310B. This corresponds to Figure 26 step 706 of the process flow 700 as shown. In other embodiments, the position of the front-side alignment mark 70B may be detected before detecting the position of the front-side alignment mark 70A (see Figure 14 ) or before forming the first alignment mark 372A (see Figure 15 ). In Figure 17 accordance with some embodiments, the second marking tool 330B fabricates a second alignment mark 372B on the backside of the second semiconductor device 310B. This corresponds to Figure 26Step 708 of the process flow 700 shown. The second alignment mark 372B can be similar to the first alignment mark 372A and can be formed using similar techniques. For example, the second alignment mark 372B can be fabricated at or near the backside surface of the semiconductor substrate 52B. In some embodiments, a second offset 380B can be determined between the front-side alignment mark 70B and the second alignment mark 372B. In some embodiments, the second offset 380B is determined before forming the second alignment mark 372B, and in other embodiments, the second offset 380B is determined after forming the second alignment mark 372B. Techniques similar to those described for the first offset 380A can be used to determine the second offset 380B. In some embodiments, the second alignment mark 372B can be fabricated at a location based on the measured position of the front-side alignment mark 70B. In some embodiments, the position of the second alignment mark 372B can be detected (e.g., by the second microscope 130B) after formation, and the second offset 380B can be determined from the detected position. In other embodiments, the second alignment mark 372B can be formed before detecting the position of the front-side alignment mark 70A (see Figure 14 ) or before forming the first alignment mark 372A (see Figure 15 ).

[0073] Turning Figure 18 , according to some embodiments, after determining the positions of the front-side alignment marks 70A - 70B, forming the alignment marks 372A - 72B, and determining any offsets 380A - 80B, the semiconductor devices 310A - 310B can be joined using a bonding process to form a bonded structure 350. This corresponds to Figure 26 steps 710 and 712 of the process flow 700 shown. The bonding process can be similar to the bonding process described for Figure 6 . For example, the semiconductor devices 310A - 310B can be aligned by detecting the positions of the alignment marks 372A - 72B, determining the positions of the front-side alignment marks 70A - 70B using the offsets 380A - 80B, and then repositioning the semiconductor devices 310A - 310B as needed to align the front-side alignment marks 70A - 70B. Once aligned, the semiconductor devices 310A - 310B can be brought into physical contact to bond the semiconductor devices 310A - 310B, as previously described. The bonded structure 350 is shown in Figure 19 and can be similar to the previously described bonded structure 350.

[0074] Figure 20 and Figure 21 show a first semiconductor device 410A and a second semiconductor device 410B bonded to form a bonded structure 450 according to some embodiments. According to some embodiments, Figure 20Shows semiconductor devices 410A - 410B before bonding, and Figure 21 shows the bonding structure 450 after bonding semiconductor devices 410A - 410B. A bonding system such as bonding system 100 or 300 described herein can be used and the bonding techniques described previously herein can be used to bond semiconductor devices 410A - 410B. Semiconductor devices 410A - 410B can be similar to the semiconductor devices 50, 110A - 110B, 210A - 210B, or 310A - 310B described previously. For example, semiconductor devices 410A - 410B can include front - side alignment marks 70A - 70B, back - side alignment marks 72A - 72B, devices 54A - 54B (e.g., active devices and / or passive devices), interconnect structures 60, conductive pads 62A - 62B, and / or surface dielectric layers 64A - 64B. In other embodiments, semiconductor devices 410A - 410B can include other components in addition to these or another combination of components in addition to these.

[0075] Semiconductor devices 410A - 410B can be, for example, chips, wafers, dies, packages, etc. One or both of semiconductor devices 410A - 410B can be logic devices, such as a central processing unit (CPU), a graphics processing unit (GPU), a system - on - chip (SoC), a microcontroller, etc. One or both of semiconductor devices 410A - 410B can be memory devices, such as a dynamic random - access memory (DRAM) die, a static random - access memory (SRAM) die, a hybrid memory cube (HMC) module, a high - bandwidth memory (HBM) module, etc. Semiconductor devices 410A - 410B can be formed in processes of the same technology node or can be formed in processes of different technology nodes. For example, the first semiconductor device 410A can have a more advanced technology node than the second semiconductor device 410B.

[0076] The semiconductor devices 410A-410B can be devices of a similar type or different types. For example, in some embodiments, both of the semiconductor devices 410A-410B include integrated circuit dies, such as CMOS dies and the like. In some embodiments, one of the semiconductor devices 410A-410B can include a region of one type of transistor (e.g., n-type or p-type), and the other of the semiconductor devices 410A-410B can include a region of another type of transistor. For example. The first semiconductor device 410A can include an n-type FET (e.g., NFET) coupled to the conductive pad 62A, and the second semiconductor device 410B can include a p-type FET (e.g., PFET) coupled to the conductive pad 62B. The conductive pads 62A-62B can be bonded during a bonding process such that the n-type FET is coupled to the p-type FET in the bonding structure 450. In some embodiments, the second semiconductor device 410B can include a memory array (e.g., semiconductor device 410A (e.g., SRAM array, etc.)), and the first semiconductor device 410A can include logic devices (e.g., peripheral logic circuits). The above-described semiconductor devices 410A-410B and the bonding structure 450 are intended as illustrative examples of devices that can be bonded using the techniques described herein to form a bonding structure, and other types or combinations of devices, components, or bonding structures are possible.

[0077] Figures 22 to 24 Intermediate steps of forming a bonding structure 550 (see Figure 24 ) are shown according to some embodiments. Turning to Figure 22 , according to some embodiments, a semiconductor device 510 and a substrate 511 are shown. Subsequently, the semiconductor device 510 and the substrate 511 are bonded (see Figure 23 ), as part of the formation of the bonding structure 550. The semiconductor device 510 can be similar to the semiconductor devices 50, 110A-110B, 210A-210B, 310A-310B, or the previously described 410A-410B. For example, the semiconductor device 510 can include backside alignment marks 72, devices 54 (e.g., active devices and / or passive devices), conductive pads 62, and / or a surface dielectric layer 64. In some embodiments, the semiconductor device 510 includes optional frontside alignment marks 70. In other embodiments, the semiconductor device 510 can include other components or another combination of components in addition to these. In some embodiments, an offset can be determined between the frontside alignment marks 70 and the backside alignment marks 72. This offset can be similar to the previously described offset 80.

[0078] According to some embodiments, the substrate 511 may include a semiconductor substrate 552, a semiconductor layer 555, and / or a surface dielectric layer 564. The semiconductor substrate 552 may be similar to the semiconductor substrate 52. For example, the semiconductor substrate 552 may be a silicon wafer, a semiconductor-on-insulator (SOI) substrate, etc.

[0079] The semiconductor layer 555 may be one or more layers of semiconductor material, such as doped or undoped silicon, the active layer of an SOI substrate, the active layer of a semiconductor substrate on sapphire, etc. The semiconductor layer 555 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the semiconductor layer 555 may be part of the semiconductor substrate 552 or may be the same material as the semiconductor substrate 552. In some embodiments, the semiconductor layer 555 may be different from the semiconductor substrate 552. For example, the semiconductor substrate 552 may be silicon, and the semiconductor layer 555 may be SiGe, but other materials than these are possible. In some embodiments, the surface dielectric layer 564 is formed on the semiconductor layer 555, and the surface dielectric layer 564 may be similar to the previously described surface dielectric layer 64.

[0080] In Figure 23 it, according to some embodiments, the substrate 511 is bonded to the semiconductor device 510 to form a bonding structure 550. For example, the surface dielectric layer 564 may be bonded to the surface dielectric layer 64 using dielectric-to-dielectric bonding, oxide-to-oxide bonding, or other types of bonding. The bonding may be performed using bonding processes similar to those previously described.

[0081] In Figure 24 it, according to some embodiments, the bonding structure 550 is further processed to form the device 554. The processing may include various suitable semiconductor processing steps, such as lithography steps or those used to form the semiconductor device 50. In some embodiments, the position of the front-side alignment mark 70 may be used to align the photomask during various lithography steps. In some embodiments, the position of the front-side alignment mark 70 may be determined from a previously determined offset and the position of the back-side alignment mark 72. The position of the back-side alignment mark 72 may be detected using a microscope, etc., similar to Figures 3A to 3B the process described in it. In this way, the alignment of the photomask can be improved, which can improve device performance and yield.

[0082] In some embodiments, the semiconductor substrate 552 may be removed or partially removed using, for example, grinding, CMP, etching, etc., or combinations thereof. In some embodiments, the device 554 (byFigure 24 The transistor shown in Figure 24 can be formed at the surface of the semiconductor layer 555. The device 554 can be similar to the device 54 and can be, for example, an integrated circuit device including active devices and / or passive devices, etc. The device 554 of the bonding structure 550 can be similar to or different from the device 54 of the bonding structure 550. For example, in some embodiments, the device 54 can include an n-type FET, and the device 554 can include a p-type FET. Other devices or combinations of devices are possible.

[0083] In some embodiments, an ILD 556 is formed around and can cover the device 554. The ILD 556 can be similar to the previously described ILD 56. In some embodiments, an interconnect structure 560 can be formed above the ILD 56 to interconnect the device 554. The interconnect structure 560 can be similar to the previously described interconnect structure 60. For example, the interconnect structure 560 can include one or more metallization patterns in one or more dielectric layers located on the ILD 566. In some embodiments, a conductive component 570 can be formed above the interconnect structure 560 or extend through the interconnect structure 560. The conductive component 570 can include conductive pads, vias, etc. For example, the conductive component 570 can include a through-hole extending through the interconnect structure 560 to physically and electrically contact the interconnect structure 60. For example, in some embodiments, a trench can be etched, the trench exposing the conductive region of the interconnect structure 60, and then a conductive material can be deposited in the trench to form the through-hole. Other techniques for forming the through-hole or other conductive components 570 are possible. In this way, the bonding structure 550 can be formed. Figure 24 The bonding structure 550 shown in Figure 24 is an example, and other bonding structures 550 can be formed to have different components or can be formed using different techniques.

[0084] Other components and processes can also be included in the embodiments described herein. For example, test structures can be included to assist in the verification testing of 3D packaging or 3DIC devices. The test structures can include, for example, test pads formed in the redistribution layer or on the substrate, the test pads allowing the testing of the 3D packaging or 3DIC using a probe and / or a probe card, etc. Verification testing can be performed on the intermediate structure as well as the final structure. In addition, the structures and methods disclosed herein can be used in combination with test methods for intermediate verification of known good dies to increase the yield and reduce the cost.

[0085] The embodiments described herein can achieve advantages. By using front-side alignment marks and back-side alignment marks to align semiconductor devices, the alignment of semiconductor devices can be improved during the bonding process. For example, an offset can be determined between the front-side alignment marks and the back-side alignment marks, which allows the front-side alignment marks to be aligned by detecting the position of the back-side alignment marks. This allows for improved alignment of the front-side alignment marks without the need to detect the front-side alignment marks (e.g., through the device or substrate) during alignment. In this way, in some cases, an opaque substrate or material can be used to fabricate the bonding structure. This can allow for the use of a greater variety of materials within the semiconductor device and can allow for design flexibility of opaque components (e.g., metal components) within the semiconductor device. Additionally, any misalignment of the bonding structure after bonding can be more accurately measured by measuring the relative position of the back-side alignment marks. This can allow for more effective identification of good device or process metrics. The bonding techniques described herein can be applied to a variety of bonding processes (e.g., wafer-to-wafer, chip-to-chip, wafer-to-chip, etc.) and materials to form a variety of bonding structures, etc. Additionally, in some cases, the techniques described herein can be performed without the need for additional equipment or specialized equipment.

[0086] In an embodiment, a method includes: determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer with a third alignment mark on a first side of a second wafer, including detecting the position of the second alignment mark of the first wafer; determining the position of the first alignment mark of the first wafer based on the first offset and the position of the second alignment mark of the first wafer; and, based on the determined position of the first alignment mark, repositioning the first wafer to align the first alignment mark with the third alignment mark; and bonding a first side of the first wafer to a first side of the second wafer to form a bonded structure. In an embodiment, the method includes determining a second offset between the third alignment mark on the first side of the second wafer and a fourth alignment mark on a second side of the second wafer. In an embodiment, repositioning the first wafer to align the first alignment mark with the third alignment mark includes detecting the position of the fourth alignment mark of the second wafer; determining the position of the third alignment mark of the second wafer based on the second offset and the position of the fourth alignment mark of the second wafer. In an embodiment, the method includes detecting the position of the second alignment mark on the bonded structure; detecting the position of the fourth alignment mark on the bonded structure; and determining a misalignment between the first alignment mark and the third alignment mark, wherein the determination is based on the first offset, the second offset, the position of the second alignment mark, and the position of the fourth alignment mark. In an embodiment, aligning the first alignment mark of the first wafer with the third alignment mark on the first side of the second wafer includes repositioning the second wafer to align the third alignment mark with the first alignment mark. In an embodiment, bonding the first side of the first wafer to the first side of the second wafer includes a hybrid bonding process. In an embodiment, bonding the first side of the first wafer to the first side of the second wafer electrically connects the first wafer to the second wafer. In an embodiment, the method includes debonding a carrier substrate from the bonded structure. In an embodiment, determining the first offset includes detecting the first alignment mark using a first microscope and detecting the second alignment mark using a second microscope.

[0087] In an embodiment, a method includes positioning a first semiconductor device above a second semiconductor device, wherein a front side of the first semiconductor device faces a front side of the second semiconductor device, wherein the front side of the first semiconductor device includes a first alignment component and the front side of the second semiconductor device includes a second alignment component; detecting a position of the second alignment component using a first microscope, wherein the first microscope faces the front side of the second semiconductor device; after detecting the position of the second alignment component using the first microscope, forming a third alignment component on a back side of the second semiconductor device using a first marking tool, wherein a position of the third alignment component is based on the position of the second alignment component; detecting a position of the first alignment component using a second microscope, wherein the second microscope faces the front side of the first semiconductor device; after detecting the position of the first alignment component using the second microscope, forming a fourth alignment component on a back side of the first semiconductor device using a second marking tool, wherein a position of the fourth alignment component is based on the position of the first alignment component; repositioning the first semiconductor device and the second semiconductor device to align the first alignment component with the second alignment component, wherein the repositioning is based on the positions of the third alignment component and the fourth alignment component; and bonding the first semiconductor device to the second semiconductor device. In an embodiment, the first alignment component is a conductive component of the first semiconductor device. In an embodiment, the first marking tool forms the third alignment component using an electron beam. In an embodiment, the first microscope includes the second marking tool. In an embodiment, the first semiconductor device includes a first semiconductor die and the second semiconductor device includes a second semiconductor die. In an embodiment, bonding the first semiconductor device to the second semiconductor device includes bonding a first conductive pad of the first semiconductor device to a second conductive pad of the second semiconductor device. In an embodiment, the method includes determining a lateral offset between the first alignment component and the fourth alignment component, wherein the repositioning is further based on the lateral offset.

[0088] In an embodiment, a method includes placing a first device wafer on an upper retainer, wherein the first device wafer includes a first front-side alignment mark; a first back-side alignment mark; a first interconnect structure; a first surface dielectric layer located above the first interconnect structure; and a first contact pad located in the first surface dielectric layer, wherein the first contact pad is connected to the first interconnect structure; placing a second device wafer on a lower retainer, wherein the second device wafer includes a second front-side alignment mark; a second back-side alignment mark; a second interconnect structure; a second surface dielectric layer located above the second interconnect structure; and a second contact pad located in the second surface dielectric layer, wherein the second contact pad is connected to the second interconnect structure; detecting, using a lower microscope, positions of the first front-side alignment mark and the second back-side alignment mark; detecting, using an upper microscope, positions of the second front-side alignment mark and the first back-side alignment mark; determining a first alignment offset between the first front-side alignment mark and the second front-side alignment mark based on positions of the first back-side alignment mark and the second back-side alignment mark; aligning the first front-side alignment mark with the second front-side alignment mark based on the first alignment offset; and bonding the first contact pad to the second contact pad. In an embodiment, the method includes, after bonding the first contact pad to the second contact pad, determining a second alignment offset between the first front-side alignment mark and the second front-side alignment mark, wherein the determination of the second alignment offset is based on positions of the first back-side alignment mark and the second back-side alignment mark. In an embodiment, aligning the first front-side alignment mark with the second front-side alignment mark includes determining a third alignment offset between the first back-side alignment mark and the second back-side alignment mark. In an embodiment, the method includes bonding the first surface dielectric layer to the second surface dielectric layer.

[0089] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method for bonding semiconductor devices, comprising: Facing a first side of a first wafer with a first side of a second wafer, wherein a first microscope is disposed above the second wafer and a second microscope is disposed below the first wafer; After retracting the second wafer to face the first microscope towards the first wafer, determining a first offset between a first alignment mark on the first side of the first wafer and a second alignment mark on a second side of the first wafer through the first microscope and the second microscope; Aligning the first alignment mark of the first wafer with a third alignment mark on the first side of the second wafer, comprising: Detecting a position of the second alignment mark of the first wafer; Based on the first offset and the position of the second alignment mark of the first wafer, determining a position of the first alignment mark of the first wafer; and Based on the determined position of the first alignment mark, repositioning the first wafer to align the first alignment mark with the third alignment mark; and Bonding the first side of the first wafer to the first side of the second wafer to form a bonding structure.

2. The method according to claim 1, further comprising, after retracting the first wafer to face the second microscope towards the second wafer, determining a second offset between the third alignment mark on the first side of the second wafer and a fourth alignment mark on a second side of the second wafer through the first microscope and the second microscope.

3. The method according to claim 2, wherein, Repositioning the first wafer to align the first alignment mark with the third alignment mark includes: Detecting a position of the fourth alignment mark of the second wafer; and Based on the second offset and the position of the fourth alignment mark of the second wafer, determining a position of the third alignment mark of the second wafer.

4. The method according to claim 2, further comprising: Detecting a position of the second alignment mark on the bonding structure; Detecting a position of the fourth alignment mark on the bonding structure; And Determining a misalignment between the first alignment mark and the third alignment mark, wherein the determination of the misalignment between the first alignment mark and the third alignment mark is based on the first offset, the second offset, the position of the second alignment mark, and the position of the fourth alignment mark.

5. The method according to claim 1, wherein Aligning the first alignment mark of the first wafer with the third alignment mark on the first side of the second wafer further includes repositioning the second wafer to align the third alignment mark with the first alignment mark.

6. The method according to claim 1, wherein, Bonding the first side of the first wafer to the first side of the second wafer includes a hybrid bonding process.

7. The method according to claim 1, wherein Bonding the first side of the first wafer to the first side of the second wafer electrically connects the first wafer to the second wafer.

8. The method according to claim 1, further comprising debonding a carrier substrate from the bonding structure.

9. The method according to claim 1, wherein Determining the first offset includes detecting the first alignment mark using a first microscope and detecting the second alignment mark using a second microscope.

10. A method for bonding semiconductor devices, comprising: Positioning a first semiconductor device above a second semiconductor device, wherein a front side of the first semiconductor device faces a front side of the second semiconductor device, wherein the front side of the first semiconductor device includes a first alignment component, and the front side of the second semiconductor device includes a second alignment component; Retracting the first semiconductor device to detect a position of the second alignment component using a first microscope, wherein the first microscope faces the front side of the second semiconductor device; After detecting the position of the second alignment component using the first microscope, forming a third alignment component on a back side of the second semiconductor device using a first marking tool, wherein a position of the third alignment component is based on the position of the second alignment component; Retracting the second semiconductor device to detect a position of the first alignment component using a second microscope, wherein the second microscope faces the front side of the first semiconductor device; After detecting the position of the first alignment component using the second microscope, forming a fourth alignment component on a back side of the first semiconductor device using a second marking tool, wherein a position of the fourth alignment component is based on the position of the first alignment component; Relocating the first semiconductor device and the second semiconductor device to align the first alignment component with the second alignment component, wherein the relocation is based on the positions of the third alignment component and the fourth alignment component; and Bonding the first semiconductor device to the second semiconductor device.

11. The method according to claim 10, wherein, The first alignment component is a conductive component of the first semiconductor device.

12. The method according to claim 10, wherein The first marking tool forms the third alignment component using an electron beam.

13. The method according to claim 10, wherein The first microscope includes the second marking tool.

14. The method according to claim 10, wherein, The first semiconductor device includes a plurality of first semiconductor die, and the second semiconductor device includes a plurality of second semiconductor die.

15. The method according to claim 10, wherein, Bonding the first semiconductor device to the second semiconductor device includes bonding a first conductive pad of the first semiconductor device to a second conductive pad of the second semiconductor device.

16. The method according to claim 10, further comprising determining a lateral offset between the first alignment member and the fourth alignment member, wherein, The relocation is further based on the lateral offset.

17. A method for bonding semiconductor devices, comprising: Placing a first device wafer on an upper retainer, wherein the first device wafer includes: A first front side alignment mark; A first back side alignment mark; A first interconnect structure; A first surface dielectric layer located above the first interconnect structure; and A first contact pad located in the first surface dielectric layer, wherein the first contact pad is connected to the first interconnect structure; Placing a second device wafer on a lower retainer, wherein the second device wafer includes: A second front side alignment mark; A second back side alignment mark; A second interconnect structure; A second surface dielectric layer located above the second interconnect structure; and A second contact pad located in the second surface dielectric layer, wherein the second contact pad is connected to the second interconnect structure; The positions of the first front-side alignment mark and the second back-side alignment mark are detected using a lower microscope, wherein when detecting the position of the first front-side alignment mark, the second device wafer is retracted to orient the lower microscope towards the first device wafer; The positions of the second front-side alignment mark and the first back-side alignment mark are detected using an upper microscope, wherein when detecting the position of the second front-side alignment mark, the first device wafer is retracted to orient the upper microscope towards the second device wafer; Based on the positions of the first back-side alignment mark and the second back-side alignment mark, a first alignment offset between the first front-side alignment mark and the second front-side alignment mark is determined; Based on the first alignment offset, the first front-side alignment mark is aligned with the second front-side alignment mark; and The first contact pad is bonded to the second contact pad.

18. The method according to claim 17, further comprising, after bonding the first contact pad to the second contact pad, determining a second alignment offset between the first front-side alignment mark and the second front-side alignment mark, wherein, The determination of the second alignment offset is based on the positions of the first back-side alignment mark and the second back-side alignment mark.

19. The method according to claim 17, wherein Aligning the first front-side alignment mark with the second front-side alignment mark further includes determining a third alignment offset between the first back-side alignment mark and the second back-side alignment mark.

20. The method according to claim 17, further comprising bonding the first surface dielectric layer to the second surface dielectric layer.

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