Scalable high-voltage control circuits using thin-film electronics

Abstract

The present invention is entitled "Scalable High-Voltage Control Circuit Using Thin-Film Electronics." A device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor functions as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first source and the second source are connected together. The first drain and the second drain are connected together. The second transistor functions as an output, a driver, or both. One or more electrodes, the second gate, or a combination thereof function as a tapped drain configured to sample a stepped voltage across the second transistor.

Description

Technical Field

[0001] The present teachings relate generally to microelectromechanical systems (MEMS), and more particularly to a high voltage switching device for driving a MEMS actuator. Background Art

[0002] MEMS are small (e.g., microscopic) systems, specifically systems with moving parts. MEMS are made of components with sizes between 1 micron and 100 microns (μm), and the sizes of MEMS are typically in the range of 20 microns to 1 millimeter (mm). MEMS typically include a central unit (e.g., a microprocessor) that processes data and several components 1148 that interact with the surrounding environment (e.g., microsensors). Due to the large surface area to volume ratio of MEMS, the forces generated by ambient electromagnetism (e.g., electrostatic charge and magnetic torque) and fluid dynamics (e.g., surface tension and viscosity) are more relevant design considerations than with larger-scale mechanical devices.

[0003] MEMS typically use electrostatic, piezoelectric, or thermal actuation. Electrostatic actuation scales down to smaller sizes better than electromagnetic and thermal actuation. However, electrostatic actuation typically relies on higher voltages (e.g., several kV) than electromagnetic and thermal actuation to generate sufficient output. Generating and controlling such high voltages in microelectronic devices with comparable actuator size and weight is a challenge. Summary of the Invention

[0004] The following is a brief summary of the invention to provide a basic understanding of some aspects of one or more embodiments of the present teachings. This summary is not a comprehensive overview, nor is it intended to identify key or important elements of the present teachings, nor is it intended to describe the scope of the present disclosure. Instead, its primary purpose is simply to present one or more concepts in a simplified form as a prelude to the detailed embodiments presented later.

[0005] A device is disclosed. The device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor functions as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first source and the second source are connected together. The first drain and the second drain are connected together. The second transistor functions as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof function as a tapped drain, the tapped drain being configured to sample a stepped voltage of the second transistor.

[0006] A switching device for driving an actuator is also disclosed. The switching device includes a first transistor configured to function as an inverter. The first transistor includes a first source, a first gate, a first drain, and a plurality of electrodes spaced apart from each other. The electrodes are positioned at least partially between the first gate and the first drain. The switching device also includes a second transistor configured to function as an output, a driver, or both. The second transistor includes a second source. The first source and the second source are connected together. The second transistor also includes a second gate. The second transistor also includes a second drain. The first drain and the second drain are connected together. The second transistor also includes a plurality of field plates spaced apart from each other. The field plates are positioned at least partially between the second source and the second drain. Each field plate is connected to one of the electrodes. The electrodes, the second gate, or a combination thereof function as a tapped drain, which is configured to sample a stepped voltage of the second transistor and provide a voltage to the field plate of the second transistor.

[0007] A high-voltage switching device for driving a microelectromechanical system (MEMS) actuator is also disclosed. The switching device includes a first transistor configured to function as an inverter. The first transistor includes a first source, a first gate, a first drain, and a plurality of electrodes, the plurality of electrodes being spaced apart from one another over a high-voltage drift region of a gateless channel of the first transistor. The electrode and the gateless channel of the first transistor are positioned at least partially between the first gate and the first drain. The switching device also includes a second transistor configured to function as an output, a driver, or both. The second transistor includes a second source. The first source and the second source are connected together. The second transistor also includes a second gate. The gate of the second gate is connected to one of the electrodes. The second transistor also includes a second drain. The first drain and the second drain are connected together. The second transistor also includes a plurality of field plates spaced apart from one another over the gateless channel of the second transistor. The field plates are configured to substantially evenly distribute the high voltage over the gateless channel of the second transistor. The field plates and the gateless channel of the second transistor are positioned at least partially between the second source and the second drain. Each field plate is connected to one of the electrodes. The electrode, the second gate or a combination thereof serves as a tapped drain, the tapped drain being distributed between the first gate and the first drain, and the tapped drain being configured to sample the stepped voltage of the second transistor and provide a voltage for the field plate of the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present teachings and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0009] Figure 1 Depicted is a schematic diagram of a high voltage switchgear for driving a MEMS actuator according to one embodiment.

[0010] Figure 2 Depicted according to one embodiment Figure 1 A magnified view of a portion of the .

[0011] Figure 3 A circuit diagram of a first stage of an apparatus according to one embodiment is depicted.

[0012] Figure 4 Depicted is a circuit diagram of multiple (eg, 4) levels of devices stacked together according to one embodiment.

[0013] Figure 5 Depicted is a schematic cross-sectional side view of a portion of a first stage of an apparatus according to one embodiment.

[0014] Figure 6 Depicted are graphs showing current and voltage characteristics of a first stage of a device according to one embodiment.

[0015] Figure 7 Depicted are graphs showing current and voltage characteristics of multiple stacked and / or cascaded stages (eg, four stages) of a device according to one embodiment.

[0016] Figure 8 Depicted is a schematic cross-sectional side view of a portion of a first stage of an apparatus according to one embodiment.

[0017] Figure 9 Depicted are graphs showing current and voltage characteristics of an optical switch of a device when an n+ doped a-Si:H layer is at least partially positioned between the S / D metal layer and the channel, according to one embodiment.

[0018] Figure 10 Depicted is a diagram showing that when the S / D metal layer is at least partially positioned on (ie, in direct contact with) the channel according to one embodiment (eg, Figure 8 ), a graph of the current and voltage characteristics of the optical switch.

[0019] Figure 11 Depicted is a schematic diagram of another high voltage switchgear for driving a MEMS actuator according to one embodiment.

[0020] Figure 12 Depicted according to one embodiment Figure 11 The enlarged part.

[0021] Figure 13 Depicted according to one embodiment Figure 11 Schematic cross-sectional side view of a portion of the device shown in .

[0022] Figure 14 Depicted is a diagram showing a Figure 11 Figure 5. Transfer characteristics of the device in FIG. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to exemplary implementations of the present teachings, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same, similar or like parts.

[0024] The present disclosure relates to microelectromechanical systems (MEMS). A first embodiment of the MEMS may be or include an optical coupler (also known as an optocoupler). The optical coupler approach simplifies the interface and separation to the low voltage control circuit. The optical coupler approach can also cascade (e.g., stack) multiple stages to increase the rated voltage. The optical coupler approach can have reduced energy efficiency because a light source is required to turn the device on and off. A second embodiment of the MEMS may be or include a two-stage inverter / buffer transistor structure in which the inverter thin film transistor (TFT) and the buffer TFT are tightly integrated at the sub-device level. Such tight integration helps to evenly distribute the high voltage across the drain region of the buffer TFT so that a high rated voltage can be achieved.

[0025] High-voltage (HiV)-TFTs based on hydrogenated amorphous silicon (a-Si:H), particularly the "offset gate" TFT architecture, can provide operating voltages of 200V-500V or 300V-400V. The offset gate TFT architecture can have a gateless drift channel region that provides one or more semiconductor segments to distribute the high voltage across the gateless region to prevent any turn-off process due to high electric fields. The length of the gateless region can be scaled to maintain the same electric field (e.g., E=V / L) with any voltage. In one example, an 800V HiV-TFT can be constructed based on this design.

[0026] However, for scaling voltages above 800V, the approach becomes increasingly inefficient. It is difficult to keep the high voltage evenly distributed over the gate-free area so that it does not concentrate locally to cause a runaway breakdown process. In addition, having a longer gate-free area may have a negative impact on the on-current. Gate-free channels are naturally "resistive". For the same channel width, the on-current of a TFT with a long gate-free channel can be small. Increasing the length of the gate-free channel may cause the on / off ratio to decrease rapidly. An 800V HiV-TFT can have an on / off ratio of about 3-4 orders of magnitude. The fundamental difficulty of a scalable high-voltage driver with a reliable way of implementing a wide range of desired voltages is to prevent the high voltage from focusing on a small area of ​​the channel material or device, which would cause a runaway breakdown process.

[0027] Multiple discrete transistors can be cascaded to extend the operating voltage range. However, implementing the circuit in a TFT is a challenge and has not been done before. There are several differences between using discrete devices and the TFT process. In the a-Si:H TFT process, only N-type metal oxide semiconductor (NMOS) active devices are available. There are no P-type metal oxide semiconductor (PMOS) or bipolar devices available. Resistors have a limited range in the a-Si:H TFT process and are generally considered an inefficient use of layout real estate. Support subcircuits to provide multiple voltage rails to control the gates of the cascaded transistor array are generally not available because they are typically complex DC-DC converters that are beyond the capabilities of the TFT circuit.

[0028] Figure 1 A schematic diagram of a high voltage switchgear 100 for driving a MEMS actuator is depicted, and Figure 2 Depicted according to one embodiment Figure 1 1. Device 100 may include one or more optical switches (ten shown: 110A-110J). Optical switches 110A-110J may be or include photodiodes (e.g., semiconductor diodes) that convert light into current. In one embodiment, the semiconductor may be or include a-Si:H. The semiconductors may each include two terminal contacts. The terminal contacts may form a Schottky barrier for the semiconductor. The terminal contact material may be or include TiW, MoCr, Mo, ITO, or a combination thereof.

[0029] Device 100 may also include one or more first transistors (ten shown: 120A-120J). First transistors 120A-120J may be or include TFTs. First transistors 120A, 120J may be long and narrow to provide a discharge path for the gate of a second transistor (which is introduced and described below). For example, first transistors 120A-120J may have a length of about 20 μm to about 500 μm and a width of about 3 μm to about 10 μm.

[0030] Each of the first transistors 120A-120J may include a source 122A, a gate 124A, and a drain 124A. Each of the first transistors 120A-120J may be connected to a corresponding one of the optical switches 110A-110J, as described in more detail below. For example, the first transistor 120A may be connected to the optical switch 110A, the first transistor 120B may be connected to the optical switch 110B, and so on. The first transistors 120A-120J may have a W / L ratio less than 1. For example, the W / L ratio may be about 0.1 to about 0.01.

[0031] The device 100 may also include one or more second transistors (ten are shown: 140A-140J). The second transistors 140A-140J may be or include HiV-TFTs. More specifically, the second transistors 140A-140J may be configured to operate at a higher voltage than the first transistors 120A-120J. For example, the rated voltage of the first transistors 120A-120J may be about 10V to about 100V (e.g., 20V), and the rated voltage of the second transistors 140A-140J may be about 200V to about 1000V (e.g., 400V). The second transistors 140A-140J may be shorter and wider / thicker than the first transistors 120A-120J. For example, the second transistors 140A-140J may have a length of about 3μm to about 10μm and a width of about 10μm to about 1000μm.

[0032] Each of the second transistors 140A-140J may include a source 142A, a gate 144A, and a drain 144A. Each of the second transistors 140A-140J may be connected to a corresponding one of the optical switches 110A-110J and to a corresponding one of the first transistors 120A-120J. For example, the second transistor 140A may be connected to the optical switch 110A and to the first transistor 120A, the second transistor 140B may be connected to the optical switch 110B and to the first transistor 120B, and so on. The gates 144A-144J of the second transistors 140A-140B may be controlled by the optical switches 110A-110J. For example, each of the second transistors (e.g., 140A) can be controlled using a corresponding one of the optical switches (e.g., 110A) and / or a corresponding one of the first transistors (e.g., 120A), which causes the gate (e.g., 144A) of the second transistor (e.g., 140A) to be at the same potential as the source (e.g., 142A) of the second transistor (e.g., 140A). This may cause the second transistor (e.g., 140A) to be in an off state when the optical switch 110A is not illuminated.

[0033] The optical switch 110A, the first transistor 120A, and the second transistor 120A can form a first stage of the device 100, the optical switch 110B, the first transistor 120B, and the second transistor 120B can form a second stage of the device 100, and so on. Thus, the device 100 can include multiple (e.g., 10) stages that are stacked and / or cascaded, which can help the device 100 achieve a higher (e.g., 10 times) operational voltage range than a single TFT can handle / withstand. For example, the optical switches 110A-110J and the second transistors 140A-140J can be connected in cascade series to extend the operating voltage range of the device 100.

[0034] Device 100 may also include one or more pads (two are shown: 150A, 150B). Pads 150A, 150B may be metal pads configured for probing using a probe station. First pad 150A may be connected to a first stage (e.g., to first transistor 120A and / or second transistor 140A). Second pad 150B may be connected to a last (e.g., tenth) stage (e.g., to first transistor 120J and / or second transistor 140J).

[0035] Device 100 may also include one or more pads (ten shown: 160A-160J). First pad 160A may be connected to a first stage (e.g., to first transistor 120A and / or second transistor 140A), second pad 160B may be connected to a second stage (e.g., to first transistor 120B and / or second transistor 140B), and so on.

[0036] To turn on the device 100, a light source (e.g., an LED controlled by a low-voltage control circuit) illuminates the optical switches 110A-110J, which induces a photocurrent and biases the gate potential of the second transistors 140A-140J toward the drain voltage. This causes the second transistors 140A-140J to turn on. The first transistors 120A-120J can act as a load for the optical switches 110A-110J. A predetermined resistance is required to induce a sufficient gate voltage due to the photocurrent, which actuates the second transistors 140A-140J to the on state.

[0037] Figure 3 A circuit diagram of a first stage of the apparatus 100 according to one embodiment is depicted. As described above, the first transistor 120A may include a source 122A, a gate 124A, and a drain 126A, and the second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The drain 126A of the first transistor 120A may be connected to a first side of the optical switch 110A and to the gate 144A of the second transistor 140A. The source 122A of the first transistor 120A may be connected to the gate 124A of the first transistor 120A and to the source 142A of the second transistor 140A (e.g., at a common node 170A). The drain 146A of the second transistor 140A may be connected to a second side of the optical switch 110A.

[0038] Figure 4 A circuit diagram 400 is depicted for multiple (e.g., four) stages of stacked device 100 according to one embodiment. As shown, optical switch 110A and drain 146A of second transistor 140A of the first stage can be connected to common node 170B of the second stage, optical switch 110B and drain 146B of second transistor 140B of the second stage can be connected to common node 170C of the third stage, and optical switch 110C and drain 146C of second transistor 140C of the third stage can be connected to common node 170D of the fourth stage. Optical switches 110A-110D can be closely positioned together in the illuminated area to ensure light utilization and illumination uniformity. Optical switches 110A-110D can be grouped together and controlled by one (or more) light sources actuated by low-voltage electronics.

[0039] Figure 5 A schematic cross-sectional side view of a portion of a first stage of a device 100 according to one embodiment is depicted. The first stage can be formed using a back channel etch stop a-Si:H TFT process. The first stage can include a gate dielectric layer (also referred to as a bottom nitride layer) 510, an interlayer dielectric (ILD) layer 512 positioned on the gate dielectric layer 510, and a (top) passivation layer 514 positioned on the ILD layer 512.

[0040] The first stage may further include an optical switch 110A, a first transistor 120A ( Figure 5 512 and the second transistor 140A. The optical switch 110A may be at least partially positioned within the ILD layer 512 and / or the passivation layer 514. The optical switch 110A may be implemented on an S / D metal layer (six portions are shown: 120A-120F). As shown, a first side of the optical switch 110A may be implemented on a first portion of an S / D metal layer 520A, and a second side of the optical switch 110A may be implemented on a second portion of an S / D metal layer 520B. The first and second portions of the S / D metal layers 520A and 520B may be positioned within the ILD layer 512. The first and second portions of the S / D metal layers 520A and 520B may be separated from each other (i.e., a portion of the ILD layer 512 may be positioned between the first and second portions). The second portion of the S / D metal layer 520B may be connected to a third portion of the S / D metal layer 520C, which may be at least partially positioned within the gate dielectric layer 510. A third portion of the S / D metal layer 520C can be positioned on and / or connected to the field plate 522, which is positioned within the gate dielectric layer 510. The third portion of the S / D metal layer 520C can be connected to a fourth portion of the S / D metal layer 520D, which is positioned within the ILD layer 512.

[0041] An n+ doped a-Si:H layer (five portions shown: 524A-524E) may be at least partially positioned within the ILD layer 512. As shown, a first portion of an S / D metal layer 520A may be at least partially positioned on a first portion of the n+ doped a-Si:H layer 524A, a second portion of an S / D metal layer 520B may be at least partially positioned on a second portion of the n+ doped a-Si:H layer 524B, and a fourth portion of an S / D metal layer 520D may be at least partially positioned on a third portion of the n+ doped a-Si:H layer 524C.

[0042] The second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The second transistor 140A may also include a field plate 530 that is offset from the gate 144A within the gate dielectric layer 510. The field plate 530 may be positioned between the gate 144A and the drain 146A. A gateless channel (e.g., an offset region) 532 may be positioned within the gate dielectric layer 510. The gateless channel 532 may be positioned between the gate 144A and the field plate 530. The gateless channel 532 may also or alternatively be positioned between the gate 144A and the drain 146A. The field plate 530 and / or the gateless channel region 532 may be positioned near the drain 146A to extend the approximately 10-second volt S / D operating range to a few hundred volts operating range. This is unique to the offset gate HiV-TFT architecture.

[0043] The second transistor 140A may further include a fifth portion and a sixth portion of the S / D metal layers 520E and 520F. The fifth portion and the sixth portion of the S / D metal layers 520E and 520F may be positioned within the ILD layer 512. The fifth portion and the sixth portion of the S / D metal layers 520E and 520F may be separated from each other (i.e., a portion of the ILD layer 512 may be positioned between the fifth portion and the sixth portion). The fifth portion and the sixth portion of the S / D metal layers 520E and 520F may have a stepped profile such that as they move closer to each other, they each move closer to the passivation layer 514.

[0044] The second transistor 140A may further include fourth and fifth portions of the n+-doped a-Si:H layers 524D and 524E. The fourth and fifth portions of the n+-doped a-Si:H layers 524D and 524E may be positioned within the ILD layer 512. The fourth and fifth portions of the n+-doped a-Si:H layers 524D and 524E may be separated from one another (i.e., a portion of the ILD layer 512 may be positioned between the fourth and fifth portions). The fourth and fifth portions of the n+-doped a-Si:H layers 524D and 524E may have a stepped profile such that as they move closer to one another, they each progress closer to the passivation layer 514.

[0045] The second transistor 140A may further include a channel 540 (e.g., comprising a-Si:H) and a top nitride (T.Nit.) layer 542. The channel 540 may be positioned on the gate dielectric layer 510 and / or within the ILD layer 512. The channel 540 may be at least partially positioned between the fourth and fifth portions of the n+-doped a-Si:H layers 524D and 524E. The top nitride layer 542 may be positioned on the channel 540. The top nitride layer 542 may be at least partially positioned between the fourth and fifth portions of the n+-doped a-Si:H layers 524D and 524E. The channel 540 may have a greater width than the top nitride layer 542.

[0046] Source 142A may include at least a portion of the sixth portion of S / D metal layer 520F, a fifth portion of n+-doped a-Si:H layer 524E, channel 540, and a top nitride layer 542. Drain 146A may include at least a portion of the fifth portion of S / D metal layer 520E, a fourth portion of n+-doped a-Si:H layer 524D, channel 540, and a top nitride layer 542. Channel 540 and top nitride layer 542 may be at least partially positioned between source 142A and drain 146A.

[0047] In one embodiment, the separated a-Si:H layer 520 of the optical switch 110A can be implemented in the same a-Si:H channel material. However, process modifications are required to ensure that the optical switch 110A has a predetermined on / off ratio. This alternative implant will be discussed later.

[0048] Figure 6 depicts a graph 600 showing current and voltage characteristics of a first stage of apparatus 100 according to one embodiment, and Figure 7 A graph 700 is depicted showing the current and voltage characteristics of multiple stacked and / or cascaded stages (e.g., four stages) of device 100. Both graphs 600 and 700 show one curve for a first (e.g., on) state of device 100 and another curve for a second (e.g., off) state of device 100. As can be seen, when device 100 has four stages, device 100 can generate four times the voltage when compared to when device 100 has a single stage. For example, the single-stage embodiment operates at up to approximately 300V, and the multi-stage embodiment operates at up to approximately 1200V. The current limit for the single-stage embodiment is set to 20μA, and the current limit for the multi-stage embodiment is set to 50μA. On / off ratios exceeding six orders of magnitude are demonstrated for both the single-stage and multi-stage embodiments.

[0049] Figure 8 Depicted is a schematic cross-sectional side view of a portion of a first stage of apparatus 100 according to one embodiment. Figure 8The implementation plan is Figure 5 In this embodiment, the first level may include a gate dielectric layer 510 and an interlayer dielectric (ILD) layer 512 positioned on the gate dielectric layer 510. The (top) passivation layer 514 may optionally be omitted.

[0050] The optical switch 110A may include two portions of S / D metal layers 820A and 820B. The portions of the S / D metal layers 820A and 820B may have a stepped profile such that as they move closer together, they each move further away from the gate dielectric layer 510. The optical switch 110A may also include a channel 840 (e.g., comprising a-Si:H) and a top nitride layer 842. The channel 840 may be positioned on the gate dielectric layer 510 and / or within the ILD layer 512. The channel 840 may be at least partially positioned between the portions of the S / D metal layers 820A and 820B. The top nitride layer 842 may be positioned on the channel 840. The top nitride layer 842 may be at least partially positioned between the portions of the S / D metal layers 820A and 820B.

[0051] As described above, optical switch 110A and second transistor 140A can share the same a-Si:H material layer, which can simplify the layer structure and process. As shown, because optical switch 110A is a two-terminal device, second transistor 140A (shown on the left) and optical switch 110A (shown on the right) share a nearly identical structure, except that optical switch 110A does not include a gate. In addition, there is no n+-doped a-Si:H layer between S / D metal layers 820A, 820B and channel 840. Compared to conventional a-Si:H TFT processes, this structure may require additional steps to construct, which assumes that the S / D metal and n+-doped a-Si:H are patterned in a single step, sharing the same mask pattern.

[0052] However, Figure 9 and Figure 10 The importance of using different contact structures for the optical switch 110A and the second transistor 140A, respectively, is shown.

[0053] Figure 9 Depicted is a graph 900 showing current and voltage characteristics of an optical switch 110A when an n+ doped a-Si:H layer is at least partially positioned between the S / D metal layer and the channel, according to one embodiment. More specifically, Figure 9 Shown with Figure 8 The optical switch 110A shown on the right side of FIG has current and voltage characteristics of an optical switch of similar structure, except that the n+ doped a-Si:H layer is positioned between the S / D metal layer and the channel, similar to FIG. Figure 8The second transistor 140A is shown on the left. The on / off ratio of this device is less than 10, which is poor.

[0054] Figure 10 Depicted is a diagram showing when the S / D metal layers 820A, 820B are at least partially positioned on (ie, in direct contact with) the channel 840 according to one embodiment (eg, Figure 8 Graph 1000 of the current and voltage characteristics of optical switch 110A is shown on the right side of FIG. The on / off ratio is improved by more than 2 orders of magnitude to greater than 1000. Similarly, without the n+-doped a-Si:H layer for second transistor 140A, second transistor 140A can have a very small on-state current.

[0055] Figure 11 A schematic diagram of another high voltage switchgear 1100 for driving a MEMS actuator is depicted, and Figure 12 Depicted according to one embodiment Figure 11 Device 1100 may be or include an all-electrical implant. Figure 11 The device 1100 shown in FIG. Figure 1-10 One difference between the described devices 100 is that Figure 11 The device 1100 in can directly scale up to the KV range.

[0056] Device 1100 may be or include a composite device. Device 1100 may include one or more transistors (two are shown: 1120, 1140). The first (e.g., upper) transistor 1120 may be or include a TFT. For example, the first transistor 1120 may be or include a HiV-TFT having a source 1122, a gate 1124, and a drain 1126. The first transistor 1120 may be long and narrow. For example, the first transistor 1120 may have a length of about 20 μm to about 1000 μm and a width / thickness of about 3 μm to about 20 μm. The first transistor 1120 may be used as an inverter (e.g., a first-stage inverter). In the embodiment shown, there is no load resistor for the first transistor 1120, which is different from a conventional inverter circuit.

[0057] The device 1100 can be actuated between a first (e.g., off) state and a second (e.g., on) state. When the gate 1124 turns off the first transistor 1120, the device 1100 can be in the off (e.g., low current) state. When the gate 1124 turns on the first transistor 1120, the device 1100 can be in the on (e.g., higher current) state.

[0058] The second (e.g., lower) transistor 1140 may also be or include a TFT. For example, the second transistor 1140 may be or include a HiV-TFT having a source 1242, a gate 1144, and a drain 1146. The second transistor 1140 may be wider than the first transistor 1120. For example, the width of the second transistor 1140 may be from about 20 μm to about 1000 μm. The second transistor 1140 may function as a driver and / or output transistor.

[0059] Sources 1122 and 1142 may be connected (e.g., by metal); however, sources 1122 and 1142 may not be shared (e.g., their semiconductor channels may be separated). Similarly, drains 1126 and 1146 may be connected (e.g., by metal); however, drains 1126 and 1146 may not be shared (e.g., their semiconductor channels may be separated). The subcomponents of transistors 1120 and 1140 are tightly coupled, so that device 1100 is not a conventional inverter + output transistor. Instead, device 1100 is a composite three-terminal device with a source, a gate, and a drain.

[0060] The first transistor 1120 may include one or more tap electrodes (five are shown: 1130A-1130E). The electrodes 1130A-1130E may be distributed over a high-voltage drive region of a gateless channel (also referred to as a gateless drift region) 1132 of the first transistor 1120. The electrodes 1130A-1130E of the first transistor 1120 may be at least partially positioned between the gate 1124 and the drain 1126. One of the electrodes 1130A may be connected to the gate 1144 of the second transistor 1140.

[0061] The second transistor 1140 may include one or more field plates (five are shown: 1148A-1148E). The gate 1144 and field plates 1148A-1148E of the second transistor 1140 may be connected (e.g., directly) to the electrodes 1130A-1130E of the first transistor 1120. The field plates 1148A-1148E may be at least partially positioned between the gate 1144 and one or more drains 1126, 1146. The field plates 1148A-1148E may distribute the high voltage substantially evenly across the gateless channel (also referred to as the gateless drift region) 1152 of the second transistor 1140, which may reduce and / or prevent premature breakdown. As shown, the gateless channels 1132, 1152 may be at least partially positioned between the one or more gates 1124, 1144 and the one or more drains 1126, 1146. The operating voltage range of the device 1100 may be extended by increasing the number of electrodes 1130A- 1130E of the first transistor 1120 and / or increasing the number of field plates 1148A- 1148E of the second transistor 1140 .

[0062] The sources 1122, 1142, gate 1144, drains 1126, 1146, electrodes 1130A-1130E, or a combination thereof can be made of a first material (e.g., S / D metal). The gate 1124, field plates 1148A-1148E, or a combination thereof can be made of a second material (e.g., gate metal) different from the first material. The channels 1132, 1152 can be made of a third material (e.g., a:Si:H) that is different from the first and second materials.

[0063] like Figure 11 As shown in FIG, device 1100 can be connected to one or more pads (four are shown: 1160A-1160D). Pads 1160A-1160D can be metal pads configured for probing using a probe station. As shown, pad 1160A can be connected to one or more sources 1122, 1142, pad 1160B can be connected to gate 1144, and pad 1160D can be connected to one or more drains 1126, 1146.

[0064] The first transistor 1120 may have a modified (e.g., unconventional) structure. More specifically, in addition to the source 1122, the gate 1124, and the drain 1126, the first transistor 1120 may also include one or more tapped drains distributed along the gateless drift region 1132 between the gate 1124 and the drain 1126. The tapped drain may be or include a gate 1144 and / or electrodes 1130A-1130E. The tapped drain may be configured to sample the stepped voltage of the second transistor 1140. The tapped drain may also or alternatively be configured to provide a field plate voltage for the second transistor 1140. In one embodiment, the tapped drain may be a field plate for the first transistor 1120. In another embodiment, the tapped drain may not be a field plate for the first transistor 1120.

[0065] In one embodiment, the electrode 1130 can function as a field plate and / or drain of the first transistor 1120. In one embodiment, the gate 1144 can function as a field plate and / or drain of the first transistor 1120. In one embodiment, the electrode 1130 can function as a field plate of the second transistor 1140.

[0066] Figure 13 Depicts a method according to one embodiment of the present invention. Figure 11 13-13 in a schematic cross-sectional side view of a portion of the device 1100. Figure 11 The cross section is shown as being through gate 1144, but the cross section may also or instead be taken through any one of electrodes 1130A-1130E.

[0067] Device 1100 can include a first (e.g., lower) metal layer 1310. First metal layer 1310 can be made of the same type of metal as gate 1124. Gate dielectric layer 1120 can be at least partially positioned on first metal layer 1310. Second (e.g., upper) metal layer 1330 can be at least partially positioned on gate dielectric layer 1120. Second metal layer 1330 can be made of the same type of metal as drain 1126. In at least one embodiment, metal layers 1310 and 1330 can be made of the same type of metal. In another embodiment, metal layers 1310 and 1330 can be made of different types of metal. Second metal layer 1330 can include one or more legs (two shown: 1332 and 1334) extending at least partially through gate dielectric layer 1120 toward first metal layer 1310. In at least one embodiment, legs 1332 and 1334 are positioned on and / or contact first metal layer 1310.

[0068] Channel 1340 may be at least partially positioned within second metal layer 1330. Channel 1340 may be made of a:Si:H. N+ layer 1350 may be at least partially positioned within second metal layer 1330. N+ layer 1350 may be at least partially positioned on and / or above channel 1340. N+ layer 1350 may be or include an n+-doped a-Si:H layer. Top nitride layer 1360 may be at least partially positioned within second metal layer 1330. Top nitride layer 1360 may be at least partially positioned between channel 1340 and n+ layer 1350. For example, top nitride layer 1360 may be positioned above channel 1340 and below top nitride layer 1360.

[0069] Third metal layer 1370 can be at least partially positioned on and / or over second metal layer 1330 and / or n+ layer 1350. Third metal layer 1370 can be made of the same type of metal as second metal layer 1330. In at least one embodiment, layers 1330, 1370 can be the same layer.

[0070] Figure 14 A graph 1400 is depicted showing the transfer characteristics of the device 1100 according to one embodiment. At low input gate voltage (V g <2V), the device 1100 is in the "on" state with a conduction current >10uA (e.g., device compliance setting). For high gate input voltages (V g >2.5V), the device 1100 is in the "off" state, and the leakage current can be several hundred pA at 1100V. In one embodiment, 1100V can be the highest voltage that the device 1100 can provide. The input voltage can be swept from -5V to 10V, and the S / D drain can be set to the maximum voltage range of the measurement setup (e.g., 1100V). The compliance current is set to 10μA. The device 1100 can achieve 4-5 orders of magnitude on / off.

[0071] Although the numerical ranges and parameters setting forth the broad scope of the present teachings are approximate, the numerical values ​​given in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors, which are necessarily caused by the standard deviation present in their respective test measurements. In addition, all ranges disclosed herein are understood to encompass any and all subranges contained therein. For example, a range of "less than 10" can include any and all subranges between (and including) a minimum value of 0 and a maximum value of 10, i.e., any and all subranges having a minimum value equal to or greater than 0 and a maximum value equal to or less than 10, such as 1 to 5.

[0072] Although the present teachings have been shown with respect to one or more embodiments, changes and / or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, it should be understood that although the process is described as a series of actions or events, the present teachings are not limited by the ordering of such actions or events. Some actions may occur in different orders and / or simultaneously with other actions or events other than those described herein. In addition, not all process stages are required to implement the method according to one or more aspects or embodiments of the present teachings. It should be understood that structural objects and / or processing levels can be added, or existing structural objects and / or processing levels can be removed or modified. In addition, one or more of the actions depicted herein can be performed in one or more separate actions and / or stages. In addition, if the terms "comprises," "comprising," "having," "with" or their variations are used in specific embodiments and claims, such terms are intended to be inclusive in a manner similar to the term "comprising." The term "at least one of..." is used to refer to one or more of the selected listed items. Furthermore, in the discussion and claims herein, the term "on..." used with respect to two materials that are "on" one another means at least some contact between the two materials, while "over..." means that the two materials are in proximity, but there may be one or more additional intervening materials so that contact is possible but not required. Neither "on..." nor "over..." implies any directionality as used herein. The term "conformal" describes a coating material in which the angles of the underlying material are preserved due to the conformal material. The term "about" indicates that the listed values ​​may be slightly varied, as long as the variation does not cause the process or structure to deviate from the illustrated embodiment. The terms "couple," "coupled," "connect," "connection," "connected," "in connection with," and "connecting" mean "directly connected to" or "connected to via one or more intermediate elements or components." Finally, the terms "exemplary" or "illustrative" indicate that the description serves as an example and do not imply that it is ideal. Other embodiments of the present teachings may be apparent to those skilled in the art from consideration of this specification and practice of the disclosure herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the present teachings being indicated by the following claims.

Claims

1. A switching device for driving an actuator, comprising: an optical switch configured to convert light into an electric current; a first transistor connected to the optical switch, the first transistor comprising a first source, a first gate, a first drain, and one or more electrodes, wherein the first transistor functions as an inverter; a second transistor comprising a second source, a second gate, and a second drain, wherein the first source and the second source are connected together, wherein the first drain and the second drain are connected together, wherein the second transistor functions as an output, a driver, or both, and wherein the one or more electrodes, the second gate, or a combination thereof functions as a tapped drain, the tapped drain configured to sample a stepped voltage of the second transistor; interlayer dielectric layer; as well as A source-drain (S / D) metal layer is at least partially positioned within the interlayer dielectric layer, wherein the optical switch is positioned on a first portion and a second portion of the source-drain (S / D) metal layer, and wherein the first portion and the second portion are separated from each other by a portion of the interlayer dielectric layer.

2. The device of claim 1, wherein the one or more electrodes include a plurality of electrodes spaced apart from one another between the first gate and the first drain, and wherein the electrodes are positioned within a drift region of a gateless channel of the first transistor. The device of claim 1 , wherein the first transistor is narrower than the second transistor. 4 . The device of claim 1 , wherein semiconductor channels of the first source and the second source are separated such that the first source and the second source are not shared. 5 . The device of claim 1 , wherein semiconductor channels of the first drain and the second drain are separated such that the first drain and the second drain are not shared.

6. The device of claim 1 , wherein the first transistor includes a first electrode and a second electrode spaced apart from each other, wherein the second transistor includes a first field plate and a second field plate spaced apart from each other, wherein the first electrode is connected to the first field plate, and wherein the second electrode is connected to the second field plate. The device of claim 6 , wherein the gate of the second transistor is connected to the first electrode. 8 . The device of claim 6 , wherein the first field plate and the second field plate are at least partially positioned between the gate of the second transistor and the drain of the second transistor. 9 . The device of claim 6 , wherein the first electrode and the second electrode are distributed over a high-voltage drift region of a gateless channel of the first transistor. 10 . The device of claim 9 , wherein the first electrode and the second electrode are positioned between the gate and the drain of the first transistor.

11. A switching device for driving an actuator, the switching device comprising: an optical switch configured to convert light into an electric current; a first transistor connected to the optical switch, wherein the first transistor is configured to function as an inverter, and wherein the first transistor comprises: First Source; a first gate; a first drain; and a plurality of electrodes spaced apart from one another, wherein the electrodes are at least partially positioned between the first gate and the first drain; and a second transistor configured to function as an output, a driver, or both, wherein the second transistor comprises: a second source electrode, wherein the first source electrode and the second source electrode are connected together; a second gate; a second drain electrode, wherein the first drain electrode and the second drain electrode are connected together; and a plurality of field plates spaced apart from one another, wherein the field plates are at least partially positioned between the second source and the second drain, wherein each field plate is connected to one of the electrodes, and wherein the electrode, the second gate, or a combination thereof serves as a tapped drain configured to sample the stepped voltage of the second transistor and provide a voltage to the field plate of the second transistor; a gate dielectric layer; an interlayer dielectric layer positioned on the gate dielectric layer; a passivation layer positioned on the interlayer dielectric layer, wherein the optical switch is at least partially positioned within the interlayer dielectric layer, the passivation layer, or both; and A source-drain S / D metal layer is at least partially positioned within the interlayer dielectric layer, wherein the optical switch is positioned on the source-drain S / D metal layer, wherein the optical switch is positioned on a first portion and a second portion of the source-drain S / D metal layer, and wherein the first portion and the second portion are separated from each other by a portion of the interlayer dielectric layer. 12 . The switching device of claim 11 , wherein the gate electrode of the second gate electrode is connected to one of the electrodes. 13 . The switching device of claim 11 , wherein the electrode is distributed over a high-voltage drift region of a gate-free channel of the first transistor.

14. The switch device of claim 11, wherein the field plate is configured to distribute a high voltage substantially evenly across a gateless channel of the second transistor.

15. The switching device of claim 11 , wherein the gateless channel of the first transistor is at least partially positioned between the gate of the first transistor and the drain of the first transistor, and wherein the gateless channel of the second transistor is at least partially positioned between the source of the second transistor and the drain of the second transistor.

16. A high-voltage switch device for driving a micro-electromechanical system (MEMS) actuator, the switch device comprising: an optical switch configured to convert light into an electric current; a first transistor connected to the optical switch, wherein the first transistor is configured to function as an inverter, wherein the first transistor comprises: First Source; a first gate; a first drain; and a plurality of electrodes spaced apart from one another over a high-voltage drift region of a gateless channel of the first transistor, wherein the electrodes and the gateless channel of the first transistor are at least partially positioned between the first gate and the first drain; a second transistor configured to function as an output, a driver, or both, wherein the second transistor comprises: a second source electrode, wherein the first source electrode and the second source electrode are connected together; a second gate, wherein the gate electrode of the second gate is connected to one of the electrodes; a second drain electrode, wherein the first drain electrode and the second drain electrode are connected together; and a plurality of field plates spaced apart from one another across the gateless channel of the second transistor, wherein the field plates are configured to distribute a high voltage substantially evenly across the gateless channel of the second transistor, wherein the field plates and the gateless channel of the second transistor are at least partially positioned between the second source and the second drain, wherein each field plate is connected to one of the electrodes, wherein the electrodes, the second gate, or a combination thereof serve as a tapped drain, the tapped drain being distributed between the first gate and the first drain, and wherein the tapped drain is configured to sample a stepped voltage of the second transistor and provide a voltage to the field plate of the second transistor; a gate dielectric layer; an interlayer dielectric layer positioned on the gate dielectric layer; a passivation layer positioned on the interlayer dielectric layer, wherein the optical switch is at least partially positioned within the interlayer dielectric layer, the passivation layer, or both; and A source-drain S / D metal layer is at least partially positioned within the interlayer dielectric layer, wherein the optical switch is positioned on the source-drain S / D metal layer, wherein the optical switch is positioned on a first portion and a second portion of the source-drain S / D metal layer, and wherein the first portion and the second portion are separated from each other by a portion of the interlayer dielectric layer. 17 . The switching device of claim 16 , wherein the first source, the second source, the second gate, the first drain, the second drain, and the field plate are made of a first material. The switching device of claim 17 , wherein the first gate and the field plate are made of a second material different from the first material. 19 . The switching device of claim 18 , wherein the gateless channel of the first transistor and the gateless channel of the second transistor are made of a third material different from the first material and the second material.

20. The switching device of claim 19, wherein the first material comprises a first metal, wherein the second material comprises a second metal, and wherein the third material comprises hydrogenated amorphous silicon (a-Si:H).

21. The apparatus according to claim 1, further comprising: a gate dielectric layer, wherein the interlayer dielectric layer is positioned on the gate dielectric layer; A passivation layer is positioned on the interlayer dielectric layer, wherein the optical switch is at least partially positioned within the interlayer dielectric layer, the passivation layer, or both. 22 . The device of claim 21 , wherein the source-drain (S / D) metal layer further comprises a third portion connected to the second portion, and wherein the third portion is positioned within the gate dielectric layer.

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