Display panel and display terminal

Abstract

The present application provides a display panel and a display terminal, including a display area, wherein the display panel further includes: an array substrate, including a passivation layer and at least one flat layer located on the passivation layer; a light-emitting substrate, including a pixel definition layer, the pixel definition layer is formed on the flat layer; the light-emitting substrate further includes a plurality of pixels; and an encapsulation layer, including a first inorganic layer, the first inorganic layer is formed on the light-emitting substrate; wherein a connection groove penetrating the flat layer is provided on the flat layer, the connection groove is annular and located at the edge of the display area; a portion of the flat layer is filled in the connection groove and connected to the passivation layer, the first inorganic layer, the pixel definition layer and the passivation layer form a first inorganic film layer closed loop in the display area, and the pixel is located in the first inorganic film layer closed loop. The display panel and the display terminal provided by the present application can realize self-encapsulation of the display area and achieve a narrow frame effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] The packaging structure of a traditional active matrix organic light emitting diode (AMOLED) display screen includes a leveling area located at the edge of the display screen, two blocking structures, a first blocking wall and a second blocking wall, and an O-CUT (PI deep groove) structure located at the very edge of the display screen. The first inorganic layer of the packaging structure and the second blocking layer on the double polyimide film in the substrate form an inorganic closed loop structure. Since the inorganic closed loop structure is located in the border area and occupies a large area, it is not conducive to forming a narrow border. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display terminal that can realize self-packaging of a display area to achieve a narrow frame effect.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides a display panel, including a display area, and the display panel further includes:

[0006] An array substrate, comprising a passivation layer and at least one planar layer located on the passivation layer;

[0007] A light-emitting substrate, comprising a pixel definition layer, wherein the pixel definition layer is formed on the planar layer; the light-emitting substrate further comprises a plurality of pixels; and

[0008] An encapsulation layer, comprising a first inorganic layer, wherein the first inorganic layer is formed on the light-emitting substrate;

[0009] Among them, a connecting groove is opened on the flat layer and passes through the flat layer. The connecting groove is annular and is located at the edge of the display area; part of the flat layer is filled in the connecting groove and is connected to the passivation layer, and the first inorganic layer, the pixel definition layer and the passivation layer form a first inorganic film layer closed loop in the display area, and the pixel is located in the first inorganic film layer closed loop.

[0010] In an optional embodiment of the present application, the display panel further includes a leveling area, and the leveling area is disposed adjacent to the display area;

[0011] The array substrate comprises a first flat layer and a second flat layer, the first flat layer is formed on the passivation layer, the second flat layer is formed on the first flat layer, the pixel definition layer is formed on the second flat layer, the connection groove passes through the first flat layer, and the orthographic projection of the connection groove on the passivation layer falls outside the orthographic projection of the second flat layer located in the display area on the passivation layer;

[0012] A portion of the pixel definition layer and a portion of the first planar layer are located in the leveling area, and a first undercut groove is formed between the pixel definition layer and the first planar layer located in the leveling area;

[0013] The light emitting substrate further includes a cathode formed on the pixel definition layer and cut off at the first undercut groove;

[0014] The first inorganic layer is connected to a surface of the pixel definition layer exposed from the first undercut groove.

[0015] In an optional embodiment of the present application, the display panel further includes a peripheral area located outside the leveling area;

[0016] The display panel further comprises at least one retaining wall, the retaining wall being located in the peripheral area and formed on the passivation layer; a first spacing groove is provided between the retaining wall and the pixel definition layer in the display area, and the first undercut groove is connected to the first spacing groove;

[0017] The encapsulation layer further includes an organic layer and a second inorganic layer. The organic layer is formed on the first inorganic layer and filled in the first spacing groove and the first undercut groove. The second inorganic layer covers the organic layer and the barrier wall.

[0018] In an optional embodiment of the present application, the retaining wall includes the first planar layer, the second planar layer, the pixel definition layer, and a spacer layer formed on the pixel definition layer;

[0019] A second undercut groove is formed on at least one side of the retaining wall, wherein the second undercut groove is formed between the pixel definition layer and the second planar layer of the retaining wall;

[0020] The cathode is formed on the retaining wall and is isolated at the second undercut groove, and the first inorganic layer is connected to the surface of the pixel definition layer exposed from the second undercut groove;

[0021] A portion of the pixel definition layer of the retaining wall is formed on the second planar layer, and another portion of the pixel definition layer is formed from the second planar layer on the side surfaces of the second planar layer and the first planar layer of the retaining wall away from the first undercut groove and extends from the second planar layer to the passivation layer;

[0022] A second inorganic film layer closed loop is formed between the pixel definition layer of the retaining wall, the first inorganic layer and the passivation layer.

[0023] In an optional embodiment of the present application, the display panel further includes at least one anti-crack structure, and a second spacing groove is provided between the retaining wall and the anti-crack structure;

[0024] The anti-crack structure includes the first flat layer and the pixel definition layer formed on the first flat layer, the first flat layer of the anti-crack structure has a receiving groove, part of the pixel definition layer is formed on the first flat layer, and another part of the pixel definition layer is filled in the receiving groove and contacts the passivation layer;

[0025] A third undercut groove and / or a fourth undercut groove is provided between the first planar layer and the pixel definition layer of the crack prevention structure, the third undercut groove is communicated with the second spacing groove, and the fourth undercut groove is located on a side of the crack prevention structure away from the second spacing groove;

[0026] The cathode is formed on the crack prevention structure and is interrupted at the third undercut groove and / or the fourth undercut groove.

[0027] In an optional embodiment of the present application, the first inorganic layer is connected to the surface of the pixel definition layer exposed from the third undercut groove;

[0028] A third inorganic film layer closed loop is formed between the pixel definition layer, the first inorganic layer and the passivation layer of the anti-crack structure.

[0029] In an optional embodiment of the present application, the first inorganic layer is connected to the surface of the pixel definition layer exposed from the fourth undercut groove;

[0030] A fourth inorganic film layer closed loop is formed between the pixel definition layer, the first inorganic layer and the passivation layer of the anti-crack structure.

[0031] In an optional embodiment of the present application, the array substrate further includes a thin film transistor array layer, the passivation layer is formed on the thin film transistor array layer, the thin film transistor array layer includes a GOA circuit, and the GOA circuit is located at least in the peripheral area and the leveling area.

[0032] In an optional embodiment of the present application, the pixel definition layer of the crack structure has a depression, and the depression is opposite to the receiving groove;

[0033] The display panel further includes a protection layer, which is formed on the second inorganic layer of the encapsulation layer and filled in the second spacing groove, the third undercut groove and / or the fourth undercut groove and the recess.

[0034] The present application also provides a display terminal, comprising the display panel as described above.

[0035] The display panel and display terminal provided by the present application are provided with a connection groove which is annular and penetrates the flat layer and is located at the edge of the display area on at least one flat layer, and the pixel is located in the ring formed by the connection groove; the pixel definition layer is formed on the flat layer and part of the pixel definition layer is filled in the connection groove and connected to the passivation layer, so that the first inorganic layer, the pixel definition layer and the passivation layer form a first inorganic film layer closed loop in the display area, and the pixel is located in the first inorganic film layer closed loop. In this way, it is possible to prevent the pixel from being corroded by external water and oxygen, and to realize self-packaging of the display area, thereby reducing the occupied area of ​​the peripheral area, which is conducive to realizing a narrow frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 An overall schematic diagram of a display panel with pixels provided in an embodiment of the present application.

[0038] Figure 2 The display panel provided by the first embodiment of the present application is Figure 1 Sectional view along section line II.

[0039] Figure 3 The display panel provided by the first embodiment of the present application is Figure 1 Sectional view along section line II-II.

[0040] Figure 4 The display panel provided by the second embodiment of the present application is Figure 1 Sectional view along section line II.

[0041] Figure 5 The display panel provided by the second embodiment of the present application is Figure 1 Sectional view along section line II-II. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0043] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0044] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0045] The display panel and the display terminal provided in the present application will be described in detail below in conjunction with specific embodiments and drawings.

[0046] See also Figure 1-3 A first embodiment of the present application provides a display panel 100 , which includes an array substrate 110 , a light-emitting substrate 120 and a packaging layer 130 , wherein the light-emitting substrate 120 is formed on the array substrate 110 , and the packaging layer 130 is formed on the light-emitting substrate 120 .

[0047] The display panel 100 includes a display area 101 , a leveling area 102 adjacent to the display area 101 , and a peripheral area 103 adjacent to the leveling area 102 .

[0048] The array substrate 110 includes a substrate 10 , a thin film transistor array layer 30 formed on the substrate 10 , a passivation layer 40 formed on the thin film transistor array layer 30 , and at least one planar layer formed on the passivation layer 40 .

[0049] In an optional embodiment of the present application, the substrate 10 includes a first polyimide film layer (not shown), a first support layer (not shown), a second polyimide layer (not shown) and a second support layer (not shown) stacked in sequence.

[0050] In other embodiments, the number of polyimide film layers and the number of support layers included in the substrate 10 are not limited to 2, and can be 1 or more than 2, or can be a substrate of other materials such as a ceramic substrate.

[0051] In an optional embodiment of the present application, the array substrate 110 further includes a buffer layer 20 , wherein the buffer layer 20 is formed on the substrate 10 , and the thin film transistor array layer 30 is formed on the buffer layer 20 .

[0052] The thin film transistor array layer 30 includes a driving circuit 31 and a GOA circuit 32. The driving circuit 31 is located in the display area 101, and the GOA circuit 32 is located in the peripheral area 103 and the leveling area 102. In other embodiments, the GOA circuit 32 may also be partially located in the display area 101.

[0053] The driving circuit 31 and the GOA circuit 32 each include at least one thin film transistor, and the film layer structure of the thin film transistor is the film layer structure of the thin film transistor in the prior art, which is not repeated here. The thin film transistors of the driving circuit 31 and the GOA circuit 32 may be a single-gate structure, a double-gate structure, a bottom-gate structure, or a top-gate structure.

[0054] The flat layer has a connection groove 511 penetrating the flat layer. The connection groove 511 is annular and located at the edge of the display area 101 .

[0055] Wherein, the passivation layer 40 is an inorganic film layer.

[0056] In this embodiment, the array substrate 110 includes two flat layers, namely: a first flat layer 51 and a second flat layer 52. The first flat layer 51 is formed on the passivation layer 40, and the second flat layer 52 is formed on the first flat layer 51. The connection groove 511 penetrates the first flat layer 51, and the second flat layer 52 is disconnected at the connection groove 511.

[0057] Specifically, the orthographic projection of the connection groove 511 on the passivation layer 40 falls outside the orthographic projection of the second flat layer 52 located in the display area 101 on the passivation layer 40 . Part of the passivation layer 40 is exposed from the connection groove 511 .

[0058] In an optional embodiment of the present application, the array substrate 110 further includes a transfer terminal 53 , which is formed on the first planar layer 51 and electrically connected to the drain of the thin film transistor of the driving circuit 31 , and the second planar layer 52 covers the transfer terminal 53 .

[0059] In other embodiments of the present application, the array substrate 110 may not include the transfer terminal 53 .

[0060] The light-emitting substrate 120 includes an anode 54, a pixel definition layer 61, a plurality of light-emitting units 62, a common layer 71 and a cathode 72. The anode 54 and the pixel definition layer 61 are formed on the flat layer (for example, formed on the second flat layer 52). The pixel definition layer 61 is provided with a plurality of pixel openings 611. Part of the anode 54 is exposed from the pixel openings 611. One light-emitting unit 62 is formed in one pixel opening 611. The common layer 71 is formed on the pixel definition layer 61 and covers the light-emitting unit 62. The cathode 72 is formed on the common layer 71. The anode 54 is electrically connected to the drain of the thin film transistor of the driving circuit 31. Specifically, the anode 54 is electrically connected to the drain of the thin film transistor of the driving circuit 31 through the adapter terminal 53.

[0061] One of the light emitting units 62 and the corresponding anode 54 and cathode 72 constitutes one pixel. The pixel is located in the display area 101 .

[0062] The encapsulation layer 130 includes a first inorganic layer 81 , an organic layer 82 and a second inorganic layer 83 . The first inorganic layer 81 is formed on the cathode 72 , the organic layer 82 is formed on the first inorganic layer 81 , and the second inorganic layer 83 is formed on the organic layer 82 .

[0063] Since the second flat layer 52 is disconnected at the connecting groove 511, the connecting groove 511 is exposed from the second flat layer 52, and part of the pixel definition layer 61 is formed on the first flat layer 51, and at least part of the pixel definition layer 61 is filled in the connecting groove 511 and connected to the passivation layer 40, so that the first inorganic layer 81 of the encapsulation layer 130, the pixel definition layer 61 and the passivation layer 40 form a first inorganic film layer closed loop in the display area 101, and the pixel is located in the first inorganic film layer closed loop. In this way, it is possible to prevent the pixel from being corroded by external water and oxygen, and to achieve self-encapsulation of the display area 101, thereby reducing the occupied area of ​​the peripheral area 103, which is conducive to achieving a narrow frame.

[0064] Part of the pixel definition layer 61 and part of the first flat layer 51 are located in the leveling area 102, a first undercut groove 604 is formed between the pixel definition layer 61 and the first flat layer 51 located in the leveling area 102, the common layer 71 and the cathode 72 are separated at the first undercut groove 604, and the first inorganic layer 81 is connected to the surface of the pixel definition layer 61 exposed from the first undercut groove 604. In this way, the first inorganic layer 81 can be connected to the pixel definition layer 61 to further enhance the sealing performance of the closed loop of the first inorganic film layer.

[0065] The display panel 100 further includes at least one retaining wall 601, which is located in the peripheral area 103 and formed on the passivation layer 40; a first spacing groove 104 is provided between the retaining wall 601 and the pixel definition layer 61 of the display area 101, and the first undercut groove 604 is connected to the first spacing groove 104. The organic layer 82 is filled in the first spacing groove 104 and the first undercut groove 604, and the second inorganic layer 83 also covers the organic layer 82 and the retaining wall 601.

[0066] Among them, the retaining wall 601 includes the first flat layer 51, the second flat layer 52, the pixel definition layer 61 and the spacing layer 63 formed on the pixel definition layer 61; the common layer 71 and the cathode 72 are separated at the first bottom cutting groove 604 and fall on the passivation layer 40 exposed from the first spacing groove 104 and are formed on the outer wall of the retaining wall 601.

[0067] In which, the display panel 100 also includes at least one anti-crack structure 602, a second spacing groove 105 is provided between the retaining wall 601 and the anti-crack structure 602, the anti-crack structure 602 includes the first flat layer 51 and the pixel definition layer 61 formed on the first flat layer 51, the first flat layer 51 of the anti-crack structure 602 has a receiving groove 512, part of the pixel definition layer 61 is formed on the first flat layer 51, and another part of the pixel definition layer 61 is filled in the receiving groove 512 and contacts the passivation layer 40, and the pixel definition layer 61 of the crack structure 602 has a recess 612, and the recess 612 is opposite to the receiving groove 512.

[0068] There is a third undercut groove 605 and / or a fourth undercut groove 606 between the first planar layer 51 and the pixel definition layer 61 of the crack prevention structure 602, the third undercut groove 605 is communicated with the second spacing groove 105, and the fourth undercut groove 606 is located on a side of the crack prevention structure 602 away from the second spacing groove 105. Specifically, there may be only the third undercut groove 605, only the fourth undercut groove 606, or both the third undercut groove 605 and the fourth undercut groove 606 between the first planar layer 51 and the pixel definition layer 61 of the crack prevention structure 602.

[0069] The cathode 72 and the common layer 71 are formed on the anti-crack structure 602 and are separated at the third undercut groove 605 and / or the fourth undercut groove 606 .

[0070] Among them, the first inorganic layer 81 is connected to the surface of the pixel definition layer 61 exposed from the third bottom cutting groove 605, so that the first inorganic layer 81 is connected to the pixel definition layer 61, and the pixel definition layer 61 is connected to the passivation layer 40, so as to form a third inorganic film layer closed loop between the pixel definition layer 61 of the anti-crack structure 602, the first inorganic layer 81 and the passivation layer 40.

[0071] Among them, the first inorganic layer 81 is connected to the surface of the pixel definition layer 61 exposed from the fourth bottom cut groove 606, so that the first inorganic layer 81 is connected to the pixel definition layer 61, and the pixel definition layer 61 is connected to the passivation layer 40, so as to form a fourth inorganic film layer closed loop between the pixel definition layer 61 of the anti-crack structure 602, the first inorganic layer 81 and the passivation layer 40.

[0072] The display panel 100 further includes a protection layer 84 , which is formed on the second inorganic layer 83 and fills the second spacing groove 105 , the third undercut groove 605 , the fourth undercut groove 606 and the recess 612 .

[0073] The anti-crack structure 602 may further include a second planar layer 52 . At this time, the third undercut groove 605 and the fourth undercut groove 606 are formed between the pixel definition layer 61 and the second planar layer 52 .

[0074] See also Figure 4 and Figure 5The second embodiment of the present application provides a display panel 200. The structure of the display panel 200 is similar to that of the display panel 100, and the difference is that: a second undercut groove 607 is formed on at least one side of the retaining wall 601, and the second undercut groove 607 is formed between the pixel definition layer 61 and the second flat layer 52 of the retaining wall 601, the cathode 72 is formed on the retaining wall 601 and is isolated at the second undercut groove 607, and the first inorganic layer 81 and the pixel definition layer exposed from the second undercut groove 607 are connected to each other. The surface of the retaining wall 601 is connected, part of the pixel definition layer 61 of the retaining wall 601 is formed on the second flat layer 52, and another part of the pixel definition layer 61 is formed from the second flat layer 52 on the side of the second flat layer 52 and the first flat layer 51 of the retaining wall 601 away from the first bottom cutting groove 604 and extends from the second flat layer 52 to the passivation layer 40; a second inorganic film layer closed loop is formed between the pixel definition layer 61 of the retaining wall 601, the first inorganic layer 81 and the passivation layer 40.

[0075] The present application also provides a display terminal (not shown), comprising the display panel 100 / 200 as described above and a main body (not shown), wherein the display panel 100 / 200 is formed on the main body. The display terminal may be a mobile phone, a computer, a display screen, etc.

[0076] The display panel and display terminal provided by the present application are provided with a connection groove which is annular and penetrates the flat layer and is located at the edge of the display area on at least one flat layer, and the pixel is located in the ring formed by the connection groove; the pixel definition layer is formed on the flat layer and part of the pixel definition layer is filled in the connection groove and connected to the passivation layer, so that the first inorganic layer, the pixel definition layer and the passivation layer form a first inorganic film layer closed loop in the display area, and the pixel is located in the first inorganic film layer closed loop. In this way, it is possible to prevent the pixel from being corroded by external water and oxygen, and to realize self-packaging of the display area, thereby reducing the occupied area of ​​the peripheral area, which is conducive to realizing a narrow frame.

[0077] In addition, by setting a first undercut groove between the pixel definition layer and the first flat layer located on the outside of the connecting groove, and connecting the first inorganic layer to the surface of the pixel definition layer exposed from the first undercut groove, so that the first inorganic layer is connected to the pixel definition layer, the sealing performance of the closed loop of the first inorganic film layer is further enhanced.

[0078] In addition, by setting a second undercut groove between the pixel definition layer and the second flat layer on at least one side of the retaining wall, the first inorganic layer is connected to the surface of the pixel definition layer exposed from the second undercut groove, and the pixel definition layer of the retaining wall is partially connected to the passivation layer, so that the first inorganic layer is connected to the pixel definition layer, and the pixel definition layer is connected to the passivation layer, so that the pixel definition layer of the retaining wall, the first inorganic layer and the passivation layer directly form a second inorganic film layer closed loop, thereby further enhancing the sealing performance of the display area.

[0079] In addition, by setting a third undercut groove and / or a fourth undercut groove between the pixel definition layer and the first flat layer on at least one side of the anti-crack structure, the first inorganic layer is connected to the surface of the pixel definition layer exposed from the third undercut groove and / or the fourth undercut groove, and part of the pixel definition layer of the anti-crack structure is connected to the passivation layer, so that the first inorganic layer is connected to the pixel definition layer, and the pixel definition layer is connected to the passivation layer, so that the pixel definition layer, the first inorganic layer and the passivation layer of the anti-crack structure directly form a third inorganic film layer and / or a fourth inorganic film layer closed loop, thereby further enhancing the sealing performance of the display area.

[0080] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A display panel, comprising a display area, characterized in that: The display panel further includes: An array substrate, comprising a passivation layer and at least one planar layer located on the passivation layer; A light-emitting substrate, comprising a pixel definition layer, wherein the pixel definition layer is formed on the planar layer; the light-emitting substrate further comprises a plurality of pixels; and An encapsulation layer, comprising a first inorganic layer, wherein the first inorganic layer is formed on the light-emitting substrate; Among them, a connecting groove is opened on the flat layer and penetrates the flat layer. The connecting groove is annular and is located at the edge of the display area; part of the pixel definition layer is filled in the connecting groove and is connected to the passivation layer, and the first inorganic layer, the pixel definition layer and the passivation layer form a first inorganic film layer closed loop in the display area, and the pixel is located in the first inorganic film layer closed loop.

2. The display panel according to claim 1, wherein: The display panel further includes a leveling area, and the leveling area is disposed adjacent to the display area; The array substrate comprises a first flat layer and a second flat layer, the first flat layer is formed on the passivation layer, the second flat layer is formed on the first flat layer, the pixel definition layer is formed on the second flat layer, the connection groove passes through the first flat layer, and the orthographic projection of the connection groove on the passivation layer falls outside the orthographic projection of the second flat layer located in the display area on the passivation layer; A portion of the pixel definition layer and a portion of the first planar layer are located in the leveling area, and a first undercut groove is formed between the pixel definition layer and the first planar layer located in the leveling area; The light emitting substrate further includes a cathode formed on the pixel definition layer and cut off at the first undercut groove; The first inorganic layer is connected to a surface of the pixel definition layer exposed from the first undercut groove.

3. The display panel according to claim 2, wherein: The display panel further includes a peripheral area located outside the leveling area; The display panel further comprises at least one retaining wall, the retaining wall being located in the peripheral area and formed on the passivation layer; a first spacing groove is provided between the retaining wall and the pixel definition layer in the display area, and the first undercut groove is connected to the first spacing groove; The encapsulation layer further includes an organic layer and a second inorganic layer. The organic layer is formed on the first inorganic layer and filled in the first spacing groove and the first undercut groove. The second inorganic layer covers the organic layer and the barrier wall.

4. The display panel according to claim 3, wherein: The retaining wall includes the first flat layer, the second flat layer, the pixel definition layer, and a spacer layer formed on the pixel definition layer; A second undercut groove is formed on at least one side of the retaining wall, wherein the second undercut groove is formed between the pixel definition layer and the second planar layer of the retaining wall; The cathode is formed on the retaining wall and is isolated at the second undercut groove, and the first inorganic layer is connected to the surface of the pixel definition layer exposed from the second undercut groove; A portion of the pixel definition layer of the retaining wall is formed on the second planar layer, and another portion of the pixel definition layer is formed from the second planar layer on the side surfaces of the second planar layer and the first planar layer of the retaining wall away from the first undercut groove and extends from the second planar layer to the passivation layer; A second inorganic film layer closed loop is formed between the pixel definition layer of the retaining wall, the first inorganic layer and the passivation layer.

5. The display panel according to claim 3, wherein: The display panel further comprises at least one anti-crack structure, and a second spacing groove is provided between the retaining wall and the anti-crack structure; The anti-crack structure includes the first flat layer and the pixel definition layer formed on the first flat layer, the first flat layer of the anti-crack structure has a receiving groove, part of the pixel definition layer is formed on the first flat layer, and another part of the pixel definition layer is filled in the receiving groove and contacts the passivation layer; A third undercut groove and / or a fourth undercut groove is provided between the first planar layer and the pixel definition layer of the crack prevention structure, the third undercut groove is communicated with the second spacing groove, and the fourth undercut groove is located on a side of the crack prevention structure away from the second spacing groove; The cathode is formed on the crack prevention structure and is interrupted at the third undercut groove and / or the fourth undercut groove.

6. The display panel according to claim 5, wherein: The first inorganic layer is connected to the surface of the pixel definition layer exposed from the third undercut groove; A third inorganic film layer closed loop is formed between the pixel definition layer, the first inorganic layer and the passivation layer of the anti-crack structure.

7. The display panel according to claim 5 or 6, characterized in that: The first inorganic layer is connected to the surface of the pixel definition layer exposed from the fourth undercut groove; A fourth inorganic film layer closed loop is formed between the pixel definition layer, the first inorganic layer and the passivation layer of the anti-crack structure.

8. The display panel according to any one of claims 3 to 6, characterized in that: The array substrate further includes a thin film transistor array layer, the passivation layer is formed on the thin film transistor array layer, the thin film transistor array layer includes a GOA circuit, and the GOA circuit is at least located in the peripheral area and the leveling area.

9. The display panel according to claim 5, wherein: The pixel definition layer of the crack structure has a depression, and the depression is opposite to the receiving groove; The display panel further includes a protection layer, which is formed on the second inorganic layer of the encapsulation layer and filled in the second spacing groove, the third undercut groove and / or the fourth undercut groove and the recess.

10. A display terminal, characterized in that: Comprising a display panel as described in any one of claims 1 to 9.

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