Wiring board group, method of manufacturing wiring board group, and method of manufacturing wiring board

Abstract

To provide a wiring board group capable of accurately measuring a thickness of an inorganic layer, a method of manufacturing a wiring board group, and a method of manufacturing a wiring board.SOLUTION: A wiring board group 10 includes a plurality of wiring regions 15, and a cut region 16 which is positioned between the wiring regions 15 adjacent to each other. The wiring board group 10 comprises a carrier board 12, and a wiring layer 20 which is positioned on the carrier board 12 in the wiring region 15. The wiring layer 20 includes a conductive layer 25, and an insulation layer 21 which at least partially covers the conductive layer 25. The insulation layer 21 includes an inorganic layer 23 which at least partially covers the conductive layer 25, and an organic layer 22 which is positioned on the inorganic layer 23. The inorganic layer 23 extends from the wiring region 15 to the cut region 16.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board group, a method for manufacturing a wiring board group, and a method for manufacturing a wiring board. [Background technology]

[0002] Packaging technology that densely mounts multiple semiconductor elements with different functions, such as CPUs and memories, on a single substrate is attracting attention. A structure that electrically connects multiple semiconductor elements is also called an interposer. An interposer includes, for example, a wiring layer that includes a conductive layer and an insulating layer. The wiring layer performs the function of, for example, relocating pads or terminals of the semiconductor elements to another location. Such a wiring layer is also called a rewiring layer.

[0003] The wiring layer includes a conductive layer and an insulating layer that at least partially covers the conductive layer. Patent Document 1 discloses a structure in which the insulating layer has an inorganic layer that at least partially covers the conductive layer and an organic layer that covers the inorganic layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-22894 Summary of the Invention [Problem to be solved by the invention]

[0005] In the wiring layer formation process, in order to confirm whether the inorganic layer is properly formed, it is conceivable to measure the thickness of the inorganic layer, for example, by a non-contact optical measurement method. However, in this case, there is a concern that the inorganic layer formed on the conductive layer having a fine pattern will cause light scattering, making it difficult to accurately measure the thickness of the inorganic layer.

[0006] An object of the embodiments of the present disclosure is to provide a wiring board group, a method for manufacturing a wiring board group, and a method for manufacturing a wiring board that can effectively solve such problems. [Means for solving the problem]

[0007] The embodiments of the present disclosure relate to the following [1] to

[11] .

[0008] [1] A wiring board group including a plurality of wiring areas and a cutting area located between adjacent wiring areas, a carrier substrate; a wiring layer located on the carrier substrate in the wiring region; the wiring layer includes a conductive layer and an insulating layer at least partially covering the conductive layer; the insulating layer includes an inorganic layer at least partially covering the conductive layer and an organic layer located on the inorganic layer; The inorganic layer extends from the wiring region to the cutting region.

[0009] [2] The carrier substrate includes a flat surface facing the wiring layer; The wiring board group according to [1], wherein the inorganic layer includes a surface parallel to the flat surface in the cutting region.

[0010] [3] The wiring board group according to [1] or [2], wherein the width of the cutting region is 1 μm or more.

[0011] [4] The wiring board group according to any one of [1] to [3], further comprising a light-reflecting layer located between the carrier substrate and the inorganic layer.

[0012] [5] The wiring board group according to any one of [1] to [4], wherein the organic layer is continuously formed from the wiring region to the cutting region.

[0013] [6] The wiring board group according to any one of [1] to [4], wherein the organic layer includes an opening formed in the cutting region.

[0014] [7] The wiring layer includes a plurality of the wiring layers, The wiring board group according to any one of [1] to [6], wherein in at least one of the plurality of wiring layers, the insulating layer includes the inorganic layer.

[0015] [8] The wiring board group according to [7], wherein in at least one of the plurality of wiring layers, the organic layer includes an opening formed in the cutting region.

[0016] [9] A method for manufacturing a wiring board group including a plurality of wiring regions and a cutting region located between adjacent wiring regions, comprising: a carrier substrate preparation step of preparing a carrier substrate; a wiring layer forming step of forming a wiring layer on the carrier substrate in the wiring region, the wiring layer forming step includes a conductive layer forming step of forming a conductive layer, and an insulating layer forming step of forming an insulating layer so as to at least partially cover the conductive layer, the insulating layer forming step includes an inorganic layer forming step of forming an inorganic layer so as to at least partially cover the conductive layer, and an organic layer forming step of forming an organic layer on the inorganic layer, In the inorganic layer forming step, the inorganic layer is formed so as to extend from the wiring region to the cutting region.

[0017]

[10] The method for manufacturing a wiring board group according to [9], further comprising a thickness measurement step of measuring the thickness of the inorganic layer in the cutting region.

[0018]

[11] A method for manufacturing a wiring board, a wiring board group preparation step of preparing the wiring board group according to any one of [1] to [8]; a cutting step of cutting the wiring substrate group in the cutting region. [Effects of the Invention]

[0019] According to embodiments of the present disclosure, the thickness of an inorganic layer can be accurately measured. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 2 is a plan view showing a wiring board group according to an embodiment. [Figure 2] 2 is a cross-sectional view of the wiring board group taken along line II-II of FIG. 1. [Figure 3] 3 is an enlarged cross-sectional view showing the wiring board group of FIG. 2. FIG. [Figure 4] 4 is an enlarged cross-sectional view showing an inorganic layer and a conductive layer included in the wiring board group of FIG. 3. FIG. [Figure 5] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 6] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 7] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 8] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 9] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 10] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 11] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 12] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 13] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 14] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 15] 10A to 10C are cross-sectional views for explaining a method for manufacturing a wiring board group according to an embodiment. [Figure 16]1A to 1C are cross-sectional views illustrating a method for manufacturing a wiring substrate according to an embodiment. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a wiring substrate according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a wiring substrate according to an embodiment. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a wiring substrate according to an embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a wiring board group according to a first modified example. [Figure 21] FIG. 10 is a cross-sectional view showing a wiring board group according to a second modified example. [Figure 22] 10A and 10B are cross-sectional views for explaining a method for manufacturing a wiring board group according to a second modified example. [Figure 23] 10A and 10B are cross-sectional views for explaining a method for manufacturing a wiring board group according to a second modified example. [Figure 24] 10A and 10B are cross-sectional views for explaining a method for manufacturing a wiring board group according to a second modified example. [Figure 25] FIG. 11 is a cross-sectional view showing a wiring board group according to a third modified example. [Figure 26] FIG. 10 is a cross-sectional view showing a wiring board group according to a fourth modified example. [Figure 27] FIG. 11 is a cross-sectional view showing a wiring board group according to a fifth modified example. [Figure 28] FIG. 13 is a cross-sectional view showing a wiring board group according to a sixth modified example. [Figure 29] 1A and 1B are diagrams illustrating examples of products on which a wiring layer is mounted. DETAILED DESCRIPTION OF THE INVENTION

[0021] The following describes a wiring board group, a method for manufacturing a wiring board group, and a method for manufacturing a wiring board with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure is not limited to these embodiments. Terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the term "substrate" encompasses components that may be called sheets or films. A "surface" refers to a surface that coincides with the planar direction of a target plate-like component when viewed holistically and comprehensively. A normal direction used with respect to a plate-like component refers to a normal direction to the surface of the component. As used herein, terms such as "parallel" and "orthogonal," as well as length and angle values, that specify shape, geometric conditions, and their degrees, are interpreted without strict meaning, but rather within a range within which similar functions can be expected.

[0022] In this specification, when multiple upper limit candidates and multiple lower limit candidate values ​​are listed for a certain parameter, the numerical range of the parameter can be constructed by combining any one upper limit candidate with any one lower limit candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or A6 or less." In this case, the numerical range of parameter B can be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0023] In the drawings referred to in this embodiment, the same or similar reference numerals are used to designate the same parts or parts having similar functions, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the sake of explanation, and some components may be omitted from the drawings.

[0024] (wiring board group) Fig. 1 is a plan view showing an example of a wiring board group 10. Fig. 2 is a cross-sectional view of the wiring board group 10 taken along line II-II of Fig. 1.

[0025] The wiring board group 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface directions of the wiring board group 10. The second direction D2 is a direction perpendicular to the first direction D1. The third direction D3 is a thickness direction of the wiring board group 10. The third direction D3 is perpendicular to both the first direction D1 and the second direction D2. In this specification, observing an object along the third direction D3 is also referred to as "planar view."

[0026] The wiring board group 10 includes a plurality of wiring boards having the same structure. The wiring board group 10 includes a plurality of wiring regions 15 and a cutting region 16. The wiring region 15 includes a wiring board. One wiring region 15 may correspond to one wiring board. The wiring region 15 may have a rectangular shape in a plan view. The wiring regions 15 may be regularly arranged in the first direction D1 and the second direction D2. The cutting region 16 is located between adjacent wiring regions 15. The cutting region 16 may be located between adjacent wiring regions 15 in the first direction D1 and between adjacent wiring regions 15 in the second direction D2. As described below, a plurality of wiring boards are obtained by cutting the wiring board group 10 in the cutting region 16.

[0027] The length L1 of the wiring region 15 varies depending on the application. As an example, the length L1 of the wiring region 15 is, for example, 20 μm or more, or may be 30 μm or more, or 40 μm or more. The length L1 of the wiring region 15 is, for example, 100 μm or less, or may be 80 μm or less, or may be 60 μm or less. As another example, the length L1 of the wiring region 15 is, for example, 10 mm or more, or may be 20 mm or more, or may be 30 mm or more. The length L1 of the wiring region 15 is, for example, 100 mm or less, or may be 80 mm or less, or may be 60 mm or less. The length L1 of the wiring region 15 is the dimension of the wiring region 15 (wiring substrate) in the first direction D1 or the second direction D2.

[0028] The width W1 of the cutting region 16 is, for example, 1 μm or more, and may be 5 μm or more, or 10 μm or more. The width W1 of the cutting region 16 is, for example, 200 μm or less, and may be 100 μm or less, or 20 μm or less. The width W1 of the cutting region 16 is the distance between adjacent wiring regions 15 in the first direction D1 or the second direction D2. The width W1 of the cutting region 16 is calculated by subtracting the width of the wiring substrate after cutting from the width of the wiring substrate group 10 before cutting.

[0029] The wiring board group 10 includes a carrier substrate 12, a release layer 13, a light reflecting layer 14, and a wiring layer 20. Each of the components will be described below.

[0030] (carrier board) The carrier substrate 12 is a member that supports the wiring layer 20. The carrier substrate 12 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, or the like. The resin substrate may include an organic material. For example, the resin substrate may include epoxy resin, polyethylene, polypropylene, or the like. The carrier substrate 12 may also include a metal substrate including copper, aluminum, nickel, SUS, or the like.

[0031] The carrier substrate 12 includes a flat surface 121. The flat surface 121 is a surface of the carrier substrate 12 that is formed flat. The flat surface 121 faces the wiring layer 20. The release layer 13, the light reflecting layer 14, and the wiring layer 20 are located on this flat surface 121.

[0032] The thickness of the carrier substrate 12 is, for example, 100 μm or more, optionally 200 μm or more, or 500 μm or more, and is, for example, 2000 μm or less, optionally 1500 μm or less, or 1000 μm or less.

[0033] The wiring board group 10 may include an electrode-equipped core substrate having through holes penetrating the front and back of the substrate and through electrodes provided in the through holes for electrical connection between the front and back of the substrate, instead of the carrier substrate 12. Furthermore, a wiring layer 20 (described later) may be located on the front and back of the carrier substrate 12 or the electrode-equipped core substrate, respectively.

[0034] (peeling layer) The release layer 13 is located on the carrier substrate 12. The release layer 13 is located between the carrier substrate 12 and the wiring layer 20. More specifically, the release layer 13 is located between the carrier substrate 12 and the light reflecting layer 14.

[0035] The release layer 13 is a layer that facilitates the operation of peeling the wiring layer 20 from the carrier substrate 12. The release layer 13 includes, for example, a resin. The release layer 13 is configured so that adhesion between the release layer 13 and the wiring layer 20 is reduced by some kind of trigger. The trigger may be irradiation of the release layer 13 with light of a specific wavelength. For example, the release layer 13 may be decomposed by being irradiated with light of a specific wavelength. The trigger may be heating the release layer 13. For example, the release layer 13 may include a thermoplastic resin. Furthermore, for example, the release layer 13 may include a material that exhibits foaming properties when heated or the like.

[0036] The thickness of the release layer 13 is, for example, 0.1 μm or more, optionally 0.2 μm or more, or 0.3 μm or more. The thickness of the release layer 13 is, for example, 1 μm or less, optionally 0.8 μm or less, or optionally 0.5 μm or less.

[0037] (light reflective layer) The light-reflecting layer 14 is located on the carrier substrate 12. More specifically, the light-reflecting layer 14 is located on the release layer 13. The light-reflecting layer 14 is located between the carrier substrate 12 and the wiring layer 20. More specifically, the light-reflecting layer 14 is located between the release layer 13 and the wiring layer 20. The light-reflecting layer 14 is located between the carrier substrate 12 and the inorganic layer 23. More specifically, the light-reflecting layer 14 is located between the release layer 13 and the inorganic layer 23. The light-reflecting layer 14 extends to overlap the inorganic layer 23 in a planar view. In particular, the light-reflecting layer 14 overlaps the inorganic layer 23 in a planar view in the cutting region 16. The light-reflecting layer 14 may also overlap the inorganic layer 23 in a planar view in the wiring region 15.

[0038] The light-reflecting layer 14 has light reflectivity. The total light reflectance of the light-reflecting layer 14 is, for example, 60% or more, optionally 70% or more, or optionally 80% or more. The total light reflectance of the light-reflecting layer 14 is, for example, 95% or less, optionally 90% or less, or optionally 80% or less.

[0039] Here, "total light reflectance" refers to the sum of specular reflectance and diffuse reflectance. Total light reflectance is determined in accordance with the total light reflectance measurement method of JIS K7375. Specifically, total light reflectance is determined by measuring the reflectance when light is incident at an angle on the light-reflecting layer 14 at light wavelengths of 380 nm to 780 nm at 10 nm intervals using a spectrophotometer and an integrating sphere test stand, and calculating the average value. Total light reflectance is determined as a relative value, with the reflectance of a standard white plate containing barium sulfate set to 100%.

[0040] The light-reflecting layer 14 may contain a metal. The light-reflecting layer 14 may contain, as a main component, a metal different from the metal constituting the lower surface of the conductive layer 25 described below. For example, the light-reflecting layer 14 may contain, as a main component, titanium, copper, nickel, molybdenum, tungsten, tantalum, chromium, or an alloy containing these metals. The light-reflecting layer 14 may be a multilayer film in which such metals are stacked. The light-reflecting layer 14 may be made of a metal nitride as long as it has good total light reflectance.

[0041] The thickness of the light reflecting layer 14 is, for example, 30 nm or more, optionally 50 nm or more, or 100 nm or more. The thickness of the light reflecting layer 14 is, for example, 2000 nm or less, optionally 1000 nm or less, or 500 nm or less.

[0042] The wiring board group 10 does not have to include the light reflecting layer 14. For example, when the wiring board group 10 includes a core substrate with electrodes instead of the carrier substrate 12, the wiring layer 20 described below may be formed on the surface of the core substrate without forming the light reflecting layer 14.

[0043] (wiring layer) The wiring layer 20 is located on the carrier substrate 12. More specifically, the wiring layer 20 is located on the light reflecting layer 14. The wiring layer 20 is located on the carrier substrate 12 in the wiring region 15. The wiring layer 20 includes a lower surface 201 and an upper surface 202. The lower surface 201 faces the carrier substrate 12. The upper surface 202 is located opposite the lower surface 201. In this specification, a "lower surface" such as the lower surface 201 refers to a surface facing the carrier substrate 12 in the state of the wiring substrate group 10. An "upper surface" such as the upper surface 202 refers to a surface located opposite the "lower surface" in the third direction D3.

[0044] The wiring layer 20 includes an insulating layer 21 and a plurality of conductive layers 25. The insulating layer 21 at least partially covers the conductive layer 25. The insulating layer 21 may extend from the lower surface 201 to the upper surface 202 in the third direction D3.

[0045] The insulating layer 21 is located at least in the wiring region 15. The insulating layer 21 may also be located in the cutting region 16. The insulating layer 21 may be formed continuously from the wiring region 15 to the cutting region 16. The insulating layer 21 may be formed so as to straddle a plurality of wiring regions 15 and cutting regions 16.

[0046] Some of the multiple conductive layers 25 may be pads 26. The pads 26 may have upper or lower surfaces that include portions that are not in contact with an insulating material such as the insulating layer 21. For example, when the pads 26 are located on the lower surface 201 of the wiring layer 20, the lower surfaces of the pads 26 are not in contact with an insulating material. For example, when the pads 26 are located on the upper surface 202 of the wiring layer 20, the upper surfaces of the pads 26 are not in contact with an insulating material. For example, when a portion of the upper surface of the pads 26 is connected to a through electrode 28 described below, it can be said that the upper surface of the pads 26 includes a portion that is not in contact with an insulating material. The pads 26 have dimensions in a plan view that are larger than the dimensions of the wiring 27 described below and the dimensions of the through electrode 28 described below.

[0047] Some of the conductive layers 25 may be wirings 27. The wirings 27 extend at least partially in the first direction D1 or the second direction D2. Both the upper and lower surfaces of the wirings 27 may be in contact with an insulating material such as the insulating layer 21.

[0048] Some of the multiple conductive layers 25 may be through electrodes 28. The through electrodes 28 extend in the third direction D3. For example, the through electrodes 28 are located in openings formed in the insulating layer 21. The through electrodes 28 electrically connect the conductive layers 25 of two wiring layers adjacent to each other in the third direction D3, for example. The through electrodes 28 may be connected to the pads 26.

[0049] The wiring layer 20 may include multiple wiring layers. The multiple wiring layers may be stacked. In the illustrated example, the wiring layer 20 includes two wiring layers. The wiring layer 20 includes a first wiring layer 20A and a second wiring layer 20B. The wiring layer 20 may include three or more wiring layers. Each of the multiple wiring layers may include an insulating layer 21 and multiple conductive layers 25. In each of the multiple wiring layers, the insulating layer 21 at least partially covers the conductive layer 25.

[0050] The first wiring layer 20A may be located on the light reflecting layer 14. The first wiring layer 20A may include a lower surface 201 of the wiring layer 20. The second wiring layer 20B may be located on the first wiring layer 20A. The second wiring layer 20B may include an upper surface 202 of the wiring layer 20. The wiring board group 10 may include a conductive layer 25 located on the second wiring layer 20B. This conductive layer 25 may include pads 26.

[0051] The wiring layer 20 has a thickness T1. The thickness T1 is, for example, 8 μm or more, and may be 16 μm or more, or 24 μm or more. The thickness T1 is, for example, 100 μm or less, and may be 90 μm or less, or 80 μm or less. The thickness T1 is the distance from the lower surface 201 to the upper surface 202 in the third direction D3.

[0052] The thickness T2 of each wiring layer included in the wiring layer 20 is, for example, 4 μm or more, and may be 6 μm or more, or 8 μm or more. The thickness T2 of each wiring layer included in the wiring layer 20 is, for example, 14 μm or less, and may be 12 μm or less, or 10 μm or less. The thicknesses T2 of the wiring layers may be the same as or different from each other.

[0053] 3 is an enlarged cross-sectional view of the wiring board group 10. The insulating layer 21 includes an organic layer 22 and an inorganic layer 23. In each of the multiple wiring layers, the insulating layer 21 includes the organic layer 22. In at least one wiring layer among the multiple wiring layers, the insulating layer 21 includes the inorganic layer 23. In the example shown in FIG. 3, in both the first wiring layer 20A and the second wiring layer 20B, the insulating layer 21 includes the inorganic layer 23.

[0054] The inorganic layer 23 at least partially covers the conductive layer 25. The inorganic layer 23 may be in contact with the conductive layer 25. Here, "covering" means that the inorganic layer 23 and the conductive layer 25 at least partially overlap in a plan view. A portion of the inorganic layer 23 of the first wiring layer 20A that does not overlap with the conductive layer 25 may be in contact with the light reflecting layer 14. A portion of the inorganic layer 23 of the second wiring layer 20B that does not overlap with the conductive layer 25 may be in contact with the organic layer 22 of the first wiring layer 20A.

[0055] The inorganic layer 23 is located in the wiring region 15, and also in the cutting region 16. The inorganic layer 23 extends from the wiring region 15 to the cutting region 16. The inorganic layer 23 is formed continuously without interruption from the wiring region 15 to the cutting region 16. The inorganic layer 23 may be formed so as to straddle a plurality of wiring regions 15 and cutting regions 16. Note that the inorganic layer 23 may be formed intermittently, rather than continuously, in a plurality of wiring regions 15 and cutting regions 16.

[0056] The inorganic layer 23 has parallel surfaces 233 in the cutting region 16. The parallel surfaces 233 are surfaces parallel to the flat surface 121 of the carrier substrate 12. The parallel surfaces 233 are located at least in the cutting region 16. The parallel surfaces 233 may also be located in the wiring region 15. The thickness of the inorganic layer 23 is measured at such parallel surfaces 233 by a non-contact optical measurement method.

[0057] The organic layer 22 is located on the inorganic layer 23. The organic layer 22 may cover the inorganic layer 23. The organic layer 22 may be in contact with the inorganic layer 23.

[0058] The organic layer 22 is located at least in the wiring region 15. The organic layer 22 may also be located in the cutting region 16. The organic layer 22 may be formed continuously from the wiring region 15 to the cutting region 16. The organic layer 22 may be formed so as to straddle a plurality of wiring regions 15 and cutting regions 16.

[0059] The organic layer 22 includes an organic material having insulating properties, such as polyimide, epoxy, and acrylic.

[0060] The organic layer 22 may contain multiple fillers distributed in the organic material. By including multiple fillers in the organic material, the mechanical properties, thermal properties, etc. of the organic layer 22 are adjusted. The filler may contain an inorganic material or an organic material. Examples of filler materials include silicon oxide.

[0061] The inorganic layer 23 includes an inorganic material. Examples of the inorganic material include a metal material, an inorganic oxide, and an inorganic nitride. The inorganic material may have insulating properties. For example, the inorganic material may be an insulating inorganic oxide or inorganic nitride. Examples of the inorganic oxide include silicon oxide such as SiO2. Examples of the inorganic nitride include silicon nitride such as SiN. The inorganic material may be SiOC, SiC, SiOF, SiON, SiCN, or the like.

[0062] The thermal expansion coefficient of the inorganic material of the inorganic layer 23 is smaller than the thermal expansion coefficient of the organic material of the organic layer 22. The thermal expansion coefficient of the inorganic layer 23 is, for example, 10 ppm / °C or less, or may be 8 ppm / °C or less, or may be 5 ppm / °C or less.

[0063] The thickness of the inorganic layer 23 is, for example, 0.1 μm or more, optionally 0.3 μm or more, or optionally 0.5 μm or more. The thickness of the inorganic layer 23 is, for example, 5 μm or less, optionally 3 μm or less, or optionally 1 μm or less.

[0064] The process of forming the wiring layer 20 may include a process performed at high temperature, such as a heating process of the organic layer 22. The thermal expansion coefficient of the organic material of the organic layer 22 is greater than that of the other components of the wiring layer 20. For example, the thermal expansion coefficient of the organic material of the organic layer 22 is greater than that of a substrate, such as the carrier substrate 12. For example, the thermal expansion coefficient of the organic material of the organic layer 22 is greater than that of the conductive layer 25. When the temperatures of the components of the wiring layer 20 decrease after the heating process, stress may be generated due to the difference in the thermal expansion coefficient between the organic layer 22 and the other components. For example, stress may be generated in the substrate, the conductive layer 25, etc.

[0065] In contrast, in the present embodiment, the wiring layer 20 includes the inorganic layer 23, and therefore, the stress caused by the organic layer 22 is prevented from affecting components other than the inorganic layer 23. This prevents, for example, warping from occurring in the wiring layer 20, the wiring board group 10, or the wiring board. Furthermore, stress is prevented from occurring in the conductive layer 25, and defects such as deformation and breakage of the conductive layer 25 are prevented.

[0066] The inorganic layer 23 may be composed of one layer made of the above-mentioned inorganic material. The inorganic layer 23 may include multiple layers. FIG. 4 is an enlarged cross-sectional view showing the inorganic layer 23 and the conductive layer 25. In the example shown in FIG. 4, the inorganic layer 23 includes a first inorganic layer 231 and a second inorganic layer 232. The first inorganic layer 231 is located on the conductive layer 25 so as to be in contact with the conductive layer 25. The second inorganic layer 232 is located on the first inorganic layer 231.

[0067] The first inorganic layer 231 may have higher adhesion to the conductive layer 25 than the second inorganic layer 232. The second inorganic layer 232 may have a lower relative dielectric constant than the first inorganic layer 231. For example, the first inorganic layer 231 may contain a silicon nitride such as SiN, and the second inorganic layer 232 may contain a silicon oxide such as SiO2.

[0068] The thickness of the first inorganic layer 231 may be smaller than the thickness of the second inorganic layer 232. The thickness of the first inorganic layer 231 is, for example, 0.05 μm or more, optionally 0.1 μm or more, or optionally 0.2 μm or more. The thickness of the first inorganic layer 231 is, for example, 2 μm or less, optionally 1 μm or less, or optionally 0.5 μm or less. The thickness of the second inorganic layer 232 is, for example, 0.1 μm or more, optionally 0.2 μm or more, or optionally 0.5 μm or more. The thickness of the second inorganic layer 232 is, for example, 5 μm or less, optionally 2 μm or less, or optionally 1 μm or less.

[0069] The conductive layer 25 includes a material having electrical conductivity. The conductive layer 25 may include a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these. The thickness T3 of the conductive layer 25 is, for example, 0.1 μm or more, or may be 0.5 μm or more, or may be 1 μm or more. The thickness T3 of the conductive layer 25 is, for example, 10 μm or less, or may be 6 μm or less.

[0070] 4, the conductive layer 25 may include a seed layer 252 and a plating layer 253. The seed layer 252 is a conductive layer formed by physical film formation such as sputtering. The plating layer 253 is a conductive layer formed on the seed layer 252 by electrolytic plating. The conductive layer 25 may include an adhesion layer 251 located between the insulating layer 21 and the seed layer 252. The adhesion layer 251 is also a conductive layer.

[0071] The material of the adhesion layer 251 is different from the material of the seed layer 252 and the material of the plating layer 253. Examples of materials for the adhesion layer 251 include titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, and oxides, nitrides, compounds, and alloys thereof. The adhesion layer 251 may be a single layer or a laminate of multiple layers. The adhesion layer 251 may have higher adhesion to the insulating layer 21 than the seed layer 252.

[0072] The seed layer 252 may contain a metal material such as copper, nickel, titanium, chromium, zinc, or gold. The seed layer 252 may also contain a compound of these metal materials. The seed layer 252 may include multiple layers. The plating layer 253 may contain a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these metals.

[0073] In the above, the length L1 of the wiring region 15 and the width W1 of the cutting region 16 are calculated based on a planar image of the wiring board group 10 taken by a scanning electron microscope. The thickness of the carrier substrate 12, the thickness of the release layer 13, the thickness of the light-reflecting layer 14, the thickness of the wiring layer 20, and the thickness of the conductive layer 25 are calculated based on a cross-sectional image of the wiring board group 10 taken by a scanning electron microscope. The thickness of the inorganic layer 23 is measured by a non-contact optical measurement method, and is a value measured by a spectroscopic ellipsometry measuring instrument. An example of a measuring instrument is the spectroscopic ellipsometry measuring instrument "RE-3500" manufactured by SCREEN Semiconductor Solutions.

[0074] (Method of manufacturing a wiring board group) Next, a method for manufacturing the wiring board group 10 will be described. Figures 5 to 15 are cross-sectional views for explaining the method for manufacturing the wiring board group 10. The method for manufacturing the wiring board group 10 includes a carrier substrate preparation step, a release layer formation step, a light reflecting layer formation step, and a wiring layer formation step.

[0075] First, a carrier substrate preparation step is performed in which the carrier substrate 12 is prepared.

[0076] Next, a release layer forming step is performed. In the release layer forming step, as shown in FIG. 5, a release layer 13 is formed on the carrier substrate 12. More specifically, the release layer 13 is formed on the flat surface 121 of the carrier substrate 12. The release layer forming step includes, for example, a coating step and a drying step. In the coating step, a solution containing a resin and a solvent is applied to the flat surface 121 of the carrier substrate 12. In the drying step, after the coating step, the solvent is evaporated. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying step includes, for example, a step of heating the carrier substrate 12.

[0077] Next, a light-reflecting layer forming step is carried out. In the light-reflecting layer forming step, as shown in Fig. 6, a light-reflecting layer 14 is formed on a carrier substrate 12. More specifically, the light-reflecting layer 14 is formed on a release layer 13. The light-reflecting layer 14 is formed by, for example, a sputtering method.

[0078] Thereafter, a wiring layer forming process is carried out. In the wiring layer forming process, a wiring layer 20 is formed on the carrier substrate 12. More specifically, the wiring layer 20 is formed on the light reflecting layer 14. The wiring layer 20 is formed on the carrier substrate 12 in the wiring region 15. More specifically, the wiring layer 20 is formed on the light reflecting layer 14 in the wiring region 15.

[0079] The wiring layer forming process includes, for example, a first wiring layer forming process and a second wiring layer forming process. In the first wiring layer forming process, a first wiring layer 20A is formed on the light reflecting layer 14. In the second wiring layer forming process, a second wiring layer 20B is formed on the first wiring layer 20A. The wiring layer forming process also includes a conductive layer forming process and an insulating layer forming process. For example, the first wiring layer forming process and the second wiring layer forming process each include a conductive layer forming process and an insulating layer forming process. In the conductive layer forming process, a conductive layer 25 is formed. In the insulating layer forming process, an insulating layer 21 is formed so as to at least partially cover the conductive layer 25.

[0080] In the conductive layer forming step, as shown in FIG. 7 , a conductive layer 25 is formed on the light reflecting layer 14 in the wiring region 15. For example, first, an adhesion layer 251 and a seed layer 252 are formed on the light reflecting layer 14 by sputtering. Next, a resist layer is formed on the seed layer 252 in a position where the conductive layer 25 is not to be formed. Next, a plating layer 253 is formed by electrolytic plating on the portions of the adhesion layer 251 and the seed layer 252 that are not covered by the resist layer. Thereafter, the resist layer and the adhesion layer 251 and the seed layer 252 that overlap the resist layer are removed. In this manner, the conductive layer 25 including the adhesion layer 251, the seed layer 252, and the plating layer 253 is formed.

[0081] The insulating layer forming step includes an inorganic layer forming step and an organic layer forming step. A thickness measurement step may be provided between the inorganic layer forming step and the organic layer forming step.

[0082] First, in the inorganic layer forming step, as shown in Fig. 8, the inorganic layer 23 is formed so as to at least partially cover the conductive layer 25. The inorganic layer 23 is formed so as to extend from the wiring region 15 to the cutting region 16. The inorganic layer 23 is formed so as to straddle the plurality of wiring regions 15 and the cutting region 16. The inorganic layer 23 is formed in the cutting region 16 so as to have parallel surfaces 233. The inorganic layer 23 is formed by, for example, a CVD method.

[0083] Next, in the thickness measurement step, as shown in FIG. 9, the thickness of the inorganic layer 23 is measured in the cutting region 16. The thickness of the inorganic layer 23 is measured by a non-contact optical measurement method. The thickness of the inorganic layer 23 is measured by spectroscopic ellipsometry. More specifically, in the cutting region 16, polarized incident light L1 is irradiated from an irradiation unit 31 toward the inorganic layer 23, and the reflected light L2 is received by a light receiving unit 32. The thickness (film thickness) of the inorganic layer 23 is calculated from the change in the polarization state. In this way, the thickness of the inorganic layer 23 of the first wiring layer 20A is measured.

[0084] Subsequently, in the organic layer formation step, an organic layer 22 is formed on the inorganic layer 23, as shown in FIG. 10. The organic layer 22 is formed so as to cover the inorganic layer 23. The organic layer 22 is formed continuously from the wiring region 15 to the cutting region 16. The organic layer 22 is formed so as to straddle a plurality of wiring regions 15 and cutting regions 16. For example, the organic layer 22 is formed by applying an organic material onto the inorganic layer 23 by spin coating. In this way, the first wiring layer 20A is formed, as shown in FIG.

[0085] 11, a conductive layer 25 is formed on the first wiring layer 20A in the wiring region 15. Here, openings may be formed in the inorganic layer 23 and the organic layer 22 of the first wiring layer 20A so that parts of the conductive layer 25 form through electrodes 28.

[0086] 12, in the inorganic layer forming step, the inorganic layer 23 is formed so as to at least partially cover the conductive layer 25. The inorganic layer 23 is formed so as to extend from the wiring region 15 to the cutting region 16. The inorganic layer 23 is formed so as to straddle a plurality of wiring regions 15 and the cutting region 16. The inorganic layer 23 is formed in the cutting region 16 so as to have parallel surfaces 233. The inorganic layer 23 is formed by, for example, a CVD method.

[0087] Next, in the thickness measurement step, as shown in FIG. 13, the thickness of the inorganic layer 23 is measured in the cutting region 16. As in the case described with reference to FIG. 9, the thickness of the inorganic layer 23 is measured by a non-contact optical measurement method. The thickness of the inorganic layer 23 is measured by spectroscopic ellipsometry. More specifically, in the cutting region 16, polarized incident light L1 is irradiated from an irradiation unit 31 toward the inorganic layer 23, and the reflected light L2 is received by a light receiving unit 32. The thickness (film thickness) of the inorganic layer 23 is calculated from the change in the polarization state. In this way, the thickness of the inorganic layer 23 of the second wiring layer 20B is measured.

[0088] Here, for example, even if the wiring board group 10 includes a core substrate with electrodes instead of the carrier substrate 12, and the wiring layer 20 is formed on the surface of the core substrate without the light reflecting layer 14, the angle of incidence is adjusted to reflect the incident light L1 irradiated from the irradiation unit 31. Furthermore, although not shown, the thickness of the inorganic layer 23 may be estimated by irradiating light perpendicularly onto the substrate from above the wiring board group 10, transmitting the light through the substrate, detecting the light transmitted from the opposite surface of the substrate, and checking the rate of decrease in transmittance.

[0089] Subsequently, in the organic layer forming step, an organic layer 22 is formed on the inorganic layer 23, as shown in FIG. 14. The organic layer 22 is formed so as to cover the inorganic layer 23. The organic layer 22 is formed continuously from the wiring region 15 to the cutting region 16. The organic layer 22 is formed so as to straddle a plurality of wiring regions 15 and cutting regions 16. For example, the organic layer 22 is formed by applying an organic material onto the inorganic layer 23 by spin coating. In this way, the second wiring layer 20B is formed, as shown in FIG. 14.

[0090] 15, a conductive layer 25 is formed on the second wiring layer 20B in the wiring region 15. Here, openings may be formed in the inorganic layer 23 and the organic layer 22 of the second wiring layer 20B so that parts of the conductive layer 25 form through electrodes 28. The conductive layer 25 may also include pads 26.

[0091] In this way, a wiring board group 10 as shown in FIG. 15 is obtained.

[0092] In the above description, the thickness measurement step is performed between the inorganic layer formation step and the organic layer formation step. However, this is not limiting, and the thickness measurement step may be performed at any timing after the inorganic layer formation step and before the cutting step described below. For example, the thickness measurement step may be performed after the organic layer formation step and before the subsequent conductive layer formation step. Furthermore, for example, the thickness measurement step may be performed after the wiring substrate group 10 is obtained and before the cutting step described below.

[0093] (Method of manufacturing a wiring board) Next, a method for manufacturing wiring board 11 will be described. Figures 16 to 19 are cross-sectional views for explaining the method for manufacturing wiring board 11. The method for manufacturing wiring board 11 includes a wiring board group preparation step and a cutting step.

[0094] First, a wiring board group preparation step is carried out. In the wiring board group preparation step, the above-described wiring board group 10 is prepared. The wiring board group 10 may be manufactured by the above-described method for manufacturing the wiring board group 10.

[0095] Next, a cutting process is performed. In the cutting process, the wiring board group 10 is cut in cutting regions 16 as shown in Fig. 16. This results in a plurality of wiring boards 11. Here, each wiring board 11 includes a carrier substrate 12, a release layer 13, a light reflecting layer 14, and a wiring layer 20.

[0096] A bonding process may be performed after the cutting process. In the bonding process, as shown in FIGS. 17 and 18 , the wiring board 11 is bonded to a substrate 81. The substrate 81 may include a base material 811, a plurality of terminals 812, and an adhesive layer 813. The plurality of terminals 812 are located on the base material 811. The adhesive layer 813 is located on the base material 811 so as to cover the plurality of terminals 812. The adhesive layer 813 may be provided on the wiring board 11. In the bonding process, as shown in FIG. 18 , the pads 26 of the wiring layer 20 of the wiring board 11 may be electrically connected to the terminals 812 of the substrate 81.

[0097] Subsequently, a peeling process may be performed. In the peeling process, the wiring layer 20 is peeled from the carrier substrate 12 as shown in FIGS. 18 and 19. The peeling process may include an irradiation process. In the irradiation process, light L3 is irradiated onto the peeling layer 13 as shown in FIG. 18. In the irradiation process, the light L3 may reach the peeling layer 13 after passing through the carrier substrate 12. The peeling layer 13 may be decomposed by heat generated by the irradiation of light L3. The decomposition reduces the adhesion between the carrier substrate 12 and the wiring layer 20. Therefore, as shown in FIG. 19, the wiring layer 20 is transferred from the carrier substrate 12 to the substrate 81.

[0098] Thereafter, a light-shielding layer removing step may be performed. In the light-shielding layer removing step, the light-shielding layer 14 is removed from the structure including the transferred wiring layer 20, as shown in Fig. 19. The light-shielding layer 14 may be removed by, for example, an etching method.

[0099] The structure including the transferred wiring layer 20 includes a substrate 81 and the wiring layer 20. The wiring layer 20 is located on the substrate 81. This structure may also be referred to as a wiring substrate. In the wiring substrate shown in FIG. 19, an upper surface 202 of the wiring layer 20 faces the substrate 81.

[0100] Although not shown, the method of use and distribution of the wiring layer 20 are not particularly limited. For example, a semiconductor element may be mounted on the lower surface 201 of the wiring layer 20. The semiconductor element may include a transistor formed of a semiconductor such as silicon. The semiconductor element may be, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like. The semiconductor element may be, for example, a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, a memory, or the like are divided according to function.

[0101] Although not shown, the wiring layer 20 may be manufactured on a member including a conductive layer such as a terminal 812, such as a substrate 81. In this case, the wiring layer 20 is used with the lower surface 201 of the wiring layer 20 facing the substrate 81. In this case, a semiconductor element may be mounted on the upper surface 202 of the wiring layer 20.

[0102] The wiring layer 20 may be distributed in the form of a wiring board group 10. The wiring layer 20 may be distributed in the form of a wiring board 11. The wiring layer 20 may be distributed after being transferred from the carrier substrate 12 to the substrate 81.

[0103] According to this embodiment, the inorganic layer 23 extends from the wiring region 15 to the cutting region 16. This allows the thickness of the inorganic layer 23 to be measured in the cutting region 16 by a non-contact optical measurement method during the manufacturing of the wiring board group 10. When measuring the thickness of the inorganic layer 23 by a non-contact optical measurement method, the presence of the wiring 27 having a fine pattern included in the wiring layer 20 in the wiring region 15 causes light scattering, which may prevent accurate measurement of the thickness of the inorganic layer 23. Therefore, by measuring the thickness of the inorganic layer 23 in the cutting region 16, which does not include the wiring 27, as in this embodiment, the thickness of the inorganic layer 23 can be accurately measured. As a result, it is possible to reliably confirm whether the inorganic layer 23 has been properly formed in the wiring layer formation step during the manufacturing of the wiring board group 10.

[0104] Furthermore, according to this embodiment, the inorganic layer 23 has a parallel surface 233 in the cutting region 16 that is parallel to the flat surface 121 of the carrier substrate 12. This parallel surface 233 can prevent the incident light L1 irradiated from the irradiating unit 31 from being diffusely reflected by the inorganic layer 23 when measuring the thickness of the inorganic layer 23. This allows the thickness of the inorganic layer 23 to be measured more accurately.

[0105] Furthermore, according to this embodiment, the width W1 of the cutting region 16 is 1 μm or more. This allows the width W1 of the cutting region 16 to be larger than the spot size of the incident light L1 irradiated from the irradiation unit 31 when measuring the thickness of the inorganic layer 23. This makes it possible to prevent the incident light L1 irradiated from the irradiation unit 31 from being diffusely reflected by the inorganic layer 23. This allows the thickness of the inorganic layer 23 to be measured more accurately.

[0106] Furthermore, according to this embodiment, the light-reflecting layer 14 is located between the carrier substrate 12 and the inorganic layer 23. This allows the incident light L1 irradiated from the irradiating unit 31 to be more reliably specularly reflected when measuring the thickness of the inorganic layer 23. This improves the measurement accuracy of the non-contact optical measurement method. As a result, the thickness of the inorganic layer 23 can be measured even more accurately.

[0107] The above-described embodiment can be modified in various ways. Below, modified examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in modified examples, the description of those effects may be omitted.

[0108] (First Modification) Fig. 20 is a cross-sectional view showing a wiring board group 10 according to a first modified example. In the example shown in Fig. 3, in both the first wiring layer 20A and the second wiring layer 20B, the insulating layer 21 includes the inorganic layer 23. However, this is not limited thereto, and as shown in Fig. 20, in the first wiring layer 20A, the insulating layer 21 may not include the inorganic layer 23, and in the second wiring layer 20B, the insulating layer 21 may include the inorganic layer 23. In this way, it is sufficient that the insulating layer 21 includes the inorganic layer 23 in at least one wiring layer among the plurality of wiring layers.

[0109] (Second Modification) Fig. 21 is a cross-sectional view showing a wiring substrate group 10 according to a second modified example. In the example shown in Fig. 3, the organic layer 22 is continuously formed from the wiring region 15 to the cutting region 16. However, this is not limiting, and as shown in Fig. 21, the organic layer 22 does not have to be formed in the cutting region 16. In the example shown in Fig. 21, the organic layer 22 includes an opening 221 formed in the cutting region 16. That is, in the cutting region 16, the opening 221 is formed in the organic layer 22 of the wiring layer 20.

[0110] 21 , the organic layer 22 includes an opening formed in the cutting region 16. In the example shown in Fig. 21 , the opening 221 includes a first opening 221A formed in the organic layer 22 of the first wiring layer 20A and a second opening 221B formed in the organic layer 22 of the second wiring layer 20B. That is, the organic layer 22 of the first wiring layer 20A includes the first opening 221A formed in the cutting region 16, and the organic layer 22 of the second wiring layer 20B includes the second opening 221B formed in the cutting region 16.

[0111] The first opening 221A and the second opening 221B may overlap in a plan view. As shown in FIG. 21 , the width W2 of the first opening 221A and the width W3 of the second opening 221B may be equal. The width W2 of the first opening 221A may be equal to the width W1 of the cutting region 16. The width W2 of the first opening 221A may be greater or smaller than the width W1 of the cutting region 16. The width W3 of the second opening 221B may be equal to the width W1 of the cutting region 16. The width W2 of the second opening 221B may be greater or smaller than the width W1 of the cutting region 16. The width W2 of the first opening 221A is the maximum dimension of the first opening 221A in the first direction D1 or the second direction D2. The width W3 of the second opening 221B is the maximum dimension of the second opening 221B in the first direction D1 or the second direction D2.

[0112] 21, the openings 221 may penetrate the organic layer 22. That is, the first openings 221A may penetrate the organic layer 22 of the first wiring layer 20A, and the second openings 221B may penetrate the organic layer 22 of the second wiring layer 20B. In this case, as shown in FIG. 21, in the cutting region 16, the inorganic layer 23 of the first wiring layer 20A and the inorganic layer 23 of the second wiring layer 20B may overlap so as to be in contact with each other.

[0113] 22 to 24 are cross-sectional views illustrating a method for manufacturing a wiring board group 10 according to a second modified example. In the method for manufacturing a wiring board group 10 according to the second modified example, after forming a first wiring layer 20A as shown in FIG. 10, first openings 221A are formed in the organic layer 22 of the first wiring layer 20A as shown in FIG. 22. The first openings 221A are formed by, for example, dry etching. If the organic layer 22 is photosensitive, the first openings 221A may be formed by photolithography. If the organic layer 22 is not photosensitive, the first openings 221A may be formed by removal with an energy beam such as laser light.

[0114] 23 , a conductive layer 25 and an inorganic layer 23 are formed on the first wiring layer 20A in the wiring region 15. Here, in the cutting region 16, the inorganic layer 23 of the second wiring layer 20B is formed so as to be in contact with the inorganic layer 23 of the first wiring layer 20A. The opening in the organic layer 22 for providing the through electrode 28 may be formed simultaneously with the formation of the first opening 221A, or may be formed separately. In this case, when the opening in the organic layer 22 is formed simultaneously with the first opening 221A or when the opening in the organic layer 22 is formed after the formation of the first opening 221A, the inorganic layer 23 exposed from the first opening 221A may be covered with an etching mask such as a resist when removing the inorganic layer 23 at the bottom of the opening in the organic layer 22.

[0115] Next, as shown in FIG. 24, the thickness of the inorganic layer 23 is measured in the cutting region 16. The thickness of the inorganic layer 23 is measured by a non-contact optical measurement method. The thickness of the inorganic layer 23 is measured by spectroscopic ellipsometry. More specifically, in the cutting region 16, polarized incident light L1 is irradiated from an irradiation unit 31 toward the inorganic layer 23, and the reflected light L2 is received by a light receiving unit 32, and the thickness (film thickness) of the inorganic layer 23 is calculated from the change in the polarization state. In this way, the thickness of the inorganic layer 23 of the second wiring layer 20B is measured.

[0116] Thereafter, the organic layer 22 is formed on the inorganic layer 23 to form the second wiring layer 20B, and the second opening 221B is formed in the organic layer 22 of the second wiring layer 20B. The second opening 221B is formed by, for example, dry etching. If the organic layer 22 is photosensitive, the second opening 221B may be formed by photolithography. If the organic layer 22 is not photosensitive, the second opening 221B may be formed by removal with an energy beam such as laser light.

[0117] According to this modification, the organic layer 22 includes the opening 221 formed in the cutting region 16, and thus, when measuring the thickness of the inorganic layer 23, it is possible to prevent the incident light L1 irradiated from the irradiation unit 31 from being diffusely reflected in the organic layer 22. As a result, the thickness of the inorganic layer 23 can be measured more accurately.

[0118] (Third Modification) FIG. 25 is a cross-sectional view showing a wiring board group 10 according to a third modified example. In the example shown in FIG. 21, the opening 221 includes a first opening 221A formed in the organic layer 22 of the first wiring layer 20A and a second opening 221B formed in the organic layer 22 of the second wiring layer 20B. However, this is not limited thereto. As shown in FIG. 25, the opening 221 may include the second opening 221B without including the first opening 221A. That is, the opening 221 may be formed by the second opening 221B formed in the organic layer 22 of the second wiring layer 20B. In this case, as shown in FIG. 25, the second opening 221B may overlap the organic layer 22 of the first wiring layer 20A in a plan view.

[0119] (Fourth Modification) FIG. 26 is a cross-sectional view showing a wiring board group 10 according to a fourth modified example. In the example shown in FIG. 21, the opening 221 includes a first opening 221A formed in the organic layer 22 of the first wiring layer 20A and a second opening 221B formed in the organic layer 22 of the second wiring layer 20B. However, this is not limiting. As shown in FIG. 26, the opening 221 may include the first opening 221A but not the second opening 221B. That is, the opening 221 may be formed by the first opening 221A formed in the organic layer 22 of the first wiring layer 20A. In this case, as shown in FIG. 26, the first opening 221A may be filled with the organic layer 22 of the second wiring layer 20B.

[0120] (Fifth Modification) Fig. 27 is a cross-sectional view showing a wiring board group 10 according to a fifth modified example. In the example shown in Fig. 21, the width W2 of the first opening 221A and the width W3 of the second opening 221B are equal. However, this is not limited to this, and as shown in Fig. 27, the width W3 of the second opening 221B may be larger than the width W2 of the first opening 221A. In this case, as shown in Fig. 27, a step may be formed between the first opening 221A and the second opening 221B.

[0121] (Sixth Modification) Fig. 28 is a cross-sectional view showing a wiring substrate group 10 according to a sixth modified example. In the example shown in Fig. 21, the width W2 of the first opening 221A and the width W3 of the second opening 221B are equal. However, this is not limiting, and as shown in Fig. 28, the width W3 of the second opening 221B may be smaller than the width W2 of the first opening 221A. In this case, as shown in Fig. 28, the organic layer 22 of the second wiring layer 20B may extend into a part of the first opening 221A, particularly near the wall of the first opening 221A.

[0122] (Example of a product equipped with a wiring layer) 29 is a diagram showing an example of a product equipped with the wiring layer 20. The wiring layer 20 can be used in a variety of products. For example, the wiring layer 20 is equipped in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

[0123] The components disclosed in the above-described embodiment and the above-described modified examples may be appropriately combined as needed. [Explanation of symbols]

[0124] 10. Wiring board group 11 Wiring board 12 Carrier board 121 Flat surface 14 Light reflective layer 15 Wiring area 16 cutting area 20 wiring layer 21 Insulating layer 22 Organic layer 221 Aperture 23 Inorganic layer 233 Parallel Planes 25 Conductive layer

Claims

1. A wiring board group including a plurality of wiring regions and a cutting region located between adjacent wiring regions, a carrier substrate; a wiring layer located on the carrier substrate in the wiring region; the wiring layer includes a conductive layer and an insulating layer at least partially covering the conductive layer; the insulating layer includes an inorganic layer at least partially covering the conductive layer and an organic layer located on the inorganic layer; The inorganic layer extends from the wiring region to the cutting region.

2. the carrier substrate includes a flat surface facing the wiring layer; The wiring board group according to claim 1 , wherein the inorganic layer includes a surface parallel to the flat surface in the cutting region.

3. The wiring board group according to claim 1 , wherein the width of the cutting region is 1 μm or more.

4. The wiring substrate group of claim 1 , further comprising a light-reflecting layer located between the carrier substrate and the inorganic layer.

5. The wiring board group according to claim 1 , wherein the organic layer is formed continuously from the wiring region to the cutting region.

6. The wiring board group according to claim 1 , wherein the organic layer includes an opening formed in the cutting region.

7. the wiring layer includes a plurality of the wiring layers, The wiring board group according to claim 1 , wherein the insulating layer includes the inorganic layer in at least one of the plurality of wiring layers.

8. The wiring board group according to claim 7 , wherein the organic layer in at least one of the plurality of wiring layers includes an opening formed in the cutting region.

9. A method for manufacturing a wiring board group including a plurality of wiring regions and a cutting region located between adjacent wiring regions, the method comprising: a carrier substrate preparation step of preparing a carrier substrate; a wiring layer forming step of forming a wiring layer on the carrier substrate in the wiring region, the wiring layer forming step includes a conductive layer forming step of forming a conductive layer, and an insulating layer forming step of forming an insulating layer so as to at least partially cover the conductive layer, the insulating layer forming step includes an inorganic layer forming step of forming an inorganic layer so as to at least partially cover the conductive layer, and an organic layer forming step of forming an organic layer on the inorganic layer, In the inorganic layer forming step, the inorganic layer is formed so as to extend from the wiring region to the cutting region.

10. The method for manufacturing a wiring board group according to claim 9 , further comprising a thickness measurement step of measuring a thickness of the inorganic layer in the cutting region.

11. A method for manufacturing a wiring substrate, a wiring board group preparation step of preparing the wiring board group according to any one of claims 1 to 8; a cutting step of cutting the wiring substrate group in the cutting region.

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