Oscillation period matching device, method, memory and computer-readable medium

Abstract

This invention provides an oscillation period matching device, method, memory, and computer-readable medium capable of accurately matching the oscillation period of an oscillator unit with the output signal delay of a matching object with a simple structure, without requiring additional calibration commands. The oscillation period matching device includes: a matching object unit whose output signal is delayed relative to an input signal by a certain delay; an oscillation unit that generates a pulse signal oscillating with an oscillation period and inputs the pulse signal as the input signal to the matching object unit; and a calibration unit that obtains the output signal from the matching object unit, obtains the pulse signal from the oscillation unit, compares the output signal and the pulse signal, and outputs a calibration signal to the oscillation unit based on the comparison result to calibrate the oscillation period, thereby matching the oscillation period with the delay.

Description

Technical Field

[0001] This invention relates to an oscillation period matching device, and more particularly to an oscillation period matching device for matching the oscillation period of a DQS intermittent oscillator used in the field of memory technologies such as DDR5 / LPDDR4, an oscillation period matching method, a computer-readable medium storing a program that results in executing the oscillation period matching method, and a memory equipped with the oscillation period matching device. Background Technology

[0002] In the field of memory such as DDR5 and LPDDR4, the DQS signal is often used as a data strobe signal to control the read and write timing of the data signal DQ. Figure 12 This is a circuit diagram illustrating an example of the structure of a data strobe signal processing circuit (hereinafter also referred to as a "DQS2DQ circuit") in the prior art. The DQS2DQ circuit is used to perform the conversion of the differential signals DQS_T and DQS_C of the data strobe signal into read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, which are the timing references for reading and writing the data signal DQ.

[0003] like Figure 12 As shown, the DQS2DQ circuit includes a DQS signal receiver (e.g., a comparator for converting differential signals DQS_T and DQS_C into DQS_OUTd and DQS_OUTb signals) and a series of circuits (including two D latches and multiple inverters) for changing the frequency of the DQS signal to obtain read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db. Finally, the converted read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, along with the data signal DQ, are input to the buffer D_DATA_INPUT_BUFFER. A subsequent circuit (not shown) reads these signals from the buffer and uses the read / write timing signals as the timing reference for data read / write operations.

[0004] As described above, the read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, after being converted by the DQS2DQ circuit, will have a certain delay relative to the DQS signal. To ensure that the delayed read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db are aligned with the DQ signal, it is necessary to know the timing deviation between the DQS and DQ signals, i.e., the time delay caused by the DQS2DQ circuit (hereinafter also referred to as "tDQS2DQ"). This allows determining how much earlier the DQS signal needs to be sent compared to the DQ signal, in order to compensate for the optimal set / hold time of the input DQ signal.

[0005] However, since the parameters of the components constituting the DQS2DQ circuit vary from production batch to batch, the aforementioned tDQS2DQ will deviate due to differences in the production batches of the circuit components. Furthermore, the aforementioned tDQS2DQ will also deviate with variations in temperature and voltage. In other words, the time delay tDQS2DQ of this DQS2DQ circuit is affected by PVT (Process, Voltage, Temperature).

[0006] In existing technologies, an oscillator (hereinafter sometimes simply referred to as "OSC"), such as a DQS interval oscillator, is typically used. This DQS interval oscillator is placed in the same temperature and circuit environment as the DQS2DQ circuit to represent its delay. The aforementioned tDQS2DQ is then determined by measuring the oscillation period of the oscillation pulse signal generated by the DQS interval oscillator. This eliminates the influence of PVT on the measurement results of tDQS2DQ. Summary of the Invention

[0007] The technical problem to be solved by the present invention

[0008] In existing technologies, to improve the accuracy of obtaining tDQS2DQ, the oscillation period of the DQS intermittent oscillator is measured multiple times and the average value is calculated to obtain tDQS2DQ. For different PVT conditions, the oscillation period tDQS of the DQS intermittent oscillator is... OSC The required deviation is the average value of OSC between the deviation from the actual time delay tRX_DQS2DQ of the corresponding DQS2DQ circuit. offset That is, the deviation adjustment amount is between -150ps and 150ps, and the adjusted deviation OSC is required to be within the range of -150ps. Match =[tRX_DQS2DQ-tDQS OSC -OSC offset Between -10ps and 10ps.

[0009] However, due to the inherent errors in the parameters of the components constituting the DQS intermittent oscillator, it is difficult to meet the aforementioned average deviation OSC. offset and adjusted deviation OSC Match This raises the issue of specification requirements. Using a less precise OSC to equivalently represent the time delay of the DQS2DQ circuit reduces the timing alignment accuracy of the DQS and DQ signals, thus affecting the accuracy of memory read / write data.

[0010] In addition, although the oscillation period of the OSC can be calibrated by setting additional calibration commands, this will increase the workload of the memory controller and reduce the read and write speed of the memory.

[0011] The present invention was made to solve the above-mentioned problems. Its purpose is to provide an oscillation period matching device, an oscillation period matching method, a computer-readable medium storing a program that executes the oscillation period matching method, and a memory equipped with the oscillation period matching device, which can accurately match the oscillation period of an oscillation unit with the output signal delay of the matching object with a simple structure and without the need for additional calibration commands.

[0012] Technical solutions to solve technical problems

[0013] To address the aforementioned technical problems, the oscillation period matching device according to the first aspect of the present invention includes: a matching target unit, wherein the output signal of the matching target unit is delayed relative to the input signal by a certain delay amount; an oscillation unit, which generates a pulse signal that oscillates with an oscillation period and inputs the pulse signal as the input signal to the matching target unit; and a calibration unit, which obtains the output signal from the matching target unit, obtains the pulse signal from the oscillation unit, compares the output signal with the pulse signal, and outputs a calibration signal to the oscillation unit based on the comparison result to calibrate the oscillation period, thereby matching the oscillation period with the delay amount.

[0014] Furthermore, the memory according to the second aspect of the present invention includes: an oscillation period matching device as described in the first aspect of the present invention, wherein the matching target unit corresponds to a data gating signal processing circuit, the data gating signal processing circuit converts the input data gating signal into a read / write timing signal as a timing reference for reading and writing data in the memory; and a control module, which acquires the pulse signal from the oscillation unit, calculates the oscillation period by counting the pulse signal, and compensates for the time delay between the data gating signal and the read / write timing signal based on the oscillation period, wherein the calibration unit completes the matching of the oscillation period and the delay amount during the counting of the pulse signal by the control module.

[0015] Furthermore, the oscillation period matching method according to the third aspect of the present invention is used in an oscillation period matching device, the oscillation period matching device comprising: a matching target unit, wherein the output signal of the matching target unit is delayed relative to an input signal by a certain delay amount; and an oscillation unit, wherein the oscillation unit generates a pulse signal oscillating with an oscillation period, the oscillation period matching method being characterized in that it includes: a pulse signal input step, wherein the pulse signal is input as the input signal to the matching target unit; and a calibration step, wherein the output signal is obtained from the matching target unit, the pulse signal is obtained from the oscillation unit, the output signal and the pulse signal are compared, and a calibration signal is output to the oscillation unit based on the comparison result to calibrate the oscillation period, such that the oscillation period matches the delay amount.

[0016] Furthermore, the computer-readable medium according to the fourth aspect of the present invention stores a program for executing the oscillation period matching method as described in the third aspect of the present invention.

[0017] Invention Effects

[0018] According to the oscillation period matching device, oscillation period matching method, computer-readable medium storing a program that executes the oscillation period matching method, and memory equipped with the oscillation period matching device, the oscillation period matching device can be performed with high precision in a simple structure, and the matching of the oscillation period of the oscillation unit and the output signal delay of the matching object can be completed with high precision without the need for additional calibration commands. Attached Figure Description

[0019] Figure 1 This is a block diagram representing the structure of a memory equipped with an oscillation period matching device.

[0020] Figure 2 This is a circuit diagram representing an example of the structure of a matching object unit.

[0021] Figure 3 This is a circuit diagram illustrating an example of the structure of an oscillating unit.

[0022] Figure 4 This is a circuit diagram illustrating an example of the structure in the calibration unit used to generate calibration direction signals and lock signals.

[0023] Figure 5 This is a circuit diagram illustrating an example of the structure used to generate calibration signals in a calibration unit.

[0024] Figure 6 This is a circuit diagram illustrating an example of the structure used to generate a reset signal in a calibration unit.

[0025] Figure 7 This is a timing diagram illustrating the operation timing of the oscillation period matching device.

[0026] Figure 8 This is a timing diagram illustrating an example of the calibration operation of the calibration unit.

[0027] Figure 9 This is a timing diagram illustrating another example of the calibration action of the calibration unit.

[0028] Figure 10 This is a flowchart illustrating the oscillation period matching method.

[0029] Figure 11 This is a timing diagram illustrating the oscillation period matching method.

[0030] Figure 12 This is a circuit diagram illustrating an example of the structure of a data gating signal processing circuit in the prior art. Detailed Implementation

[0031] The following reference Figures 1-6 The structure of the oscillation period matching device and the memory having the oscillation period matching device according to the present invention will be described.

[0032] Figure 1 This is a block diagram illustrating the structure of a memory equipped with an oscillation period matching device. For example... Figure 1 As shown, the memory involved in this embodiment includes a storage module 100 and a control module 200.

[0033] The storage module 100 is, for example, a DRAM storage module such as DDR5, LPDDR4, or LPDDR5. This storage module 100 includes a DQ receiver 20. Although not shown, the DQ receiver 20 is connected via... Figure 12 The data strobe signal processing circuit, as shown in the example, obtains the data strobe signal DQS from the control module 200 and directly obtains the data signal DQ from the control module 200. Furthermore, as... Figure 1 As shown, the DQ receiver 20 receives the compensation tDQS2DQ signal (described later) from the control module 200, and uses this tDQS2DQ signal to compensate for the delay of the DQ signal relative to the DQS signal, so that... Figure 12 The timing of the delayed read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, as shown, is aligned with the timing of the DQ signal, thereby enabling accurate capture of the data signal DQ using the compensated read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db.

[0034] Alternatively, although not illustrated, after the DQ receiver 20 receives the DQ signal and the delayed DQS signal, the delay of the DQS signal can be compensated for using the tDQS2DQ signal in the subsequent processing circuit, and then the compensated DQS signal can be used to capture the DQ signal. However, in either case, the storage module 100 needs to use tDQS2DQ to compensate for the delay of the DQS signal.

[0035] The storage module 100 also includes an oscillation period matching device 10. For example... Figure 1 As shown, the oscillation period matching device 10 includes a matching object unit 1, an oscillation unit 2, and a calibration unit 3.

[0036] In this embodiment, the matching target unit 1 corresponds to the data gating signal processing circuit described above and is an analog circuit that simulates the data gating signal processing circuit. However, the matching target unit of the present invention is not limited to this; for example, the data gating signal processing circuit described above can also be used directly as the matching target unit. However, since this embodiment uses an analog circuit as the matching target unit 1 to simulate the data gating signal processing circuit, the circuit load in the periodic matching process can be further reduced, and the power consumption of periodic matching can be reduced.

[0037] In addition, as described above, the data strobe signal processing circuit converts the input data strobe signal DQS into read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, which serve as the timing reference for the memory read / write data signal DQ, so that the memory module 100 can use the read / write timing signals to complete data read / write.

[0038] Since the data gating signal processing circuit is simulated using matching target unit 1, the output signal of matching target unit 1 is delayed relative to the input signal by a certain amount of delay (in this embodiment, the timing delay tDQS2DQ between the data gating signal DQS and the read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, i.e., the data signal DQ). Furthermore, although the read / write timing signals that serve as the output signal of the data gating signal processing circuit are DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, the timing deviation between DQS_Ab and DQS_Bb is known, and it is known that DQS_Ab and DQS_Cb, as well as DQS_Bb and DQS_Db, are out of phase. Therefore, in this embodiment, DQS_Cb is used as the representative output signal of matching target unit 1.

[0039] In this embodiment, the oscillation unit 2 is a DQS intermittent oscillator that generates a pulse signal OSC_O that oscillates with an oscillation period tOSC. However, the oscillation unit 2 of the present invention is not limited to this; any oscillator capable of generating oscillation pulses with a certain oscillation period can be applied to the present invention. For example... Figure 1 As shown, the oscillation unit 2 inputs the generated pulse signal OSC_O as an input signal to the matching target unit 1, so as to achieve matching of tOSC and tDQS2DQ between the matching target unit 1 and the oscillation unit 2.

[0040] Calibration unit 3 obtains the output signal DQS_Cb from matching unit 1 and the pulse signal OSC_O from oscillation unit 2. It compares the output signal DQS_Cb with the pulse signal OSC_O and generates a calibration signal CNT_U<1∶0> / CNT_D<1∶0> based on the comparison result to calibrate the oscillation period tOSC, ensuring that the oscillation period tOSC matches the delay tDQS2DQ. The specific method by which calibration unit 3 calibrates the oscillation period tOSC will be explained in detail later.

[0041] In addition, calibration unit 3 includes a calibration signal generation unit, a signal locking unit, and a reset unit, which will be described later. The specific structure and operation of matching unit 1, oscillation unit 2, and calibration unit 3 will be explained in detail later.

[0042] The control module 200 obtains the oscillation pulse signal OSC_O from the oscillation unit 2, and uses its internal counter (not shown) to count the pulse signal OSC_O, thereby calculating the oscillation period tOSC of the pulse signal OSC_O.

[0043] Specifically, there are two ways to calculate the oscillation period. One way is to use the Multiple Purpose Command (MPC) to set the oscillation start and stop times of oscillation unit 2. Then, the control module 200 calculates the oscillation period tOSC based on the time interval between the oscillation start and stop times of oscillation unit 2 and the oscillation period count value of the OSC_O signal obtained by the counter. The other way is to use the MPC to set a timer. During the time interval between the timer's start and stop, a counter is used to count the pulse signal OSC_O. Then, the control module 200 calculates the oscillation period tOSC based on the timer's timing interval and the counter's count value. Typically, the timer can be set to 8192 cycles. The oscillation period tOSC is obtained by calculating the average value of the cycle duration. In other words, the oscillation period tOSC can be calculated within 8192 cycles starting from the start of oscillation unit 2.

[0044] After calculating the oscillation period tOSC of oscillation unit 2, control module 200 uses this oscillation period tOSC to compensate for the timing delay tDQS2DQ between the data strobe signal DQS and the read / write timing signals DQS_Ab, DQS_Bb, DQS_Cb, and DQS_Db, i.e., the data signal DQ. In other words, control module 200 uses the oscillation period tOSC of oscillation unit 2 as the time delay tDQS2DQ to complete the timing compensation between the DQS and DQ signals.

[0045] In this embodiment, since the calibration of the oscillation period tOSC of the oscillation unit 2 by the calibration unit 3 does not affect the counting of the pulse signal OSC_O by the control module 200, and as described later, after the DQS intermittent oscillator is started, the calibration unit 3 can automatically complete the calibration of the oscillation period within approximately 6 cycles. Therefore, the matching of the oscillation period tOSC and the delay amount tDQS2DQ can be completed during the counting of the pulse signal OSC_O by the control module 200, i.e., during the period between "starting the DQS intermittent oscillator" and "stopping the DQS intermittent oscillator". In other words, the calibration of the oscillation period and the ongoing counting of the oscillation period of the DQS intermittent oscillator can be performed simultaneously. Therefore, no additional calibration commands and timing are required, which can improve the working efficiency of the memory and save data resources.

[0046] The following describes the structural examples of the matching object unit, the oscillation unit, and the calibration unit.

[0047] Figure 2 This is a circuit diagram representing an example of the structure of a matching object unit. For example... Figure 2As shown, the matching unit involved in this embodiment is an analog circuit (hereinafter also referred to as "DQS2DQ MIMIC", or simply "MIMIC") that simulates the data gating signal processing circuit. This analog circuit consists of a comparator, a D latch, and multiple inverters. The differential signals DQS_T and DQS_C of the analog data gating signal are used as input signals and input to the comparator in the DQS2DQ MIMIC. The comparator converts the differential signal into a rectangular wave signal DQS_OUTd and outputs it to the clock signal terminal CK of the D latch. The positive input terminal D of the D latch is always kept at a high level "H", the inverting input terminal Db is always kept at a low level "L", and its reset terminal RST receives a reset signal RST. As a result, the falling edge of the output signal q0b of the inverting output terminal Qb of the D latch follows the rising edge of the DQS_OUTd signal, i.e., the DQS_T signal, and the rising edge of the q0b signal follows the rising edge of the RST signal. After being delayed by two inverters, the q0b signal is converted into a lower-frequency DQS_R2 signal, and after passing through another inverter, it is converted into an output signal that simulates the read / write timing signal DQS_Cb and is then output. Using the aforementioned DQS2DQ MIMIC, the time delay of the data gating signal processing circuit can be accurately simulated.

[0048] Regarding the source of the RST signal, it can be generated either by other signal generation circuits added to the memory circuitry, or by the reset unit in the calibration unit. This will be explained in detail later.

[0049] The generation of the DQS_Cb signal has been explained above. Since the DQS_Ab signal is only out of phase with the DQS_Cb signal and its generation method is similar to that of the DQS_Cb signal, the explanation is omitted here.

[0050] In addition, through the Figure 2 Analog circuits in Figure 12A comparison with the data gating signal processing circuit reveals that this analog circuit only includes a D latch and an inverter series circuit for generating two read / write timing signals DQS_Ab and DQS_Cb, but does not include another D latch and an inverter series circuit for generating two more read / write timing signals DQS_Bb and DQS_Db. This is because the read / write timing signals DQS_Bb and DQS_Db are only out of phase with the read / write timing signals DQS_Ab and DQS_Cb. Knowing the time delay between the input signal DQS_T and the output signal DQS_Cb allows the calculation of the delay tDQS2DQ of the simulated data gating signal processing circuit. Therefore, there is no need to simulate the circuit used to generate the read / write timing signals DQS_Bb and DQS_Db, further simplifying the circuit structure, reducing the circuit load during periodic matching, and lowering the production cost of the memory.

[0051] Figure 3 This is a circuit diagram illustrating an example of the structure of an oscillating unit. For example... Figure 3 As shown, the oscillation unit includes a NAND gate and multiple inverters connected in series with the NAND gate. The oscillation start signal OSC_EN is input to the NAND gate, and the oscillator output signal OSC_O, which is delayed by each inverter, is fed back to the NAND gate, thereby generating a pulse signal OSC_O that oscillates with an oscillation period tOSC.

[0052] In addition, such as Figure 3 As shown, the oscillation unit includes two sets of delay time adjustment sections, which are connected in series between multiple inverters and are respectively connected by capacitors C in parallel. U1 ~C U3 and its corresponding switching elements, and capacitor C D1 ~C D3 It consists of the capacitor C and its corresponding switching element. U1 ~C U3 The corresponding switching element is controlled by the calibration signal CNT_U<1∶0>, and is related to capacitor C. D1 ~C D3 The corresponding switching elements are controlled by the calibration signal CNT_D<1∶0>. Specifically, the calibration signal CNT_D<1∶0> increases the delay time td, thereby lengthening the oscillation period tOSC of the pulse signal OSC_O. Conversely, the calibration signal CNT_D<1∶0> decreases the delay time td, thereby shortening the oscillation period tOSC of the pulse signal OSC_O.

[0053] like Figure 3 As shown, one way to achieve calibration signal adjustment is, for example, to set two binary digits to correspond to three capacitors C.U1 ~C U3 The switching states of the corresponding switching elements are controlled, with the default value set to "00", meaning all three switches are in the off state ("0" represents the switch state as off). Then, based on the judgment result of the calibration signal generation unit in the calibration unit described later, CNT_U<1∶0> is gradually increased to close the three switches one by one until all three switches are closed. This delay time adjustment unit controlled by the calibration signal CNT_U<1∶0> is called an "invalid delay unit".

[0054] Conversely, two binary digits can be set to correspond to three capacitors C. D1 ~C D3 The switching states of the corresponding switching elements are controlled, with the default value set to "11", meaning all three switches are closed ("1" represents a closed switch state). Then, based on the judgment result of the calibration signal generation unit in the calibration unit described later, CNT_D<1∶0> is gradually decreased to open the three switches one by one until all three switches are open. This delay time adjustment unit, controlled by the calibration signal CNT_D<1∶0>, is called an "effective delay unit".

[0055] Through the aforementioned "invalid delay unit" and "valid delay unit", the delay time td of the signal in the oscillation unit can be adjusted step by step, thereby changing the oscillation period tOSC of the pulse signal OSC_O step by step.

[0056] Figure 4 This is a circuit diagram illustrating an example of the structure used in the calibration unit to generate calibration direction signals and lock signals. The calibration direction signal and lock signal generation circuit consists of flip-flops 31-33, an XOR gate, a NAND gate, and an inverter.

[0057] like Figure 4 As shown, the pulse signal OSC_O from the oscillation unit is input to the input terminal D of the flip-flop 31, and the output signal DQS_Cb from the matching target unit is input to the clock pulse terminal of the flip-flop 31. The rising edge of the output signal DQS_Cb is used to sample the pulse signal OSC_O, and the value of the sampled pulse signal OSC_O is output from the output terminal Q of the flip-flop 31 as the calibration direction signal SIDE.

[0058] In addition, such as Figure 4As shown, flip-flop 32, together with a NAND gate, forms a delay circuit. Its function is to delay the DQS_Cb signal (inverted from DQS_Ab) for a short time before inputting it to the clock pulse terminal of flip-flop 33. Furthermore, the calibration direction signal SIDE is input to the input terminal D of flip-flop 33. Thus, the rising edge of the short-delayed output signal DQS_Cb can be used to sample the calibration direction signal SIDE, obtaining the SIDE signal after a very short time and outputting it from the output terminal Q of flip-flop 33. The SIDE signal after the very short time and the SIDE signal from the previous moment are simultaneously input to an XOR gate. At the instant the difference occurs, a pulse signal is output from the XOR gate, and this pulse signal is used as the lock signal LOCK. Therefore, the moment the calibration direction changes can be determined using the lock signal LOCK, and the calibration signal can be locked at that instant, thereby achieving a precise match between tOSC and tDQS2DQ. Furthermore, to facilitate the processing of the locking unit described later, the locking signal LOCK can be converted into an inverted locking signal LOCKb via an inverter.

[0059] Figure 5 This is a circuit diagram illustrating an example of the structure used to generate the calibration signal in a calibration unit. For example... Figure 5 As shown, the calibration signal generation circuit consists of NAND gates, NOR gates, counter 41, counter 42, inverter, locking circuit 43, and locking circuit 44.

[0060] The inverted signal of the delayed output signal DQS_Ab, i.e., the DQS_Cb signal, and Figure 4 The calibration direction signal SIDE generated in the circuit is input to a NAND gate. Therefore, when the calibration direction signal SIDE is high, the timing of the output signal DQS_Ab (DQS_Cb) can be transmitted to the clock pulse terminal of counter 41, thereby counting the period of the output signal DQS_Ab (DQS_Cb). Counter 41 outputs the counting result from the CNT terminal to the lock circuit 43, thereby generating the calibration signal CNT_U<1∶0>. Furthermore, the... Figure 4 The generated lock signal LOCK and the inverted lock signal LOCKb are input to the lock circuit 43, so that the calibration signal CNT_U<1∶0> can be locked at the moment when tOSC and tDQS2DQ are perfectly matched.

[0061] On the other hand, the inverted signal of the delayed output signal DQS_Ab, i.e., the DQS_Cb signal, and Figure 4The calibration direction signal SIDE generated in the circuit is input to a NOR gate. Therefore, when the calibration direction signal SIDE is low, the timing of the output signal DQS_Ab (DQS_Cb) can be transmitted to the clock pulse terminal of counter 42, thereby counting the period of the output signal DQS_Ab (DQS_Cb). Counter 42 outputs the counting result from the CNT terminal via an inverter to the latching circuit 44, thereby generating the calibration signal CNT_D<1∶0>. Additionally, the... Figure 4 The generated lock signal LOCK and the inverted lock signal LOCKb are input to the lock circuit 44, so that the calibration signal CNT_D<1∶0> can be locked at the moment when tOSC and tDQS2DQ are perfectly matched.

[0062] In the above Figure 4 and Figure 5 In the circuit, the part used to generate the calibration direction signal SIDE and generate the calibration signals CNT_U<1∶0> and CNT_D<1∶0> based on the SIDE signal constitutes the calibration signal generation part of the present invention, and the part used to generate the lock signal LOCK and the inverted lock signal LOCKb, as well as the lock circuits 43 and 44, constitute the signal locking part of the present invention.

[0063] Figure 6 This is a circuit diagram illustrating an example of the structure used to generate a reset signal in a calibration unit. Figure 6 The circuit corresponds to the reset section of this invention. For example... Figure 6 As shown, the reset section consists of an inverter, a NAND gate, and a NOR gate. The inverted pulse signal OSC_O and the output signal DQS_Cb of the oscillation unit are input to the NAND gate. The output signal of the NAND gate is input to one input of the NOR gate, and the output signal of the NAND gate is delayed by several inverters before being input to the other input of the NOR gate. Therefore, when the output signal DQS_Cb is high, a pulse signal is generated on the falling edge of the pulse signal OSC_O, and this pulse signal is output as the reset signal RST. Figure 2 The reset terminals of the comparator and D latch in the MIMIC are used to reset the MIMIC circuit.

[0064] Based on the above-mentioned reset unit, the MIMIC circuit can be reset with a simple structure without the need for an additional reset circuit in the memory, thus simplifying the overall circuit structure of the memory.

[0065] The following reference Figures 7-9 and combined Figures 2-6 The operation of the oscillation period matching device involved in this invention will be explained.

[0066] Figure 7This is a timing diagram illustrating the operational timing of the oscillation period matching device. For example... Figure 3 As shown, after the rising edge of the oscillation initiation signal OSC_EN is input to the NAND gate of the oscillation unit, the oscillation unit starts oscillating, generating and outputting a rectangular pulse signal OSC_O. Figure 7 As shown, the oscillation unit uses the rising edge of the pulse signal OSC_O (here designated as the "first transition edge") as the input signal DQS_T to the matching target unit. Then, the calibration unit uses approximately one oscillation cycle time to... Figure 8 or Figure 9 The action is used to perform the first calibration of the oscillation period, and then the second, third, fourth and so on can be performed based on the calibration results. The time consumed by these calibrations is about one oscillation period for the substrate.

[0067] Figure 8 This is a timing diagram illustrating an example of the calibration operation of the calibration unit. The upper part of the diagram is related to... Figure 3 The first part is the circuit diagram of the oscillation unit, and the second part is the timing diagram of each signal. For example... Figure 8 , Figure 2 As shown, after the delay of the matched object unit, the rising edge of the pulse signal OSC_O (i.e., the "first transition edge") Figure 8 (Represented by dashed lines) That is, the rising edge of the input signal DQS_T is delayed by the delay amount tDQS2DQ of the analog data gating signal processing circuit, so that the output signal DQS_Cb of the matching object unit generates a rising edge (here set as the "second rising edge"). Figure 8 (Represented by a double-dotted line). The calibration unit obtains the "second transition edge" from the output signal DQS_Cb and the rising edge after one oscillation period tOSC from the pulse signal OSC_O (here designated as the "third transition edge"). Figure 8 (represented by a single-dot dash) The above-mentioned "second transition edge" and the above-mentioned "third transition edge" are compared. Based on the comparison result, a calibration signal is output to the oscillation unit so that the "second transition edge" and the "third transition edge" coincide, thereby completing the matching of the oscillation period tOSC and the delay amount tDQS2DQ.

[0068] Specifically, combined Figure 4 , Figure 5 and Figure 8 When the "second edge transition" lags behind the "third edge transition", Figure 4 The calibration direction signal SIDE output by the output terminal Q of trigger 31 is high. For example... Figure 5As shown, the calibration signal CNT_D<1∶0> remains unchanged at its initial value "11", and the counter 41 starts counting the pulses of the DQS_Ab signal, outputting the calibration signal CNT_U<1∶0> through the locking circuit 43. Figure 8 As shown in the upper circuit diagram, CNT_U<1∶0> increases incrementally from the initial value "00", and the delay time adjustment unit C in the oscillation unit... U1 ~C U3 Based on the CNT_U<1∶0> signal, the delay time td is adjusted so that the oscillation period tOSC increases step by step. Thus, the "second edge" moves from the single-dot line on the left, through the single-dot line in the middle, and finally adjusts to coincide with the double-dot line.

[0069] Additionally, at the double-dotted line, the "second jump edge" and "third jump edge" change from not coinciding to coinciding. At this time, as shown... Figure 4 As shown, the lock signal LOCK goes high, thereby locking the calibration signal CNT_U<1∶0>. This allows the matching tDQS2DQ cycle to be obtained.

[0070] Figure 9 This is a timing diagram illustrating another example of the calibration operation of the calibration unit. The upper part of the diagram is related to... Figure 3 The first part is the circuit diagram of the oscillation unit, and the second part is the timing diagram of each signal. For example... Figure 9 , Figure 2 As shown, after the delay of the matched object unit, the rising edge of the pulse signal OSC_O (i.e., the "first transition edge") Figure 9 (Represented by dashed lines) That is, the rising edge of the input signal DQS_T is delayed by the delay amount tDQS2DQ of the analog data gating signal processing circuit, so that the output signal DQS_Cb of the matching object unit generates a rising edge (here set as the "second rising edge"). Figure 9 (Represented by a double-dotted line). The calibration unit obtains the "second transition edge" from the output signal DQS_Cb and the rising edge after one oscillation period tOSC from the pulse signal OSC_O (here designated as the "third transition edge"). Figure 9 (represented by a single-dot dash) The above-mentioned "second transition edge" and the above-mentioned "third transition edge" are compared. Based on the comparison result, a calibration signal is output to the oscillation unit so that the "second transition edge" and the "third transition edge" coincide, thereby completing the matching of the oscillation period tOSC and the delay amount tDQS2DQ.

[0071] Specifically, combined Figure 4 , Figure 5 and Figure 9 When the "second edge transition" leads the "third edge transition", Figure 4The calibration direction signal SIDE output by the output terminal Q of trigger 31 is low. For example... Figure 5 As shown, the calibration signal CNT_U<1∶0> remains unchanged at its initial value of "00", and the counter 42 starts counting the pulses of the DQS_Ab signal, outputting the calibration signal CNT_D<1∶0> through the locking circuit 44. Figure 9 As shown in the upper circuit diagram, CNT_D<1∶0> decreases step by step from the initial value "11", and the delay time adjustment part C in the oscillation unit... D1 ~C D3 Based on the CNT_D<1∶0> signal, the delay time td is adjusted so that the oscillation period tOSC decreases step by step. Thus, the "second edge" moves from the single-dotted line on the right, through the single-dotted line in the middle, and finally adjusts to coincide with the double-dotted line.

[0072] Additionally, at the double-dotted line, the "second jump edge" and "third jump edge" change from not coinciding to coinciding. At this time, as shown... Figure 4 As shown, the lock signal LOCK goes high, thereby locking the calibration signal CNT_D<1∶0>. This allows the matching tDQS2DQ cycle to be obtained.

[0073] Back Figure 7 The calibration unit uses a falling edge (here designated as the "fourth rising edge") that transitions in the opposite direction to the first rising edge (the rising edge in the figure) to reset the matched object unit. The generation of the reset signal will be explained in detail below.

[0074] In addition, regarding the number of calibrations, Figure 7 The example given is a case of performing four calibrations, but the present invention is not limited to this. It is sufficient to ensure that tDQS2DQ and tOSC are perfectly matched. However, as mentioned above, the calibration is usually completed within six calibrations. In other words, the calibration unit can complete the matching of the oscillation period tOSC and the delay amount tDQS2DQ while the control module is counting the pulse signal OSC_O.

[0075] In addition, refer to Figure 8 , Figure 9 The adjustment of a single-dot dash at level one corresponds to one calibration.

[0076] As described above, the oscillation period matching device and the memory equipped with the oscillation period matching device according to this embodiment can accurately match the oscillation period of the oscillation unit with the output signal delay of the matching object with a simple structure. This improves the accuracy of obtaining the delay of the data gating signal processing circuit DQS2DQ based on the oscillation period of the oscillation unit, thereby making the timing of the DQS signal and the DQ signal more matched and improving the data transmission and reception accuracy of the memory.

[0077] Furthermore, since tOSC calibration can be completed during the process of counting the pulse signal OSC_O to calculate the average value of the oscillation period tOSC, no additional calibration command is required, which can improve memory efficiency and save data resources.

[0078] The following is combined Figure 10 , Figure 11 The oscillation period matching method involved in this invention will be described.

[0079] Figure 10 This is a flowchart illustrating the oscillation period matching method. Figure 11 This is a timing diagram illustrating the oscillation period matching method.

[0080] like Figure 10 As shown, after the oscillation period matching begins, firstly, the oscillation initiation signal OSC_EN, which serves as the input to the DQS intermittent oscillator, rises to a high level to start the DQS intermittent oscillator. The DQS intermittent oscillator then begins oscillating, generating the pulse signal OSC_O (step ST1). Figure 11 As shown, after the OSC_EN signal goes high, a rectangular wave-shaped pulse signal OSC_O is generated. Furthermore, as... Figure 11 As shown, at the rising edge of the OSC_EN signal, the calibration signals CNT_U<1∶0> and CNT_D<1∶0> (described later) can be set to their initial values ​​"00" and "11" respectively.

[0081] Next, the pulse signal OSC_O is input as the input signal DQS_T to the matching target unit DQS2DQ MIMIC (step ST2). Specifically, the first rising edge of the pulse signal OSC_O is input as the input signal to the matching target unit DQS2DQ MIMIC. Figure 11 As shown, the waveform of OSC_O is exactly the same as that of DQS_T. The rising edge of the OSC_O signal ("first transition edge"), that is, the rising edge of the DQS_T signal at the left boundary of the leftmost tDQS2DQ interval in the figure, is input to the matching target unit DQS2DQ MIMIC, thereby generating a rising edge ("second transition edge", which is the rising edge of the leftmost pulse in the DQS_Cb signal in the figure) that is delayed relative to the first transition edge in the output signal DQS_Cb of the matching target unit DQS2DQ MIMIC.

[0082] Then, the rising edge ("third rising edge") after one oscillation period tOSC of the "first rising edge" of the pulse signal OSC_O is compared with the rising edge ("second rising edge") of the output signal DQS_Cb of the matched object unit DQS2DQ MIMIC (step ST3). Specifically, as Figure 11 As shown, the "second rising edge" is obtained from the output signal DQS_Cb, and the "third rising edge" is obtained from the pulse signal OSC_O after one oscillation period tOSC (the second rising edge of the DQS_T signal in the leftmost tDQS2DQ interval in the figure). The "second rising edge" and the "third rising edge" are compared.

[0083] When the oscillation period tOSC_O of the oscillation unit is less than or equal to the delay tDQS2DQ of the matched target unit (step ST4 is "No"), for example... Figure 11 As shown in the leftmost tDQS2DQ interval, tOSC_O < tDQS2DQ, in which case the "second transition edge" lags behind the "third transition edge". In this case, the calibration signal CNT_U<1∶0> is counted up (step ST10), and then the process proceeds to step ST11. Figure 11 As shown, changing from "00" to "01" increases the delay time of the delay time adjustment part in the oscillation unit, thereby increasing the oscillation period tOSC of the oscillation unit.

[0084] In step ST11, the matched object cell DQS2DQ MIMIC is reset at the falling edge of OSC_O (step ST11). Specifically, as follows... Figure 6 , Figure 11 As shown, a "fourth transition edge" (i.e., the falling edge of the OSC_O signal) that is opposite in direction to the "first transition edge" is obtained from the pulse signal OSC_O. This "fourth transition edge" is compared with the aforementioned "second transition edge" (i.e., the rising edge of the DQS_Cb signal). When the timing changes from leading the "second transition edge" to lagging behind the "second transition edge", the signal is generated from... Figure 6 The OR gate in the DQS2DQ MIMIC outputs a reset signal RST pulse to the matched object unit, i.e. Figure 11 The leftmost pulse of the RST signal in the diagram. For example... Figure 2 As shown, the RST pulse is used to reset the matched target unit DQS2DQ MIMI, thereby achieving the desired result. Figure 11 As shown, after a short period of time, the DQS_Cb signal is reset to a low level.

[0085] Next, the rising edge of the OSC_O signal is compared again with the rising edge of the DQS_Cb signal (step ST12). Specifically, as follows: Figure 11 As shown, the second rising edge of the DQS_T signal in the middle tDQS2DQ interval of the figure is compared with the rising edge of the middle pulse in the DQS_Cb signal, and it is determined again whether tOSC > tDQS2DQ is true (step ST13). When step ST13 is "no", return to step ST10, count up again CNT_U<1∶0> (become "10"), and then repeat steps ST11 to ST13 until tOSC = tDQS2DQ.

[0086] On the other hand, when the oscillation period tOSC_O of the oscillation unit is greater than the delay amount tDQS2DQ of the matching target unit (step ST4 is "Yes"), the calibration signal CNT_D<1∶0> is counted down (step ST5), and then the process proceeds to step ST6, where the matching target unit DQS2DQ MIMIC is reset at the falling edge of OSC_O (step ST6).

[0087] Next, the rising edge of the OSC_O signal is compared with the rising edge of the DQS_Cb signal again (step ST7), and it is determined again whether tOSC > tDQS2DQ is true (step ST8). When step ST8 is "yes", return to step ST5, count down CNT_D<1∶0> again, and then repeat steps ST6 to ST8 until tOSC = tDQS2DQ.

[0088] When it is determined in step ST8 or step ST13 that tOSC = tDQS2DQ, proceed to step ST9, lock the calibration signals CNT_D<1∶0> and CNT_U<1∶0> (step ST9), and then end the process. Specifically, as follows... Figure 4 , Figure 5 , Figure 11 As shown, the "second rising edge" of the DQS_Cb signal is compared with the "third rising edge" of the OSC_O signal. The timing at which the "second rising edge" and the "third rising edge" change from non-coinciding to coinciding is... Figure 11 The timing of the second rising edge of the DQS_T signal in the rightmost tDQS2DQ interval coinciding with the rising edge of the rightmost pulse in the DQS_Cb signal, from... Figure 4 The XOR gate in the middle outputs a high-level LOCK signal, from Figure 4 The inverter in the circuit outputs a low-level LOCKb signal, thereby utilizing... Figure 5 The locking circuits 43 and 44 in the middle lock the calibration signals CNT_D<1∶0> and CNT_U<1∶0>.

[0089] The above describes the implementation of the oscillation period matching method in hardware. However, this invention is not limited to hardware implementation; it can also be implemented in software, or a combination of software and hardware. Furthermore, the program for executing the oscillation period matching method of this invention can be stored in various computer-readable media and loaded into a processor or similar device for execution when needed. There are no particular limitations on the computer-readable media; for example, optical discs such as HDD, CD-ROM, CD-R, MO, MD, DVD, IC cards, floppy disks, and semiconductor memories such as mask ROM, EPROM, EEPROM, and flash memory ROM can be used.

[0090] Furthermore, the description of the falling edge and rising edge of each signal in this embodiment is merely an example, and the oscillation period matching device and oscillation period matching method of the present invention are not limited to this. For example, each signal can be inverted via an inverter, thereby inverting the phase of all subsequently generated signals. Therefore, in the above description, "jumping edge" is sometimes used instead of "rising edge" and "falling edge" to define the operation of the oscillation period matching device.

[0091] Furthermore, it should be considered that all aspects of the embodiments disclosed herein are merely illustrative and not restrictive. The scope of the invention is defined by the claims, not by the above embodiments, and includes all modifications and variations within the meaning and scope equivalent to the claims.

[0092] Industrial practicality

[0093] As described above, the oscillation period matching apparatus, oscillation period matching method, memory, and computer-readable medium according to the present invention are effective in application scenarios where a high-precision match between the oscillation period and the delay of the matching object is required. They are particularly useful for signal timing calibration in memories such as DDR5 and LPDDR4, and for improving signal matching accuracy under various PVT conditions in LPDDR5.

[0094] Label Explanation

[0095] 1 Matching object unit

[0096] 2 Oscillation Unit

[0097] 3 Calibration Unit

[0098] 10 Oscillation Period Matching Device

[0099] 20 DQ receiver

[0100] Triggers 31, 32, and 33

[0101] Counters 41 and 42

[0102] 43, 44 Locking circuit

[0103] 100 storage modules

[0104] 200 control module

Claims

1. An oscillation period matching device, characterized in that, include: A matching object unit, wherein the output signal of the matching object unit is delayed relative to the input signal by a certain delay amount; An oscillation unit generates a pulse signal that oscillates with an oscillation period, and inputs the pulse signal as the input signal to the matching target unit; as well as The calibration unit obtains the output signal from the matching object unit and the pulse signal from the oscillation unit, compares the output signal with the pulse signal, and outputs a calibration signal to the oscillation unit based on the comparison result to calibrate the oscillation period so that the oscillation period matches the delay amount.

2. The oscillation period matching device as described in claim 1, characterized in that, The oscillation unit inputs the first rising edge of the pulse signal as the input signal to the matching target unit. The calibration unit obtains a second transition edge from the output signal after being delayed by the delay amount relative to the first transition edge, obtains a third transition edge from the pulse signal after one oscillation cycle of the first transition edge, compares the second transition edge with the third transition edge, and outputs a calibration signal to the oscillation unit based on the comparison result, so that the second transition edge coincides with the third transition edge, thereby matching the oscillation cycle with the delay amount.

3. The oscillation period matching device as described in claim 2, characterized in that, The oscillation unit includes a delay time adjustment unit that receives the calibration signal from the calibration unit and adjusts the delay time based on the calibration signal, thereby adjusting the oscillation period. The calibration unit includes a calibration signal generation unit that compares the second transition edge with the third transition edge. When the second transition edge leads the third transition edge, the calibration signal is generated to reduce the delay time. When the second transition edge lags the third transition edge, the calibration signal is generated to increase the delay time.

4. The oscillation period matching device as described in claim 2 or 3, characterized in that, The calibration unit includes a signal locking unit that compares the second transition edge with the third transition edge and locks the calibration signal when the second transition edge and the third transition edge change from non-coinciding to coinciding.

5. The oscillation period matching device as described in claim 2 or 3, characterized in that, The calibration unit includes a reset unit, which obtains a fourth transition edge from the pulse signal that is opposite to the transition direction of the first transition edge, compares the fourth transition edge with the second transition edge, and outputs a reset signal to the matching target unit at a timing when the fourth transition edge changes from leading the second transition edge to lagging behind the second transition edge, thereby resetting the output signal.

6. A memory, characterized in that, include: The oscillation period matching device according to any one of claims 1 to 5, wherein the matching target unit corresponds to a data gating signal processing circuit, which converts the input data gating signal into a read / write timing signal that serves as a timing reference for the read / write data of the memory; as well as The control module acquires the pulse signal from the oscillation unit, calculates the oscillation period by counting the pulse signal, and compensates for the time delay between the data strobe signal and the read / write timing signal based on the oscillation period. The calibration unit completes the matching of the oscillation period and the delay amount during the counting process of the pulse signal by the control module.

7. The memory as claimed in claim 6, characterized in that, The matching object unit is an analog circuit that simulates the data gating signal processing circuit.

8. An oscillation period matching method, the oscillation period matching method being used in an oscillation period matching device, the oscillation period matching device comprising: A matching object unit, wherein the output signal of the matching object unit is delayed relative to the input signal by a certain delay amount; as well as An oscillation unit that generates a pulse signal that oscillates according to an oscillation period. The oscillation period matching method is characterized by including: A pulse signal input step, wherein the pulse signal is input as the input signal to the matching target unit; as well as The calibration step involves obtaining the output signal from the matching object unit, obtaining the pulse signal from the oscillation unit, comparing the output signal with the pulse signal, and outputting a calibration signal to the oscillation unit based on the comparison result to calibrate the oscillation period, so that the oscillation period matches the delay amount.

9. The oscillation period matching method as described in claim 8, characterized in that, In the pulse signal input step, the first rising edge of the pulse signal is used as the input signal and input to the matching target unit. In the calibration step, a second transition edge delayed by the delay amount relative to the first transition edge is obtained from the output signal, and a third transition edge after one oscillation cycle of the first transition edge is obtained from the pulse signal. The second transition edge and the third transition edge are compared, and a calibration signal is output to the oscillation unit based on the comparison result, so that the second transition edge and the third transition edge coincide, thereby matching the oscillation cycle with the delay amount.

10. The oscillation period matching method as described in claim 9, characterized in that, The oscillation unit includes a delay time adjustment unit that receives the calibration signal and adjusts the delay time based on the calibration signal, thereby adjusting the oscillation period. The calibration step includes a calibration signal generation step, in which the second transition edge and the third transition edge are compared. When the second transition edge leads the third transition edge, the calibration signal is generated, thereby reducing the delay time. When the second transition edge lags the third transition edge, the calibration signal is generated, thereby increasing the delay time.

11. The oscillation period matching method as described in claim 9 or 10, characterized in that, The calibration step includes a signal locking step, in which the second transition edge and the third transition edge are compared, and the calibration signal is locked when the second transition edge and the third transition edge change from non-coinciding to coinciding.

12. The oscillation period matching method as described in claim 9 or 10, characterized in that, The calibration step includes a reset step, in which a fourth transition edge opposite to the transition direction of the first transition edge is obtained from the pulse signal, the fourth transition edge is compared with the second transition edge, and a reset signal is output to the matching object unit at a timing when the fourth transition edge changes from leading the second transition edge to lagging behind the second transition edge, thereby resetting the output signal.

13. A computer-readable medium storing a program for performing the oscillation period matching method as described in any one of claims 8 to 12.

Images