A semiconductor device and its fabrication method

Abstract

The application provides a semiconductor device and a manufacturing method. The semiconductor device comprises an epitaxial wafer having a first surface and a second surface opposite to each other, the second surface is directed to the direction of the first surface, the epitaxial wafer comprises a substrate, a first epitaxial layer, a buried layer and a second epitaxial layer arranged in sequence, the epitaxial wafer comprises a first region and a second region in the direction parallel to the first surface, a Schottky diode structure arranged in the first region, and a trench MOSFET structure arranged in the second region. The technical scheme of the application integrates the Schottky diode structure and the MOSFET device structure on the same epitaxial wafer. Since the Schottky diode structure and the MOSFET device structure are prepared on the same epitaxial wafer, and the preparation processes of the two are completely compatible, the stability and reliability of the device under high voltage and large current can be improved while the manufacturing cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, more particularly, relates to a semiconductor device and a manufacturing method. BACKGROUND

[0002] Silicon carbide (SiC) material as a kind of semiconductor material, its strike field is strong, thermal conductivity is big, forbidden band width is big, carrier saturation drift speed is high, dielectric constant is small, anti-radiation ability is strong, chemical performance is good and the like, can be used to manufacture various high-temperature high-frequency high-power devices, be applied to the occasion that traditional silicon devices cannot undertake, or produce the effect that silicon devices cannot produce in general application.

[0003] The SiC-based power device generally has two kinds, which are Schottky diode structure device and MOSFET (metal oxide semiconductor field effect transistor) structure device, and the reverse bias of the Schottky diode structure device in the Schottky diode structure device is too low, and the reverse leakage current is large, and the opening voltage of the MOSFET structure device is high, and the phenomenon of flow interruption occurs in the use process, for this, the Schottky diode structure device and the MOSFET structure device are anti-parallel and then packaged in the prior art, in this scheme, although the above problems can be well solved, but in this scheme, the two kinds of power devices need to be prepared respectively, which will lead to the problems of increasing the manufacturing cost and reducing the stability and reliability of the device under high voltage and large current. SUMMARY

[0004] Therefore, the present application provides a semiconductor device and a manufacturing method, and the scheme is as follows:

[0005] A semiconductor device, comprising:

[0006] An epitaxial wafer having opposite first and second surfaces; the second surface is directed to the direction of the first surface, the epitaxial wafer comprises a substrate, a first epitaxial layer, a buried layer and a second epitaxial layer arranged in sequence; in the direction parallel to the first surface, the epitaxial wafer comprises a first region and a second region;

[0007] A Schottky diode structure arranged in the first region;

[0008] A trench MOSFET structure arranged in the second region.

[0009] Preferably, the Schottky diode structure comprises:

[0010] A trench structure located in the surface of the second epitaxial layer;

[0011] an electric field shielding structure in the first surface; the electric field shielding structure surrounds the trench structure in a direction perpendicular to the epitaxial wafer; the electric field shielding structure has a spacing from the trench structure in a direction parallel to the first surface;

[0012] a Schottky contact layer on the first surface; the Schottky contact layer covers the trench structure and is in contact with the electric field shielding structure;

[0013] wherein the electric field shielding structure comprises a buried layer in the first region.

[0014] Preferably, the electric field shielding structure comprises:

[0015] a first doped region below the trench structure, penetrating the buried layer, and having a spacing from the trench structure;

[0016] a second doped region in the second epitaxial layer, in contact with the buried layer; the second doped region surrounds and has a spacing from the trench structure in a direction perpendicular to the epitaxial wafer;

[0017] a third doped region in the second epitaxial layer, in contact with the second doped region on a side away from the substrate, and having a spacing from the trench structure.

[0018] Preferably, the trench structure further comprises:

[0019] a fourth doped region in the second epitaxial layer, in contact with the trench structure on a side away from the first surface, and having a spacing from the buried layer.

[0020] Preferably, the trench structure comprises:

[0021] a first trench in the first surface, having a spacing from the buried layer;

[0022] a first filling medium filling the first trench;

[0023] wherein the first trench and the first filling medium have an insulating layer therebetween.

[0024] Preferably, the Schottky diode structure further comprises:

[0025] a first electrode on a surface of the Schottky contact layer;

[0026] a second electrode on the second surface;

[0027] wherein the first electrode and a source and a gate of the trench MOSFET structure are in the same metal layer;

[0028] The second electrode and the drain of the trench MOSFET structure are located in the same metal layer.

[0029] Preferably, the MOSFET structure includes:

[0030] The trench gate structure is located within the surface of the second epitaxial layer and is spaced apart from the buried layer;

[0031] A well region, located within the first surface, surrounds the trench gate structure in a direction perpendicular to the epitaxial wafer;

[0032] The source region is located within the second epitaxial layer, in contact with the surface of the well region facing away from the substrate, and in contact with the trench gate structure;

[0033] The fifth doped region is located below the trench gate structure, penetrates the buried layer, and is spaced apart from the trench gate structure.

[0034] Preferably, the trench gate structure further includes the following below:

[0035] The sixth doped region is located within the second epitaxial layer, in contact with the side of the trench gate structure opposite to the first surface, and is spaced apart from the buried layer.

[0036] Preferably, the well region includes:

[0037] The first well region is a buried layer divided by the fifth doped region;

[0038] The second well region is located within the second epitaxial layer. In a direction perpendicular to the epitaxial wafer, the second well region surrounds the trench gate structure, contacts the surface of the first well region, and has a gap with the trench gate.

[0039] The third well region is located within the second epitaxial layer. In a direction perpendicular to the epitaxial wafer, the third well region surrounds the trench gate structure, contacts the surface of the second well region opposite to the substrate, and contacts the trench gate.

[0040] Preferably, the trench gate structure includes:

[0041] The second groove is located within the first surface;

[0042] The second filling medium fills the second trench;

[0043] A gate oxide layer is provided between the second trench and the second filling medium.

[0044] This application also provides a method for fabricating a semiconductor device, including:

[0045] An epitaxial wafer is provided, the epitaxial wafer having opposing first and second surfaces; in a direction pointing from the second surface to the first surface, the epitaxial wafer includes a substrate, a first epitaxial layer, a buried layer, and a second epitaxial layer disposed sequentially; in a direction parallel to the first surface, the epitaxial wafer includes a first region and a second region;

[0046] A Schottky diode structure is formed in the first region, and a MOSFET structure is formed in the second region.

[0047] Preferably, a Schottky diode structure is formed in the first region and a MOSFET structure is formed in the second region, comprising:

[0048] An electric field shielding structure is formed in the first region, and a well region and a source region are formed in the second region; the electric field shielding structure is located within the first surface; the well region is located within the first surface; the source region is located within the second epitaxial layer and is located on the side of the well region away from the substrate, and is in contact with the well region;

[0049] A first trench is formed in the surface of the first region, and a second trench is formed in the surface of the second region, wherein the first trench and the second trench are spaced apart from the buried layer.

[0050] Based on the first trench, a first doped region penetrating the buried layer is formed; based on the second trench, a fifth doped region penetrating the buried layer is formed.

[0051] A first filling medium is formed in the first trench, and a second filling medium is formed in the second trench; wherein, an insulating layer is provided between the first trench and the first filling medium, and a gate oxide layer is provided between the second trench and the second filling medium;

[0052] A Schottky contact layer is formed on the surface of the first region to contact the first surface, a source electrode is formed on the surface of the second region to connect with the source region, and a gate electrode is formed to connect with the trench gate.

[0053] Preferably, after the first doped region and the fifth doped region are formed, and before the insulating layer is formed, the method further includes:

[0054] Based on the first trench, a fourth doped region is formed in the first region, and based on the second trench, a sixth doped region is formed in the second region; the fourth doped region is located in the second epitaxial layer, contacts the side of the trench structure opposite to the first surface, and has a gap with the buried layer; the fifth doped region is located in the second epitaxial layer, contacts the side of the trench gate structure opposite to the first surface, and has a gap with the buried layer.

[0055] As described above, the semiconductor device and its fabrication method provided in this application include: an epitaxial wafer having opposing first and second surfaces; in the direction from which the second surface points to the first surface, the epitaxial wafer includes a substrate, a first epitaxial layer, a buried layer, and a second epitaxial layer sequentially disposed; in the direction parallel to the first surface, the epitaxial wafer includes a first region and a second region; a Schottky diode structure disposed in the first region; and a trench MOSFET structure disposed in the second region. This application's technical solution integrates both a Schottky diode structure and a MOSFET device structure on the same epitaxial wafer. Since the Schottky diode structure and the MOSFET device structure are fabricated on the same epitaxial wafer, and their fabrication processes are completely compatible, this reduces manufacturing costs while improving the stability and reliability of the device under high voltage and high current. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0057] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0058] Figure 1 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application;

[0059] Figure 2 This is a schematic diagram of another semiconductor device structure provided in an embodiment of this application;

[0060] Figure 3 This is a schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0061] Figure 4 This is a schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0062] Figure 5 This is a schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0063] Figures 6-17 A process flow diagram of a semiconductor device fabrication provided for an embodiment of this application;

[0064] Figure 18 This is a schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0065] Figure 19 This is a schematic diagram of ion implantation provided for an embodiment of this application. Detailed Implementation

[0066] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0067] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0068] There are two common optimization methods for SiC-based semiconductor devices: one is to connect diodes in antiparallel and then package them, and the other is to directly fabricate a Schottky metal integrated planar SBD inside the MOSFET device.

[0069] While connecting a diode and a MOSFET in antiparallel and then packaging them can effectively solve the problem of high turn-on voltage of MOSFET devices, it also leads to increased power consumption in the circuit and a shorter lifespan for the diode.

[0070] In contrast to directly fabricating a Schottky metal integrated planar SBD inside the MOSFET device by anti-parallel connection of the diode and MOSFET device and then packaging it, this method can effectively solve the problem of high power consumption. However, because the area of ​​the SBD region formed by this method is limited, the reliability of the device is not high under high voltage and current.

[0071] In view of this, embodiments of this application provide a semiconductor device, including:

[0072] An epitaxial wafer has a first surface and a second surface opposite to each other; the second surface points toward the first surface, and the epitaxial wafer includes a substrate, a first epitaxial layer, a buried layer and a second epitaxial layer disposed sequentially; in a direction parallel to the first surface, the epitaxial wafer includes a first region and a second region;

[0073] A Schottky diode structure disposed in the first region;

[0074] A trench MOSFET structure disposed in the second region.

[0075] As can be seen, the technical solution of this application integrates a Schottky diode structure and a MOSFET structure on the same epitaxial wafer. When the device is working, the structure acts as a freewheeling diode, thereby improving the working efficiency and reliability of the circuit and reducing the cost of the circuit.

[0076] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0077] refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor includes an epitaxial wafer having a first surface and a second surface opposite to each other. In the direction from the second surface to the first surface, the epitaxial wafer includes a substrate 11, a first epitaxial layer 12, a buried layer 13, and a second epitaxial layer 14 disposed sequentially. In the direction parallel to the first surface, the epitaxial wafer includes a first region 100 and a second region 200, a Schottky diode structure disposed in the first region 100, and a trench MOSFET structure disposed in the second region 200.

[0078] Specifically, in this embodiment, the Schottky diode structure and the MOSFET structure are formed on the same substrate 11. In this case, the Schottky diode functions as a freewheeling diode, which can improve the operating efficiency and reliability of the circuit.

[0079] Optionally, the details of the Schottky diode structure in the above embodiments are as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of this application.

[0080] refer to Figure 2 The Schottky diode structure includes: a trench structure 110 located within the surface of the second epitaxial layer 14; an electric field shielding structure 120 located within the first surface, wherein the electric field shielding structure 120 surrounds the trench structure 110 in a direction perpendicular to the epitaxial wafer and has a distance between the electric field shielding structure 120 and the trench structure 110 in a direction parallel to the first surface; and a Schottky contact layer 21 located on the first surface, wherein the Schottky contact layer 21 covers the trench structure 110 and contacts the electric field shielding structure 120, wherein the electric field shielding structure 120 includes a buried layer 13 located in the first region 100.

[0081] Specifically, the electric field shielding structure 120 not only surrounds the trench structure 110, but also the Schottky contact layer 21 of the Schottky diode structure is within the protection range of the electric field shielding structure 120 and is in contact with the surface of the electric field shielding structure 120. Therefore, the electric field shielding structure 120 can enhance the stability and reliability of the Schottky diode structure and reduce the reverse leakage current.

[0082] The electric field shielding structure 120 described in the above embodiments is formed by combining multiple structures. The electric field shielding structure 120 includes: a first doped region 15, located below the trench structure, penetrating the buried layer 13, and having a distance from the trench structure 110; a second doped region 16, located within the second epitaxial layer 14, contacting the buried layer 13, and in a direction perpendicular to the epitaxial wafer, the second doped region 16 surrounds the trench structure 110 and has a distance from the trench structure 110; and a third doped region 17, located within the second epitaxial layer 14, contacting the side of the second doped region 16 away from the substrate 11, and having a distance from the trench structure 110.

[0083] Specifically, the first doped region 15 is generally N. - Ion implantation, while the second doped region 16 is typically P. - Ion implantation, the third doped region 17 generally uses P + In ion implantation, it should be noted that the second doped region 16 can be formed in two ways. The first way is that the second doped region 16 is formed directly, while the second way is that it is formed in two stages simultaneously with the second layer well region 24 and the third layer well region 25 located in the second region 200.

[0084] The above embodiments introduced the Schottky diode structure. In practical applications, there is another factor affecting device lifespan: inrush current, which is the peak current flowing into the device at the moment the power is turned on. If the inrush current is too large, it will affect the lifespan of the device. Therefore, this application provides a solution for suppressing inrush current. Figure 3 As shown, Figure 3 This is a schematic diagram of another semiconductor device structure provided in an embodiment of this application. A fourth doped region 18 can also be formed below the trench structure 110. The fourth doped region 18 is located in the second epitaxial layer 14, contacts the side of the trench structure 110 opposite to the first surface, and has a gap with the buried layer 13.

[0085] Specifically, the fourth doped region 18 can form a JFET region with the underlying buried layer 13. This region can suppress surge current. This region is connected to the trench structure 110 and is spaced from the underlying buried layer 13. This region is connected through P +Formed by ion implantation.

[0086] The above description explains that the Schottky diode structure also includes a trench structure 110. Therefore, this embodiment will describe the detailed composition of the trench structure 110 in detail. (Refer to...) Figure 2 The trench structure 110 includes: a first trench located within the first surface, having a distance from the buried layer 13, and a first filling medium 19 filling the first trench, wherein an insulating layer 20b is provided between the first trench and the first filling medium 19.

[0087] Specifically, the trench structure is formed in steps: first, a first trench is formed, then an insulating layer 20b is formed, and finally a first filling medium 19 is formed. In the above embodiment, the first doped region 15 is prepared after the first trench is formed and before the insulating layer 20b is formed. Similarly, the above embodiment also introduces a fourth doped region 18, which is formed after the first doped region 15 is prepared and before the insulating layer is prepared.

[0088] The semiconductor devices described in the above embodiments include Schottky diode structures and MOSFET structures. While the Schottky diode structure has been described in detail in the above embodiments, the MOSFET structure will be described in detail in this application. Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application.

[0089] refer to Figure 4 The MOSFET structure includes: a trench gate structure 210 located within the surface of the second epitaxial layer 14 and spaced from the buried layer 13; a well region 220 located within the first surface and surrounding the trench gate structure 210 in a direction perpendicular to the epitaxial wafer; a source region 26 located within the second epitaxial layer 14, contacting the surface of the well region 220 opposite to the substrate 11 and also contacting the trench gate structure 210; and a fifth doped region 23 located below the trench gate structure 210, penetrating the buried layer 13 and spaced from the trench gate structure 210.

[0090] Specifically, the source region 26 is divided into two parts: a first source region 26a and a second source region 26b. The first source region 26a is located within the second epitaxial layer 14, contacting the surface of the well region 220 opposite to the substrate 11, and is spaced from the trench gate structure 210. The second source region 26b is also located within the second epitaxial layer 14, contacting the surface of the well region 220 opposite to the substrate 11, but also contacting the trench gate structure 210 and the first source region 26a. Clearly, the second source region 26b is located between the first source region 26a and the trench gate structure 210, and is connected to both.

[0091] The above introduction mentioned that a structure can exist in a Schottky diode to suppress inrush current; similarly, this structure is also applicable to MOSFET structures, such as... Figure 5 As shown, Figure 5 This is a schematic diagram of another semiconductor device structure provided in the embodiments of this application.

[0092] refer to Figure 5 The sixth doped region 27 is located within the second epitaxial layer 14, contacts the side of the trench gate structure 210 away from the first surface, and has a gap with the buried layer 13.

[0093] Specifically, the sixth doped region 27 is the P-type region that suppresses surge current. + The ion-implanted region, together with the underlying buried layer 13, forms the JFET region. Similarly, the sixth doped region 27 is also formed by P... + It was formed by ion implantation, and the formation time was consistent with the fourth doped region mentioned above.

[0094] The well region 220 involved in the above embodiments is formed by combining multiple well regions. The well region 220 includes: a first well region, which is a buried layer 13 divided by the fifth doped region 23; a second well region 24, located in the second epitaxial layer 14, which surrounds the trench gate structure 210 in a direction perpendicular to the epitaxial wafer, contacts the surface of the first well region, and has a gap with the trench gate 210; and a third well region 25, located in the second epitaxial layer 14, which surrounds the trench gate structure 210 in a direction perpendicular to the epitaxial wafer, contacts the surface of the second well region 24 on the side away from the substrate 11, and contacts the trench gate structure 210.

[0095] Similarly, the source region 26 described above is also composed of multiple parts, including: a first source region 26a, located on the surface of the third layer well region 25 away from the substrate 11 and spaced apart from the trench gate structure 210; and a second source region 26b, located on the surface of the third layer well region 25 away from the substrate 11, between the trench gate structure 210 and the first source region 26a, and in contact with both the trench gate structure 210 and the first source region 26a.

[0096] Specifically, the first source region 26a is through P + It was formed by ion implantation, while the second source region 26b was formed by N. + When the second source region 26b is formed by ion implantation, there is no need to reserve a region for the trench gate structure 210. In subsequent processes, it can be directly etched.

[0097] The trench gate structure 210 described above includes: a second trench located within the first surface, and a second filling medium 28 filling the second trench, wherein a gate oxide layer 20c is present between the second trench and the second filling medium 28.

[0098] Specifically, the gate oxide layer 20c, the insulating layer 20b inside the trench structure 110 described above, and the 20a located on the device surface are all made of the same material, and the gate oxide layer 20c and the insulating layer 20b are formed simultaneously.

[0099] The above description details the location of the fifth doped region 23. This fifth doped region 23 is formed after the second trench of the trench gate structure 210 and before the gate oxide layer 20c is formed, using N-doped metals. - The fifth doped region 23 is formed by ion implantation. After the fifth doped region 23 is formed, the buried layer 13 becomes the first well region. The second well region 24 and the third well region 25 both use P- ions, but because the implantation ranges are different, they need to be implanted in two separate steps. The sixth doped region 27, located below the trench gate structure 210 as described above, is formed after the fifth doped region 23 is formed and before the gate oxide layer 20c is formed, through P- ion implantation. + Formed by ion implantation.

[0100] After the second trench is formed, ion implantation is performed on the fifth doped region 23 and the sixth doped region 27. This method can effectively implant ions into deeper regions of the epitaxial wafer, thus solving the technical problem of ion implantation in deep regions.

[0101] Another embodiment of this application also provides a method for manufacturing a semiconductor, which can be as follows: Figures 6-17 As shown,Figures 6-17 A process flow diagram of a semiconductor manufacturing method provided in this application.

[0102] Step S100, as follows Figure 6 As shown, an epitaxial wafer is provided.

[0103] Specifically, the epitaxial wafer has a first surface and a second surface opposite to each other, the second surface pointing in the direction of the first surface, the epitaxial wafer includes a substrate 11, a first epitaxial layer 12, a buried layer 13 and a second epitaxial layer 14 disposed sequentially, and in the direction parallel to the first surface, the epitaxial wafer includes a first region 100 and a second region 200.

[0104] In the next step, a Schottky diode structure is formed in the first region 100, and a MOSFET structure is formed in the second region 200.

[0105] Step S110, as follows Figure 7 As shown, an electric field shielding structure 120 is formed in the first region 100, and a well region 220 and a source region 26 are formed in the second region 200. The electric field shielding structure 120 is located within the first surface, the well region 220 is located within the first surface, and the source region 26 is located within the second epitaxial layer 14 and is located on the side of the well region 220 away from the substrate 11, and is in contact with the well region 220.

[0106] Specifically, this step involves ion implantation of the second doped region 16 and the third doped region 17 of the Schottky diode structure, and ion implantation of the well region 220 and the source region 26 of the MOSFET structure. The second doped region 16 of the Schottky diode structure and the second well region 24 and the third well region 25 of the MOSFET structure are implanted simultaneously. The second doped region 16 can be implanted during the formation of the second well region 24 of the MOSFET structure, or it can be formed during the formation of the third well region 25 of the MOSFET structure. Alternatively, the structure can be divided into two parts and formed with the second well region 24 and the third well region 25 of the MOSFET structure respectively. That is, 16a is formed when the second well region 24 is formed and 16b is formed when the third well region 25 is formed. It can be understood that the result of this method is exactly the same as the two methods mentioned above, but using this method can reduce the fabrication difficulty and thus reduce the fabrication time.

[0107] Step S120, as follows Figure 8As shown, a first trench 30 is formed in the surface of the first region 100, and a second trench 31 is formed in the surface of the second region 200. Both the first trench 30 and the second trench 31 are spaced from the buried layer 13. Trench etching is performed on the second epitaxial layer 14 of the first region 100 and the second epitaxial layer 14 of the second region 200 to form the first trench 30 and the second trench 31.

[0108] Specifically, when forming the first trench 30 and the second trench 31, a gate oxide layer 20a needs to be formed on one side of the entire device surface first. This gate oxide layer 20a is used to protect other parts that are not etched. Therefore, in this step, a gate oxide layer 20a can be formed on the entire device surface first, and then the gate oxide layer 20a above the area where the first trench 30 and the second trench 31 need to be formed can be etched away, and then the required trenches can be formed. Similarly, the gate oxide layer can also be formed directly in the area other than the area where the trench will be formed, so that the required trenches can be formed directly by etching.

[0109] Step S130, as Figure 9 As shown, a first doped region 15 is formed through the buried layer 13 based on the first trench 30, and a fifth doped region 23 is formed through the buried layer 13 based on the second trench 31.

[0110] Specifically, the first doped region 15 is located in the buried layer below the first trench 30 and penetrates the buried layer 13. The fifth doped region 23 is located below the second trench 31, penetrates the buried layer 13, and is spaced from the trench gate structure. It is worth noting that the area of ​​the first doped region 15 is slightly smaller than that of the first trench, and the area of ​​the fifth doped region is slightly smaller than that of the second trench. The first and fifth doped regions formed using this method can effectively avoid defects caused by excessive ion implantation depth.

[0111] like Figure 19 As shown, Figure 19 This is a schematic diagram of ion implantation provided in an embodiment of the present application. A first trench 30 and a second trench 31 are formed on the first surface of the epitaxial wafer. Ion implantation is performed in the buried layer 13 based on the first trench 30 and the second trench 31, forming a first doped region 15 and a fifth doped region 23 in the buried layer 13 corresponding to the regions of the first trench 30 and the second trench 31, respectively. The doped regions can be set to be slightly smaller than their corresponding trenches.

[0112] Step S140, as Figure 10 As shown, an insulating layer 20b is formed in the first trench 30, and a gate oxide layer 20c is formed in the second trench 31.

[0113] Specifically, the insulating layer 20b formed in the first trench 30 and the gate oxide layer 20c formed in the second trench 31 are made of the same material, and are formed simultaneously from the same layer. They are simply called by different names because of their different locations.

[0114] Step S150, as follows Figure 11 As shown, a filling medium is formed.

[0115] A first filling medium 19 is formed in the first groove 30, and a second filling medium 28 is formed in the second groove 31.

[0116] Specifically, the first filling medium 19 and the second filling medium 28 are formed simultaneously. The formed filling medium not only fills the first trench 20 and the second trench 31, but also covers other areas. This method is chosen because if only the medium filling the first trench 30 and the second trench 31 is formed, it is not possible to effectively control the uniformity of the filling thickness within the two trench regions. Therefore, this method is selected, and in the following steps, the useless filling medium in other locations is etched away. This ensures, to the greatest extent possible, that the filling medium thickness within the first trench 30 and the second trench 31 is the same. Furthermore, the first filling medium 19 and the second filling medium 28 are made of the same polycrystalline silicon material.

[0117] Step S160, as follows Figure 12 As shown, excess filler medium is removed by etching.

[0118] Specifically, since a large amount of filler medium is formed in the above steps, it is necessary to remove the useless filler medium. This is generally done by using a mixture of HBr (hydrogen bromide), chlorine, and oxygen to etch and remove the filler medium. Removing excess filler medium in this way ensures...

[0119] Step S170, as follows Figure 13 As shown, an etched opening is made in the gate oxide layer 20a above the source region of the second region 200.

[0120] Specifically, since the gate oxide layer 20a is non-conductive, it is necessary to etch an opening in the gate oxide layer 20a before the source electrode 33 can be connected to the outside. This etching of the gate oxide layer 20a is performed using one or more of F-based gases such as CHF3 and CF4, or chlorine-based gases containing Cl.

[0121] Step S180, as follows Figure 14 As shown, an ohmic contact metal is formed in the second region 200 opening region.

[0122] Specifically, the ohmic contact metal formed here is used to connect the source region 26 to the source electrode 33 formed in the following steps. It has no other properties in itself. During the preparation process, PVD (vapor deposition) deposition technology is generally used. However, this technology can lead to the formation of metal in other areas. Therefore, after deposition, the metal in other locations needs to be removed. After removal, it needs to be subjected to RTA (rapid thermal annealing) at 900℃-1100℃ for 30 seconds to 5 minutes. At this point, the ohmic contact metal is complete. The ohmic contact metal is generally made of one or more metal materials such as Ni, Ti, and Al.

[0123] Step S190, as follows Figure 15 As shown, an opening is etched into the gate oxide layer 20a of the first region 100.

[0124] Specifically, the gate oxide layer 20a located in the first region 100 is called the insulating layer 20b in the first region 100, and the purpose of etching an opening in it is to expose the electric field shielding structure 120.

[0125] Step S200, as follows Figure 16 As shown, a Schottky contact metal 21 is formed in the opening region of the first region 100.

[0126] Specifically, the Schottky contact metal 21 covers the portion of the first region 100 without an insulating layer, and is connected not only to the trench region 119, but also to the electric field shielding structure 120. This connection method can effectively ensure the performance of the Schottky contact metal 21, thereby achieving a longer service life.

[0127] Step S210, as follows Figure 17 As shown, a first electrode 22 and a second electrode 29 are formed in the first region 100, and a source electrode 33, a gate electrode 32 and a drain electrode 29 are formed in the second region 200.

[0128] Specifically, the first electrode 22 formed in the first region 100 is connected to the source electrode 33 formed on one side of the second region 200, and the materials used are the same, namely metal materials such as Ti and Al. The gate electrode 32 is located above the trench gate structure 210 of the second region 200 and does not contact the source electrode 33. The drain electrode 29 located on the second surface of the substrate 11 is a co-layer electrode with the second electrode 29 of the first region 100. These two electrodes are connected and are also fabricated simultaneously during the fabrication process.

[0129] The above embodiments describe a method for reducing device surge current. The fabrication of the fourth doped region 18 located in the first region 100 and the sixth doped region 27 located in the second region 200, used to reduce surge current, occurs between steps S130 and S140. (Refer to...) Figure 18, Figure 18 This is a process flow diagram for fabricating another semiconductor device provided in an embodiment of this application.

[0130] Step S131, as follows Figure 18 As shown, a fourth doped region 18 is formed in the first region 100, and a sixth doped region 27 is formed in the second region 200.

[0131] The fourth doped region 18 is located within the second epitaxial layer 14, contacts the side of the trench structure 110 away from the first surface, and is spaced apart from the buried layer 13; the sixth doped region is located within the second epitaxial layer 14, contacts the side of the trench gate structure 210 away from the first surface, and is spaced apart from the buried layer 13.

[0132] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. Regarding the manufacturing methods disclosed in the embodiments, since they correspond to the semiconductor devices disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the semiconductor device section.

[0133] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0134] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0135] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0136] The description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, characterized by, The application relates to an epitaxial wafer, comprising: a first surface and a second surface; the second surface is arranged in the direction of the first surface; the epitaxial wafer comprises a substrate, a first epitaxial layer, a buried layer and a second epitaxial layer arranged in sequence; the epitaxial wafer comprises a first region and a second region in the direction parallel to the first surface; a Schottky diode structure is arranged in the first region; a trench MOSFET structure is arranged in the second region; the Schottky diode structure comprises: a trench structure in the surface of the second epitaxial layer; an electric field shielding structure in the first surface; the electric field shielding structure surrounds the trench structure in the direction perpendicular to the epitaxial wafer; the electric field shielding structure has a spacing from the trench structure in the direction parallel to the first surface; the electric field shielding structure comprises the buried layer in the first region; a Schottky contact layer is arranged on the first surface; the Schottky contact layer covers the trench structure and is in contact with the electric field shielding structure; the MOSFET structure comprises: a trench gate structure in the surface of the second epitaxial layer and spaced from the buried layer; a well region in the first surface and surrounding the trench gate structure in the direction perpendicular to the epitaxial wafer; a source region in the second epitaxial layer and in contact with the well region on the side surface away from the substrate and in contact with the trench gate structure; a fifth doped region below the trench gate structure, penetrating through the buried layer and having a spacing from the trench gate structure; after the fifth doped region is formed, the buried layer becomes a first layer well region; the electric field shielding structure comprises: a first doped region below the trench structure, penetrating through the buried layer and having a spacing from the trench structure; a second doped region in the second epitaxial layer and in contact with the buried layer; the second doped region surrounds the trench structure and has a spacing from the trench structure in the direction perpendicular to the epitaxial wafer; a third doped region in the second epitaxial layer and in contact with the second doped region on the side away from the substrate and having a spacing from the trench structure; the trench structure further comprises: a fourth doped region in the second epitaxial layer and in contact with the trench structure on the side away from the first surface and having a spacing from the buried layer; the trench structure comprises: a first trench in the first surface and having a spacing from the buried layer; a first filling medium filling the first trench; the first trench and the first filling medium have an insulating layer therebetween; the Schottky diode structure further comprises: a first electrode on the surface of the Schottky contact layer; a second electrode on the second surface; the first electrode and the source and the gate of the trench MOSFET structure are in the same metal layer; the second electrode and the drain of the trench MOSFET structure are in the same metal layer; the trench gate structure further comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The semiconductor device according to claim 1, wherein ​ ​ ​ ​ 3. The semiconductor device of claim 1, wherein ​ ​ 4. The semiconductor device of claim 1, wherein ​ ​ ​ ​ 5. The semiconductor device of claim 1, wherein ​ ​ ​ ​ ​ 6. The semiconductor device of claim 1, wherein ​ A sixth doped region is in the second epitaxial layer and is in contact with a side of the trench gate structure that is away from the first surface and is spaced apart from the buried layer.

7. The semiconductor device of claim 1, wherein The well region includes: A first layer of well region is a buried layer that is divided by the fifth doped region; A second layer of well region is in the second epitaxial layer and surrounds the trench gate structure in a direction perpendicular to the epitaxial wafer, is in contact with a surface of the first layer of well region, and is spaced apart from the trench gate structure; A third layer of well region is in the second epitaxial layer and surrounds the trench gate structure in a direction perpendicular to the epitaxial wafer, is in contact with a surface of the second layer of well region that is away from the substrate, and is in contact with the trench gate structure.

8. The semiconductor device of claim 1, wherein, The trench gate structure includes: A second trench is in the first surface; A second filling medium fills the second trench; Wherein, there is a gate oxide layer between the second trench and the second filling medium.

9. A method of fabricating a semiconductor device, characterized by, It includes: An epitaxial wafer is provided, the epitaxial wafer has opposite first and second surfaces; the second surface is directed in the direction of the first surface, the epitaxial wafer includes a substrate, a first epitaxial layer, a buried layer, and a second epitaxial layer arranged in sequence; in a direction parallel to the first surface, the epitaxial wafer includes a first region and a second region; A Schottky diode structure is formed in the first region, and a MOSFET structure is formed in the second region; Wherein, a Schottky diode structure is formed in the first region, and a MOSFET structure is formed in the second region, including: An electric field shielding structure is formed in the first region, and a well region and a source region are formed in the second region; the electric field shielding structure is in the first surface, the electric field shielding structure includes a buried layer in the first region; the well region is in the first surface; the source region is in the second epitaxial layer and is on a side of the well region away from the substrate and in contact with the well region; A first trench is formed in the surface of the first region, and a second trench is formed in the surface of the second region; the first trench and the second trench are both spaced apart from the buried layer; Based on the first trench, a first doped region is formed through the buried layer, and based on the second trench, a fifth doped region is formed through the buried layer; after the fifth doped region is formed, the buried layer becomes a first layer of well region; A first filling medium is formed in the first trench, and a second filling medium is formed in the second trench; wherein, there is an insulating layer between the first trench and the first filling medium, and there is a gate oxide layer between the second trench and the second filling medium; A Schottky contact layer is formed on the surface of the first region and is in contact with the first surface, a source electrode is formed on the surface of the second region and is connected to the source region, and a gate electrode is connected to the trench gate.

10. The method of manufacturing according to claim 9, wherein, After the first doped region and the fifth doped region are formed, before the insulating layer is formed, it further includes: Based on the first trench, a fourth doped region is formed in the first region, and based on the second trench, a sixth doped region is formed in the second region; the fourth doped region is located in the second epitaxial layer, contacts a side of the trench structure which is away from the first surface, and is spaced apart from the buried layer; the sixth doped region is located in the second epitaxial layer, contacts a side of the trench gate structure which is away from the first surface, and is spaced apart from the buried layer.

Images