Memory device and method of manufacturing a memory device

Abstract

A memory device and a manufacturing method thereof are provided. The memory device of an embodiment includes a circuit (CC) disposed on a first surface of a semiconductor substrate (9), including a first contact portion (53); an aluminum oxide layer (63) disposed above the substrate (9) in a direction perpendicular to the first surface; a memory cell (MC) including a capacitor (10) disposed within the aluminum oxide layer (63); a conductive layer (61) disposed between the substrate (9) and the aluminum oxide layer (63) in a first direction, electrically connected to the memory cell (MC); a first insulating layer (60) disposed between the conductive layer (61) and the substrate (9) in the first direction; a second insulating layer (80) disposed above the substrate (9) in a second direction parallel to a surface of the substrate (9) adjacent to the aluminum oxide layer (63); and a second contact portion (70) disposed within the second insulating layer (80), disposed above the first contact portion (53) in the first direction, electrically connecting the memory cell (MC) to the first contact portion (53).

Description

[0001] This application is based on and claims the priority interest of Japanese Patent Application No. 2021-049586, filed on March 24, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The embodiments of the present invention relate to a storage device and a method for manufacturing a storage device. Background Technology

[0003] Research and development of new storage devices with novel structures and new manufacturing methods for storage devices are being promoted. Summary of the Invention

[0004] One embodiment of the present invention provides a storage device with low manufacturing cost.

[0005] The storage device according to the embodiment includes: a semiconductor substrate; a circuit disposed on a first surface of the semiconductor substrate, including a first contact portion; an aluminum oxide layer disposed above the semiconductor substrate in a first direction perpendicular to the first surface; a storage cell including a capacitor disposed within the aluminum oxide layer; a first conductive layer disposed between the semiconductor substrate and the aluminum oxide layer in the first direction and electrically connected to the storage cell; a first insulating layer disposed between the first conductive layer and the semiconductor substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and disposed above the semiconductor substrate in the first direction; and a second contact portion disposed within the second insulating layer and disposed above the first contact portion in the first direction, electrically connecting the storage cell to the first contact portion.

[0006] The above configuration enables the provision of storage devices with low manufacturing costs. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of the storage device according to the first embodiment.

[0008] Figure 2 This is an equivalent circuit diagram of the memory cell array of the memory device according to the first embodiment.

[0009] Figure 3 This is a diagram showing an example of the configuration of the storage cell of the storage device according to the first embodiment.

[0010] Figure 4 This is a cross-sectional view showing a construction example of the storage device according to the first embodiment.

[0011] Figure 5This is a cross-sectional view showing a construction example of the storage device according to the first embodiment.

[0012] Figure 6 This is a cross-sectional view showing a construction example of the storage device according to the first embodiment.

[0013] Figure 7 This is a top view showing a construction example of the storage device according to the first embodiment.

[0014] Figure 8 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0015] Figure 9 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0016] Figure 10 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0017] Figure 11 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0018] Figure 12 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0019] Figure 13 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0020] Figure 14 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0021] Figure 15 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0022] Figure 16 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0023] Figure 17 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0024] Figure 18 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0025] Figure 19 This is a diagram illustrating one step of the manufacturing method of the storage device according to the second embodiment.

[0026] Figure 20 This is a diagram illustrating one step of the manufacturing method of the storage device according to the second embodiment. Detailed Implementation

[0027] [Implementation Method]

[0028] Reference Figures 1 to 20 The storage device of the embodiment and the method of manufacturing the storage device will be described.

[0029] Hereinafter, this embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having the same function and structure will be labeled with the same reference numerals. In addition, in the following embodiments, components (e.g., circuits, wiring, various voltages, and signals) that are marked with reference numerals at the end for distinction may be described using reference numerals with the numerals / letters at the end omitted, where they may not be distinguished from each other.

[0030] (1) First Embodiment

[0031] Reference Figures 1 to 18 The storage device of the first embodiment and the method for manufacturing the storage device will be described.

[0032] (a) Example of composition

[0033] Reference Figures 1 to 7 Here, an example of the configuration of the storage device in this embodiment will be described.

[0034] <Circuit Structure>

[0035] Figure 1 This is a block diagram illustrating an example of the configuration of the storage device in this embodiment.

[0036] like Figure 1 As shown, the storage device 1 in this embodiment includes a storage cell array 100 and a storage control circuit CC.

[0037] The storage cell array 100 includes multiple storage cells MC, multiple word lines WL, and multiple bit lines BL. Each storage cell MC is connected to at least one word line WL and at least one bit line BL. Each storage cell MC can store more than one bit of data.

[0038] For example, the storage device 1 in this embodiment is DRAM (Dynamic Random Access Memory). Each storage cell MC of DRAM 1 includes a field-effect transistor (hereinafter also referred to as a cell transistor) and a capacitor element (hereinafter also referred to as a cell capacitor). A more detailed description of the storage cell array 100 and the storage cells MC will be provided later.

[0039] The memory control circuit (hereinafter also referred to as CMOS circuit) is a circuit group consisting of multiple elements (such as field-effect transistors) formed on a semiconductor substrate (such as a silicon substrate).

[0040] The storage control circuit CC includes a row control circuit 110, a column control circuit 120, a read / write circuit 130, an input / output circuit 170, and a control circuit 190, etc.

[0041] Row control circuit 110 controls multiple rows of memory cell array 100. The decoded address result (row address) is supplied to row control circuit 110. Row control circuit 110 sets the row (e.g., word line) based on the decoded address result to a selected state. Hereinafter, the row (or word line) set to a selected state is referred to as a selected row (or selected word line). Rows other than selected rows are referred to as non-selected rows (or non-selected word lines). For example, row control circuit 110 includes a multiplexer (word line selection circuit) and a word line driver, etc.

[0042] Column control circuit 120 controls multiple columns of memory cell array 100. The decoded address (column address) from control circuit 190 is supplied to column control circuit 120. Column control circuit 120 sets a column (e.g., at least one bit line) to a selected state based on the decoded address. Hereinafter, the column (or bit line) set to the selected state is referred to as the selected column (or selected bit line). Columns other than the selected columns are referred to as non-selected columns (or non-selected bit lines). Column control circuit 120 includes a multiplexer (bit line selection circuit), bit line drivers, etc.

[0043] The read / write circuit 130 performs data writing (write operation) to the memory cell array 100 and data reading from the memory cell array 100 (read operation). During data writing, the read / write circuit 130 sends a signal (voltage or current) corresponding to the written data to the memory cell array 100 via the column control circuit 120. During data reading, the read / write circuit 130 receives a signal (voltage or current) corresponding to the read data from the memory cell array 100 via the column control circuit 120. Furthermore, the circuitry for data writing and data reading can be independently configured within the DRAM 1.

[0044] Input / output circuit (I / O circuit) 170 is an interface circuit for transmitting and receiving various signals between DRAM1 and other devices (hereinafter referred to as external devices) 2. During write operations, I / O circuit 170 transmits data DT from external device (controller or host device) 2 as write data to write circuit 140. During read operations, I / O circuit 170 transmits data output from memory cell array 100 to read circuit 150 as read data to external device 2. I / O circuit 170 transmits address ADR and command CMD from external device 2 to control circuit 190. I / O circuit 170 transmits and receives various control signals CNT between control circuit 190 and external device 2.

[0045] The control circuit (hereinafter also referred to as the sequencer) 190 controls other circuits 110, 120, 130, and 170 based on the command CMD and the control signal CNT.

[0046] In the case that the storage device 1 is DRAM, the control circuit 190 controls and performs the refresh (refresh operation) of the data in the storage cell array 100 in addition to the write and read operations.

[0047] For example, control circuit 190 controls circuits 110 to 170 at timings synchronized with clock signal CLK. As a result, write operations, read operations, and data transfers are performed at timings synchronized with clock signal CLK. Clock signal CLK is generated internally in DRAM 1A or supplied from external device 2.

[0048] In addition, DRAM1 may also include refresh control circuitry, clock generation circuitry, and internal voltage generation circuitry.

[0049] (Storage cell array)

[0050] Figure 2 This is an equivalent circuit diagram used to illustrate an example of the configuration of the DRAM memory cell array of this embodiment. As described above, the memory cell array 100 includes a plurality of memory cells MC. The plurality of memory cells MC are arranged in a matrix in the XY plane of the memory cell array 100.

[0051] One terminal of the memory cell MC is connected to the bit line BL. The other terminal of the memory cell MC is connected to the plate line (hereinafter also referred to as the plate electrode) PL. The control terminal of the memory cell MC is connected to the word line WL.

[0052] Multiple memory cells MC arranged in the X direction are connected to a word line WL among multiple word lines WL. Multiple memory cells MC arranged in the Y direction are connected to a bit line BL among multiple bit lines BL. Multiple memory cells MC of a certain control unit are connected to a common board line PL.

[0053] The memory cell MC includes a cell capacitor 10 and a cell transistor 20. The cell capacitor 10 holds a charge associated with more than one bit of data. The cell capacitor 10 functions as a storage element of the memory cell MC. The cell transistor 20 switches the connection between the memory cell MC and the bit line BL. The cell transistor 20 functions as a selection element (hereinafter also referred to as a switching element) of the memory cell MC.

[0054] One terminal of the transistor 20 (one source / drain) is connected to the bit line BL as a terminal of the memory cell MC. The other terminal of the transistor 20 (the other source / drain) is connected to one terminal of the cell capacitor 10 via node ND. The other terminal of the cell capacitor 10 is connected to the board line PL as a terminal of the memory cell MC. The gate of the transistor 20 is connected to the word line WL. The gate of the transistor 20 serves as the control terminal of the memory cell MC.

[0055] (Storage unit)

[0056] Figure 3 This is a bird's-eye view showing a construction example of a memory cell in the DRAM of this embodiment.

[0057] like Figure 3 As shown, in this embodiment, the unit transistor 20 overlaps vertically with the unit capacitor 10 in the Z direction. The Z direction is perpendicular to the XY plane. The Z direction intersects the X and Y directions.

[0058] The unit capacitor 10 includes at least two electrodes 11 and 13 and an insulating layer 12. The insulating layer (hereinafter also referred to as the capacitor insulating layer) 12 is disposed between the two electrodes (hereinafter also referred to as the capacitor electrodes) 11 and 13. One capacitor electrode 11 is electrically connected to the board line PL. The other capacitor electrode 13 is connected to the source / drain of the unit transistor 20.

[0059] At the bottom of the unit capacitor 10, a capacitor insulating layer 12 and a capacitor electrode 11 are disposed between the capacitor electrode 13 and the plate line PL. The capacitor insulating layer 12 and the capacitor electrode 13 are not in direct contact with the plate line PL.

[0060] The unit transistor 20 includes at least a semiconductor layer 21, a gate insulating layer 22, and a gate electrode 23. The semiconductor layer 21 (hereinafter also referred to as the channel layer or body) 21 has a columnar structure extending in the Z direction. The gate electrode 23 faces the side surface of the columnar semiconductor layer 21 (the Z-direction surface of the semiconductor layer 21) across the gate insulating layer 22. The gate insulating layer 22 is disposed between the side surface of the semiconductor layer 21 and the gate electrode 23. Hereinafter, the columnar semiconductor layer 21 is also referred to as a semiconductor pillar (or channel pillar).

[0061] The channel region 210 of the unit transistor 20 is disposed within the semiconductor layer 21. The two source / drain regions 211 and 212 of the unit transistor 20 are disposed within the semiconductor layer 21. The channel region 210 is disposed between the two source / drain regions 211 and 212.

[0062] In this embodiment, the unit transistor 20 is a vertical transistor. One of the two source / drain regions 211 and 212 (here, source / drain region 211) is disposed at one end (upper part) of the semiconductor layer 810 in the Z direction. The other of the two source / drain regions (here, source / drain region 212) is disposed at the other end (bottom) of the semiconductor layer 21 in the Z direction. The two source / drain regions 211 and 212 of the vertical transistor 20 are arranged in the Z direction. One of the two source / drain regions 211 and 212 is positioned above the other of the two source / drain regions in the Z direction.

[0063] The source / drain region 211 on the upper side of the unit transistor 20 is electrically connected to the bit line BL. The source / drain region 212 on the lower side of the unit transistor 20 is electrically connected to the capacitor electrode 13.

[0064] Thus, the current path of the vertical unit transistor 20 is along the Z direction. Current flows in the unit transistor 20 in the Z direction.

[0065] In this embodiment, the unit transistor 20 has a gate structure with a GAA (Gate all around) configuration. In the GAA configuration of the unit transistor 20, the gate electrode 23 completely overlaps with the sidewall of the channel region 210 within the semiconductor layer 21. The gate electrode 23 covers the sidewall of the channel region 210 in a ring shape, separated by the gate insulating layer 22. Therefore, the unit transistor 20 has high gate electrostatic control.

[0066] The gate electrode 23 is electrically connected to the conductive layer (hereinafter also referred to as the gate wiring) 25. The gate electrode 23 and the gate wiring 25 are a continuous layer (wiring) WL. The layer WL containing the gate electrode 23 and the conductive layer 25 functions as a word line. The layer WL is a word line WL and is used as the gate electrode 23 of the unit transistor 20.

[0067] In this embodiment, the memory cell array 100 and the memory cell MC are disposed above the semiconductor substrate 9 in the Z direction.

[0068] In this embodiment, the unit capacitor 10 is disposed within the pores of the alumina layer (hereinafter also referred to as the alumina layer). For example, the alumina layer is a porous alumina layer.

[0069] <Construction Example>

[0070] Reference Figures 4-7 The construction example of the DRAM in this embodiment will be described.

[0071] Figures 4-6 This is a cross-sectional view showing a construction example of the DRAM in this embodiment. Figure 4 The image shows a cross-section (XZ plane) of DRAM1 along the X direction. Figure 5 and Figure 6 The image shows a cross-section of DRAM1 along the Y direction (YZ plane). Figure 7 This is a top view showing a construction example of the DRAM in this embodiment. Figure 7 The diagram shows the plane (XY) of the memory cell array of DRAM1 as viewed from the Z direction.

[0072] like Figures 4-6 As shown, the DRAM1 of this embodiment has a structure in which the surface-side memory cell array 100 of the semiconductor substrate 9 is stacked on the memory control circuit CC.

[0073] The storage control circuit CC is disposed on the surface (first side) of the semiconductor substrate (e.g., silicon substrate) 9.

[0074] The memory cell array 100 is positioned above the memory control circuit CC in a direction perpendicular to the surface of the semiconductor substrate 9 (Z direction).

[0075] The memory control circuit CC includes multiple field-effect transistors (hereinafter simply referred to as transistors) TR. The transistors TR constitute circuits 110, 120, 130, 170, and 190, excluding the memory cell array of DRAM1. The multiple transistors TR are respectively disposed within active regions AA within the semiconductor substrate 9. Active regions AA are semiconductor regions within the semiconductor substrate 9 defined by the component separation region (insulating layer 41). A well region 40 of a certain conductivity type is disposed within the active regions AA. The conductivity type of the well region 40 corresponds to the conductivity type (n-channel or p-channel) of the transistor TR.

[0076] The gate electrode 31 of the transistor TR is disposed above the well region 40 in the Z direction, separated by a gate insulating layer 30. The gate insulating layer 30 is disposed between the gate electrode 31 and the well region 40. The source / drain regions 32a and 32b of the transistor TR are disposed within the well region 40. The two source / drain regions 32a and 32b sandwich the channel region of the transistor TR in a direction parallel to the upper surface of the semiconductor substrate 9. The gate electrode 31 faces the channel region within the well region 40, separated by the gate insulating layer 30.

[0077] The gate electrode 31 of the transistor TR is covered by an interlayer insulating layer 59 on the semiconductor substrate 9. A plurality of plugs (contacts) 50, 52 and conductive layers (pads or wiring) 51, 53 (53a, 53b, 53c) are provided in the interlayer insulating layer 59.

[0078] A plug 50 is disposed on the source / drain regions 32 (32a, 32b). A conductive layer (intermediate wiring) 51 is connected to the source / drain regions 32 via the plug 50. A plug 52 is disposed on the conductive layer 51. A conductive layer 53 is disposed above the conductive layer 51 in the Z direction. The conductive layer 53 is connected to the conductive layer 51 via the plug 52.

[0079] Thus, the storage control circuit CC includes a multilayer wiring structure 500 composed of plugs 50 and 52 within the interlayer insulating layer 59 and conductive layers 51 and 53. Within the multilayer wiring structure 500, multiple conductive layers 51 and 53 are layered in the Z direction. In this embodiment, the layering of the multilayer wiring structure 500 in which the conductive layers 51 and 53 are disposed is referred to as a wiring level (or layer). A wiring level indicates the position (height) of the wiring (conductive layer) in a direction perpendicular to the surface of the semiconductor substrate 9.

[0080] For example, alignment marks 49 are disposed in a region of the semiconductor substrate 9 (hereinafter referred to as the alignment mark region). Alignment marks 49 are used for positioning alignment between components in a manufacturing process during the formation of DRAM 1 (e.g., positioning alignment of the mask and the semiconductor substrate during lithography). Alternatively, alignment marks 49 may also be disposed within the multilayer wiring structure 500.

[0081] The memory cell array 100 includes an aluminum oxide layer 63. The aluminum oxide layer 63 is disposed above the semiconductor substrate 9 in the Z direction. The aluminum oxide layer 63 is a porous layer having multiple pores (hereinafter also referred to as aluminum oxide pores) MH. The aluminum oxide pores MH extend in the Z direction.

[0082] The unit capacitor 10 is disposed within the aluminum oxide layer 63. The unit transistor 20 is disposed above the aluminum oxide layer 63 in the Z direction. The unit capacitor 10 is disposed between the unit transistor 20 and the storage control circuit CC in the Z direction.

[0083] Figure 7 This illustrates an example of the layout of multiple capacitors (memory cells) within the memory cell array 100 of the DRAM in this embodiment.

[0084] Viewed from the Z-direction, multiple cell capacitors 10 are arranged in a hexagonal grid arrangement LY within the XY plane of the storage cell array 100 (alumina layer 63). One unit of the hexagonal grid arrangement LY comprises seven cell capacitors 10. Regarding the arrangement of the seven cell capacitors 10 within the hexagonal grid arrangement LY, six cell capacitors 10 are respectively positioned at the vertices of the hexagons, and the remaining cell capacitor 10 is positioned at the center of the hexagon.

[0085] For example, two unit capacitors 10 arranged in the X direction are arranged with a certain spacing D1. Two unit capacitors 10 arranged in the Y direction are arranged with a certain spacing D2.

[0086] According to the layout of the unit capacitor 10, the unit transistor 20 and the memory cell MC (and the alumina hole MH) are arranged in a hexagonal grid within the memory cell array 100.

[0087] return Figures 4-6 The construction of the memory cell MC will be explained.

[0088] Unit capacitor 10 is disposed within the alumina hole MH of the alumina layer 63 formed by anodizing.

[0089] The unit capacitor 10 includes two capacitor electrodes 11 and 13, a capacitor insulating layer 12, and a storage node electrode (embedded electrode) 14.

[0090] The storage node electrode 14 has, for example, a cylindrical (or elliptical) cylindrical structure. The storage node electrode 14 has a planar shape that is circular (or elliptical) when viewed from the Z direction.

[0091] The capacitor electrode 11 faces the side and bottom of the storage node electrode 14. The capacitor electrode 11 has a cylindrical (cup-shaped) structure. For example, the capacitor electrode 11 has a structure in which a cylindrical portion extending in the Z direction is connected to a bottom surface with a planar shape having a circular (or elliptical) shape.

[0092] The capacitor electrode 13 faces the side and bottom of the capacitor electrode 11 across the capacitor insulating layer 12. The capacitor electrode 13 is disposed between the storage node electrode 14 and the capacitor insulating layer 12. The capacitor electrode 13 has a cylindrical (or cup-shaped) structure. For example, the capacitor electrode 13 has a structure in which a cylindrical portion extending in the Z direction is connected to a bottom surface having a planar shape with a circular (or elliptical) shape. Furthermore, the capacitor electrode 13 and the storage node electrode 14 can also be a single structure formed of the same material.

[0093] A capacitor insulating layer 12 is disposed between capacitor electrode 11 and capacitor electrode 13. The side and bottom surfaces of capacitor insulating layer 12 face each other. Capacitor insulating layer 12 has a cylindrical structure. For example, capacitor insulating layer 12 has a structure in which a cylindrical portion extending in the Z direction is connected to a bottom surface having a planar shape with a circular (or elliptical) shape.

[0094] Capacitor electrode 11 and capacitor insulating layer 12 are disposed between capacitor electrode 13 and conductive layer 62. Capacitor electrode 11 is directly connected to plate electrode PL. Capacitor electrode 13 is separated from plate electrode PL.

[0095] The capacitor electrodes 11 and 13 comprise conductive compound layers (e.g., titanium nitride layers). The capacitor insulating layer 12 comprises a single or multiple highly dielectric layers (e.g., zirconium oxide layers or aluminum oxide layers). The storage node electrode 14 comprises a metal layer (e.g., a tungsten layer) or a conductive semiconductor layer (e.g., a polycrystalline silicon layer). Furthermore, the materials of the components 11, 12, 13, and 14 of the unit capacitor 10 are not limited to the materials described above.

[0096] Multiple unit transistors (vertical field-effect transistors with GAA structure) 20 are arranged in a hexagonal lattice in the XY plane. Within each memory cell MC, the position of the unit transistor 20 overlaps with the position of the unit capacitor 10 in the Z direction. The unit transistor 20 is positioned above the unit capacitor 10 and the memory control circuit CC in the Z direction. The unit transistor 20 is positioned below the bit line BL and above the board line PL in the Z direction.

[0097] As described above, the unit transistor 20 has a semiconductor layer 21, a gate insulating layer 22, and a gate electrode 23. The source / drain region and the channel region of the unit transistor 20 are disposed within the semiconductor layer 21.

[0098] Semiconductor layer 21 has a cylindrical structure extending in the Z direction. The planar shape of semiconductor layer 21 is circular. Semiconductor layer 21 extends in the Z direction across multiple layers 81, 65, and 82 stacked in the Z direction. Semiconductor layer 21 is an oxide semiconductor layer. For example, when an oxide semiconductor layer such as InGaZnO or InAlZnO is used in semiconductor layer 21 containing the channel region of the unit transistor, the off-leakage characteristics of the unit transistor 20 are improved. Furthermore, semiconductor layer 21 can also be a silicon layer, a germanium layer, or a compound semiconductor layer.

[0099] The gate insulating layer 22 has a cylindrical structure extending in the Z direction. The gate insulating layer 22 covers the side surface of the semiconductor layer 21. The cylindrical gate insulating layer 22 is concentric with respect to the cylindrical semiconductor layer 21. The gate insulating layer 22 is disposed on the side surface of the semiconductor layer 21. The gate insulating layer 22 is disposed between the semiconductor layer 21 and the gate electrode 23. The gate insulating layer 22 may comprise, for example, at least one of a silicon oxide layer and a highly dielectric insulating film. The gate insulating layer 22 can be a single-layer structure or a multilayer structure.

[0100] Multiple conductive layers 65 are disposed on the insulating layer 81 above the aluminum oxide layer 63 in the Z direction. Each conductive layer 65 extends in the X direction. Each conductive layer 65 includes a gate electrode 23 and a gate wiring 25. Thus, the gate electrode 23 and the gate wiring 25 are a continuous layer 65. The semiconductor layer 21 penetrates within the conductive layers 65.

[0101] The gate electrode 23 faces the side of the semiconductor layer 21 across the gate insulating layer 22. The portion of the semiconductor layer 21 facing the gate electrode 23 forms the effective channel region of the unit transistor 20. The gate electrode 23 may also have a cylindrical structure, for example.

[0102] Gate electrode 23 is connected to gate wiring 25. The gate electrodes 23 of a plurality of adjacent unit transistors 20 in the X direction are connected via gate wiring 25. Gate electrode 23 and gate wiring 35 function as word line WL. The conductive layer 65 containing gate electrode 23 and gate wiring 25 is, for example, a metal layer such as a tungsten layer, a conductive semiconductor layer, or a conductive compound layer.

[0103] Multiple conductive layers 66 are disposed in the Z direction on an insulating layer 82 above a conductive layer 65 (word line WL). The insulating layer 82 covers the conductive layer 65. Each conductive layer 66 extends in the Y direction. However, the conductive layer 66 may also have a portion that is parallel to the XY plane and extends in a direction inclined relative to the X and Y directions.

[0104] The conductive layer 66 functions as bit lines BL. Multiple bit lines BL are positioned in the Z direction overlapping with the unit transistor 20. For example, the bit lines BL are positioned above the unit transistor 20 in the Z direction. The bit lines BL are electrically connected to the semiconductor layer 21. The bit lines BL can also be electrically connected to the semiconductor layer 21 via plugs (not shown).

[0105] The conductive layer 66 is, for example, a metal layer such as an aluminum layer or a copper layer, a conductive semiconductor layer, or a conductive compound layer.

[0106] The plate electrode (plate line) PL is disposed in the Z direction between the memory cell array 100 and the memory control circuit CC. More specifically, the plate electrode PL is disposed in the Z direction between the cell capacitor 10 and the multilayer wiring structure 500.

[0107] The plate electrode PL includes two conductive layers (hereinafter also referred to as plate electrode layers) 61 and 62. Conductive layer 61 is disposed between conductive layer 62 and insulating layer 60. Conductive layer 62 is disposed between conductive layer 61 and alumina layer 63. Conductive layer 62 is in direct contact with capacitor electrode 11. Conductive layer 61 is electrically connected to capacitor electrode 11 via conductive layer 62. Conductive layer 61 includes a metal layer (e.g., a tungsten layer). Conductive layer 62 includes a conductive compound layer (e.g., a titanium nitride layer). The materials of plate electrode layers 61 and 62 are not limited to the materials described above.

[0108] The conductive layer 61 has a plate-like structure extending in the XY plane. The plate-like conductive layer 61 is electrically connected to a plurality of unit capacitors 10 arranged in two dimensions as the main part of the plate line PL. For example, the film thickness of the conductive layer 61 is uniform compared to that of the conductive layer 62.

[0109] The conductive layer 62 has a recess, for example, below the unit capacitor 10 (bottom of the unit capacitor 10) in the Z direction. The film thickness (dimension in the Z direction) t1 of the conductive layer 62 below the unit capacitor 10 is thinner than the film thickness t2 of the conductive layer 62 below the alumina layer 63. Furthermore, the conductive layer 62 may not be provided between the capacitor electrode 11 and the conductive layer 61. Even in this case, the conductive layer 62 is preferably provided between the alumina layer 63 and the conductive layer 61. However, the plate electrode PL may also have a single-layer structure with the conductive layer 61 but without the conductive layer 62. The insulating layer 60 functions as a protective layer for the storage control circuit CC in the manufacturing process, as described later. The insulating layer 60 is, for example, an oxide layer, a nitride layer, or a oxynitride layer. The insulating layer 60 may also be a layer continuous with the insulating layer of the multilayer wiring structure 500.

[0110] In this embodiment, the aluminum oxide layer 63 is adjacent to the insulating layer 80 in directions parallel to the surface of the semiconductor substrate 9 (X and Y directions). The insulating layer 80 is made of a different material than the aluminum oxide. For example, the insulating layer 80 is a layer containing silicon oxide.

[0111] Multiple contact plugs 70 (70a, 70b, 70c) are disposed within the insulating layer 80. The contact plugs 70 extend in the Z direction. The contact plugs 70 are arranged in the memory cell array 100 in either the X or Y direction. The contact plugs 70 penetrate in the Z direction within a region adjacent to the memory cell array 100 in either the X or Y direction.

[0112] Contact plug 70 electrically connects the wiring of the memory cell array 100 to the wiring of the memory control circuit CC. Figure 4 In this example, one end (bottom) of the contact plug 70a contacts the upper surface of the conductive layer 53a of the storage control circuit CC. The other end (upper part) of the contact plug 70a contacts the bottom surface of the plug 75 connected to the conductive layer 65 of the storage cell array 100. Figure 4 The diagram shows a configuration where a contact plug 70a is connected to the wiring (here, conductive layer 65) of the memory cell array 100 via another plug 75. However, the contact plug 70a may also directly contact and connect to the wiring 65 of the memory cell array 100 without using another plug.

[0113] exist Figure 5 In this example, one end (bottom) of the contact plug 70b contacts the upper surface of the conductive layer 53b of the storage control circuit CC. The other end (upper part) of the contact plug 70b contacts the bottom surface of the plug 76a connected to the conductive layer 66 of the storage cell array 100. Figure 5The diagram shows a configuration in which a contact plug 70b is connected to the wiring (here, conductive layer 66) of the memory cell array 100 via another plug 76a. However, the contact plug 70b may also directly contact and connect to the wiring 66 of the memory cell array 100 without going through another plug.

[0114] exist Figure 6 In this example, one end of contact plug 70c contacts the upper surface of the conductive layer 62 of the plate electrode PL. The other end of contact plug 70c contacts the bottom surface of the conductive layer 67 on the insulating layer 82 via plug 76b within the insulating layers 81 and 82. One end of contact plug 70d contacts the upper surface of the conductive layer 53c of the storage control circuit CC. The other end of contact plug 70d contacts the bottom surface of the conductive layer 67 via plug 76c within the insulating layers 81 and 82. The conductive layer 67 electrically connects the two contact plugs 70a and 70b. The plate electrode PL is connected to the wiring (conductive layer 53c) of the storage control circuit CC, which is located at a position lower than the unit capacitor 10Z, via the contact plugs 70a and 70b arranged in the Y direction and via the conductive layer 67, which is located at a position higher than the unit capacitor 10Z. Alternatively, the plate electrode PL can also be connected to the conductive layer within the storage control circuit CC via contact plugs arranged parallel to contact plug 70c in the X direction.

[0115] For example, the unit capacitor 10Z is a unit capacitor of a dummy unit that is not used for storing user data. In the dummy unit, a unit transistor may also be provided on the unit capacitor 10Z.

[0116] In this embodiment, the region 900 above the storage control circuit CC in the Z direction, where a plurality of contact plugs 70 are arranged, is referred to as the contact region 900. Hereinafter, the region where the storage cell array 100 is arranged is also referred to as the storage cell array region.

[0117] For example, Figure 7 As shown, a contact region 900 (and insulating layer 80) is disposed above the semiconductor substrate 9 in the Z direction, such that it surrounds the memory cell array 100 (alumina layer 63) in both the X and Y directions. The contact region 900 partially overlaps with the memory control circuit CC in the Z direction. Wiring within the memory cell array 100 (e.g., bit lines BL, word lines WL, and board lines PL) extends from the memory cell array (memory cell array region) 100 to the contact region 900. The wiring within the memory cell array 100 is electrically connected to the underlying memory control circuit CC (wiring within the multilayer wiring structure 500) via contact plugs 70 within the contact region 900.

[0118] As described above, within the alumina layer 63, alumina holes MH are regularly arranged in the X or Y direction at predetermined intervals (spaces) D1 and D2. Multiple alumina holes MH are arranged in a hexagonal grid LY in the XY plane.

[0119] For example, an alumina layer 63 containing multiple alumina pores MH is formed by an anodizing process on an aluminum layer.

[0120] Therefore, in this embodiment, it is possible to provide DRAM with high storage density and / or low bit cost.

[0121] Furthermore, the DRAM1 in this embodiment performs various work sequences, such as write operations and read operations, through well-known operations. Therefore, the description of the operation of DRAM1 is omitted in this embodiment.

[0122] (b) Manufacturing method

[0123] Reference Figures 8 to 18 The manufacturing method of the DRAM in this embodiment will be described.

[0124] Figure 8 This is a cross-sectional process diagram used to illustrate one process of the DRAM in this embodiment.

[0125] like Figure 8 As shown, multiple transistors TR are formed on the active region AA (well region 40) of the semiconductor substrate (silicon wafer) 9 using well-known layer formation techniques and well-known lithography / etching techniques. Each transistor TR includes a gate insulating layer 30, a gate electrode 31, and source / drain regions 32 (32a, 32b).

[0126] Multiple insulating layers (interlayer insulating layer 59) and multiple conductive layers (wiring, plugs and pads) 50, 51, 52, 53 for the multilayer wiring structure 500 are formed on top of the transistor TR and the semiconductor substrate 9 using well-known multilayer wiring techniques.

[0127] Therefore, the storage control circuit CC of DRAM1 is formed on the semiconductor substrate 9.

[0128] Figure 9 This is a cross-sectional process diagram used to illustrate one process of the DRAM in this embodiment.

[0129] like Figure 9As shown, the insulating layer 60 is formed on the multilayer wiring structure 500, for example, by a CVD (chemical vapor deposition) method. The insulating layer 60 functions as a protective film for the memory control circuit CC on the semiconductor substrate 9 during the anodizing process described later. The material of the insulating layer 60 is an oxide, nitride, or oxynitride. For example, the insulating layer 60 is a silicon oxide layer.

[0130] In addition, Figure 9 The insulating layer 60 is shown to cover only the upper surface of the semiconductor substrate 9, but the insulating layer 60 can also be formed to cover both the side and bottom surfaces of the semiconductor substrate 9. The insulating layer 60 can also be formed continuously with the insulating layer of the multilayer wiring structure 500 (e.g., the uppermost insulating layer of the multilayer wiring structure 500). In this case, the insulating layer 60 becomes a layer continuous with the insulating layer of the multilayer wiring structure 500.

[0131] The conductive layer 61 is formed on the insulating layer 60, for example, by sputtering, CVD, or ALD. For example, the conductive layer 61 is a tungsten layer. The conductive layer 62 is formed on the conductive layer 61, for example, by sputtering, CVD, or ALD. For example, the conductive layer 62 is a titanium nitride layer. Alternatively, the conductive layer 61 may be formed on the insulating layer 60 without forming the conductive layer 62.

[0132] A conductive layer 63A is formed on the conductive layer 62. The conductive layer 63A is, for example, an aluminum layer.

[0133] For example, the thickness of the aluminum layer 63A is approximately a few μm to several hundred μm. Preferably, the aluminum layer 63A uses high-purity aluminum with a purity of 99.90% or higher.

[0134] The aluminum layer 63A is formed, for example, by sputtering, plating, CVD, or bonding to the aluminum layer (aluminum substrate, aluminum foil) of the conductive layer 61.

[0135] For example, conductive layers 61 and 62 can be removed above the alignment mark 49 in the Z direction. This forms a step 999A at the end of the conductive layers 61 and 62. Furthermore, a protrusion comprising one or more of the multiple layers 60, 61, and 62 can be formed on the multilayer wiring structure 500 above the alignment mark 49. For example, this protrusion can be a step formed based on a component (e.g., an alignment mark) within the semiconductor substrate 9 or the multilayer wiring structure 500.

[0136] Figure 10 This is a cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0137] like Figure 10As shown, a mask layer (e.g., a resist mask or a hard mask) 90 is formed on the surface (upper surface) of the aluminum layer 63A in the Z direction by lithography (e.g., photolithography) and etching. The mask layer 90 has a plurality of openings (holes) 91. The openings 91 are portions used to form the reaction starting point for anodizing the aluminum layer 63A. For example, the plurality of openings 91 of the mask layer 90 are arranged in the hexagonal grid arrangement (hexagonal densest configuration) described above. Viewed from the Z direction, each opening 91 has a planar shape of a circle (ellipse).

[0138] The spacing D0 between the multiple openings 91 is approximately tens to hundreds of nm. The spacing D0 represents the distance between the centers of two openings 91 in the Y direction.

[0139] For example, patterning of the mask layer 90 is performed by aligning the position of a mask (not shown) with the semiconductor substrate (wafer) 9 using alignment marks for steps 999A of conductive layers 61, 62 or steps 999B of aluminum layer 63A corresponding to steps 999A. Alignment marks 49 can also be used to perform patterning of the mask layer 90.

[0140] Preferably, the upper surface of the aluminum layer 63A is planarized by planarization treatment such as CMP before the mask layer 90 is formed.

[0141] Based on the pattern of the mask layer 90, the upper surface of the aluminum layer 63A is etched by dry etching or wet etching.

[0142] Thus, a recess 99 is formed on the upper surface of the aluminum layer 63A. The depth of the recess 99 (the dimension in the direction perpendicular to the surface of the semiconductor substrate 9) is, for example, about a few nm to tens of nm. The recess 99 formed by etching becomes the reaction starting point for the anodizing of the aluminum layer 63A.

[0143] Figure 11 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0144] like Figure 11 As shown, the anodizing process is performed on the aluminum layer.

[0145] The aluminum layer and semiconductor substrate 9 are immersed in an electrolyte solution (e.g., sulfuric acid, oxalic acid, phosphoric acid, etc.) 79 within the anodizing apparatus 70.

[0146] In the electrolyte solution 79, the conductive layer 61 is configured as the anode (hereinafter also referred to as the anode electrode) for the anodizing process. A voltage (hereinafter referred to as the anodizing voltage) V1 for the anodizing process is applied to the conductive layer 61 from the voltage circuit 71. For example, the anodizing voltage V1 has a voltage value in the range of 10V to 30V.

[0147] In this embodiment, the conductive layer 61 of the anode used in the anodizing process is the same layer used as the plate electrode in the memory cell array of a DRAM. Therefore, the voltage for anodizing the aluminum layer is applied to the aluminum layer from the outer periphery of the semiconductor substrate (wafer) 9 in the X or Y direction.

[0148] In this embodiment, the insulating layer (e.g., silicon oxide layer) 60 serves as a protective film against the electrolyte solution and the anodizing voltage V1, protecting the device TR on the semiconductor substrate 9. Thus, damage and destruction of the device TR caused by the anodizing process are suppressed.

[0149] A porous alumina layer (alumina layer) 63 is formed on the semiconductor substrate 90, which includes the storage control circuit CC, by anodizing the aluminum layer.

[0150] By adjusting the anodic oxidation voltage V1, a hole (alumina hole) MH extending in a direction perpendicular to the upper surface of the semiconductor substrate 9 is formed in the alumina layer 63 at a spacing D1 corresponding to the spacing of the pre-formed reaction initiation point.

[0151] By adjusting the anodizing process time, the depth (dimension in the Z direction) of the alumina hole MH can be adjusted to the desired size. The anodizing voltage V1 is maintained at a constant value without modulation. Thus, the cross-sectional shape of the alumina hole MH observed from the X (or Y) direction is essentially quadrilateral. Furthermore, in the anodizing process for the aluminum layer, the magnitude of the anodizing voltage V1 can also be periodically modulated (at predetermined time intervals).

[0152] In this way, the shape of the formed alumina holes MH is controlled by the formation of the reaction initiation point in the anodization of the aluminum layer and by controlling the anodization voltage. Therefore, multiple alumina holes MH with a regular arrangement (e.g., a spacing D1 in the X direction) are formed in the memory cell array region.

[0153] In the anodizing process of the DRAM manufacturing process in this embodiment, an anodizing voltage V1 is supplied to the entire aluminum layer above the semiconductor substrate (wafer) 9 through the conductive layer 61. By applying the voltage through the conductive layer 61, the entire aluminum layer to be anodized is oxidized. Therefore, no aluminum layer remains on the conductive layer 62.

[0154] In the anodizing process, sometimes, corresponding to the material of the conductive layer 62, the conductive layer 62 is oxidized at the bottom of the alumina holes MH. In this case, compound 77 is formed on the conductive layer 62. If the conductive layer 62 is a titanium nitride layer, a titanium oxide (or titanium oxynitride) layer 77 is formed on the titanium nitride layer 62.

[0155] For example, the conductive layer 62 functions as a protective film to inhibit the oxidation (or etching) of the conductive layer 61 in the anodizing process. Thus, the conductive layer (in this case, the tungsten layer) 61 used on the anode electrode remains unoxidized between the aluminum oxide layer 63 and the insulating layer 60. The conductive layer 62 maintains a plate-like shape.

[0156] Furthermore, without the formation of the conductive layer 62, the upper surface of the conductive layer 61 may be oxidized at the bottom of the alumina hole MH. Therefore, the material of the conductive layer 61 is preferably an oxidation-resistant material.

[0157] Figure 12 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0158] like Figure 12 As shown, the compound 77X of the conductive layer 62 is selectively removed through etching via the alumina hole MH. As a result, the upper surface of the conductive layer 62 is exposed within the alumina hole MH.

[0159] The alumina layer 63X is selectively removed from areas other than the memory cell array region 100A, such as the contact region 900. As a result, in the alumina layer 63, the opening region 901 is formed in the region (contact region) above the contact portion 53 of the memory control circuit in the Z direction.

[0160] When the aluminum oxide layer 63 is removed, the aluminum above the semiconductor substrate 9 is transformed into a transparent aluminum oxide layer 63. Therefore, light used for alignment is transmitted to the alignment marks 49 on the semiconductor substrate 9 (or within the multilayer wiring structure 500). Thus, the removal of the aluminum oxide layer 63 can be performed by aligning the position of a mask using the alignment marks 49 on the semiconductor substrate 9 side.

[0161] Furthermore, the order in which the alumina layer 63X and compound 77X are removed is not limited. Compound 77X may be removed after the alumina layer 63X has been removed.

[0162] Figure 13 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0163] like Figure 13 As shown, a conductive layer (e.g., a titanium nitride layer) 11A is formed on the alumina layer 63 and the conductive layer 62 by CVD or ALD. The conductive layer 11A is used to form the capacitor electrode of the unit capacitor. The thickness of the conductive layer 11A is controlled so that the alumina pores MH are not blocked by the conductive layer 11A. The thickness of the conductive layer 11A is approximately a few nm.

[0164] Figure 14 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0165] like Figure 14 As shown, the conductive layer covering the upper surface of the alumina layer 63 is selectively removed by wet etching or dry etching. Thus, the conductive layer (capacitor electrode) 11 is separated according to each alumina hole MH.

[0166] An insulating layer (e.g., a highly dielectric insulating layer such as a zirconia layer) 12 is formed on the upper surface of the alumina layer 63 and on the conductive layer 11 by CVD or ALD.

[0167] Conductive layers (e.g., titanium nitride layers) 13 and 13X are formed on the insulating layer 12 using CVD or ALD methods. For example, the film thickness of the insulating layer 12 and the conductive layers 13 and 13X are controlled to prevent the alumina pores MH from being blocked by the insulating layer 12 and the conductive layers 13 and 13X. The film thickness of the insulating layer 12 and the conductive layers 13 and 13X are each approximately a few nanometers.

[0168] Conductive layers 14 and 14X are formed on conductive layers 13 and 13X. The alumina pores MH are filled through conductive layers 14 and 14X. Conductive layers 14 and 14X are silicon layers or silicon-germanium layers, etc.

[0169] Subsequently, the conductive layers 13X and 14X on the upper surface of the alumina layer 63 are etched back using either wet or dry etching. As a result, the conductive layers 13 and 14 are separated according to the alumina holes MH. Furthermore, the conductive layer 11 and the insulating layer 12 on the upper surface of the alumina layer 63 can also be removed simultaneously with the etching back of the conductive layers 13X and 14X.

[0170] Thus, the unit capacitor 10 is formed within the alumina pore MH of the alumina layer 63.

[0171] Figure 15 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0172] like Figure 15As shown, the mask layer 93 is formed within the memory cell array region 100A by lithography and etching. The mask layer 93 has an opening within the contact region 900. Based on the mask layer 93, conductive layers 61 and 62 are selectively removed within the contact region 900. For example, alignment for forming the mask layer 93 is performed using alignment marks 49 provided on the semiconductor substrate 9 side.

[0173] Within the memory cell array region 100A, conductive layers 61 and 62 remain below the cell capacitor 10 and the aluminum oxide layer 63. Thus, a plate line PL, comprising one or more conductive layers (plate electrode layers) 61 and 62, is formed within the memory cell array region 100A.

[0174] Furthermore, the conductive layers 61 and 62 within the contact area 900 can also be removed simultaneously with the alumina layer within the contact area 900 and / or the components of the unit capacitor 10 within the contact area 900. Alternatively, after the unit capacitor 10 is formed, the alumina layer within the contact area 900 and / or the components of the unit capacitor 10 can be removed from the contact area 900 simultaneously with the removal of the conductive layers 61 and 62 within the contact area 900.

[0175] Figure 16 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0176] like Figure 16 As shown, after the mask layer is removed, an insulating layer (e.g., a silicon oxide layer) 80 is formed above the semiconductor substrate 9 in the Z direction within the memory cell array region 100A and the contact region 900, for example, by CVD or coating. The insulating layer 80 is deposited on conductive layers 13, 14 and insulating layers 12, 60, 63, etc. The insulating layer 80 is embedded within the contact region 900 (in the space adjacent to the memory cell array region 100A in the X and Y directions).

[0177] The upper surface of the formed insulating layer 80 is subjected to etching back and CMP processes, etc. The upper surface of the insulating layer 80 is planarized. Thus, the insulating layer 80 is formed within the contact area 900.

[0178] Figure 17 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0179] like Figure 17 As shown, contact holes CH are formed in the insulating layers 60 and 80 at predetermined positions within the contact area 900 by well-known lithography and etching. Below the contact area 900 in the Z direction, the upper surface of the conductive layer 53 within the multilayer wiring structure 500 is exposed through the contact holes CH.

[0180] The contact plug 70 is formed within the contact hole CH using known techniques. The contact plug 70 contacts the upper surface of the conductive layer 53. The contact plug 70 is electrically connected to the storage control circuit CC via the conductive layer 53.

[0181] Figure 18 This is a schematic cross-sectional process diagram used to illustrate one step of the DRAM manufacturing method of this embodiment.

[0182] like Figure 18 As shown, insulating layer 81 is formed on insulating layers 12 and 80 and conductive layers 13 and 14 using known techniques. Contact holes are formed within insulating layer 81. Thus, the upper surface of contact plug 70 is exposed.

[0183] The through-hole plug (contact portion) 75 is embedded in the contact hole of the insulating layer 81. The through-hole plug 75 is formed on the contact plug 70 in the Z direction.

[0184] Multiple conductive layers 65A with a predetermined pattern are formed on the insulating layer 81 by sputtering and lithographic printing / etching. The conductive layers 65A are connected, for example, to contact plugs 75. For example, the conductive layer 65A is a layer used to form word lines WL.

[0185] After that, as Figures 4-6 As shown, a plurality of unit transistors 20 and bit lines BL are formed. The plurality of unit transistors 20 are formed above an aluminum oxide layer 63 in the Z direction using known techniques. The unit transistors 20 are each formed above their corresponding unit capacitors 10 in the Z direction.

[0186] For example, an opening is formed within the insulating layers 81 and 82 and the conductive layer 65. This exposes the upper surface of the conductive layer (storage node electrode) 14 of the unit capacitor 10. A gate insulating layer 22 is formed within the opening. The gate insulating layer 22 covers the side surfaces (planes along the Z direction) of the insulating layers 81 and 82 and the conductive layer 65. After the insulating layer 22 on the storage node electrode 14 is selectively removed, a semiconductor layer (e.g., an oxide semiconductor layer) 21 is formed within the opening. The semiconductor layer 21 faces the conductive layer 23 across the gate insulating layer 22. This forms the unit transistor 20. The unit transistor 20 is electrically connected to the unit capacitor 10.

[0187] When an oxide semiconductor layer (e.g., an InGaZnO layer or an InAlZnO layer) is used for the semiconductor layer (body portion) 21 of the unit transistor 20, this oxide semiconductor layer can be formed using a relatively low-temperature process. Therefore, in this case, compared to forming the semiconductor layer 21 using a high-temperature process, it is possible to suppress the degradation of the characteristics of the unit capacitor 10 and / or the transistor TR on the semiconductor substrate 9 due to the heat generated during the formation process of the unit transistor.

[0188] Next, wiring (e.g., bit lines) 66 and pads (not shown) are formed on the insulating layer 82. Bit lines 66 are connected to the semiconductor layer 21. For example, an insulating layer (not shown) is formed on the bit lines 66 and the pads. A DRAM chip is formed by dicing the wafer.

[0189] As described above, the DRAM of this embodiment is formed.

[0190] (c) Summary

[0191] In order to increase the storage density in storage devices and reduce manufacturing costs, various structures and manufacturing methods for storage devices have been researched and developed.

[0192] In the memory device (e.g., DRAM) of this embodiment, an anodizing process is used in the formation of the memory cell array 100. The memory cell array 100 includes memory cells disposed within an alumina layer 63. In this embodiment, the memory cell includes a capacitor 10 disposed within a hole MH within the alumina layer 63 as a memory element. As described above, by forming the alumina layer 63 based on the anodizing process, a plurality of holes MH can be formed with relatively uniform spacing D1, D2.

[0193] The holes MH formed in the alumina layer 63 by the anodizing process have a relatively high aspect ratio (the ratio of the dimension of the hole in the direction parallel to the surface of the semiconductor substrate to the dimension in the direction perpendicular to the surface of the semiconductor substrate). Therefore, as in this embodiment, when forming a unit capacitor using the anodizing process, the diameter of the holes is miniaturized, and a capacitor with a relatively large capacitance can be formed. As a result, the memory device of this embodiment can improve data retention characteristics.

[0194] Compared to forming holes through dry etching, wet etching anodizing processes can form high aspect ratio holes within a layer at a relatively low cost. As a result, the memory device and its manufacturing method of this embodiment can reduce manufacturing costs.

[0195] In this embodiment, an insulating layer 60 is disposed between the aluminum oxide layer 63 of the memory cell array 100 and the semiconductor substrate 9 (a multilayer wiring structure of the memory control circuit CC). During the anodizing of the aluminum layer above the semiconductor substrate 9, the insulating layer 60 functions as a protective film for the solvent used in anodizing and / or for the memory control circuit CC that applies voltage during anodizing.

[0196] Thus, even if anodizing is performed on the aluminum layer on the semiconductor substrate 9 including the storage control circuit CC, the insulating layer 60 protects multiple components (e.g., transistor TR) within the storage control circuit CC from the solvent used for anodizing and the applied voltage.

[0197] Therefore, the memory device and its manufacturing method of this embodiment can suppress the characteristic degradation of the memory control circuit CC caused by the anodizing process.

[0198] In this embodiment, the cell transistors of the memory cells are formed after the anodizing process of the aluminum layer. Therefore, in this embodiment, there is substantially no degradation of the cell transistor characteristics caused by the anodizing process. When an oxide semiconductor layer is used for the semiconductor layer of the cell transistor, this oxide semiconductor layer can be formed at a relatively low process temperature. Therefore, damage caused by heat during the cell transistor formation process can be suppressed in components formed in the manufacturing processes preceding the cell transistor (e.g., cell capacitors and transistors in CMOS circuits). As a result, the memory device and its manufacturing method of this embodiment can improve the characteristics of the memory device.

[0199] A plurality of contact plugs 70 are provided in regions 900 adjacent to the memory cell array 100 in the X and Y directions. The contact plugs 70 electrically connect the memory cell array 100 to the memory control circuit CC.

[0200] Therefore, according to this embodiment, even when the memory cell array 100 is formed on a semiconductor substrate on which the memory control circuit CC is provided by anodizing process, the memory cell array 100 can be electrically connected to the memory control circuit CC below the memory cell array 100 without using complex manufacturing processes and / or high-cost manufacturing processes.

[0201] As a result, the storage device and its manufacturing method of this embodiment can suppress the high cost of storage devices.

[0202] As described above, the memory device of this embodiment can provide a memory device with low manufacturing cost. The memory device of this embodiment can provide a memory device with high performance.

[0203] The method for manufacturing the storage device according to this embodiment can reduce the manufacturing cost of the storage device.

[0204] (2) Second implementation method

[0205] Reference Figure 19 and Figure 20 The storage device of the second embodiment and the method for manufacturing the storage device will be described.

[0206] Figure 19 This is a top view showing one step of the manufacturing process of the storage device (e.g., DRAM) according to this embodiment.

[0207] like Figure 19 As shown above, an alumina layer containing multiple alumina pores (porous alumina layer) is formed by an anodizing process. Multiple unit capacitors 10 are formed within the alumina layer 63.

[0208] Next, the process of forming contact plugs (e.g., word line contacts) 70X within the contact area 900 is performed. Contact holes CH (CHX, CHY) are formed within the contact area 900 based on the mask pattern. Contact plugs 70 (70X, 70Y) are embedded within the contact holes CH.

[0209] In this embodiment, regarding the alignment of the mask when forming the contact plug 70, different components are used to align the formation position (configuration coordinate) of the contact hole CHX (and the contact plug 70) in the X direction in the X direction and the position in the Y direction.

[0210] The formation position of the contact hole CHX in the X direction is determined based on the contact portion (plug or pad) 53X on the semiconductor substrate 9 side (on the semiconductor substrate 9 or within the multilayer wiring structure 500). Furthermore, in Figure 19 In order to make the semiconductor substrate 9 side contact portion 53X visually recognizable, the contact portion 53X is represented by a quadrilateral planar shape, but the planar shape of the contact portion 53X can also be circular (elliptical).

[0211] At least one cell capacitor 10 within the storage cell array region 100A (e.g., two or more cell capacitors 10 arranged in the X direction) is used as alignment marks 49X to define the formation position of the contact hole CHX in the Y direction. As described above, the alumina holes MH and cell capacitors 10 within the alumina layer 63 formed by anodizing are arranged in the XY plane with a relatively uniform spacing. Therefore, as in this embodiment, it is useful to use the cell capacitors 10 as marks for mask position alignment.

[0212] Thus, multiple contact holes CHX and multiple contact plugs 70X are formed within the contact area 900 using known techniques, such that the positions of the contact holes CHX and contact plugs 70X match the positions of the word lines formed in subsequent processes.

[0213] For example, regarding the layout of the word line contacts 70X, multiple word line contacts 70X are arranged within the contact area 900 such that they are adjacent in the direction parallel to the X and Y directions and in the oblique direction.

[0214] Then, as described above, a conductive layer for forming word lines is formed above the plurality of unit capacitors 10 arranged along the X direction.

[0215] Regarding the formation of the contact plug 70Y in the Y direction region of the contact area 900, similarly to the example of forming word line contacts, multiple unit capacitors 20 arranged in the Y direction are used as alignment marks (reference components) for mask position alignment.

[0216] For example, during the alignment of the mask when forming the contact plug (e.g., bit line contact) 70Y for connecting the bit line BL to the memory control circuit CC, the contact components (e.g., contacts within the multilayer wiring structure 500) 53Y on the semiconductor substrate 9 side are used as a reference for the formation position (configuration coordinates) of the contact hole CHY (and the contact plug 70Y) in the Y direction. Within the memory cell array 100, a plurality of cell capacitors 10 arranged in the Y direction are used as alignment marks 49Y as a reference for the formation position of the contact holes in the X direction.

[0217] Thus, multiple contact plugs 70Y are formed within the contact area 900 so that the position of the contact plugs 70Y matches the position of the bit lines formed in subsequent processes.

[0218] Furthermore, regarding the positional alignment of the contact hole CH and contact plug 70 in this embodiment, the alignment mark 49 within the semiconductor substrate 9 (or the multilayer wiring structure 500) can also be used as a component on the semiconductor substrate side. Alternatively, after a rough positional alignment of the mask based on the alignment mark 49, fine adjustments to the mask's positional alignment can be performed using contacts on the semiconductor substrate side and components within the memory cell array (e.g., cell capacitors).

[0219] Figure 20 This is a top view showing one step of the manufacturing process of the storage device (e.g., DRAM) according to this embodiment.

[0220] like Figure 20 As shown, the unit transistor 20 can also be used as an alignment mark to perform position alignment of the mask for forming the contact portion.

[0221] For example, a contact portion 70Z (such as the via plug 75 described above) is formed after forming the unit transistor 20 and before forming the bit line BL.

[0222] When forming the contact portion 70Z, the formation position of the contact portion 70Z in the Y direction is set based on the alignment of the mask used to form the contact hole CHZ, according to the contact plug 70Y within the contact region 900. The formation position of the contact portion 70Z in the X direction is set using the cell transistors 20 (e.g., two or more cell transistors 20 arranged in the Y direction) within the memory cell array region 100A as alignment marks 49Z.

[0223] Thus, multiple contact holes CHZ and multiple contact portions 70Z are formed within the contact area 900 using known techniques, so that the position of the contact plug 70Z matches the position of the word lines formed in subsequent processes.

[0224] In addition, it can also be with Figure 20 Similarly, the unit transistor 20 is used as alignment mark 49 to form a contact in the X direction within the contact region 900.

[0225] Sometimes, corresponding to the method of forming the aluminum layer in the anodizing process, the alignment accuracy of the reaction starting point used to form the alumina holes may decrease. Consequently, the alignment accuracy of the contacts used to connect the wiring of the memory control circuitry to the wiring (word lines and bit lines) of the memory cell array formed after the anodizing process may also decrease.

[0226] For example, due to the reduction in alignment accuracy, multiple adjacent word lines in the Y direction will be connected to a contact plug, and multiple adjacent bit lines in the X direction will be connected to a contact plug.

[0227] In this embodiment, alignment for forming contact plugs after the anodizing process is performed using components disposed on the semiconductor substrate side (e.g., contacts of the storage control circuit) and components formed after the anodizing process (e.g., unit capacitor 10).

[0228] Therefore, in this embodiment, the alignment accuracy of wiring and contact plugs within the memory cell array and the memory control circuit is improved. For example, according to this embodiment, short circuits in the wiring within the memory cell array are reduced. As a result, the manufacturing method of the memory device according to this embodiment can improve the manufacturing yield of the memory device.

[0229] As described above, the method for manufacturing the storage device according to this embodiment can reduce the manufacturing cost of the storage device.

[0230] (3) Other

[0231] In the above embodiments, DRAM was exemplified as the memory device of this embodiment. However, the memory device of this embodiment can be any memory device other than DRAM, as long as it includes a porous alumina layer formed by anodizing.

[0232] Furthermore, in the above-described embodiment, a storage device was exemplified as the device in this embodiment. However, the device in this embodiment can be any device other than a storage device, as long as it includes a porous alumina layer formed by anodizing.

[0233] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: Semiconductor substrate; A circuit disposed on a first surface of the semiconductor substrate, including a first contact portion; An aluminum oxide layer is disposed above the semiconductor substrate in a first direction perpendicular to the first surface; Storage unit, which includes a capacitor disposed within the alumina layer; A first conductive layer is disposed in the first direction between the semiconductor substrate and the aluminum oxide layer and is electrically connected to the memory cell. A first insulating layer is disposed in the first direction between the first conductive layer and the semiconductor substrate; A second insulating layer is adjacent to the aluminum oxide layer in a second direction parallel to the first surface and is disposed above the semiconductor substrate in the first direction; as well as A second contact portion is disposed within the second insulating layer and positioned above the first contact portion in the first direction, electrically connecting the storage unit to the first contact portion.

2. The storage device according to claim 1, further comprising: Word lines, which are disposed above the alumina layer in the first direction and are electrically connected to the memory cell; and Bit lines, which are disposed above the alumina layer in the first direction and connected to the memory cells, are provided. The memory cell is electrically connected to the second contact via one of the word line and the bit line.

3. The storage device according to claim 1 or 2, The capacitor extends within the alumina layer along the first direction.

4. The storage device according to claim 1, The storage cell further includes a unit transistor disposed above the alumina layer in the first direction, the unit transistor comprising an oxide semiconductor layer.

5. The storage device according to claim 1, The materials of the first insulating layer and the second insulating layer are different from aluminum oxide.

6. A method for manufacturing a storage device, comprising: A semiconductor circuit including a first contact portion is formed on the first surface of a semiconductor substrate; A first insulating layer is formed above the semiconductor circuit in a first direction perpendicular to the first surface; A first conductive layer is formed above the first insulating layer in the first direction; An aluminum layer is formed above the first conductive layer in the first direction; A porous aluminum oxide layer is formed by anodic oxidation of the aluminum layer, in which the first conductive layer is used as the anode. A capacitor electrically connected to the first conductive layer is formed within the hole; An opening region is formed within the alumina layer above the first contact portion in the first direction; A second insulating layer is formed within the opening area; as well as A second contact portion is formed within the second insulating layer, which connects to the first contact portion.

7. The method for manufacturing a storage device according to claim 6, further comprising: Before forming the aluminum layer, a third conductive layer is formed on the first conductive layer; and The compound formed on the third conductive layer by the anodic oxidation is removed.

8. The method for manufacturing a storage device according to claim 6 or 7, further comprising: Using the first contact portion and the capacitor, position alignment is performed to form the second contact portion.

9. The method for manufacturing a storage device according to claim 6, further comprising: A transistor comprising an oxide semiconductor layer is formed above the capacitor in the first direction and is connected to the capacitor.

10. The method for manufacturing a storage device according to claim 6, further comprising: In the first direction, a second conductive layer is formed above the alumina layer and connected to the second contact portion.

Images