Low frequency oscillation circuit, oscillator, power supply and electronic equipment

Abstract

The present disclosure relates to a low-frequency oscillation circuit, an oscillator, a power supply and an electronic device, wherein the circuit comprises: a reference current generating module for generating a reference current; a loop oscillation module connected to the reference current generating module, comprising a second delay oscillation unit, a first delay oscillation unit, a first inverter, a second inverter, a second NAND gate and a first NAND gate, wherein the second delay oscillation unit is used to delay the second signal for a second time according to the reference current, and the first delay oscillation unit is used to delay the first signal for a first time according to the reference current, and the oscillation frequency of the first signal is the reciprocal of the sum of the first time and the second time. The oscillation frequency of the first signal output by the low-frequency oscillation circuit proposed in the embodiment of the present disclosure is related to the first time and the second time, and is not related to the power supply voltage, thereby eliminating the influence of the power supply voltage on the oscillation frequency and improving the stability of the oscillation frequency.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a low-frequency oscillation circuit, an oscillator, a power supply and an electronic device. Background Art

[0002] An oscillator is an electronic component used to generate repetitive electronic signals (usually sine waves or square waves). It is an indispensable device in electronic equipment and circuit design. The oscillator in related technologies is more sensitive to the power supply voltage, and its oscillation frequency often changes with the change of the power supply voltage, and its stability is relatively low. Summary of the invention

[0003] In view of this, the present disclosure proposes a low-frequency oscillation circuit, the circuit comprising:

[0004] A reference current generating module, used for generating a reference current;

[0005] The loop oscillation module is connected to the reference current generating module, and includes a second delay oscillation unit, a first delay oscillation unit, a first inverter, a second inverter, a second NAND gate, and a first NAND gate, wherein:

[0006] The first input end of the second delay oscillation unit is connected to the output end of the first inverter for receiving a second signal, the output end of the second delay oscillation unit is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the first NAND gate, the output end of the second NAND gate is connected to the second input end of the first NAND gate and the input end of the second inverter, the first input end of the first NAND gate is connected to the output end of the first delay oscillation unit, the input end of the first inverter and the first input end of the first delay oscillation unit are connected to the output end of the second inverter for receiving the first signal,

[0007] The second input end of the second delay oscillation unit and the second input end of the first delay oscillation unit are connected to the reference current generating module, the second delay oscillation unit is used to delay the second signal for a second time according to the reference current, and the first delay oscillation unit is used to delay the first signal for a first time according to the reference current.

[0008] The oscillation frequency of the first signal is the reciprocal of the sum of the first time and the second time.

[0009] In a possible implementation, the reference current generating module includes a first PMOS transistor, a second PMOS transistor, a resistor, and a first NMOS transistor, wherein:

[0010] The source of the first PMOS transistor is connected to the source of the second PMOS transistor for receiving a power supply voltage, and the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor, and the first end of the resistor.

[0011] The second end of the resistor is connected to the source of the first NMOS transistor and the ground.

[0012] The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor,

[0013] The first PMOS transistor and the second PMOS transistor have the same width-to-length ratio.

[0014] The current flowing through the resistor is the reference current.

[0015] In a possible implementation, the first delay oscillation unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a first capacitor, a third inverter, and a fourth inverter, wherein:

[0016] The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor for receiving the power supply voltage, and the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor.

[0017] The gate of the fifth PMOS transistor is connected to the gate of the second NMOS transistor, and is used to receive the first signal.

[0018] The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor, the first end of the first capacitor, and the gate of the fourth PMOS transistor.

[0019] The source of the second NMOS transistor is connected to the second end of the first capacitor, the source of the third NMOS transistor and ground,

[0020] The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor,

[0021] The drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor and the input end of the third inverter.

[0022] The output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the first input end of the first NAND gate.

[0023] In a possible implementation, the second delay oscillation unit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, a fifth inverter, and a sixth inverter, wherein:

[0024] The gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor, the source of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor for receiving the power supply voltage, and the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor.

[0025] The gate of the eighth PMOS transistor is connected to the gate of the fourth NMOS transistor, and is used to receive the second signal.

[0026] The drain of the eighth PMOS transistor is connected to the drain of the fourth NMOS transistor, the first end of the second capacitor, and the gate of the seventh PMOS transistor.

[0027] The source of the fourth NMOS transistor is connected to the second end of the second capacitor, the source of the fifth NMOS transistor and ground,

[0028] The gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor,

[0029] The drain of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor and the input terminal of the fifth inverter.

[0030] The output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the first input end of the first NAND gate.

[0031] In a possible implementation manner, the width-to-length ratio of the third PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor is the same as the width-to-length ratio of the first PMOS transistor and the second PMOS transistor.

[0032] The first NMOS transistor, the third NMOS transistor, and the fifth NMOS transistor have the same width-to-length ratio.

[0033] In a possible implementation manner, the capacitance of the first capacitor is the same as that of the second capacitor.

[0034] In a possible implementation manner, an oscillation frequency of the first signal is related to the resistor, the first capacitor, and the second capacitor.

[0035] According to another aspect of the present disclosure, an oscillator is provided, wherein the oscillator comprises the low-frequency oscillation circuit.

[0036] According to another aspect of the present disclosure, a power supply is provided, wherein the power supply comprises the oscillator.

[0037] According to another aspect of the present disclosure, an electronic device is provided, wherein the electronic device includes the power supply.

[0038] In the low-frequency oscillation circuit proposed in the embodiment of the present disclosure, both the first delay oscillation unit and the second delay oscillation unit use the reference current delay signal generated by the reference current generating module, so that the oscillation frequency of the first signal output by the oscillation circuit is related to the first time and the second time, and is independent of the power supply voltage, thereby eliminating the influence of the power supply voltage on the oscillation frequency and improving the stability of the oscillation frequency.

[0039] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0041] Figure 1 A schematic diagram of a low-frequency oscillation circuit according to an embodiment of the present disclosure is shown.

[0042] Figure 2 A schematic diagram of a low-frequency oscillation circuit according to an embodiment of the present disclosure is shown.

[0043] Figure 3 FIG. 4 is a schematic diagram showing an oscillation time according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0045] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0048] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0049] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0050] See also Figure 1 , Figure 1 A schematic diagram of a low-frequency oscillation circuit according to an embodiment of the present disclosure is shown.

[0051] like Figure 1 As shown, the circuit comprises:

[0052] A reference current generating module 10, used to generate a reference current Ir;

[0053] The loop oscillation module 20 is connected to the reference current generating module 10, and includes a second delay oscillation unit 220, a first delay oscillation unit 210, a first inverter N1, a second inverter N2, a second NAND gate NAND2, and a first NAND gate NAND1, wherein:

[0054] The first input end of the second delay oscillation unit 220 is connected to the output end of the first inverter N1, for receiving the second signal A2, the output end of the second delay oscillation unit 220 is connected to the first input end of the second NAND gate NAND2, the second input end of the second NAND gate NAND2 is connected to the output end of the first NAND gate NAND1, the output end of the second NAND gate NAND2 is connected to the second input end of the first NAND gate NAND1 and the input end of the second inverter N2, the first input end of the first NAND gate NAND1 is connected to the output end of the first delay oscillation unit 210, the input end of the first inverter N1 and the first input end of the first delay oscillation unit 210 are connected to the output end of the second inverter N2, for receiving the first signal OUT,

[0055] The second input end of the second delay oscillation unit 220 and the second input end of the first delay oscillation unit 210 are connected to the reference current generating module 10. The second delay oscillation unit 220 is used to delay the second signal A2 for a second time according to the reference current Ir. The first delay oscillation unit 210 is used to delay the first signal OUT for a first time according to the reference current Ir.

[0056] The oscillation frequency of the first signal OUT is the reciprocal of the sum of the first time and the second time.

[0057] In the low-frequency oscillation circuit proposed in the embodiment of the present disclosure, both the first delay oscillation unit and the second delay oscillation unit use the reference current delay signal generated by the reference current generating module, so that the oscillation frequency of the first signal output by the oscillation circuit is related to the first time and the second time, and is independent of the power supply voltage, thereby eliminating the influence of the power supply voltage on the oscillation frequency and improving the stability of the oscillation frequency.

[0058] In a possible implementation, the oscillation circuit of the embodiment of the present disclosure may further include an output unit for buffering and then outputting the first signal OUT. The embodiment of the present disclosure does not limit the specific implementation of the output unit.

[0059] The following is an exemplary introduction to possible implementations of the low-frequency oscillation circuit.

[0060] See also Figure 2 , Figure 2A schematic diagram of a low-frequency oscillation circuit according to an embodiment of the present disclosure is shown.

[0061] In a possible implementation, Figure 2 As shown, the reference current generating module 10 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a resistor R, and a first NMOS transistor MN1, wherein:

[0062] The source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2 for receiving the power supply voltage VDD, and the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, the drain of the first PMOS transistor MP1, and the first end of the resistor R.

[0063] The second end of the resistor R is connected to the source of the first NMOS transistor MN1 and the ground.

[0064] The drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1.

[0065] The first PMOS transistor MP1 and the second PMOS transistor MP2 have the same width-to-length ratio.

[0066] The current flowing through the resistor R is the reference current Ir.

[0067] Through the above reference current generating module, the embodiment of the present disclosure can generate the required reference current, and by setting the first PMOS transistor MP1 and the second PMOS transistor MP2 to have the same width-to-length ratio, the embodiment of the present disclosure can make the current Ir0 at the drain end of the second PMOS transistor equal to the reference current Ir, so that the reference current Ir can be used to achieve low-frequency oscillation subsequently, and generate an oscillation signal (first signal) whose oscillation frequency is independent of the power supply voltage.

[0068] In one example, a MOS tube is a metal-oxide-semiconductor field effect transistor, or a metal-insulator-semiconductor. The source and drain of a MOS tube can be swapped. In most cases, the two regions are the same, and the performance of the device will not be affected even if the two ends are swapped. PMOS tubes mainly conduct electricity through holes, while NMOS tubes mainly conduct electricity through electrons.

[0069] In a possible implementation, Figure 2As shown, the first delay oscillation unit 210 may include a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third NMOS transistor MN3, a first capacitor C1, a third inverter N3, and a fourth inverter N4, wherein:

[0070] The source of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4 for receiving the power supply voltage VDD, and the drain of the third PMOS transistor MP3 is connected to the source of the fifth PMOS transistor MP5.

[0071] The gate of the fifth PMOS transistor MP5 is connected to the gate of the second NMOS transistor MN2 and is used to receive the first signal OUT.

[0072] The drain of the fifth PMOS transistor MP5 is connected to the drain of the second NMOS transistor MN2, the first end of the first capacitor C1, and the gate of the fourth PMOS transistor MP4.

[0073] The source of the second NMOS transistor MN2 is connected to the second end of the first capacitor C1, the source of the third NMOS transistor MN3 and the ground VSS.

[0074] The gate of the third NMOS transistor MN3 is connected to the gate of the first NMOS transistor MN1 (the connection point is N_BIAS),

[0075] The drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4 and the input terminal of the third inverter N3.

[0076] The output end of the third inverter N3 is connected to the input end of the fourth inverter N4 , and the output end of the fourth inverter N4 is connected to the first input end of the first NAND gate NAND1 .

[0077] In a possible implementation, Figure 2 As shown, the second delay oscillation unit 220 may include a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a second capacitor C2, a fifth inverter N5, and a sixth inverter N6, wherein:

[0078] The gate of the sixth PMOS transistor MP6 is connected to the gate of the third PMOS transistor MP3, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 (the connection point is P_BIAS), the source of the sixth PMOS transistor MP6 is connected to the source of the seventh PMOS transistor MP7 for receiving the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8.

[0079] The gate of the eighth PMOS transistor MP8 is connected to the gate of the fourth NMOS transistor MN4 for receiving the second signal A2.

[0080] The drain of the eighth PMOS transistor MP8 is connected to the drain of the fourth NMOS transistor MN4, the first end of the second capacitor C2, and the gate of the seventh PMOS transistor MP7.

[0081] The source of the fourth NMOS transistor MN4 is connected to the second end of the second capacitor C2, the source of the fifth NMOS transistor MN5 and the ground VSS.

[0082] The gate of the fifth NMOS transistor MN5 is connected to the gate of the first NMOS transistor MN1 (the connection point is N_BIAS),

[0083] The drain of the fifth NMOS transistor MN5 is connected to the drain of the seventh PMOS transistor MP7 and the input terminal of the fifth inverter N5.

[0084] The output end of the fifth inverter N5 is connected to the input end of the sixth inverter N6 , and the output end of the sixth inverter N6 is connected to the first input end of the first NAND gate NAND1 .

[0085] The disclosed embodiment simplifies circuit design, saves costs, generates a square wave with a duty cycle of about 50%, and improves circuit operating efficiency by setting the first delay oscillation unit and the second delay oscillation unit to be symmetrical.

[0086] In a possible implementation manner, the width-to-length ratio of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 is the same as the width-to-length ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2.

[0087] The first NMOS transistor MN1 , the third NMOS transistor MN3 , and the fifth NMOS transistor MN5 have the same width-to-length ratio.

[0088] In the embodiment of the present disclosure, by setting the width-to-length ratio of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 to be the same as the width-to-length ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the width-to-length ratio of the first NMOS transistor MN1, the third NMOS transistor MN3, and the fifth NMOS transistor MN5 to be the same, the drain current Ir1 of the third PMOS transistor, the drain current Ir2 of the fourth PMOS transistor, the drain current Ir3 of the sixth PMOS transistor, and the drain current Ir4 of the seventh PMOS transistor can be equal and equal to the reference current Ir, so that low-frequency oscillation is achieved using the reference current Ir to generate an oscillation signal (first signal) whose oscillation frequency is independent of the power supply voltage.

[0089] In a possible implementation manner, the first capacitor C1 and the second capacitor C2 have the same capacitance.

[0090] In a possible implementation manner, an oscillation frequency of the first signal OUT is related to the resistor R, the first capacitor C1, and the second capacitor C2.

[0091] The following is an exemplary introduction to the principles implemented by the embodiments of the present disclosure.

[0092] In a possible implementation manner, the second NAND gate NAND2 may also receive an enable signal EN input by an external controller to control the operation of the oscillation circuit.

[0093] In one example, when the input enable signal EN=0, Figure 2 As shown, signal F2=1, signal A1=0, signal B1=1, signal D1=0, signal E1=0, signal F1=1; at the same time, signal A2=1, signal B2=0, signal D2=1, signal E2=1.

[0094] In an example, when the input enable signal EN changes from 0 to 1, since the first delay oscillation unit and the second delay oscillation unit are symmetrical, the second delay oscillation unit is taken as an example to perform logic analysis and formula derivation.

[0095] When the enable signal EN changes from 0 to 1, the second signal A2 changes from 1 to 0. At this time, the level of the signal point B2 starts to charge from 0. When the signal B2 is charged to VDD-VGSP7 (VGSP7 represents the gate-source voltage of the seventh PMOS transistor), the seventh PMOS transistor MP7 is just in the off state. When the voltage at the signal point B2 continues to increase, the seventh PMOS transistor MP7 is turned off. After the seventh PMOS transistor MP7 is turned off, the signal D2 changes from 1 to 0. At this time, the signal E2 also changes from 1 to 0, completing the delay of the second signal A2. Because the delay time of the logic gate can be ignored relative to the charging time of the capacitor, the delay time of the second delay oscillation unit can be deduced as follows.

[0096] In one example, the charging formula for a capacitor may be:

[0097] Q=I r3 *T f =(VDD-V GSP7 )*C 2 Formula 1

[0098] Where Q represents the charge of the capacitor, I r3 represents the drain current Ir3 of the sixth PMOS transistor, VDD represents the power supply voltage, C2 represents the capacitance of the second capacitor, T f Indicates charging time.

[0099] From formula 1, the charging time of the capacitor can be deduced:

[0100] T f =(VDD-V GSP7 )*C 2 / I r3 Formula 2

[0101] As mentioned above, the reference current I r It can be expressed as:

[0102] I r =(V DD -V GSP1 ) / R Formula 3

[0103] Among them, V GSP1 represents the gate-source voltage of the first PMOS transistor, and R represents the resistance of the resistor R.

[0104] Since Ir=Ir3=Ir4, C1=C2,

[0105] According to the current formula in the saturation region:

[0106]

[0107] Among them, at this time, if the current I and the width-to-length ratio W / L are equal, ignoring the offset effect, it can be considered that VGSP7=VGSP1 (K and Vth in the formula are process parameters, and it can be basically considered that all PMOS tubes have these two parameters are equal; all NMOS tubes have these two parameters are equal). Therefore, at this time, VGSP7 is approximately VGSP1, simplifying the charging time (second time):

[0108] T f =(VDD-V GSP7 )*C 2 / I r3 =(VDD-V GSP7 )*C 2 / ((V DD -V GSP1 ) / R)=R*C 2 Formula 5

[0109] Similarly, the charging time (first time) of the upper part (first delay oscillation unit) can be deduced:

[0110] T r =(VDD-V GSP4 )*C 1 / I r1 =(VDD-V GSP4 )*C 1 / ((V DD -V GSP1 ) / R)=R*C 1 Formula 6

[0111] According to Formula 5 and Formula 6, the total charging time can be obtained:

[0112] T t =T r +T f =R*C 1 +R*C 2 =2*R*C 1 Formula 7

[0113] See also Figure 3 , Figure 3 FIG. 4 is a schematic diagram showing an oscillation time according to an embodiment of the present disclosure.

[0114] In one example, if Figure 3 As shown, a clock cycle Tt = Tr + Tf, Tr / Tf is the delay generated by the upper and lower symmetrical circuits. By controlling different charging times, different Tr and Tf are generated, resulting in different delay times Tt. The relationship between frequency and delay time is F = 1 / T t .

[0115] It can be seen that the total time Tt It has nothing to do with the power supply voltage VDD, that is, the oscillation frequency has nothing to do with the power supply voltage VDD.

[0116] In the low-frequency oscillation circuit proposed in the embodiment of the present disclosure, both the first delay oscillation unit and the second delay oscillation unit use the reference current delay signal generated by the reference current generating module, so that the oscillation frequency of the first signal output by the oscillation circuit is related to the first time and the second time, and is independent of the power supply voltage, thereby eliminating the influence of the power supply voltage on the oscillation frequency and improving the stability of the oscillation frequency.

[0117] The frequency of the above oscillation circuit is less affected by the power supply, the frequency is stable under a wide power supply voltage, and the cost is low and the occupied area is small.

[0118] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A low frequency oscillation circuit, characterized in that: The circuit comprises: A reference current generating module, used for generating a reference current; The loop oscillation module is connected to the reference current generating module, and includes a second delay oscillation unit, a first delay oscillation unit, a first inverter, a second inverter, a second NAND gate, and a first NAND gate, wherein: The first input end of the second delay oscillation unit is connected to the output end of the first inverter for receiving a second signal, the output end of the second delay oscillation unit is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the first NAND gate, the output end of the second NAND gate is connected to the second input end of the first NAND gate and the input end of the second inverter, the first input end of the first NAND gate is connected to the output end of the first delay oscillation unit, the input end of the first inverter and the first input end of the first delay oscillation unit are connected to the output end of the second inverter for receiving the first signal, The second input end of the second delay oscillation unit and the second input end of the first delay oscillation unit are connected to the reference current generating module, the second delay oscillation unit is used to delay the second signal for a second time according to the reference current, and the first delay oscillation unit is used to delay the first signal for a first time according to the reference current. The oscillation frequency of the first signal is the inverse of the sum of the first time and the second time, and the second NAND gate is used to receive an enable signal input by an external controller to control the operation of the low-frequency oscillation circuit. The reference current generating module includes a first PMOS transistor, a second PMOS transistor, a resistor, and a first NMOS transistor, wherein: The source of the first PMOS transistor is connected to the source of the second PMOS transistor for receiving a power supply voltage, and the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor, and the first end of the resistor. The second end of the resistor is connected to the source of the first NMOS transistor and the ground. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor, The first PMOS transistor and the second PMOS transistor have the same width-to-length ratio. Wherein, the current flowing through the resistor is the reference current, The first delay oscillation unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a first capacitor, a third inverter, and a fourth inverter, wherein: The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor for receiving the power supply voltage, and the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the gate of the second NMOS transistor, and is used to receive the first signal. The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor, the first end of the first capacitor, and the gate of the fourth PMOS transistor. The source of the second NMOS transistor is connected to the second end of the first capacitor, the source of the third NMOS transistor and ground, The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, The drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor and the input end of the third inverter. The output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the first input end of the first NAND gate. The second delay oscillation unit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, a fifth inverter, and a sixth inverter, wherein: The gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor, the source of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor for receiving the power supply voltage, and the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the gate of the fourth NMOS transistor, and is used to receive the second signal. The drain of the eighth PMOS transistor is connected to the drain of the fourth NMOS transistor, the first end of the second capacitor, and the gate of the seventh PMOS transistor. The source of the fourth NMOS transistor is connected to the second end of the second capacitor, the source of the fifth NMOS transistor and ground, The gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, The drain of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor and the input terminal of the fifth inverter. The output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the first input end of the first NAND gate.

2. The circuit according to claim 1, characterized in that The width-to-length ratios of the third PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are the same as the width-to-length ratios of the first PMOS transistor and the second PMOS transistor, The first NMOS transistor, the third NMOS transistor, and the fifth NMOS transistor have the same width-to-length ratio.

3. The circuit according to claim 1, characterized in that The first capacitor has the same capacitance as the second capacitor.

4. The circuit according to claim 2 or 3, characterized in that The oscillation frequency of the first signal is related to the resistor, the first capacitor, and the second capacitor.

5. An oscillator, characterized in that: The oscillator comprises the low-frequency oscillation circuit according to any one of claims 1 to 4.

6. A power supply, characterized in that: The power supply comprises the oscillator of claim 5.

7. An electronic device, characterized in that: The electronic device comprises the power supply according to claim 6.

Images