Dem structure for improving dynamic performance of dac at extremely low temperature

Abstract

The present disclosure provides a DEM structure for improving dynamic performance of a DAC at an extremely low temperature, comprising: a signal input end configured to receive a three-bit binary input signal; a random control signal module connected to the signal input end and configured to generate a random control signal according to the three-bit binary input signal; and a random shift circuit comprising a first input end and a second input end, wherein the first input end is connected to the signal input end, the second input end is connected to the random control signal module, and the random shift circuit is configured to decode the three-bit binary input signal into a seven-bit thermometer code according to the random control signal. The DEM structure can alleviate the technical problems such as dynamic performance deterioration caused by transistor mismatch aggravation when a digital-to-analog converter works at an extremely low temperature.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and particularly relates to a spur-weakening DEM (Dynamic Element Matching) structure for improving the dynamic performance of a digital-to-analog converter under extremely low temperature conditions (269 DEG C and below). BACKGROUND

[0002] A DAC (Digital to analog converter) can convert a discrete digital signal into a continuous analog signal. With the continuous development of deep space exploration, quantum computing and other technologies, high-speed and high-precision DACs are required to work normally under extremely low temperature. The current steering DAC can meet the demand of high speed and high precision due to its structural characteristics. However, the mismatch caused by the process under extremely low temperature will greatly affect the performance of the DAC. Because the threshold voltage of the MOS tube becomes higher under extremely low temperature, the carriers are frozen, and the mismatch of the tube is larger under the same area. These problems make it very difficult for the low-temperature DAC to achieve the same performance as the normal-temperature DAC. Therefore, a new structure must be proposed to solve the mismatch problem of the MOS tube under low temperature.

[0003] DEM technology can be used to improve the dynamic performance of the DAC under high mismatch conditions. However, the traditional DEM has problems such as complex structure, weak randomness, high switching frequency, high power consumption, etc. Therefore, there is an urgent need for a DEM structure that can effectively improve the dynamic performance of the DAC under extremely low temperature and weaken the spur caused by the switching of the switch. SUMMARY

[0004] (I) Technical problems to be solved

[0005] Based on the above problems, the present disclosure provides a DEM structure for improving the dynamic performance of a DAC under extremely low temperature, so as to alleviate the technical problems such as dynamic performance deterioration caused by transistor mismatch under extremely low temperature in the prior art.

[0006] (II) Technical solutions

[0007] The present disclosure provides a DEM structure for improving the dynamic performance of a DAC under extremely low temperature, comprising: a signal input end, a random control signal module, and a random shift circuit.

[0008] The signal input end is used for receiving a three-bit binary input signal; the random control signal module is connected to the signal input end and is used for generating a random control signal according to the three-bit binary input signal;

[0009] The random shift circuit comprises a first input end and a second input end, the first input end is connected with a signal input end, the second input end is connected with the random control signal module, and the random shift circuit is used for decoding the three-bit binary input signal into a seven-bit thermometer code according to the random control signal.

[0010] According to the embodiment of the present disclosure, the random control signal module comprises a pseudo-random number generator circuit, a logic shift circuit, a three-bit adder, a multiplexer and a four-bit subtractor.

[0011] The pseudo-random number generator circuit is used for generating a pseudo-random code; the logic shift circuit is connected with a signal input end and is used for shifting a three-bit binary input signal; the three-bit adder is connected with the pseudo-random number generator circuit and the logic shift circuit simultaneously and is used for adding the pseudo-random code and the shifted three-bit binary input signal to generate an adder output signal; the multiplexer is used for outputting a three-bit output signal of all zeros or all ones according to the carry output of the three-bit adder; and the four-bit subtractor is connected with the multiplexer and the three-bit adder simultaneously and is used for subtracting the adder output signal and the three-bit output signal bit by bit to generate a random control signal.

[0012] According to the embodiment of the present disclosure, the logic shift circuit comprises three input signals and four output signals; and one SEL output signal provides a clock for the pseudo-random number generator circuit.

[0013] According to the embodiment of the present disclosure, the logic shift circuit is configured to change the SEL output signal and the pseudo-random number generator generates a new random code only when the three-bit binary input signal is all zeros or all ones.

[0014] According to the embodiment of the present disclosure, the pseudo-random number generator circuit comprises a plurality of D flip-flops, or gates, not gates and XOR gates.

[0015] The 15 D flip-flops are shifted constantly under the control of the clock, the multiple-input not gate ensures that the pseudo-random number generator circuit can work normally and avoids the all-zero situation, and the XOR gate is configured to enable the output of the D flip-flop to change after shifting in each clock cycle.

[0016] According to the embodiment of the present disclosure, the pseudo-random number circuit can output non-repeated codes in (2 15 -1) clock cycles.

[0017] According to the embodiment of the present disclosure, the three-bit adder circuit adopts a serial carry adder structure and comprises three one-bit full adders, and the three-bit addition operation is completed by using a plurality of clock cycles.

[0018] According to the embodiment of the present disclosure, the four-bit subtracter adopts a bit-by-bit subtraction structure, including four one-bit subtracters, and the random control signal output by the four-bit subtracter is connected to the shift control signal end of the random shift circuit through a NOT gate, so that when the three-bit binary input signal is all zero or all one, the output seven-bit thermometer code generates a shift.

[0019] According to the embodiment of the present disclosure, the multiplexer includes three one-bit multiplexers, and the three-bit output signal is determined according to the carry signal of the three-bit adder. If the three-bit adder generates a carry signal, the multiplexer outputs three high-level signals, otherwise, the multiplexer outputs three low-level signals.

[0020] According to the embodiment of the present disclosure, the random shift circuit includes three rows of seven-column multiplexer units, the output control signal of each row of multiplexer units is controlled by the random control signal output by the four-bit subtracter, and the three-bit binary input signal is connected to the seven-column multiplexer units in accordance with the binary weight ratio.

[0021] (Three) beneficial effects

[0022] From the above technical solutions, the DEM structure for improving the dynamic performance of the DAC at extremely low temperature according to the present disclosure has at least one or part of the following beneficial effects:

[0023] (1) In view of the poor dynamic performance of the conventional digital-to-analog converter in the extremely low temperature environment, the DEM decoding structure can randomly decode the input binary code, randomly disrupt the decoding order to compensate for the random mismatch of the MOS tube, and improve the dynamic performance of the digital-to-analog converter in the case of poor process or environment;

[0024] (2) The structure is simple, the area and power consumption are lower than those of the conventional DEM decoder, and no extra switching times are generated in the decoding process, which reduces the glitch phenomenon caused by high-speed switching of switches in the working process. In addition, the output result is the same as that of the thermometer decoder, and no extra low-level signal link is generated, which facilitates the design of the differential output digital-to-analog converter;

[0025] (3) The number of switches is the same as that of the conventional thermometer decoder and lower than that of the conventional DEM decoder, which maximally weakens the glitch problem caused by a large number of switching times. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 The figure is a schematic diagram of the DEM structure for improving the dynamic performance of the DAC at extremely low temperature according to the embodiment of the present disclosure.

[0027] Figure 2 The figure is a schematic diagram of the logic shift circuit structure in the embodiment of the present disclosure.

[0028] Figure 3 A schematic diagram of a pseudo-random number generator circuit structure in an embodiment of the present disclosure.

[0029] Figure 4 A schematic diagram of a random shift circuit structure in an embodiment of the present disclosure.

[0030] Figure 5 A schematic diagram of a DEM structure decoding result for improving the dynamic performance of a DAC at an extremely low temperature in an embodiment of the present disclosure.

[0031] Figure 6 A schematic diagram of SFDR distribution based on traditional thermometer decoding.

[0032] Figure 7 A schematic diagram of SFDR distribution based on DEM structure decoding in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The present disclosure provides a DEM structure for improving the dynamic performance of a DAC at an extremely low temperature, which can maintain the minimum switching times while completing random decoding, and can improve the dynamic performance of a DAC at an extremely low temperature.

[0034] To make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below with reference to the embodiments and the accompanying drawings.

[0035] In an embodiment of the present disclosure, a DEM structure for improving the dynamic performance of a DAC at an extremely low temperature is provided, as shown in the following figure. Figure 1 The DEM structure includes:

[0036] a signal input end for receiving a three-bit binary input signal;

[0037] a random control signal module connected to the signal input end, configured to generate a random control signal according to the three-bit binary input signal; and

[0038] a random shift circuit including a first input end and a second input end, the first input end being connected to the signal input end, and the second input end being connected to the random control signal module, the random shift circuit being configured to decode the three-bit binary input signal into a seven-bit thermometer code according to the random control signal.

[0039] Further, the random control signal module includes:

[0040] a pseudo-random number generator circuit (PRNG) configured to generate a pseudo-random code;

[0041] a logic shift circuit (LOGIC) connected to the signal input end, configured to shift the three-bit binary input signal;

[0042] a three-bit adder, connected to the pseudo-random number generator circuit and the logic shift circuit, for adding the pseudo-random code to the shifted three-bit binary input signal to generate an adder output signal;

[0043] a multiplexer (MUX) for outputting a three-bit output signal of all zeros or all ones according to the carry output of the three-bit adder; and

[0044] a four-bit subtracter, connected to the multiplexer and the three-bit adder, for subtracting the three-bit output signal from the adder output signal bit by bit to generate a random control signal.

[0045] In the embodiments of the present disclosure, as shown in Figure 2 The logic shift circuit includes a plurality of NOT gates, OR gates, and AND gates (specifically, three NOT gates, two three-input AND gates, and two two-input AND gates, and three two-input OR gates), receives three input signals (three-bit binary input signals B0, B1, and B2), and generates four output signals (A0, A1, A2, and SEL). The SEL output signal is used as a clock for the pseudo-random number generator circuit. When the three-bit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo-random number generator generates a new random code.

[0046] In the embodiments of the present disclosure, as shown in Figure 3 The pseudo-random number generator circuit includes a plurality of D flip-flops, OR gates, NOR gates, and XOR gates, specifically, 15 D flip-flops (Q0-Q 14 ), one two-input OR gate, one two-input XOR gate, and one fifteen-input NOR gate. The 15 D flip-flops are shifted under the control of the clock, the multi-input NOR gate ensures that the circuit can work normally and avoid the all-zero situation, and the XOR gate can make the output of the D flip-flop change after shifting in each clock cycle. The pseudo-random number circuit can output non-repeated numbers in (2 15 -1) periods, and thus can generate approximate random numbers.

[0047] In the embodiments of the present disclosure, the three-bit adder circuit adopts a serial carry adder structure, which is simpler than a look-ahead carry adder structure. The three-bit adder circuit is mainly composed of NOT gates, multi-input AND gates, and multi-input OR gates, and internally includes three one-bit full adders. The three-bit addition operation is completed by using multiple clock cycles. Although the serial carry adder has a lower running speed than the look-ahead carry adder, it occupies fewer resources and can achieve basic addition operations.

[0048] In the embodiment of the present disclosure, the multiplexer can output a three-bit output signal of all zeros or all ones according to the carry output of the three-bit adder, and further subtract the output of the three-bit adder to obtain a random control signal for controlling the random shift circuit. The three-bit multiplexer specifically includes three one-bit multiplexers, which are composed of AND gates, NOT gates, OR gates and the like. The three-bit output signal is determined according to the carry signal of the three-bit adder. If the three-bit adder generates a carry signal, the three-bit multiplexer outputs three high-level signals (all-one signals), otherwise, it outputs three low-level signals (all-zero signals).

[0049] In the embodiment of the present disclosure, the four-bit subtracter is used to implement the operation of subtracting the output signal of the three-bit adder from the three-bit output signal of the three-bit multiplexer. Similar to the three-bit adder, the subtracter adopts a bit-by-bit subtraction structure and is internally composed of four one-bit subtracters. A single one-bit subtracter includes an AND gate, an OR gate and an XOR gate. The output of the four-bit subtracter is connected to the shift control signal end of the random shift circuit through a NOT gate, so that when the input three-bit binary code is all zero or all one, the output seven-bit thermometer code generates a shift, which can make the switch that was opened / closed last time still preferentially open / close when the next clock arrives, and can minimize the glitch phenomenon caused by a large number of switch switching times.

[0050] In the embodiment of the present disclosure, as shown in Figure 4 The random shift circuit includes a plurality of multiplexers (MUXs) and has three-bit binary code (B0, B1, B2) as input and seven-bit thermometer code (W1-W7) as output. The function of the random shift circuit is to realize the decoding of binary code to thermometer code. Different from the conventional decoding circuit of binary code to thermometer code, the random control signals (PRBS0, PRBS1, PRBS2) in the random shift circuit are determined by the three-bit binary input signal. The overall layout of the random shift circuit is divided into three rows and seven columns, including three rows and seven columns of multiplexer units. Each row of multiplexer units includes 7 multiplexers, and each column of multiplexer units includes 3 multiplexers, totaling 21 multiplexers. The output control signal of each row of multiplexer units is controlled by the output of the subtracter (i.e., controlled by the random control signals PRBS0, PRBS1, PRBS2 output by the four-bit subtracter). Figure 4 As shown in Figure 4As shown, B0 connects two lines to the 4th and 7th multiplexers in the first row of multiplexer units respectively, B1 connects four lines to the 2nd, 3rd, 5th and 6th multiplexers in the first row of multiplexer units respectively, and B2 connects eight lines to the 1st-7th multiplexers in the first row of multiplexer units respectively.

[0051] In the embodiments of the present disclosure, as shown in Figure 5 As shown in the decoding result of the DEM decoder under the condition of -269℃, the leftmost column latch: 5, latch: 6, latch: 7 are the input three-bit binary code, 5, 7, 4, 6, 1, 3, 2 are the output seven-bit thermometer code, and the right side is the decoding result corresponding to the continuously changing binary input code, it can be seen that with the continuous change of the latch, the seven-bit output thermometer code always keeps the channel opened / closed in the previous clock period to be opened / closed preferentially, and it can be seen that in the adjacent clock period, the input three-bit binary code is switched constantly, and the output can still keep the number of switching times in the adjacent period to be the minimum, which can minimize the interference of frequent switching under high frequency on the dynamic performance of the DAC.

[0052] In the embodiments of the present disclosure, in combination with Figure 6 and Figure 7 As shown, it can be seen that in the case of 10% current source mismatch, the worst SFDR distribution of the traditional thermometer decoding is about 44.15dB, and after the DEM structure decoder of the present disclosure is applied, the SFDR distribution is more concentrated under the condition of large current source mismatch, and the worst case is about 53.65dB, compared with the results of the two decoders, the DAC using the new DEM decoder has a great improvement in the SFDR index relative to the DAC using the traditional thermometer decoding under extreme conditions.

[0053] Thus far, the embodiments of the present disclosure have been described in detail in combination with the drawings. It should be noted that the implementation manners not shown or described in the drawings or the text of the specification are all forms known by those skilled in the art, and are not described in detail. In addition, the definitions of the elements and methods described above are not limited to the various specific structures, shapes or manners mentioned in the embodiments, and those skilled in the art can make simple changes or replacements.

[0054] According to the above description, those skilled in the art should have a clear understanding of the DEM structure of the present disclosure for improving the dynamic performance of the DAC under extremely low temperature.

[0055] In summary, the present disclosure provides a DEM structure for improving the dynamic performance of a DAC at an extremely low temperature. In view of the poor dynamic performance of a conventional digital-to-analog converter in an extremely low temperature environment, the DEM decoding technology can randomly decode the input binary code, randomly disrupt the decoding order to ensure correct output, and compensate for the random mismatch of MOS transistors, thereby improving the dynamic performance of the digital-to-analog converter in a harsh process or environment. Compared with the conventional DEM decoder, the DEM decoder has a very simple structure, occupies less area and consumes less power than the conventional DEM decoder, and does not generate an excessive number of switch switching times during the decoding process, thereby reducing the glitch phenomenon caused by high-speed switching of switches during operation. In addition, the output result is the same as that of the thermometer decoder, and no additional low-level signal link is generated, which facilitates the design of a differential output digital-to-analog converter.

[0056] It should be noted that, in this document, unless specifically indicated otherwise, having "one" element does not necessarily mean having only one element, but can mean having one or more elements.

[0057] In addition, in this document, unless specifically indicated otherwise, the ordinal numbers "first", "second", etc. are only used to distinguish multiple elements with the same name, and do not indicate a hierarchy, a level, an execution order, or a process order between them. A "first" element and a "second" element can appear together in the same component, or separately in different components. The presence of an element with a larger ordinal number does not necessarily mean the presence of another element with a smaller ordinal number.

[0058] In this document, unless specifically indicated otherwise, the so-called feature A "or" (or) o r) or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist simultaneously; the so-called feature A "and" (and) or "with" (and) or "and" (and) feature B means that A and B exist simultaneously; the so-called "includes", "contains", "has", "contains" means including but not limited to.

[0059] In addition, in this document, the so-called "up", "down", "left", "right", "front", "back", or "between" and other terms are only used to describe the relative position between multiple elements, and in interpretation can be extended to include translation, rotation, or mirror cases. In addition, in this document, unless specifically indicated otherwise, "one element on another element" or similar statements do not necessarily mean that the element contacts the other element.

[0060] Moreover, the order of execution or performance of the above-described operations is not limited to the above-described order unless otherwise specified and can be changed or re-arranged according to the desired design or implementation. Also, the above-described embodiments can be used in combination with each other or in combination with other embodiments, based on design and reliability considerations, i.e., technical features in different embodiments can be freely combined to form further embodiments.

[0061] The above-described embodiments are further detailed to explain the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above-described embodiments are merely specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A DEM decoder for improving dynamic performance of a DAC at ultra-low temperature, comprising: a signal input terminal for receiving a three-bit binary input signal; a random control signal module connected to the signal input terminal for generating a random control signal according to the three-bit binary input signal; and a random shift circuit comprising a first input terminal and a second input terminal, the first input terminal being connected to the signal input terminal, and the second input terminal being connected to the random control signal module, the random shift circuit being configured to decode the three-bit binary input signal into a seven-bit thermometer code according to the random control signal. The random control signal module comprises: a pseudo-random number generator circuit for generating a pseudo-random code; a logic shift circuit connected to the signal input terminal for shifting the three-bit binary input signal, the logic shift circuit receiving the three-bit binary input signal to obtain four output signals, one of which is a SEL output signal for providing a clock for the pseudo-random number generator circuit, the SEL output signal changing only when the three-bit binary input signal is all zeros or all ones, and the pseudo-random number generator generating a new random code; a three-bit adder connected to the pseudo-random number generator circuit and the logic shift circuit for adding the pseudo-random code and the shifted three-bit binary input signal to generate an adder output signal; a multiplexer for outputting a three-bit output signal of all zeros or all ones according to a carry output of the three-bit adder; and a four-bit subtractor connected to the multiplexer and the three-bit adder for subtracting the adder output signal and the three-bit output signal bit by bit to generate the random control signal, the random control signal being connected to the random shift circuit so that the output seven-bit thermometer code is shifted only when the three-bit binary input signal is all zeros or all ones. The pseudo-random number generator circuit comprises 15 D flip-flops, one two-input OR gate, one fifteen-input NOR gate, and one two-input XOR gate, the output of a first D flip-flop being connected to the input of a next D flip-flop, all the flip-flops being connected to a clock, the fifteen-input NOR gate being connected to the outputs of all the D flip-flops, the two inputs of the XOR gate being from the outputs of two D flip-flops, the output of the XOR gate being fed back to the input of the OR gate connected to the input of the first D flip-flop, and the other input of the OR gate being from the output of the NOR gate; the 15 D flip-flops are shifted under the control of the clock, the fifteen-input NOR gate ensures that the pseudo-random number generator circuit can work normally and avoids all-zero situation, and the XOR gate is configured to make the output of the D flip-flop change after shifting in each clock cycle. 3.The DEM decoder of claim 1, wherein the three-bit adder circuit adopts a serial carry-adder structure comprising three one-bit full adders, and the three-bit addition is completed by using multiple clock cycles.

2. The DEM decoder of claim 1, the pseudo-random number circuit is capable of outputting without repetition in (2 15 -1) periods. ​ 4. The DEM decoder of claim 1, wherein the four-bit subtracter is a bit-by-bit subtracter including four one-bit subtracters, and the random control signal outputted by the four-bit subtracter is connected to a shift control signal terminal of the random shift circuit through a NOT gate, so that when the three-bit binary input signal is all zero or all one, the seven-bit thermometer code outputted by the four-bit subtracter generates a shift.

5. The DEM decoder of claim 1, wherein the multiplexer includes three one-bit multiplexers, and the three-bit output signal is determined according to a carry signal outputted by the three-bit adder, if the three-bit adder generates the carry signal, the multiplexer outputs three high-level signals, otherwise, the multiplexer outputs three low-level signals.

6. The DEM decoder of claim 1, wherein the random shift circuit includes three rows of seven-column multiplexer units, and the output control signal of each row of multiplexer units is controlled by the random control signal outputted by the four-bit subtracter, and the three-bit binary input signal is connected to the seven-column multiplexer units according to the binary weight proportion.

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