Flux bias wire local heating device

Abstract

Apparatus, systems, and / or methods are provided to facilitate localized heating of a superconducting flux bias loop. According to an embodiment, an apparatus (100) may include a substrate (102) having a superconducting flux bias circuit including a bias loop (104) coupled to a flux-controlled qubit device. The apparatus may further include heating means (106, 108) coupled to the bias loop.

Description

Background Technology

[0001] This invention relates to a superconducting flux bias circuit, and more specifically, to a local heating device for the flux bias line and a method for forming the same. Summary of the Invention

[0002] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, apparatus, systems, methods, computer-implemented methods, apparatuses, and / or computer program products for facilitating localized heating of a superconducting flux bias loop are described.

[0003] According to an embodiment, a device may include a substrate having a superconducting flux bias circuit, the superconducting flux bias circuit including a bias loop coupled to a flux-controlled qubit device. The device may further include a heating device coupled to the bias loop. An advantage of such a device is that it can facilitate localized heating of the bias loop (e.g., in contrast to regulating the temperature of a cryostat including the qubit device).

[0004] In some embodiments, the heating device is thermally coupled to the bias loop to control the superconductivity of the bias loop and the magnetic field of the bias loop. An advantage of such a device is that it can assist in at least one of the following: improved fidelity of flux-controlled qubit devices, improved fidelity of quantum devices including flux-controlled qubit devices, or improved performance of quantum devices including flux-controlled qubit devices.

[0005] According to an embodiment, a device may include a superconducting flux bias circuit comprising a flux-controlled qubit device coupled to a bias loop comprising a first critical temperature material and a second critical temperature material. The device may further include a heating device coupled to the bias loop. An advantage of such a device is that it can facilitate localized heating of the bias loop (e.g., in contrast to regulating the temperature of a cryostat including the qubit device).

[0006] In some embodiments, the heating device is thermally coupled to the bias loop to heat the second critical temperature material to a temperature above the critical temperature of the second critical temperature material. An advantage of such a device is that it can facilitate localized heating of the bias loop (e.g., in contrast to regulating the temperature of a cryostat including the quantum device).

[0007] According to an embodiment, a device may include a substrate having a plurality of superconducting flux bias circuits, the superconducting flux bias circuits including a plurality of bias loops coupled to a flux-controlled qubit device. The device may further include one or more heating devices coupled to one or more bias loops and one or more control circuit lines formed on the substrate. An advantage of such a device is that it can assist in the localized, individual, and / or simultaneous heating of one or more of these bias loops (e.g., in contrast to regulating the temperature of a cryostat including the quantum device).

[0008] In some embodiments, at least one of the one or more heating devices is thermally coupled to at least one of the bias loops to control the superconductivity and magnetic field of the at least one bias loop. An advantage of such a device is that it can contribute to at least one of the following: improved fidelity of at least one flux-controlled qubit device, improved fidelity of a quantum device including the at least one flux-controlled qubit device, or improved performance of the quantum device including the at least one flux-controlled qubit device. Attached Figure Description

[0009] Figure 1 and Figure 2 An orthogonal view of an example, non-limiting device that can facilitate local heating of a superconducting flux bias loop according to one or more embodiments described herein is shown.

[0010] Figure 3 A top view of an exemplary, non-limiting device that can facilitate local heating of a superconducting flux bias loop according to one or more embodiments described herein is shown.

[0011] Figure 4 and 5 A top view of an example, non-limiting system, according to one or more embodiments described herein, is shown that can facilitate local heating of a superconducting flux bias loop.

[0012] Figure 6A and 6B Top and cross-sectional views of exemplary, non-limiting devices including substrates according to one or more embodiments described herein are shown, respectively.

[0013] Figure 7A and 7B The following are illustrations, respectively, of the formation of a resist layer on a substrate according to one or more embodiments described herein. Figure 6A and 6B Example top view and cross-sectional view of a non-restrictive device.

[0014] Figure 8A and 8BThe following are shown, respectively, after a portion of the resist layer has been removed, according to one or more embodiments described herein. Figure 7A and 7B Example top view and cross-sectional view of a non-restrictive device.

[0015] Figure 9A and Figure 9B The following are shown, respectively, after the deposition of the first superconducting layer, according to one or more embodiments described herein. Figure 8A and Figure 8B Top view and cross-sectional view of an exemplary non-limiting device.

[0016] Figure 10A and 10B The following figures, respectively, illustrate the process of removing a portion of the resist layer and the first superconducting layer to form a bias loop on the substrate, according to one or more embodiments described herein. Figure 9A and 9B Top view and cross-sectional view of the exemplary, non-restrictive device.

[0017] Figure 11A and 11B The figures respectively illustrate the process after the deposition of the insulating layer according to one or more embodiments described herein. Figure 10A and 10B Example top view and cross-sectional view of a non-restrictive device.

[0018] Figure 12A and Figure 12B The following are shown, respectively, after forming a resist layer on an insulating layer according to one or more embodiments described herein. Figure 11A and Figure 11B The example non-restrictive device is shown in the top view and cross-sectional view.

[0019] Figure 13A and Figure 13B The following are illustrations, respectively, of one or more embodiments described herein, after a portion of the resist layer has been removed. Figure 12A and Figure 12B Top view and cross-sectional view of an exemplary non-limiting device.

[0020] Figure 14A and Figure 14B The following are shown, respectively, the deposition of the resistive layer according to one or more embodiments described herein. Figure 13A and Figure 13B Example top view and cross-sectional view of a non-restrictive device.

[0021] Figure 15A and Figure 15B The following are shown, respectively, of one or more embodiments described herein, after the removal of the resist layer and the resistive layer to form a resistive component. Figure 14A and Figure 14B Example top view and cross-sectional view of a non-restrictive device.

[0022] Figure 16A and 16B The following diagrams illustrate the formation of resist layers on insulating and resistive materials according to one or more embodiments described herein. Figure 15A and 15B Example top view and cross-sectional view of a non-restrictive device.

[0023] Figure 17A and 17B The following figures, after the removal of the resist layer, are shown respectively according to one or more embodiments described herein. Figure 16A and 16B The example non-restrictive device is shown in the top view and cross-sectional view.

[0024] Figure 18A and 18B The following are shown, respectively, after the deposition of the second superconducting layer, according to one or more embodiments described herein. Figure 17A and 17B Top view and cross-sectional view of an exemplary, non-limiting device.

[0025] Figure 19A and Figure 19B Correspondingly, this illustrates, according to one or more embodiments described herein, after removing multiple portions of the resist layer and the second superconducting layer to form the superconducting heater bias wire. Figure 18A and 18B Top and cross-sectional views of an exemplary, non-restrictive apparatus.

[0026] Figure 20A and 20B The following are shown, respectively, after a portion of the resist layer has been removed, according to one or more embodiments described herein. Figure 7A and 7B The example non-restrictive device is shown in the top view and cross-sectional view.

[0027] Figure 21A and 21B The following are shown, respectively, after the deposition of the first superconducting layer, according to one or more embodiments described herein. Figure 20A and 20B The example is a top view and cross-sectional view of a non-restrictive device.

[0028] Figure 22A and 22B The images show, respectively, one or more embodiments described herein, after the removal of a portion of the resist layer and the first superconducting layer to form a bias loop on the substrate using the first superconducting material. Figure 21A and 21BTop view and cross-sectional view of the exemplary, non-restrictive device.

[0029] Figure 23A and 23B Correspondingly, this illustrates the process after a resist layer is formed on the first superconducting material and the substrate, according to one or more embodiments described herein. Figure 22A and 22B Top view and cross-sectional view of an exemplary, non-restrictive device.

[0030] Figure 24A and 24B The following are shown, respectively, after a portion of the resist layer has been removed, according to one or more embodiments described herein. Figure 23A and 23B Example top view and cross-sectional view of a non-restrictive device.

[0031] Figure 25A and 25B The following are shown, respectively, after the deposition of the second superconducting layer, according to one or more embodiments described herein. Figure 24A and 24B Top view and cross-sectional view of an exemplary, non-restrictive device.

[0032] Figure 26A and Figure 26B The images show, respectively, the second superconducting material after the removal of portions of the resist layer and the second superconducting layer to form a bias loop, according to one or more embodiments described herein. Figure 25A and Figure 25B The following are top and cross-sectional views of an example non-limiting device, wherein the bias loop is formed on a substrate.

[0033] Figure 27 A block diagram is shown illustrating an example non-limiting operating environment in which one or more embodiments described herein may be facilitated. Detailed Implementation

[0034] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any express or implied information presented in the preceding background or overview or detailed description sections.

[0035] Some existing techniques for achieving locked bias (e.g., locked magnetic field) in a superconducting bias loop for adjusting superconducting flux bias circuitry in a quantum device utilize the following methods: a) raising the temperature of a cryostat comprising the quantum device above a critical temperature (e.g., the temperature of the material of the bias loop, below which a material is a superconductor); b) temporarily normalizing the bias loop (e.g., making it non-superconducting); c) changing the magnetic field applied to the bias loop and adjusting the flux bias of a target superconducting quantum interference device loop (SQUID loop) connected to the bias loop, wherein the SQUID loop has a critical temperature above the critical temperature of the bias loop and is therefore still superconducting; d) lowering the cryostat temperature and removing the applied magnetic field and thus locking the new flux in the SQUID loop.

[0036] The problem with the aforementioned prior art and / or methods is that the temperature of the entire cryostat is regulated, so if multiple bias loops or other circuits exist, they will all have to be moved to higher temperatures, which limits local control in quantum systems with many qubits (e.g., limiting individual and / or simultaneous control of multiple qubits in a quantum device, such as a quantum processor). Another problem with the aforementioned prior art and / or methods is that they do not provide local heating of one or more of the aforementioned bias loops to enable individual and / or simultaneous control of one or more SQUID loops, qubits, and / or another type of flux-controlled qubit device coupled to this(these) bias loops. Yet another problem with the aforementioned prior art and / or methods is that when regulating the temperature of the entire cryostat, temperature changes also consume time and / or energy to stabilize the temperature between high and low values.

[0037] In view of the problems of the prior art described above, this disclosure can be implemented as a solution to these problems in the form of devices, systems, and / or methods (e.g., computer-implemented methods, manufacturing methods, etc.) that can assist in heating a superconducting flux bias loop coupled to a flux-controlled qubit device (e.g., qubit, SQUID loop, etc.) in a quantum device (e.g., a quantum processor). An advantage of such devices, systems, and / or methods is that they can assist in the localized heating of the superconducting flux bias loop (e.g., in contrast to regulating the temperature of a cryostat including the quantum device).

[0038] In some embodiments, this disclosure can be implemented as a solution to the problems described above in the form of an apparatus, system, and / or method (e.g., a computer-implemented method, manufacturing method, etc.) that can assist in the localized, individual, and / or simultaneous heating of one or more superconducting flux bias loops on one or more flux-controlled qubit devices (e.g., a qubit, a SQUID loop, etc.) coupled to a quantum device (e.g., a quantum processor) to control the one or more flux-controlled qubit devices. The advantage of such apparatus, systems, and / or methods is that they can assist in at least one of the following: improved fidelity of the one or more flux-controlled qubit devices, improved fidelity of the quantum device including the one or more flux-controlled qubit devices, or improved performance of the quantum device including the one or more flux-controlled qubit devices.

[0039] One or more embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent, in various circumstances, that one or more embodiments may be practiced without these specific details. It should be noted that the accompanying drawings provided with this application are for illustrative purposes only, and therefore, the drawings are not drawn to scale.

[0040] It will be understood that when an element referred to as a layer (also known as a film), region, and / or substrate is “on” or “above” another element, it may be directly on the other element, or an intermediate element may be present. Conversely, when an element is referred to as “directly on” or “directly on” another element, no intermediate element is present. It should also be understood that when an element is referred to as “below” or “under” another element, it may be directly below or under the other element, or an intermediate element may be present. Conversely, when an element is referred to as “directly below” or “directly under” another element, no intermediate element is present. It should also be understood that when an element is referred to as “coupled” to another element, it may describe one or more different types of coupling, including but not limited to chemical coupling, communication coupling, electrical coupling, electromagnetic coupling, operational coupling, optical coupling, physical coupling, thermal coupling, and / or another type of coupling.

[0041] Figure 1An orthogonal view of an example, non-limiting device 100, which can facilitate local heating of a superconducting flux bias loop according to one or more embodiments described herein, is shown. Device 100 may include semiconductor and superconducting devices that can be implemented in a quantum device. For example, device 100 may include integrated semiconductor and superconducting circuitry (e.g., quantum circuitry) that can be implemented in a quantum device, such as quantum hardware, a quantum processor, a quantum computer, and / or another quantum device.

[0042] Device 100 may include a substrate 102. Substrate 102 may include any material having semiconductor properties, including but not limited to silicon (Si), sapphire (e.g., aluminum oxide (Al₂O₃)), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), silicon carbide (SiC), germanium (Ge) alloys, III / V compound semiconductors, II / VI compound semiconductors, and / or another material. In some embodiments, substrate 102 may include layered semiconductors, including but not limited to silicon / silicon-germanium (Si / SiGe), silicon / silicon carbide (Si / SiC), silicon-on-insulators (SOIs), silicon-germanium-on-insulators (SGOIs), and / or another layered semiconductor.

[0043] Substrate 102 may have a superconducting flux bias circuit formed thereon and / or therein (e.g., integrated on and / or therein). This superconducting flux bias circuit may include a bias loop 104. Bias loop 104 may include a continuous flux bias loop that may (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operational ground, optical ground, physical ground, thermal ground, etc.) be coupled to a flux-controlled qubit device (in... Figure 1 (Not shown in the image). Flux-controlled qubit devices may include qubits, superconducting quantum interference device circuits (SQUID circuits), and / or other flux-controlled qubit devices. Although in Figure 1 Not shown, flux-controlled qubit devices (e.g., qubits, SQUID loops, etc.) can be positioned in close proximity to bias loop 104. For example, in embodiments where bias loop 104 is formed on the surface of substrate 102 (e.g., as shown in the diagram), Figure 1 As shown, the flux-controlled qubit device can be integrated into the substrate 102. In another embodiment, the flux-controlled qubit device can be formed on a surface of the substrate 102 opposite to the surface on which the bias loop 104 is formed. For example, in one embodiment, the flux-controlled qubit device can be formed on the bottom surface of the substrate 102, wherein the bias loop 104 is formed on the top surface of the substrate 102 (or vice versa in another embodiment).

[0044] Flux-controlled qubit devices (e.g., qubits, SQUID loops, etc.) may include one or more materials with superconducting properties. These flux-controlled qubit devices can be formed using one or more materials with corresponding critical temperatures (e.g., below which the material behaves as a superconductor).

[0045] The bias loop 104 may comprise any material having superconducting properties, including but not limited to aluminum (Al), titanium nitride (TiN), lanthanum (La), molybdenum (Mo), molybdenum nitride (MoN), tantalum (Ta), tantalum nitride (TaN), and / or another material. One or more materials having corresponding critical temperatures may be used to form the bias loop 104. In some embodiments, a single material having a certain critical temperature may be used to form the bias loop 104. In some embodiments, multiple materials having different corresponding critical temperatures may be used to form the bias loop 104. For example, the bias loop 104 may comprise a first critical temperature material and a second critical temperature material, the first critical temperature material comprising a first superconducting material having a first critical temperature, and the second critical temperature material comprising a second superconducting material having a second critical temperature lower than the first critical temperature (e.g., see below). Figure 3 The bias loop 304e of the device 300e shown is described. The bias loop 104 can be formed using at least one material having a critical temperature lower than that of any material used to form the flux-controlled qubit device described above.

[0046] The bias loop 104 may be coupled (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operational ground, optical ground, physical ground, thermal ground, etc.) to a heating device formed on and / or within (e.g., integrated on and / or within) the substrate 102. The heating device may include a resistive material 106 coupled (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operational ground, optical ground, physical ground, thermal ground, etc.) to one or more superconducting heater bias wires 108.

[0047] The resistive material 106 may include any material having resistive properties (e.g., non-superconducting properties), including but not limited to nickel-chromium alloy (NiCr), gold-palladium (AuPd), manganese (Mn), constantan (e.g., copper-nickel alloy) and / or another resistive material (e.g., another common metal).

[0048] The superconducting heater bias wire 108 may comprise any material having superconducting properties, including but not limited to niobium (Nb), niobium nitride (NbN), niobium titanium nitride (NbTiN), niobium titanium (NbTi), niobium germanium (Nb3Ge), and / or another material. The superconducting heater bias wire 108 may comprise a material with a critical temperature higher than the critical temperature of one or more materials used to form the bias loop 104. For example, in an embodiment where the bias loop 104 is formed using a single superconducting material having a certain critical temperature, the superconducting heater bias wire 108 may be formed using a material with a critical temperature higher than the critical temperature of the single superconducting material used to form the bias loop 104. In another example, in an embodiment where the bias loop 104 is formed using a first superconducting material having a first critical temperature and a second superconducting material having a second critical temperature lower than the first critical temperature of the first superconducting material, the superconducting heater bias wire 108 may be formed using a material having a critical temperature higher than the first critical temperature of the first superconducting material and / or higher than the second critical temperature of the second superconducting material. The superconducting heater bias wire 108 may include such a higher critical temperature as described above to minimize heat transfer away from the heating device (e.g., away from the resistive material 106 and / or the superconducting heater bias wire 108).

[0049] The heating device (e.g., including resistive material 106 and superconducting heater bias wire 108) may include and / or be implemented as a resistor that can be thermally coupled to the bias loop 104 to locally heat one or more portions of the bias loop 104 (e.g., one or more materials of the bias loop 104). In some embodiments, the heating device may be physically coupled to the bias loop 104. For example, as... Figure 1 As shown, the resistive material 106 of the heating device can be physically coupled to the bias loop 104. In some embodiments, the heating device is not physically coupled to the bias loop 104, but is positioned in close proximity to the bias loop 104 (e.g., below, above, inside, partially overlapping, completely overlapping, etc.) so that the heating device can be thermally coupled to the bias loop 104. For example, the resistive material 106 of the heating device can be positioned in close proximity to the bias loop 104 so that the resistive material 106 can be thermally coupled to the bias loop 104.

[0050] As described below, the heating device may be thermally coupled to the bias loop 104 to locally heat at least one segment of the bias loop 104 to a temperature above the critical temperature of the bias loop 104 (e.g., above the critical temperature of one or more materials used to form the bias loop 104 as described above). Additionally or alternatively, as described below, the heating device may be thermally coupled to the bias loop 104 to control the superconductivity of the bias loop 104 and / or the magnetic field of the bias loop 104.

[0051] In this example, to locally heat the bias loop 104, the superconducting heater bias wire 108 can be connected (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operative ground, optical ground, physical ground, thermal ground, etc.) to a power source (e.g., a voltage source and / or current source, not shown) that can be external to the device 100. In this example, such a power source can be used to apply current to the superconducting heater bias wire 108, which can pass through the resistive material 106, thereby heating the resistive material 106 and the bias loop 104, which can be physically and / or thermally coupled to the resistive material 106 as described above. In this example, the resistive material 106 and / or one or more materials used to form the bias loop 104 can be heated to a temperature above the critical temperature of such one or more materials used to form the bias loop 104. Based on heating the bias loop 104 to a temperature above the critical temperature of one or more materials used to form the bias loop 104, such materials can become normal (e.g., non-superconducting) over a period of time. By normalizing (e.g., non-superconducting) these materials, the current circulating in the bias loop 104 and / or the magnetic field of the bias loop 104 (e.g., the magnetic field applied to the bias loop 104) can be attenuated due to dissipation in the normal cross-section of the bias loop 104. Based on this attenuation of the circulating current and / or magnetic field of the bias loop 104, a new magnetic field can be applied to the bias loop 104 (e.g., via a flux bias source outside the device 100), and the heating device, including the resistive material 106 and the superconducting heater bias wire 108, can be shut down (e.g., by removing the power source described above). Once the heating device is turned off, the bias loop 104 can cool and return to the superconducting state, which can cause the flux (e.g., a newly applied magnetic field) to be permanently trapped in the bias loop 104, and at this point, the external flux bias that could be used to apply a new magnetic field to the bias loop 104 can be removed. The process described above can be implemented to locally heat the bias loop 104 and / or tune the flux-controlled qubit device (e.g., to adjust the flux bias of the flux-controlled qubit device).

[0052] The heat flow from the heating device (e.g., resistive material 106 and / or superconducting heater bias wire 108) to the substrate 102 can depend on (e.g., can be varied). For example, in an embodiment where the substrate 102 comprises sapphire (e.g., aluminum oxide (Al2O3)), the thermal conductivity of sapphire at 200 milliklvin (mK) can be equal to le⁻⁴ W (.0001 W) / cm Kelvin (e.g., the thermal conductivity of sapphire at 200 mK = le⁻⁴ W / cm-K). In this example, the power flowing through the substrate 102 can be determined using equation (1) as defined below:

[0053]

[0054] Where A represents the area of ​​the sample, L represents the thickness of the sample, T1 represents the temperature of the top surface, T2 represents the temperature of the bottom surface, K represents the thermal conductivity, and T represents the integral variable of temperature.

[0055] In this example, it is assumed that the top surface of substrate 102 has a K value of 200 mK and the bottom surface has a K value of 10 mK. In this example, for a 1 mm x 1 mm substrate... 2 The substrate 102, which provides approximately through the substrate 102 A power flow of microwatts (μW). In this example, this can heat the cryostat including device 100 to a certain level. However, in this example, typically at 100 mK, the cryostat has a cooling power of over 400 μW, so a 3 μW load will have only a small effect on the base temperature. In this example, for a heater resistor of 3 ohms (e.g., the resistance of resistive material 106), a heater current of 1 mA (e.g., the current flowing through the superconducting heater bias line 108 and / or resistive material 106) will be sufficient to make the temperature higher than 200 mK of the heating device. Kapitza resistance is not considered in this embodiment. Including Kapitza resistance in this example will reduce the heater power required to raise the temperature, however, the time to recool the sample may increase. In this example, the superconducting heater bias line 108, which contains a material with a high critical temperature, can be used to feed the heating device (e.g., resistive material 106) without too many thermal connections.

[0056] Figure 2 An orthogonal view of an exemplary, non-limiting device 200 according to one or more embodiments described herein is shown, which can assist in the local heating of a superconducting flux bias loop. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0057] Device 200 may include an example, or a non-limiting alternative embodiment, of device 100, wherein device 200 may include a recess 202 that may be positioned below one or more portions of the bias loop 104, the resistive material 106, and / or the superconducting heater bias wire 108, as in Figure 2As illustrated in the illustrations, the pouch 202 can be etched into the substrate 102 during the fabrication of device 200 using one or more etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.). The recess 202 can reduce undesirable thermal coupling of one or more components of device 200 (e.g., flux-controlled qubit device, substrate 102, bias loop 104, resistive material 106, superconducting heater bias wire 108, etc.). By reducing this undesirable thermal coupling of one or more components of device 200, the recess 202 can thereby facilitate improved localized heating of the bias loop 104 (e.g., relative to device 100) by means of a heating device including resistive material 106 and superconducting heater bias wire 108 as described above.

[0058] Figure 3 Top views of exemplary, non-limiting devices 300a, 300b, 300c, 300d, 300e that can facilitate local heating of a superconducting flux bias loop according to one or more embodiments described herein are shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0059] Devices 300a, 300b, 300c, 300d, and 300e may include examples and non-limiting alternative embodiments of device 100 and / or device 200. Devices 300a, 300b, 300c, 300d, and 300e may be formed on and / or in substrate 102 (e.g., integrated on and / or in substrate 102); however, for clarity, in Figure 3 The substrate 102 is not shown in the illustrations of devices 300a, 300b, 300c, 300d, and 300e.

[0060] like Figure 3 The devices 300a, 300b, 300c, 300d, and 300e shown may each include flux-controlled qubit devices 302a, 302b, 302c, 302d, and 302e, which may each include the aforementioned [details omitted]. Figure 1 and 2Embodiments of flux-controlled qubit devices (e.g., qubits, SQUID loops, etc.) of the described device 100 and / or device 200; bias rings 304a, 304b, 304c, 304d, 304e, each bias ring may include an example of bias ring 104, or a non-limiting alternative embodiment; resistive materials 306a, 306b, 306c, 306d, 306e, each resistive material may include an example of resistive material 106, or a non-limiting alternative embodiment; and / or one or more superconducting heater bias wires 308a, 308b, 308c, 308d, 308e, these superconducting heater bias wires may each include an example of superconducting heater bias wire 108, or a non-limiting alternative embodiment.

[0061] like Figure 3 As shown, the resistive materials 306a, 306b, 306c, 306d, and 306e of devices 300a, 300b, 300c, 300d, and 300e can be formed in various shapes and / or positioned in various locations relative to bias rings 304a, 304b, 304c, 304d, and 304e. For example, as depicted in devices 300a, 300b, and 300e, the resistive materials 306a, 306b, and 306e can include substantially rectangular shapes. In this example, as shown in device 300a, the resistive material 306a can be positioned on a portion of the bias ring 304a, while in devices 300b and 300e, the resistive materials 306b and 306e can be positioned approximately at the center of the bias rings 304b and 304e, respectively.

[0062] In another example, as depicted in device 300c, resistive material 306c may include a substantially serpentine shape and may be positioned above a portion of bias loop 304a. In this example, this substantially serpentine shape of resistive material 306c can achieve higher resistance of resistive material 306c and (e.g., device 300c, bias loop 304c, resistive material 306c, superconducting heater bias wire 308c, etc.) increased temperature control during operation. In another example, as depicted in device 300d, resistive material 306d may include substantially the same shape as bias loop 304d and may be positioned substantially above bias loop 304d.

[0063] In another example, as depicted in device 300e, bias loop 304e may include a first superconducting material 310 and a second superconducting material 312. In this example, the first superconducting material 310 may include a first superconducting material having a first critical temperature, and the second superconducting material 312 may include a second superconducting material having a second critical temperature, wherein the second critical temperature of the second superconducting material 312 is lower than the first critical temperature of the first superconducting material 310. In this example, as depicted in device 300e, the first superconducting material 310 and the second superconducting material 312 may be positioned in series in bias loop 304e. In this example, using the first superconducting material 310 and the second superconducting material 312 to form bias loop 304e can promote (e.g., faster temperature cycling of bias loop 304e). In this example, see [link to relevant documentation] Figure 1 To locally heat and control the superconductivity of the bias loop 304e, a power supply can be applied to the bias line 308e of the superconducting heater to heat the resistive material 306e and the second superconducting material 312 to a temperature above the aforementioned second critical temperature of the second superconducting material 312. In this example, by heating the second superconducting material 312 above its critical temperature, the bias loop 304e can become normal (e.g., non-superconducting), thereby enabling the application of a new magnetic field and / or the tuning flux-controlled qubit device 302e in the bias loop 304e, as described above. Figure 1 As described.

[0064] Figure 4 A top view of an exemplary, non-limiting system 400 according to one or more embodiments described herein is shown, which can facilitate local heating of a superconducting flux bias loop. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0065] System 400 may include one or more devices 300a, which may be formed on substrate 102 and may be coupled (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operational ground, optical ground, physical ground, thermal ground, etc.) to one or more control circuit lines 402 that may be formed on substrate 102. Although Figure 4 The present invention depicts a system 400 having multiple devices 300a, but it should be understood that the subject matter disclosure is not limited thereto. For example, system 400 may include one or more of devices 100, 200, 300a, 300b, 300c, 300d, and / or 300e. Figure 4 As shown, in one embodiment, system 400 may include a plurality of devices 300a that may be coupled in parallel to each other via control circuit lines 402 (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operational ground, optical ground, physical ground, thermal ground, etc.). In an example, Figure 4The control circuit wires 402 depicted may include a common bias line. Although in Figure 4 As not shown, the control circuit line 402 may be further coupled to other control circuit components (e.g., components of the control grid outside the system 400) that facilitate operation of the device 300a.

[0066] System 400 may include control circuitry (e.g., a control gate) configured to operate one or more devices 300a individually and / or simultaneously (e.g., to individually and / or simultaneously locally heat and / or control the superconductivity of bias loop 304a). In some embodiments, system 400 may include one or more tunable resistors 404a, 404b that may be coupled to one or more devices 300a (e.g., chemical, communication, electrical, electromagnetic, operational, optical, physical, thermal) to individually and / or simultaneously control the operation of such devices 300a (e.g., by individually and / or simultaneously adjusting the current to a resistive material 306a of device 300a to individually and / or simultaneously locally heat and / or control the superconductivity of bias loop 304a). Although Figure 4 Not depicted, but one or more of the tunable resistors 404a, 404b may be further coupled to other control circuit components that facilitate operation of the device 300a (e.g., components of a control grid outside the system 400). In some embodiments, one or more of the tunable resistors 404a, 404b may be formed on and / or in the substrate 102 (e.g., integrated on and / or in the substrate 102) or located at a location outside the substrate 102.

[0067] Figure 5 A top view of an exemplary, non-limiting system 500 according to one or more embodiments described herein is shown, which is capable of assisting in the local heating of a superconducting flux bias loop. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0068] System 500 may include an example, non-limiting alternative embodiment of system 400, wherein system 500 may include a switch 502 that can (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operative ground, optical ground, physical ground, thermal ground, etc.) be connected to one or more superconducting heater bias wires 308a of one or more devices 300a, such as Figure 5 As shown, it is used to control the operation of this or these devices 300a. Although not in Figure 5As shown, switch 502 may also be coupled (e.g., chemical ground, communication ground, electrical ground, electromagnetic ground, operating ground, optical ground, physical ground, thermal ground, etc.) to other control circuit components (e.g., components of a control grid outside system 500) that facilitate operation of device 300a.

[0069] In one example, switch 502 can be actuated (e.g., via a power source external to system 500) to facilitate coupling switch 502 (e.g., chemical, communication, electrical, electromagnetic, operative, optical, physical, thermal, etc.) to one or more superconducting heater bias wires 308a of one or more devices 300a to individually and / or simultaneously control the operation of such or such devices 300a (e.g., via individually and / or simultaneously regulating the current to the resistive material 306a of one or more devices 300a to individually and / or simultaneously locally heat and / or control the superconductivity of one or more bias loops 304a). In some embodiments, switch 502 may be formed on and / or in substrate 102 (e.g., integrated on and / or in substrate 102) or located at a location external to substrate 102.

[0070] Figure 6A-26B Examples, non-limiting multi-step manufacturing sequences, are shown that can be implemented to manufacture one or more embodiments of the present disclosure described herein and / or illustrated in the accompanying drawings. For example, Figure 6A-19B The non-limiting multi-step manufacturing sequence shown can be implemented as manufacturing equipment 1900, wherein equipment 1900 may include the above-mentioned... Figure 1-5 Examples, non-limiting alternative embodiments, of the described devices 100, 200, 300a, 300b, 300c, 300d, 400, and / or 500. In another example, Figure 20A-26B The non-limiting multi-step manufacturing sequence shown can be implemented to manufacture device 2600, wherein device 2600 may include the above-mentioned... Figure 3 Examples and non-limiting alternative embodiments of the described device 300e.

[0071] although Figure 6A-26B The non-limiting multi-step manufacturing sequence shown describes the manufacture of devices 1900 and 2600, but it should be understood that the subject matter disclosure is not limited thereto. For example, Figure 6A-26B The non-restrictive multi-step manufacturing sequence shown can be modified and implemented accordingly to manufacture the above-mentioned products. Figure 1-5 The devices 100, 200, 300a, 300b, 300c, 300d, 300e, 400 and / or 500 are described.

[0072] See below for reference. Figure 6A-26BThe manufacture of various embodiments of this disclosure described herein and / or shown in the figures (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) may include a multi-step sequence of, for example, photolithography and / or chemical processing steps, which facilitates the stepwise construction of electronic-based systems, devices, components, and / or circuits in semiconductor and superconducting devices (e.g., integrated circuits). For example, various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be manufactured using techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomask technology, patterning technology, photoresist technology (e.g., positive photoresist, negative photoresist, hybrid photoresist, etc.), etching technology, etc. Techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation techniques, sputtering techniques, plasma ashing techniques, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), back polishing techniques and / or another technique used to manufacture integrated circuits.

[0073] See below for reference. Figure 6A-26B As described herein, various embodiments of the present disclosure described and / or illustrated in the figures (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be manufactured using various materials. For example, the various embodiments disclosed in the subject matter described herein and / or illustrated in the figures (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be manufactured using one or more different material classes, including but not limited to: conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, nonconducting materials, and / or another material that can be used in conjunction with one or more of the techniques described above for manufacturing integrated circuits.

[0074] Figure 6A The figure shows a top view of an example non-limiting device 600 including a substrate according to one or more embodiments described herein. Figure 6BA cross-sectional side view of the device 600, as viewed along a plane defined by line 602, is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0075] Device 600 may include substrate 604. Substrate 604 may include substrate 102. For example, substrate 604 may include the same material as substrate 102 (e.g., silicon (Si), sapphire (e.g., aluminum oxide (Al2O3)), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), silicon carbide (SiC), germanium (Ge) alloy, iii / v compound semiconductor, ii / vi compound semiconductor, silicon / silicon-germanium (Si / SiGe), silicon / silicon carbide (Si / SiC), silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGO1s), etc.). Substrate 604 may include a thickness (e.g., height) ranging from about 50 micrometers (μm) to about 800 μm. In some embodiments, one or more sides of substrate 604 (e.g., top side, bottom side, etc.) may be polished (e.g., using chemical mechanical planarization (CMP), back lapping, etc.).

[0076] Figure 7A The figure illustrates the formation of a resist layer on a substrate according to one or more embodiments described herein. Figure 6A and 6B A top view of an example non-restrictive device 600. Figure 7B A cross-sectional side view of the device 700 as defined along line 702 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0077] The device 700 may include examples and non-limiting alternative embodiments of the device 600 after the formation of the resist layer 704 on the substrate 604, such as... Figure 7A and 7B As shown. The resist layer 704 may include a photoresist material, which may be formed on the substrate 604 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above. In this example, the resist layer 704 may be deposited onto the substrate 604 using a spin-coating technique. The resist layer 704 may include a photoresist, including but not limited to a positive-tone photoresist, a negative-tone photoresist, a mixed-tone photoresist, and / or another photoresist.

[0078] Figure 8A The following is illustrated after a portion of the resist layer has been removed, according to one or more embodiments described herein. Figure 7A and 7B A top view of an example non-restrictive device 700. Figure 8BA cross-sectional side view of the device 800, viewed along a plane defined by line 802, is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0079] The device 800 may include, for example, non-limiting alternative embodiments of the device 700 after a portion of the resist layer 704 has been removed from the substrate 604 to form the void 804, such as... Figure 8A and 8B As shown. The void 804 can be formed in the resist layer 704 by removing a portion of the resist layer 704 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above. In an example (not shown in the figure), the resist layer 704 and / or void 804 can be formed using an ion milling process to form a reverse profile of the resist layer 704 and / or void 804 on the substrate 604. Although Figure 8A and 8B The void 804 shown comprises a generally rectangular annulus, but it should be understood that this disclosure is not limited thereto. For example, the void 804 can be formed in any shape (e.g., a circular ring, a square ring, a triangular ring, etc.) that enables the manufacture and / or implementation of one or more embodiments of this disclosure that can facilitate localized heating of a superconducting flux bias loop as described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.).

[0080] Figure 9A This illustrates the process after depositing a first superconducting layer, according to one or more embodiments described herein. Figure 8A and 8B A top view of an example non-restrictive device 800. Figure 9B A cross-sectional side view of the device 900 as viewed along a plane defined by line 902 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0081] Device 900 may include, for example, Figure 9A and 9BExamples and non-limiting alternative embodiments of device 800 after depositing a superconducting layer 904 on the device 800 (e.g., deposited on the resist layer 704 and on the exposed surface of the substrate 604 in the voids 804). The superconducting layer 904 can be deposited on device 800 (e.g., on the resist layer 704 and on the exposed surface of the substrate 604 in the voids 804) using one or more material deposition techniques as defined above (e.g., evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.). The superconducting layer 904 can be formed using a superconducting material, including but not limited to aluminum (Al), titanium nitride (TiN), lanthanum (La), molybdenum (Mo), molybdenum nitride (MoN), tantalum (Ta), tantalum nitride (TaN), and / or another material. The superconducting layer 904 can include a thickness (e.g., height) ranging from about 30 nanometers (nm) to about 500 nm. The superconducting layer 904 can be deposited on the device 800, such as... Figure 9A and 9B As shown, to form a bias loop, for example, as described below and in Figure 10A and 10B The bias loop 1004 is shown.

[0082] Figure 10A The image shows a portion of the resist layer and the first superconducting layer after removal to form a bias loop on the substrate, according to one or more embodiments described herein. Figure 9A and Figure 9B A top view of an example non-restrictive device 900. Figure 10B A cross-sectional side view of the device 1000 as viewed along the plane defined by line 1002 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0083] Device 1000 may include forming, after removing portions of the resist layer 704 and the superconducting layer 904 deposited on the resist layer 704, as shown in the image. Figure 10A and 10B The illustrated device 900 with bias loop 1004 is an example, not a limiting alternative embodiment. A stripping technique (e.g., solvent washing, peeling, etc.) can be used to remove portions of the resist layer 704 and the superconducting layer 904 deposited on the resist layer 704 to form the bias loop 1004 on the substrate 604, as shown. Figure 10A and 10BAs shown. The bias loop 1004 may include a portion of the superconducting layer 904 remaining on the substrate 604 after the removal of the resist layer 704, and a portion of the superconducting layer 904 deposited on the resist layer 704 as described above. In an example, the bias loop 1004 may include the portion described above and Figure 1 and Figure 2 Examples and non-limiting alternative embodiments of the bias loop 104 shown are illustrated below. In another example, the bias loop 1004 may include those described above and... Figure 3 , 4 Examples, non-limiting embodiments of the bias loops 304a, 304b, 304c, 304d and / or 304e shown in Figures 5 and 6.

[0084] Figure 11A The following is illustrated according to one or more embodiments described herein: after the deposition of an insulating layer. Figure 10A and Figure 10B Example non-restrictive device 1000 top view. Figure 11B A cross-sectional side view of the device 1100 as viewed along the plane defined by line 1102 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0085] When the insulating layer 1104 is deposited on such a Figure 11A and 11B After being deposited on the illustrated device 1000 (e.g., onto the substrate 604 and bias loop 1004), device 1100 may include example, non-limiting alternative embodiments of device 1000. An insulating layer 1104 may be deposited on device 1000 (e.g., on the substrate 604 and bias loop 1004) using one or more material deposition techniques defined above (e.g., evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.). The insulating layer 1104 may be formed using materials including, but not limited to, silicon nitride (e.g., SiN, Si3N4, etc.), silicon dioxide (SiO2), sapphire (e.g., aluminum oxide (Al2O3)) and / or another material. The insulating layer 1104 may include a thickness (e.g., height) ranging from about 0 nm to about 30 nm. In embodiments, the insulating layer 1104 may include an insulating barrier.

[0086] Figure 12A The following is illustrated after forming a resist layer on an insulating layer, according to one or more embodiments described herein. Figure 11A and 11B Example non-restrictive device 1100 top view. Figure 12BA cross-sectional side view of the device 1200 for planar observation defined along line 1202 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0087] After forming the second resist layer 704 on the insulating layer 1104, the device 1200 may include examples and non-limiting alternative embodiments of the device 1100, such as... Figure 12A and 12B As shown. The resist layer 704 may include a photoresist material, which may be formed on the insulating layer 1104 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above. In this example, the resist layer 704 may be deposited onto the insulating layer 1104 using a spin-coating technique. The resist layer 704 may include a photoresist, including but not limited to a positive-tone photoresist, a negative-tone photoresist, a mixed-tone photoresist, and / or another photoresist.

[0088] Figure 13A The image shows a process after a portion of the resist layer has been removed, according to one or more embodiments described herein. Figure 12A and 12B Example non-restrictive device 1200 top view. Figure 13B A cross-sectional side view of the device 1300 is shown as viewed along the plane defined by line 1302. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0089] like Figure 13A and 13B As shown, device 1300 may include an example, non-limiting alternative embodiment of device 1200 after removing a portion of resist layer 704 from insulating layer 1104 to form void 1304 and expose the surface of insulating layer 1104. Void 1304 can be formed in resist layer 704 by removing a portion of resist layer 704 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above. In an example (not shown in the figures), an ion milling process can be used to form resist layer 704 and / or void 1304 to form a reverse profile of resist layer 704 and / or void 1304 on insulating layer 1104. Although Figure 13A and 13BThe void 1304 depicted herein includes a generally rectangular shape, but it should be understood that this disclosure is not limited thereto. For example, the void 1304 can be formed in any shape (e.g., rectangular ring, circular ring, square ring, triangular ring, rectangle, circle, square, triangle, serpentine shape, etc.) that enables the manufacture and / or implementation of one or more embodiments of this disclosure that can facilitate localized heating of superconducting flux bias loops as described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.).

[0090] Figure 14A The following is illustrated according to one or more embodiments described herein: after the deposition of a resistive layer. Figure 13A and 13B Example non-restrictive device 1300 top view. Figure 14B A cross-sectional side view of the device 1400 as viewed along the plane defined by line 1402 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0091] Device 1400 may include, for example Figure 14A and 14B The illustrated example is a non-limiting alternative embodiment of device 1300 after the resistive layer 1404 has been deposited on device 1300 (e.g., deposited on resistive layer 704 and on the exposed surface of insulating layer 1104 deposited in voids 1304). The resistive layer 1404 can be deposited on device 1300 (e.g., deposited on resistive layer 704 and on the exposed surface of insulating layer 1104 in voids 1304) using one or more material deposition techniques defined above (e.g., evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.). The resistive layer 1404 can be formed using any material having resistive properties (e.g., non-superconducting properties), including but not limited to nickel-chromium alloy (NiCr), gold-palladium (AuPd), manganese (Mn), constantan (e.g., copper-nickel alloy), and / or another resistive material (e.g., another common metal). The resistive layer 1404 may include a thickness (e.g., height) ranging from about 5 nm to about 200 nm. The resistive layer 1404 may be deposited on the device 1300, such as... Figure 14A and 14B As shown, to form a resistive component, such as as described below and Figure 15A and 15B The resistor material shown is 1504.

[0092] Figure 15AThis illustration shows a portion of the resistive and resistive layers after removal to form a resistive component, according to one or more embodiments described herein. Figure 14A and 14B Example of a top view of a non-restrictive device 1400. Figure 15B A cross-sectional side view of the device 1500 as seen along the plane defined by line 1502 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0093] Device 1500 may include, for example, non-limiting alternative embodiments of device 1500 after removing portions of resist layer 704 and resistive layer 1404 deposited on resist layer 704 to form resistive material 1504. Figure 15A and 15B As shown. Figure 15A and 15B As shown, a stripping technique (e.g., solvent washing, peeling, etc.) can be used to remove the resist layer 704 and portions of the resistive layer 1404 deposited on the resist layer 704 to form a resistive material 1504 on the insulating layer 1104. The resistive material 1504 may include portions of the resistive layer 1404 retained on the insulating layer 1104 after the removal of the resist layer 704, as described above, as well as portions of the resistive layer 1404 deposited on the resist layer 704. In an example, the resistive material 1504 may include the portions described above and... Figure 1-5 Examples and non-limiting alternative embodiments of resistive materials 106, 306a, 306b, 306c, 306d and / or 306e are shown in the figure.

[0094] Figure 16A The diagram illustrates the process after forming a resist layer on an insulating layer and a resistive material, according to one or more embodiments described herein. Figure 15A and 15B A top view of an example non-restrictive device 1500. Figure 16B This illustration shows a cross-sectional side view of the device 1600 as viewed along the plane defined by line 1602. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0095] Device 1600 may include, for example, non-limiting alternative embodiments of device 1600 after forming a third resist layer 704 on insulating layer 1104 and resistive material 1504, such as Figure 16A and 16BAs shown. The resist layer 704 may include a photoresist material, which may be formed on the insulating layer 1104 and the resistive material 1504 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithography patterning processes) as defined above. In this example, the resist layer 704 may be deposited onto the insulating layer 1104 and the resistive material 1504 using a spin coating technique. The resist layer 704 may include a photoresist, including but not limited to a positive-tone photoresist, a negative-tone photoresist, a mixed-tone photoresist, and / or another photoresist.

[0096] Figure 17A The image shows a portion of the resist layer after removal, according to one or more embodiments described herein. Figure 16A and 16B Example non-restrictive device 1600 top view. Figure 17B A cross-sectional side view of the device 1700 as viewed along the plane defined by line 1702 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0097] like Figure 17A and 17B As shown, device 1700 may include an example, non-limiting alternative embodiment of device 1600 after removing portions of the resist layer 704 from the insulating layer 1104 and resistive material 1504 to form a void 1704 and expose the surfaces of the insulating layer 1104 and resistive material 1504. The void 1704 may be formed in the resist layer 704 by removing portions of the resist layer 704 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above. In an example (not shown in the figures), the resist layer 704 and / or the void 1704 may be formed using an ion milling process to form a reverse profile of the resist layer 704 and / or the void 1704 on the insulating layer 1104 and resistive material 1504. Although Figure 17A and 17B The void 1704 depicted herein includes a generally rectangular shape, but it should be understood that this disclosure is not limited thereto. For example, the void 1704 can be formed in any shape that enables the manufacture and / or implementation of one or more embodiments of this disclosure, which shape can facilitate localized heating of a superconducting flux bias loop (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) as described herein.

[0098] Figure 18A The following is illustrated after the deposition of the second superconducting layer, according to one or more embodiments described herein. Figure 17A and 17BA top view of an example non-restrictive device 1700. Figure 18B A cross-sectional side view of the device 1800 as viewed along the plane defined by line 1802 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0099] Device 1800 may include instances of device 1700 after the superconducting layer 1804 has been deposited on device 1700, and non-limiting alternative embodiments, such as... Figure 18A and 18B As shown (e.g., deposited on the resist layer 704 and on the exposed surfaces of the insulating layer 1104 and resistive material 1504 deposited in the voids 1704). A superconducting layer 1804 can be deposited on the device 1700 (e.g., on the resist layer 704 and on the exposed surfaces of the insulating layer 1104 and resistive material 1504 in the voids 1704) using one or more material deposition techniques defined above (e.g., evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.). The superconducting layer 1804 can be formed using a superconducting material, including but not limited to niobium (Nb), niobium nitride (NbN), niobium titanium nitride (NbTiN), niobium titanium (NbTi), niobium germanium (Nb3Ge), and / or another material. The superconducting layer 1804 can include a thickness (e.g., height) ranging from about 10 nm to about 200 nm. The superconducting layer 1804 can be deposited on the device 1700, such as Figure 18A and 18B As shown, to form the superconducting heater bias line, for example, superconducting heater bias line 1904, as described below, as follows. Figure 19A and 19B As shown.

[0100] Figure 19A The following diagram illustrates the process, according to one or more embodiments described herein, after removing multiple portions of the resist layer and the second superconducting layer to form the superconducting heater bias wire. Figure 18A and 18B A top view of the exemplary, non-restrictive device 1800. Figure 19B A cross-sectional side view of the device 1900 as viewed from a plane defined along line 1902 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0101] The device 1900 may include examples, and non-limiting alternative embodiments, of the device 1900, of forming a superconducting heater bias wire 1904 on an insulating layer 1104 and a resistive material 1504 after removing a portion of the resist layer 704 and the superconducting layer 1804 deposited on the resist layer 704. Figure 19A and 19B As shown. A portion of the resist layer 704 and the superconducting layer 1804 deposited on the resist layer 704 can be removed using stripping techniques (e.g., solvent washing, peeling, etc.) to form the superconducting heater bias line 1904 on the insulating layer 1104 and the resistive material 1504, as shown. Figure 19A and 19B As shown. The superconducting heater bias line 1904 may include portions of the superconducting layer 1804 remaining on the insulating layer 1104 and resistive material 1504 after the removal of the resist layer 704, as well as portions of the superconducting layer 1804 deposited on the resist layer 704 as described above. In an example, the superconducting heater bias line 1904 may include the components described above and... Figure 1-5 Examples and non-limiting alternative embodiments of the superconducting heater bias wires 108, 308a, 308b, 308c, 308d, and / or 308e shown in the figure.

[0102] Figure 20A This illustrates one or more embodiments according to the description herein, after removing a portion of the resist layer, Figure 7A and 7B Example non-restrictive device 700 top view. Figure 20B The illustration shows a cross-sectional side view of the device 2000 as viewed along the plane defined by line 2002. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0103] A portion of the resist layer 704 is removed from the substrate 604 to form, as shown in the figure. Figure 20A and 20B Following the shown void 2004, device 2000 may include example, non-limiting alternative embodiments of device 700. Void 2004 can be formed in resist layer 704 by removing a portion of resist layer 704 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above. In an example (not shown in the figures), resist layer 704 and / or void 2004 can be formed using an ion milling process to form a reverse profile of resist layer 704 and / or void 2004 on substrate 604. Although Figure 20A and Figure 20BThe void 2004 depicted herein includes a generally “C”-shaped void, but it should be understood that this disclosure is not so limiting. For example, the void 2004 can be formed in any shape that enables the manufacture and / or implementation of one or more embodiments of this disclosure, which can facilitate localized heating of a superconducting flux bias loop as described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.).

[0104] Figure 21A The following is illustrated after the deposition of a first superconducting layer, according to one or more embodiments described herein. Figure 20A and 20B A top view of an example non-restrictive device 2000. Figure 21B A cross-sectional side view of the device 2100 as defined by line 2102 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0105] Device 2100 may include, for example Figure 21A and 21B Examples and non-limiting alternative embodiments of the device 2000 after depositing a superconducting layer 904 on the device 2000 (e.g., deposited on the resist layer 704 and on the exposed surface of the substrate 604 in the voids 2004). The superconducting layer 904 can be deposited on the device 2000 (e.g., on the resist layer 704 and on the exposed surface of the substrate 604 in the voids 2004) using one or more material deposition techniques as defined above (e.g., evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.). The superconducting layer 904 can be formed using a superconducting material, including but not limited to aluminum (Al), titanium nitride (TiN), lanthanum (La), molybdenum (Mo), molybdenum nitride (MoN), tantalum (Ta), tantalum nitride (TaN), and / or another material. The superconducting layer 904 may include a thickness (e.g., height) ranging from about 10 nm to about 100 nm. The superconducting layer 904 may be as follows: Figure 21A and 21B The first superconducting material shown is deposited on device 2000 to form a bias loop, for example, as described below. Figure 22A and 22B The first superconducting material shown is 2204.

[0106] Figure 22AThe diagram illustrates, according to one or more embodiments described herein, the first superconducting material after removing multiple portions of the resist layer and the first superconducting layer to form a bias loop on the substrate. Figure 21A and 21B A top view of an example non-restrictive device 2100. Figure 22B A cross-sectional side view of the device 2200 as defined by line 2202 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0107] Device 2200 may include examples of device 2100, and non-limiting alternative embodiments, such as those following the formation of a first superconducting material 2204 with a bias loop on substrate 604 after removal of a portion of the resist layer 704 and the superconducting layer 904 deposited on the resist layer 704. Figure 22A and 22B As shown. A portion of the resist layer 704 and the superconducting layer 904 deposited on the resist layer 704 can be removed using a stripping technique (e.g., solvent washing, peeling, etc.) to form a first superconducting material 2204 on the substrate 604, as shown. Figure 22A and 22B As shown. As described above, the first superconducting material 2204 may include a portion of the superconducting layer 904 retained on the substrate 604 after the removal of the resist layer 704, and a portion of the superconducting layer 904 deposited on the resist layer 704.

[0108] In an example, the first superconducting material 2204 may include a first superconducting material for a bias loop, which includes a variety of superconducting materials that can be developed on the substrate 604. For example, the first superconducting material 2204 may include the following described and Figure 26A and 26B The first superconducting material of bias loop 2606 shown in the image (bias loop 2606 in...) Figure 26A and 26B (Represented by thick dashed lines), wherein the bias loop 2606 may include a first superconducting material 2204 and a second superconducting material 2604. In an embodiment, the first superconducting material 2204 may include the above-described and Figure 3 Examples and non-limiting alternative embodiments of the first superconducting material 310 of the device 300e shown.

[0109] Figure 23A The illustration shows the formation of a resist layer on the first superconducting material and the substrate according to one or more embodiments described herein. Figure 22A and 22B A top view of an example non-restrictive device 2200. Figure 23BA cross-sectional side view of the device 2300 as seen along the plane defined by line 2302 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0110] like Figure 23A and 23B As shown, device 2300 may include examples and non-limiting alternative embodiments of device 2200 after forming a second photoresist layer 704 on the first superconducting material 2204 and substrate 604. The photoresist layer 704 may include a photoresist material formed on the first superconducting material 2204 and substrate 604 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithography patterning processes) as defined above. In an example, the photoresist layer 704 may be deposited onto the first superconducting material 2204 and substrate 604 using spin coating. The photoresist layer 704 may include photoresists, including but not limited to positive-tone photoresists, negative-tone photoresists, mixed-tone photoresists, and / or another photoresist.

[0111] Figure 24A The following is illustrated after a portion of the resist layer has been removed, according to one or more embodiments described herein. Figure 23A and 23B Example non-restrictive device 2300 top view. Figure 24B A cross-sectional side view of the device 2400 as defined along line 2402 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0112] Device 2400 may include examples, non-limiting alternative embodiments, of device 2300, following the removal of a portion of the resist layer 704 from the first superconducting material 2204 and the substrate 604 to form a void 2404 and expose the surfaces of the first superconducting material 2204 and the substrate 604. Figure 24A and 24B As shown. By removing portions of the resist layer 704 using one or more photolithography, patterning, and / or photoresist techniques (e.g., photolithographic patterning processes) as defined above, voids 2404 can be formed in the resist layer 704. In an example (not shown in the figure), an ion milling process can be used to form the resist layer 704 and / or voids 2404 to form a reverse profile of the resist layer 704 and / or voids 2404 on the first superconducting material 2204 and the substrate 604. Although Figure 24A and Figure 24BThe void 2404 depicted herein includes a generally rectangular shape, but it should be understood that this disclosure is not limited thereto. For example, the void 2404 can be formed in any shape that enables the manufacture and / or implementation of one or more embodiments of this disclosure, which shape can facilitate localized heating of a superconducting flux bias loop (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) as described herein.

[0113] Figure 25A The following is illustrated after the deposition of a second superconducting layer, according to one or more embodiments described herein. Figure 24A and 24B A top view of the non-restrictive device 2400. Figure 25B A cross-sectional side view of the device 2500 as defined along line 2502 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0114] Device 2500 may include, for example Figure 25A and 25B Examples and non-limiting alternative embodiments of the device 2400 after depositing a superconducting layer 2504 on the device 2400 (e.g., deposited on the resist layer 704 and on the exposed surfaces of the first superconducting material 2204 and the substrate 604 within the voids 2404). The superconducting layer 2504 can be deposited on the device 2400 (e.g., on the resist layer 704 and on the exposed surfaces of the first superconducting material 2204 and the substrate 604 within the voids 2404) using one or more material deposition techniques as defined above (e.g., evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.) using superconducting materials including, but not limited to, titanium (Ti), aluminum (Al), rhenium (Re), zinc (Zn), zirconium (Zr), hafnium (Hf), and / or another material). The superconducting layer 2504 may include a thickness (e.g., height) ranging from about 10 nm to about 100 nm. The superconducting layer 2504 may be deposited on the device 2400, such as... Figure 25A and 25B As shown, a second superconducting material is used to form a bias loop, for example, as described below and Figure 26A and 26B The second superconducting material shown is 2604.

[0115] Figure 26AThe illustration shows a second superconducting material after removing multiple portions of the resist layer and the second superconducting layer, according to one or more embodiments described herein, to form a bias loop formed on the substrate. Figure 25A and 25B A top view of the exemplary, non-restrictive device 2500. Figure 26B A cross-sectional side view of the device 2600 as defined along line 2602 is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0116] Device 2600 may include examples, non-limiting alternative embodiments, of device 2500 after removing multiple portions of the resist layer 704 and the superconducting layer 2504 deposited on the resist layer 704 to form a bias loop 2606 formed on the substrate 604. Figure 26A and 26B As shown (bias loop 2606 in) Figure 26A and 26B (Used as a thick dashed line in the middle). For example... Figure 26A and 26B As shown, a stripping technique (e.g., solvent washing, peeling, etc.) can be used to remove the resist layer 704 and a portion of the superconducting layer 2504 deposited on the resist layer 704 to form a second superconducting material 2604 on the first superconducting material 2204 and the substrate 604. As described above, the second superconducting material 2604 may include a portion of the superconducting layer 2504 remaining on the first superconducting material 2204 and the substrate 604 after the removal of the resist layer 704, as well as a portion of the superconducting layer 2504 deposited on the resist layer 704.

[0117] In this example, the second superconducting material 2604 may include the second superconducting material of the bias loop 2606, which may include a variety of superconducting materials that can be developed on the substrate 604. For example, such as Figure 26A and 26B As shown, the bias loop 2606 may include a first superconducting material 2204 and a second superconducting material 2604. In an embodiment, the second superconducting material 2604 may include the materials described above and... Figure 3 Examples and non-limiting alternative embodiments of the second superconducting material 312 in the device 300e shown in the figure.

[0118] Although not shown in the accompanying drawings, it should be understood that device 2600 can be further developed into one or more embodiments of this disclosure, which can facilitate localized heating of a superconducting flux bias loop (e.g., device 100, 200, 300e, system 400, 500, etc.) as described herein. In some embodiments, the above-described and Figure 6A-19BThe non-limiting multi-step manufacturing sequence shown herein includes one or more manufacturing steps to facilitate further development of device 2600 to one or more embodiments disclosed herein, which may facilitate localized heating of the superconducting flux bias loop (e.g., devices 100, 200, 300e, systems 400, 500, etc.) as described herein. For example, the above and... Figure 11A-11B The manufacturing steps shown are for forming an insulating layer 1104 on the substrate 604 and the bias loop 2606 of the device 2600. In another example, the above and Figure 12A-15B The manufacturing steps shown herein are to form resistive material 1504 on one or more portions of insulating layer 1104 that can be deposited on substrate 604 and bias loop 2606 of device 2600, as described above. In another example, the above and Figure 16A-19B The manufacturing steps shown are to form superconducting heater bias lines 1904 on multiple portions of the resistive material 1504 and the insulating layer 1104, these superconducting heater bias lines can be deposited on the device 2600 as described above. In embodiments where the device 2600 is further developed as described above to form the insulating layer 1104, the resistive material 1504, and the superconducting heater bias lines 1904 on the device 2600, such further development of the device 2600 can include the above-described and Figure 3 Examples and non-limiting alternative embodiments of the device 300e shown herein.

[0119] The various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be associated with various technologies. For example, the different embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be associated with semiconductor and / or superconductor device technology, semiconductor and / or superconductor device manufacturing technology, quantum computing device technology, quantum computing device manufacturing technology, superconducting flux bias circuit technology, superconducting flux bias circuit manufacturing technology, flux-controlled qubit device technology, flux-controlled qubit device manufacturing technology, and / or other technologies.

[0120] The various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can provide technical improvements over the various technologies listed above. For example, the different embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can achieve individual and / or simultaneous local heating of one or more bias loops in a superconducting flux bias circuit in order to individually and / or simultaneously control the superconductivity of this or these bias loops and / or the magnetic field of this or these bias loops. In this example, by enabling such individual and / or simultaneous control of the superconductivity and / or magnetic field of this or these bias loops, the various embodiments disclosed in the subject matter described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can enable individual and / or simultaneous tuning of one or more flux-controlled qubit devices (e.g., a qubit, a SQUID loop, etc.) coupled to this or these bias loops. In this example, by enabling such individual and / or simultaneous tuning of the flux-controlled qubit devices coupled to the bias loops, the various embodiments disclosed in this description (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can thereby assist in at least one of the following: improved fidelity of the flux-controlled qubit devices, improved fidelity of a quantum device including the flux-controlled qubit devices, or improved performance of a quantum device including the flux-controlled qubit devices.

[0121] The various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) may provide technical improvements to the processing units associated with one or more of the various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.). For example, as described above, the various embodiments disclosed herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can assist in at least one of the following: improved fidelity of this or these flux-controlled qubit devices, improved fidelity of a quantum device including this or these flux-controlled qubit devices, or improved performance of a quantum device including this or these flux-controlled qubit devices. In this example, such a quantum device may include a processing unit, such as a quantum processor, which includes one or more of the various embodiments described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.). Such improvements (or more) to such processing units can further contribute to improved accuracy and / or efficiency of the processing units, as well as reduced computational costs.

[0122] The practical application of the various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) is that they can be implemented in quantum computing devices (e.g., quantum processors, quantum computers, etc.) to improve the processing fidelity, processing performance, and / or processing cost of such devices, which can facilitate fast and / or potentially universal quantum computing. This practical application can improve the output (e.g., computational and / or processing results) of one or more compilation jobs (e.g., quantum computing jobs) executed on such devices.

[0123] It should be understood that the various embodiments disclosed in the subject matter described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) provide a novel method for locally heating one or more bias loops in a superconducting flux bias circuit individually and / or simultaneously to tune one or more flux-controlled qubit devices (e.g., qubits, SQUID loops, etc.) coupled individually and / or simultaneously to such bias loops, which are driven by relatively new quantum computing techniques. For example, the various embodiments disclosed in the subject matter described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) provide a novel approach for individually and / or simultaneously tuning one or more flux-controlled qubit devices (e.g., a qubit, a SQUID loop, etc.) coupled to the bias loops of the superconducting flux bias circuits, which may assist in at least one of improved fidelity of the flux-controlled qubit devices, including improved fidelity of the quantum devices of the one or more flux-controlled qubit devices, or improved performance of the quantum devices of the one or more flux-controlled qubit devices.

[0124] The various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be coupled to hardware and / or software to solve problems that are inherently highly technical, not abstract, and cannot be performed as a set of human mental actions. For example, the various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can be implemented in quantum computing devices that can process information and / or perform computations that are not abstract and cannot be performed as a set of human mental actions.

[0125] It should be understood that the various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) can utilize various combinations of electrical components, mechanical components, and circuits that cannot be replicated in the human mind or performed by a human. For example, assisting in the individual and / or simultaneous tuning of one or more flux-controlled qubit devices (e.g., a qubit, a SQUID loop, etc.) in a quantum computing device is an operation beyond the capabilities of the human mind. For example, the amount of data processed, the speed at which such a quantum computing device (e.g., device 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, system 400, 500, etc.) using various embodiments of the present disclosure described herein, the amount of data processed, the speed at which such data is processed, and / or the type of data processed may be greater than, faster than, and / or different from the amount, speed, and / or type of data that the human mind can process in the same amount of time.

[0126] The various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) may also be fully operable to perform one or more other functions (e.g., full power-on, full execution, etc.) while simultaneously performing the aforementioned operations. It should also be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be understood that the different embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) may include information that cannot be manually obtained by an entity (such as a human user). For example, the types, quantities, and / or various types of information processed by the various embodiments of this disclosure described herein (e.g., devices 100, 200, 300a, 300b, 300c, 300d, 300e, 1900, 2600, systems 400, 500, etc.) are more complex than information manually obtained by a human user.

[0127] See above Figure 6A-26B The described example of a non-limiting multi-step manufacturing sequence can be derived from a computational system (e.g., Figure 27 The operating environment 2700 shown in the diagram and described below, and / or computing devices (e.g., Figure 27The computer 2712 shown in the figures and described below is implemented in a multi-step manufacturing sequence that can be implemented to manufacture one or more embodiments of the present disclosure described herein and / or shown in the figures. In a non-limiting exemplary embodiment, such a computing system (e.g., operating environment 2700) and / or such a computing device (e.g., computer 2712) may include one or more processors and one or more memory devices on which executable instructions may be stored, which, when executed by the one or more processors, facilitate the use of the components described herein. Figure 6A-26B The described example is the execution of a non-limiting multi-step manufacturing operation. As a non-limiting example, the one or more processors described herein can facilitate the manufacture of semiconductor and / or superconductor devices by directing and / or controlling one or more systems and / or devices for performing such manufacturing. Figure 6A-26B The example described is the execution of a non-limiting multi-step manufacturing operation.

[0128] For the sake of simplicity, the methods described herein (e.g., computer-implemented methods) are depicted and described as a series of actions. It should be understood and recognized that the subject matter innovation is not limited to the actions shown and / or the order of actions; for example, actions may occur in different orders and / or simultaneously, and may occur with other actions not presented or described herein. Furthermore, depending on the disclosed subject matter, not all actions shown are necessary to implement the methods described herein (e.g., computer-implemented methods). Moreover, those skilled in the art will understand and appreciate that such methods may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the methods disclosed below and throughout this specification (e.g., computer-implemented methods) can be stored on an article of art to facilitate the transfer and transfer of such methods (e.g., computer-implemented methods) to a computer. As used herein, the term "article of art" is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0129] In order to provide context for the various aspects of the disclosed subject, Figure 27 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 27 A block diagram of an example non-limiting operating environment is shown, which may facilitate one or more embodiments described herein. For example, operating environment 2700 may be used to implement the embodiments described herein. Figure 6A-26B The described example, non-limiting multi-step manufacturing operations facilitate the implementation of one or more embodiments of the subject matter disclosed herein. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0130] See Figure 27The appropriate operating environment 2700 for implementing various aspects of this disclosure may also include a computer 2712. The computer 2712 may also include a processing unit 2714, system memory 2716, and a system bus 2718. The system bus 2718 couples system components (including, but not limited to, system memory 2716) to the processing unit 2714. The processing unit 2714 may be any of the various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 2714. The system bus 2718 may be any of several types of bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of the various available bus architectures, including (but not limited to) Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0131] System memory 2716 may also include volatile memory 2720 and non-volatile memory 2722. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 2722, and the BIOS contains basic routines for transferring information between components within computer 2712, such as during startup. Computer 2712 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 27 Disk storage 2724 is shown as an example. Disk storage 2724 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 2724 may also include storage media, either alone or in combination with other storage media. To facilitate connection of disk storage 2724 to system bus 2718, a removable or non-removable interface, such as interface 2726, is typically used. Figure 27 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 2700 is also described. Such software may also include, for example, an operating system 2728. The operating system 2728, which can be stored on disk storage 2724, is used to control and allocate the resources of computer 2712.

[0132] System application 2730 utilizes operating system 2728 to manage resources through program modules 2732 and program data 2734, for example, stored in system memory 2716 or disk storage 2724. It should be understood that this disclosure can be implemented using different operating systems or combinations of operating systems. Users input commands or information into computer 2712 via input device 2736. Input device 2736 includes, but is not limited to, pointing devices such as a mouse, trackball, pen, touchpad, keyboard, microphone, joystick, gamepad, disc satellite dish, scanner, TV tuner card, digital camera, digital camcorder, and webcam. These and other input devices are connected to processing unit 2714 via system bus 2718 through one or more interface ports 2738. Interface ports 2738 include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 2740 uses some of the same type of ports as input device 2736. Therefore, for example, a USB port can be used to provide input to computer 2712 and output information from computer 2712 to output device 2740. Output adapter 2742 is provided to illustrate that, in addition to other output devices 2740 that require special adapters, there are other output devices 2740, such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 2742 includes video and sound cards that provide a connection between output device 2740 and system bus 2718. It should be noted that other devices and / or device systems provide both input and output capabilities, such as one or more remote computers 2744.

[0133] Computer 2712 can operate in a networked environment using a logical connection to one or more remote computers (such as remote computer 2744). Remote computer 2744 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other public network node, and may typically include many or all of the elements described relative to computer 2712. For simplicity, only memory storage device 2746 is shown as having remote computer 2744. Remote computer 2744 is logically connected to computer 2712 via network interface 2748 and then physically connected via communication connection 2750. Network interface 2748 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and their variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 2750 refers to the hardware / software used to connect network interface 2748 to system bus 2718. Although communication connection 2750 is shown inside computer 2712 for clarity, it may also be external to computer 2712. The hardware / software used to connect to network interface 2748 may also include (for illustrative purposes only) internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0134] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible means capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards, or protrusions in slots having instructions recorded thereon, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0135] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the present invention.

[0136] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0137] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0138] While the subject matter has been described above in the general context of computer-executable instructions running on a computer and / or a computer program product on a computer, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer implementation methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be implemented in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the invention can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from memory that may include or comprise one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing code from computer executable components in a distributed manner, for example, multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" can include a single memory or memory unit at one location or multiple memory or memory units at one or more locations.

[0139] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or a thread of execution, and components may reside on a single computer and / or be distributed across two or more computers. In another instance, a corresponding component may be executed from a different computer-readable medium having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via that signal). As another example, a component may be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this scenario, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a device that provides a specific function through electronic components without mechanical parts, wherein the electronic components can include a processor or other means for performing software or firmware that at least partially imparts the functionality to the electronic components. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0140] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Additionally, the articles "a" and "an" as used in the subject matter specification and figures should generally be interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as superior to or better than other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0141] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as “storage,” “data storage,” “database,” “database,” and substantially any other information storage component, used in connection with the operation and function of a component, are used to refer to a “memory component,” an entity embodied in “memory,” or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (F... ERAM). Volatile memory may include, for example, RAM that can serve as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). In addition, the memory components of the systems or computer-implemented methods disclosed herein inherently include (but are not limited to) these and any other suitable types of memory.

[0142] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components or computer-implemented method for the purposes of describing this disclosure; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the terms “includes,” “has,” “possesses,” etc., used in the detailed description, claims, appendices, and drawings are intended to be inclusive in a manner similar to the term “comprising,” since “comprising” is interpreted as a transitional word in the claims.

[0143] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum device, comprising: A substrate having a superconducting flux bias circuit including a bias loop coupled to a flux-controlled qubit device, wherein the flux-controlled qubit device includes a superconducting quantum interference device loop. as well as A heating device is coupled to the bias loop and one or more superconducting heater bias lines.

2. The apparatus according to claim 1, wherein, The bias loop includes a continuous flux bias loop.

3. The apparatus according to any one of claims 1-2, wherein, The heating device includes a resistor thermally coupled to the bias loop.

4. The apparatus according to any one of claims 1-2, wherein, The heating device includes a superconducting heater bias line coupled to a resistive material.

5. The apparatus according to any one of claims 1-2, wherein, The heating device includes a superconducting heater bias line, which has a first critical temperature higher than the second critical temperature of the bias loop.

6. The apparatus according to any one of claims 1-2, wherein, The heating device is thermally coupled to the bias loop to heat at least one section of the bias loop to above the critical temperature of the bias loop.

7. The apparatus according to any one of claims 1-2, wherein, The heating device is thermally coupled to the bias loop to control the superconductivity of the bias loop and the magnetic field of the bias loop, thereby contributing to at least one of the following: improved fidelity of the flux-controlled qubit device, improved fidelity of a quantum device including the flux-controlled qubit device, or improved performance of a quantum device including the flux-controlled qubit device.

8. A quantum device, comprising: A superconducting flux bias circuit includes a flux-controlled qubit device coupled to a bias loop comprising a first critical temperature material and a second critical temperature material, wherein the flux-controlled qubit device includes a superconducting quantum interference device loop, and the bias circuit is integrated onto and formed entirely on the surface of a substrate. as well as A heating device is coupled to the bias loop and one or more superconducting heating bias lines.

9. The apparatus according to claim 8, wherein, The first critical temperature material includes a first superconducting material having a first critical temperature, and the second critical temperature material includes a second superconducting material having a second critical temperature lower than the first critical temperature.

10. The apparatus according to any one of claims 8 to 9, wherein, The bias loop includes a continuous flux bias loop.

11. The apparatus according to any one of claims 8 to 9, wherein, The heating device includes a resistor thermally coupled to the bias loop.

12. The apparatus according to any one of claims 8 to 9, wherein, The heating device includes a superconducting heater bias line coupled to a resistive material.

13. The apparatus according to any one of claims 8 to 9, wherein, The heating device includes a superconducting heater bias line, the critical temperature of which is higher than at least one of the first critical temperature of the first critical temperature material or the second critical temperature of the second critical temperature material.

14. The apparatus according to any one of claims 8 to 9, wherein, The heating device is thermally coupled to the bias loop to heat the second critical temperature material to a temperature higher than the critical temperature of the second critical temperature material.

15. A quantum device, comprising: A substrate having a superconducting flux bias circuit, the superconducting flux bias circuit including multiple bias loops coupled to a flux-controlled qubit device, wherein the flux-controlled qubit device includes a superconducting quantum interference device loop, the bias circuit being integrated onto the surface of the substrate and formed entirely on the surface of the substrate. as well as One or more heating devices, the one or more heating devices being coupled to one or more of the bias loops and one or more control circuit wires formed on the substrate.

16. The apparatus according to claim 15, wherein, The one or more control circuit wires or at least one of the one or more heating devices are coupled to one or more tunable resistors to control the operation of the one or more heating devices.

17. The apparatus according to any one of claims 15 to 16, wherein, The one or more control circuit wires or at least one of the one or more heating devices are coupled to one or more switches to control the operation of the one or more heating devices.

18. The apparatus according to any one of claims 15 to 16, wherein, The bias loop includes a continuous flux bias loop.

19. The apparatus according to any one of claims 15 to 16, wherein, At least one of the one or more heating devices is thermally coupled to at least one bias loop in the bias loop to heat one or more sections of the at least one bias loop to a temperature above the critical temperature of the at least one bias loop.

20. The apparatus according to any one of claims 15 to 16, wherein, At least one of the one or more heating devices is thermally coupled to at least one of the bias loops to control the superconductivity and magnetic field of the at least one bias loop, thereby contributing to at least one of the following: improved fidelity of at least one flux-controlled qubit device, improved fidelity of a quantum device including the at least one flux-controlled qubit device, or improved performance of the quantum device including the at least one flux-controlled qubit device.

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