Chip power consumption acquisition method, circuit, device and equipment

Abstract

The present application provides a chip power consumption acquisition method, circuit, device and equipment, which obtains the key feature information of the chip to be tested at the end of the first time period, and uses the key feature information of the chip to be tested as the input of the power consumption model to obtain the total power consumption of the chip to be tested in the first time period output by the power consumption model, and the power consumption model is trained based on the number of flip-flops of all triggers in the simulation system of the chip to be tested in different time periods, as well as the temperature, substrate bias voltage and operating voltage at the end of different time periods. Since the trigger in the present application is the underlying structure of the chip, the correlation with the chip running program is reduced, thereby effectively reducing the impact of different chip running programs on the establishment of the power consumption model. In addition, the present application fully considers the impact of temperature, substrate bias voltage and operating voltage on the total power consumption of the chip to be tested, further improves the accuracy of the power consumption calculation results, and makes the power consumption model highly versatile and portable.

Description

Technical Field

[0001] The present application relates to the field of digital chips, and in particular to a method, circuit, device and equipment for obtaining chip power consumption. Background Art

[0002] With the advancement of semiconductor technology, digital chips are becoming increasingly integrated. However, this increased integration leads to a sharp increase in chip power consumption, which in turn impacts chip performance, such as packaging, heat dissipation, and signal integrity. Chip power consumption measurement technology can improve the response speed and accuracy of dynamic threshold voltage and dynamic frequency and voltage modulation technologies, and is crucial for maximizing energy and performance.

[0003] Currently, a common method for measuring chip power consumption is to monitor the number of different performance events occurring in the system using different performance counters on the chip. Using multivariate linear regression, the number of performance events, such as cache misses or branch mispredictions, is then fitted to an empirical model of power consumption. However, the number of performance events is highly correlated with the programs running on the chip. Different combinations of programs running on the chip will result in different fitted empirical power consumption models, resulting in low accuracy in chip power consumption obtained using this method. Therefore, obtaining accurate chip power consumption has become an urgent issue. Summary of the Invention

[0004] The present application provides a chip power consumption acquisition method, circuit, device and equipment for obtaining accurate chip power consumption.

[0005] In a first aspect, an embodiment of the present application provides a method for obtaining chip power consumption, comprising:

[0006] At the end of the first period, key characteristic information of the chip to be tested is obtained;

[0007] Using the key feature information of the chip under test as input of a power consumption model, and obtaining the total power consumption of the chip under test in a first time period output by the power consumption model;

[0008] Among them, the power consumption model is a model pre-established by training a regression model with the key feature information and total power consumption of the simulation system obtained by simulating the chip to be tested as input and output respectively; the key feature information of the simulation system is determined based on the predetermined feature information of the simulation system, and the predetermined feature information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods, and the operating voltage of the chip to be tested at the end of different time periods.

[0009] Furthermore, before taking the key feature information of the chip under test as the input of the power consumption model and obtaining the total power consumption of the chip under test in the first time period output by the power consumption model, the method further includes:

[0010] Simulating the chip to be tested to obtain the simulation system;

[0011] Performing power consumption analysis on the simulation system to obtain predetermined characteristic information and total power consumption of the simulation system, wherein the predetermined characteristic information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip under test at the end of different time periods, the substrate bias voltage of the chip under test at the end of different time periods, and the operating voltage of the chip under test at the end of different time periods;

[0012] Determining key characteristic information of the simulation system based on predetermined characteristic information of the simulation system;

[0013] The key feature information and total power consumption of the simulation system are used as input and output respectively, and the power consumption model is established through regression model training.

[0014] Furthermore, based on the predetermined characteristic information of the simulation system, key characteristic information of the simulation system is determined, including:

[0015] The key feature information of the simulation system is information determined by performing elastic network regression model training on predetermined feature information of the simulation system; or

[0016] The key characteristic information of the simulation system is predetermined characteristic information of the simulation system.

[0017] Furthermore, the key feature information of the simulation system is information determined by performing elastic network regression model training on predetermined feature information of the simulation system, including:

[0018] Determining key feature information of the simulation system by training an elastic network regression model with a first-order norm penalty in combination with predetermined feature information of the simulation system;

[0019] The key feature information is feature information in which the coefficient corresponding to the first-order norm penalty in the predetermined feature information does not converge to 0.

[0020] Furthermore, the key characteristic information of the simulation system is information determined by training an elastic network regression model on predetermined characteristic information of the simulation system; the key characteristic information of the chip under test includes the number of flips of the key trigger within the first time period, the temperature of the chip under test at the end of the first time period, the substrate bias voltage of the chip under test at the end of the first time period, and the operating voltage of the chip under test at the end of the first time period; the key characteristic information of the simulation system and the total power consumption obtained by simulating the chip under test are used as input and output respectively, and the power consumption model is pre-established through regression model training, and includes:

[0021]

[0022] Among them, P total is the total power consumption of the chip under test, V dd is the operating voltage of the chip under test at the end of the first period, V bb is the substrate bias voltage of the chip under test at the end of the first period, T is the temperature of the chip under test at the end of the first period; n represents different key triggers, Tr n is the number of flip-flops of the nth key trigger in the first period, N gates is the number of key triggers; d is the number of preset impact factors, ω l，m 、ω n and ω i，j，k are the coefficients of the power consumption model, and i, j, k and l, m are variables with values ​​ranging from 0 to d.

[0023] Furthermore, after establishing the power consumption model by using the key feature information and the total power consumption of the simulation system as input and output respectively and training the power consumption model through a regression model, the method further includes:

[0024] Obtaining key feature information and total power consumption of the chip under test by measurement;

[0025] The key feature information and total power consumption of the chip under test obtained by measurement are used as input and output respectively, and the coefficients of the power consumption model are corrected through regression model training.

[0026] In a second aspect, an embodiment of the present application provides a chip power consumption acquisition circuit, which is integrated in the chip to be tested and is used to implement the calculation of the power consumption model as described in the first aspect, including: a monitoring unit, a weight storage unit, a control unit, a data selector, and a calculation unit;

[0027] The output ends of the monitoring unit, the weight storage unit and the calculation unit are all connected to the input end of the data selector, the output end of the data selector is connected to the input end of the calculation unit; the data selector is connected to the control unit;

[0028] The monitoring unit is used to obtain key feature information of the chip under test at the end of the first time period; the weight storage unit is used to store the coefficients of the power consumption model; the control unit is used to control the data selector to select the corresponding key feature information and / or the intermediate calculation results output by the calculation unit at different stages and output them to the calculation unit for calculation to complete the operation of the power consumption model and obtain the total power consumption of the chip under test in the first time period; the calculation unit outputs the total power consumption of the chip under test in the first time period.

[0029] Furthermore, in the circuit described above, the calculation unit includes a multiplier, an accumulator, and a first register;

[0030] The input end of the multiplier is connected to the output end of the data selector, and is used to perform multiplication calculation on the key feature information and / or the intermediate calculation result output by the data selector, and output the multiplication calculation result;

[0031] The input end of the accumulator is connected to the output end of the multiplier, and is used to perform cumulative sum calculation on the multiplication calculation results output by the multiplier, and output the intermediate calculation results at a predetermined time sequence;

[0032] The input end of the first register is connected to the output end of the accumulator, and the output end of the first register is connected to the input end of the data selector, and is used to store the intermediate calculation result output by the accumulator.

[0033] Furthermore, in the circuit described above, the monitoring unit includes: an XOR gate, a timing unit, a counter, and a second register;

[0034] The XOR gate corresponds to the trigger in the key feature information one by one, the first input end of the XOR gate is connected to the input end of the corresponding trigger, and the second input end of the XOR gate is connected to the output end of the corresponding trigger;

[0035] The counter corresponds to the XOR gate in one-to-one correspondence, and the monitoring unit includes: an XOR gate, a timing unit, a counter and a second register;

[0036] The XOR gate corresponds to the trigger in the key feature information one by one, the first input end of the XOR gate is connected to the input end of the corresponding trigger, and the second input end of the XOR gate is connected to the output end of the corresponding trigger;

[0037] The counters correspond to the XOR gates one by one, the input terminals of the counters are connected to the output terminals of the corresponding XOR gates, the reset terminals of all the counters are connected to the timing unit, and the output terminals of the counters are connected to the second register;

[0038] When the trigger does not flip, the XOR gate corresponding to the trigger outputs a first signal; when the trigger flips, the XOR gate corresponding to the trigger outputs a second signal; the timing unit is used to set a monitoring period and send a reset signal to the counter at the end of the first time period corresponding to the monitoring period; the counter is used to accumulate the number of times the second signal is output by the corresponding XOR gate within the first time period corresponding to the monitoring period, and output the current accumulated calculation result to the second register and clear it to zero according to the received reset signal; the second register is used to store the accumulated calculation result output by the counter.

[0039] In a third aspect, an embodiment of the present application provides a device for obtaining chip power consumption, including:

[0040] An acquisition module, configured to acquire key feature information of the chip to be tested at the end of the first period;

[0041] a processing module, configured to use the key feature information of the chip under test as input to the power consumption model, and obtain the total power consumption of the chip under test in the first time period output by the power consumption model;

[0042] Among them, the power consumption model is pre-established through regression model training, taking the key feature information and total power consumption of the simulation system obtained by simulating the chip to be tested as input and output respectively; the key feature information of the simulation system is determined based on the predetermined feature information of the simulation system, and the predetermined feature information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods, and the operating voltage of the chip to be tested at the end of different time periods.

[0043] In a fourth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0044] Memory: a memory for storing instructions executable by the processor;

[0045] The processor is configured to call program instructions in the memory to execute the chip power consumption acquisition method as described in the first aspect.

[0046] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the chip power consumption acquisition method as described in the first aspect.

[0047] In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the chip power consumption acquisition method as described in the first aspect.

[0048] The present application provides a chip power consumption acquisition method, circuit, device, and apparatus. By acquiring key feature information of a chip under test at the end of a first time period, and using this key feature information as input to a power consumption model, the power consumption model outputs the total power consumption of the chip under test during the first time period. The power consumption model is trained based on the number of flip-flops of all triggers in the simulation system of the chip under test during different time periods, as well as the temperature of the chip under test at the end of different time periods, the substrate bias voltage of the chip under test at the end of different time periods, and the operating voltage of the chip under test at the end of different time periods. Compared to the prior art method of fitting an empirical model of performance event count and power consumption by monitoring the number of different performance events occurring in the system, the accuracy of the fitted power consumption model is also affected because the number of performance events is largely affected by the chip's running program. In the present application, the trigger is the underlying structure of the chip and has a low correlation with the chip's running program, thereby effectively reducing the impact of different chip running programs on the power consumption model establishment, making the power consumption model highly versatile and portable. In addition, the present application fully considers the impact of the temperature, substrate bias voltage, and operating voltage of the chip under test on the total power consumption of the chip under test, further improving the accuracy of the power consumption calculation results.

[0049] It should be understood that the contents described in the above summary of the invention are not intended to limit the key or important features of the embodiments of the present application, nor are they intended to limit the scope of the present application. Other features of the present application will become easier to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application.

[0051] Figure 1 A schematic diagram of a chip power consumption acquisition device provided in this application;

[0052] Figure 2 This is a flowchart of the chip power consumption acquisition method provided in Example 1 of the present application;

[0053] Figure 3a This is a flowchart of the chip power consumption acquisition method provided in Example 3 of the present application;

[0054] Figure 3b An example flow chart of power consumption model training provided in this application;

[0055] Figure 4 A power consumption measurement flow chart provided for this application;

[0056] Figure 5aA schematic diagram of the chip power consumption acquisition circuit provided in this application;

[0057] Figure 5b A circuit diagram of the monitoring unit provided in this application;

[0058] Figure 6 This is a schematic diagram of the structure of a chip power consumption acquisition device provided by this application;

[0059] Figure 7 This is a schematic diagram of the structure of another chip power consumption acquisition device provided by this application;

[0060] Figure 8 This is a schematic diagram of the structure of an electronic device provided in this application. DETAILED DESCRIPTION

[0061] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of protection of the present application.

[0062] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] With the advancement of semiconductor technology and the increase in circuit integration, chip power consumption has increased dramatically, impacting chip performance. Therefore, to maximize energy and performance, accurate chip power consumption must be obtained. Currently, chip power consumption is typically determined using empirical models that correlate performance event counts with power consumption. Figure 1 This is a schematic diagram of a chip power consumption acquisition device provided by this application. Figure 1 As shown, after establishing a model about the number of performance events and power consumption, the number of performance events of the chip to be tested is input into the empirical model to obtain the power consumption output by the power consumption model.

[0064] In response to the above problems, the present application provides a chip power consumption acquisition method, circuit, device and apparatus to solve the above problems. The solution of the present application is illustrated below with reference to the following embodiments.

[0065] Figure 2 This is a flowchart of the chip power consumption acquisition method provided in Example 1 of this application, such as Figure 2 As shown, the chip power consumption acquisition method provided in this embodiment includes the following steps:

[0066] Step 101: At the end of the first period, obtain key feature information of the chip to be tested.

[0067] Step 102: Use the key characteristic information of the chip under test as input of the power consumption model to obtain the total power consumption of the chip under test in the first time period output by the power consumption model.

[0068] Among them, the power consumption model is pre-established through regression model training, with the key characteristic information and total power consumption of the simulation system obtained by simulating the chip to be tested as input and output respectively; the key characteristic information of the simulation system is determined based on the predetermined characteristic information of the simulation system, and the predetermined characteristic information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods, and the operating voltage of the chip to be tested at the end of different time periods.

[0069] It should be noted that the chip power consumption acquisition method provided in this embodiment may be implemented by a chip power consumption acquisition device. In practical applications, the chip power consumption acquisition device may be implemented through a computer program, such as application software, a computer program, or a medium storing a relevant computer program, such as a USB flash drive or a CD; or through a hardware device integrated into the chip, such as a circuit.

[0070] In this embodiment, in order to obtain the total power consumption of the chip under test in the first time period, the chip power consumption acquisition device can obtain the key feature information of the chip under test at the end of the first time period, and use the key feature information as the input of the power consumption model. The power consumption model outputs the total power consumption of the chip under test in the first time period.

[0071] In actual application, the start time of the first period can be triggered by the user or a pre-calibrated time. Among them, the first period can be a preset sampling duration. In combination with the scenario example, when the user expects to obtain the total power consumption of the chip under test within a period of time, the solution of the present application can be triggered to execute, and the corresponding starting point of the first period can be determined by the user. In addition, the first period can also be a single cycle in the preset sampling period. In combination with the scenario example, assuming that the total power consumption of the chip under test is obtained regularly, for example, the chip power consumption is obtained every 10 nanoseconds, then the first period can be a single cycle therein, that is, 10 nanoseconds.

[0072] In addition, the power consumption model is pre-established through regression model training by taking the key characteristic information and total power consumption of the simulation system obtained by simulating the chip to be tested as input and output respectively. The key characteristic information of the simulation system is determined based on the predetermined characteristic information of the simulation system. The predetermined characteristic information takes into account the influence of process, voltage and temperature on the power consumption model, including but not limited to the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods and the operating voltage of the chip to be tested at the end of different time periods. The number of flip-flops of the trigger is the sum of the number of flip-flops of the trigger in a certain time period. The trigger mentioned here refers to the trigger included in the circuit structure of the chip to be tested. The flip of the trigger refers to the difference between the two state values ​​of the input signal of the trigger before and after, for example, the input of the trigger changes from "1" to "0" or from "0" to "1".

[0073] Specifically, there is no limit to the method of obtaining the above parameters. For example, the temperature can be obtained by collecting through a temperature sensor, and the operating voltage can be obtained by sampling through a measurement circuit. This solution does not limit the method of obtaining each parameter.

[0074] The chip power consumption acquisition method provided in this embodiment obtains key feature information of the chip under test at the end of the first period, and uses the key feature information of the chip under test as the input of the power consumption model to obtain the total power consumption of the chip under test in the first period as output by the power consumption model. The power consumption model is trained based on the number of flip-flops of all triggers in the simulation system of the chip under test in different periods, as well as the temperature of the chip under test at the end of different periods, the substrate bias voltage of the chip under test at the end of different periods, and the operating voltage of the chip under test at the end of different periods. Compared with fitting the empirical model of performance event number and power consumption by monitoring the number of different performance events occurring in the system, the accuracy of the fitted power consumption model is also affected because the number of performance events is largely affected by the operating program of the chip. In this application, the trigger is the underlying structure of the chip and has a low correlation with the operating program of the chip, thereby effectively reducing the impact of different chip operating programs on the establishment of the power consumption model, making the power consumption model highly versatile and portable. In addition, this application fully considers the impact of the temperature, substrate bias voltage, and operating voltage of the chip under test on the total power consumption of the chip under test, further improving the accuracy of the power consumption calculation results.

[0075] A second embodiment of the present application provides a chip power consumption acquisition method for determining key characteristic information. Based on the first embodiment, the key characteristic information of the simulation system may be determined in one of the following ways based on predetermined characteristic information of the simulation system:

[0076] In the first manner, the key characteristic information of the simulation system is the predetermined characteristic information of the simulation system, that is, the predetermined characteristic information is not preprocessed.

[0077] Specifically, the key characteristic information of the simulation system is the predetermined characteristic information of the simulation system; accordingly, the key characteristic information of the chip under test includes the number of flip-flops of all triggers in the first time period, as well as the temperature of the chip under test at the end of the first time period, the substrate bias voltage of the chip under test, and the operating voltage of the chip under test. In other words, a power consumption model is established based on the predetermined characteristic information of the simulation system. This predetermined characteristic information includes the number of flip-flops of all triggers in different time periods, as well as the temperature of the chip under test at the end of different time periods, the substrate bias voltage of the chip under test at the end of different time periods, and the operating voltage of the chip under test at the end of different time periods. After the power consumption model is established, when it is necessary to obtain the total power consumption of the chip under test, the key characteristic information of the chip under test is first obtained, including the number of flip-flops of all triggers in the first time period, as well as the temperature of the chip under test at the end of the first time period, the substrate bias voltage of the chip under test, and the operating voltage of the chip under test. Then, this key characteristic information is input into the power consumption model to obtain the output result of the power consumption model, which is the total power consumption of the chip under test in the first time period.

[0078] This method establishes a power consumption model based on predetermined characteristic information of the simulation system. The power consumption model takes into account the impact of the number of flip-flops of all triggers, the temperature of the chip to be tested, the substrate bias voltage of the chip to be tested, and the operating voltage of the chip to be tested on the total power consumption of the chip to be tested, so that the total power consumption of the chip to be tested obtained in actual application is more accurate.

[0079] The second method is to pre-process the predetermined feature information to reduce the amount of data.

[0080] In practical applications, the circuit structure of the chip to be tested is often very complex, and the number of triggers is also very large. Therefore, in order to collect the flip counts of all triggers, a large number of monitoring modules need to be set up, and a huge amount of data is faced. In this regard, in order to further reduce the calculation data and increase the speed of power consumption acquisition, based on the above-mentioned embodiment one, the key feature information of the simulation system is information determined by training the elastic network regression model on the predetermined feature information of the simulation system; the key feature information of the chip to be tested includes the flip count of the key trigger in the first time period, and the temperature of the chip to be tested at the end of the first time period, the substrate bias voltage of the chip to be tested, and the operating voltage of the chip to be tested, wherein the key trigger is a part of the triggers screened from all triggers based on the elastic network regression model, and the amount of data contained in the power consumption model obtained by using the flip counts of these key triggers is less than the amount of data contained in the power consumption model obtained by using the flip counts of all triggers.

[0081] Specifically, when building the model, an Elastic Net regression model is used to filter predetermined feature information and identify key feature information for training the power consumption model. This reduces the amount of data while ensuring accuracy, simplifies the power consumption model, and speeds up power consumption acquisition. Specifically, the first-order norm penalty term in the Elastic Net regression algorithm causes the coefficients of most terms to converge to 0, thus achieving feature selection. Accordingly, this embodiment utilizes the Elastic Net regression algorithm to filter predetermined feature information and identify key feature information, thereby reducing the amount of data.

[0082] In one example, based on the above screening scheme, the key feature information of the chip to be tested includes the number of flip-flops of the key trigger in the first period, the temperature of the chip to be tested at the end of the first period, the substrate bias voltage of the chip to be tested, and the operating voltage of the chip to be tested; the key feature information and the total power consumption of the simulation system obtained by simulating the chip to be tested are used as input and output respectively, and the power consumption model pre-established by regression model training includes

[0083]

[0084] Among them, P total is the total power consumption of the chip under test, V ddis the operating voltage of the chip under test at the end of the first period, V bb is the substrate bias voltage of the chip under test at the end of the first period, T is the temperature of the chip under test at the end of the first period; n represents different key triggers, Tr n N is the number of flip-flops of the nth key trigger in the first period, gates is the number of key triggers; d is the number of preset impact factors, ω l，m 、ω n and ω i，j，k are the coefficients of the power consumption model, i, j, k and l, m are all variables with a value range of 0 to d. For the number of flip-flops of the key triggers in the first period mentioned above, for example, if there are 20 flip-flops in total, and 15 key flip-flops are obtained after screening by the elastic network regression algorithm, then N gates The value of is 14, and the value range of n is from 0 to 14. Then Tr0 represents the number of flips of the first key trigger in the first period, Tr1 represents the number of flips of the second key trigger in the first period, and so on until n reaches 14.

[0085] In this method, the key characteristic information of the simulation system can be determined by training an elastic network regression model on the predetermined characteristic information of the simulation system. Specifically, the elastic network regression model can screen the predetermined characteristic information based on the degree of correlation between each feature in the predetermined characteristic information and the total power consumption of the chip under test. Through screening, key characteristic information with a high degree of correlation with the total power consumption of the chip under test can be obtained, including the number of flips of the key trigger in different time periods, the temperature of the chip under test at the end of different time periods, the substrate bias voltage of the chip under test at the end of different time periods, and the operating voltage of the chip under test at the end of different time periods. Among them, the key trigger is a trigger determined by screening, and its correlation with the total power consumption of the chip under test is relatively high.

[0086] In actual application, when it is necessary to obtain the total power consumption of the chip to be tested, the key characteristic information of the chip to be tested is first obtained, including the number of flips of the key trigger in the first time period, and the temperature of the chip to be tested at the end of the first time period, the substrate bias voltage of the chip to be tested and the operating voltage of the chip to be tested. Then, these key characteristic information are input into the power consumption model to obtain the result output by the power consumption model, which is the total power consumption of the chip to be tested in the first time period.

[0087] The chip power consumption acquisition method provided by this method determines the key characteristic information of the simulation system by training an elastic network regression model on the predetermined characteristic information of the simulation system, thereby obtaining key characteristic information with a high degree of correlation with the total power consumption of the chip to be tested, making the characteristic information required to be obtained in actual application more streamlined and improving the speed of obtaining the total power consumption of the chip to be tested.

[0088] Figure 3aThis is a flowchart of the chip power consumption acquisition method provided in Example 3 of this application, such as Figure 3a As shown, the chip power consumption acquisition method provided in this embodiment is used to establish a power consumption model. Based on any implementation manner, before step 102, the following steps are further included:

[0089] Step 201: Simulate the chip to be tested to obtain a simulation system.

[0090] Step 202: Perform power consumption analysis on the simulation system to obtain predetermined characteristic information and total power consumption of the simulation system. The predetermined characteristic information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods, and the operating voltage of the chip to be tested at the end of different time periods.

[0091] Step 203: Determine key characteristic information of the simulation system based on predetermined characteristic information of the simulation system.

[0092] Step 204 : Using the key feature information and total power consumption of the simulation system as input and output respectively, a power consumption model is established through regression model training.

[0093] In this embodiment, to establish a power consumption model, the chip power consumption acquisition device may first simulate the chip under test based on its structure and function to obtain a simulation system. Next, the chip power consumption acquisition device may perform power consumption analysis on the simulation system to obtain predetermined characteristic information and total power consumption of the simulation system. The predetermined characteristic information includes at least the number of flip-flops of all triggers within different time periods, the temperature of the chip under test at the end of each time period, the substrate bias voltage of the chip under test at the end of each time period, and the operating voltage of the chip under test at the end of each time period.

[0094] Next, in one embodiment, the chip power consumption acquisition device may perform elastic net regression model training on predetermined feature information of the simulation system to determine key feature information of the simulation system. Specifically, step 203 includes: determining the key feature information of the simulation system by training the elastic net regression model in combination with a first-order norm penalty on the predetermined feature information of the simulation system; wherein the key feature information is feature information in the predetermined feature information for which the coefficient corresponding to the first-order norm penalty has not converged to 0.

[0095] The elastic net regression model is based on the elastic net regression algorithm, which includes a first-order norm penalty term. This first-order norm penalty term is used to cause the coefficients of predetermined feature information with a low correlation with the total power consumption of the chip under test to converge to zero. Accordingly, the key feature information is the predetermined feature information for which the coefficients corresponding to the first-order norm penalty have not converged to zero, i.e., the feature information with a high correlation with the total power consumption of the chip under test.

[0096] For example, the example process of power consumption model training is as follows: Figure 3b As shown: After the chip system is started, the chip to be tested is simulated and the power consumption analysis is performed to obtain the simulation results of the simulation system and the power consumption of the chip to be tested, wherein the format of the simulation results can be a VCD file format, and the power consumption here includes dynamic power consumption and static power consumption. The switching activity information of all triggers in the simulation system in different time periods is used as the x variable and the corresponding dynamic power consumption is used as the y variable to train the Elastic Net (elastic network) regression model, that is, dynamic feature extraction, and the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested and the working voltage of the chip to be tested are used as the x variable and the corresponding static power consumption is used as the y variable to train the Elastic Net regression model, that is, static feature extraction, to screen out key triggers and key polynomials, that is, key feature information. The extracted key feature information is then used with the total power consumption of the system for regression model training to obtain the power consumption factor coefficient, thereby establishing a power consumption model.

[0097] The chip power consumption acquisition method provided in this embodiment selects training data based on the elastic network regression model before training the model, thereby reducing the amount of data, simplifying the model, and improving the calculation speed. The relevant solutions and effects can also be found in the relevant content of the aforementioned embodiment 2.

[0098] In another embodiment, Figure 4 This application provides a power consumption measurement flow chart. In order to further improve the accuracy of chip power consumption acquisition, Figure 3a After step 204, the method further includes: step 205, obtaining key feature information and total power consumption of the chip under test through measurement. Step 206, using the key feature information and total power consumption of the chip under test obtained through measurement as input and output, respectively, to correct the coefficients of the power consumption model through regression model training.

[0099] Specifically, in order to eliminate the impact of process deviation on the accuracy of the power consumption model and thus make the power consumption model more accurate, after the power consumption model is established, before the power consumption model is actually applied to obtain the total power consumption of the chip under test, the key feature information and total power consumption of the chip under test can be obtained through measurement, and the key feature information and total power consumption of the chip under test obtained by measurement are used as input and output respectively, and the coefficients of the power consumption model are corrected through regression model training. Subsequently, when the real-time power consumption of the chip needs to be obtained, the accurate power consumption can be output based on the collected data and the power consumption model, that is, Figure 4 The process shown, Figure 4 This is a power consumption measurement flow chart provided by the present application, wherein the power consumption calculation process is the calculation solution based on the power consumption model provided by the present application.

[0100] The chip power consumption acquisition method provided in this embodiment uses the actual power consumption measurement value to retrain the power consumption model, so that the coefficients of the power consumption model can be corrected, thereby eliminating the impact of process deviation on the accuracy of the power consumption model and further improving the accuracy of the power consumption model.

[0101] The chip power consumption acquisition method provided in this embodiment simulates the chip to be tested to obtain a simulation system, performs elastic network regression model training on predetermined characteristic information of the simulation system to determine key characteristic information of the simulation system, takes the key characteristic information and total power consumption of the simulation system as input and output respectively, and establishes a power consumption model through regression model training, so that the power consumption model can be established based on key characteristic information with a high degree of correlation with the total power consumption of the chip to be tested. Compared with the power consumption model established by using characteristic information such as the number of flip flops of at least all triggers, the power consumption model established in this embodiment uses characteristic information such as the number of flip flops of key triggers with a greater degree of correlation to establish the power consumption model, thereby making the power consumption model more streamlined and improving the response speed of the power consumption model.

[0102] Figure 5a The schematic diagram of the chip power consumption acquisition circuit provided in this application is as follows: Figure 5a As shown, the chip power consumption acquisition circuit is integrated in the chip to be tested, and is used to implement the calculation of the power consumption model in any of the above embodiments, including: a monitoring unit 31, a weight storage unit 32, a control unit 33, a data selector 34 and a calculation unit 35.

[0103] Among them, the output ends of the monitoring unit 31, the weight storage unit 32 and the calculation unit 35 are all connected to the input end of the data selector 34, the output end of the data selector 34 is connected to the input end of the calculation unit 35, and the control end of the data selector 34 is connected to the control unit 33.

[0104] The number of data selectors can be determined based on the number of input ports of the data selector and the number of input data involved in the multiplication calculation. The input data mentioned here includes but is not limited to: key feature information, intermediate calculation results (for example: calculation results returned by the multiplier and register), and power consumption model coefficients. As an example, the number of data selectors can be two, which are used to receive static data (such as power consumption model coefficients) and dynamic data (such as key feature information of the chip to be tested). Figure 5aAs shown in FIG, a data input terminal of a data selector 34 is connected to the monitoring unit 31 for receiving the key characteristic information of the chip under test sent by the monitoring unit 31, while a data input terminal of another data selector 34 is connected to the weight storage unit 32 for receiving the coefficients of the power consumption model stored in the weight storage unit 32. The monitoring unit 31 is configured to obtain the key characteristic information of the chip under test at the end of the first time period. The specific acquisition method is described in the embodiment described below and is not repeated in this embodiment.

[0105] The weight storage unit 32 is used to store the coefficients of the power consumption model. The control unit 33 is used to control the data selector 34 to select the corresponding key feature information and / or the intermediate calculation results output by the calculation unit 35 at different timings and output them to the calculation unit 35 for calculation, so as to complete the operation of the power consumption model and obtain the total power consumption of the chip under test in the first time period. Exemplarily, the control unit 33 can be implemented by a state machine circuit. The state machine is composed of a state register and a combinational logic circuit. It can perform a state transfer cycle according to a pre-set state according to a control signal. The operation or output of each state is different, corresponding to a different combinational logic circuit. When the control unit 33 completes a state cycle, it completes the operation corresponding to the power consumption model. Finally, the calculation unit 33 outputs the total power consumption of the chip under test in the first time period.

[0106] In combination with the scenario example, when it is necessary to obtain the power consumption of the chip, an instruction can be issued to the control unit 33. The control unit 33 instructs the monitoring unit 31 to obtain the key feature information of the chip to be tested and send it to the data selector 34 according to the received instruction, and instructs the weight storage unit 32 to send the coefficients of the power consumption model to the data selector 34. It should be noted that the power consumption acquisition circuit provided in this embodiment is used to implement the relevant calculations of the power consumption model. In actual applications, the calculation of the power consumption model can be decomposed into calculation tasks according to different cumulative calculation granularities (such as multiplication calculation, addition calculation, accumulation calculation, etc.), and the relevant execution logic is compiled and stored in the control unit 33. That is to say, different data is used to perform corresponding calculation tasks in different states, and finally the calculation corresponding to the power consumption model is realized, such as the calculation formula in Example 2. Correspondingly, the control unit 33 also controls the data selector 34 to transmit the parameters required for this calculation task to the calculation unit 35 according to the current calculation task. After the calculation unit 35 completes the calculation task this time, the control unit 33 repeats the above similar process until all calculation tasks are completed, thereby realizing the calculation corresponding to the power consumption model.

[0107] It should be noted that each circuit unit in the power consumption acquisition circuit can be implemented by a variety of circuit structures, that is, any circuit structure that can support the functions required by each circuit unit itself. The following examples illustrate the structure of each circuit unit in conjunction with the embodiments:

[0108] In one embodiment, the calculation unit 35 may include a multiplier 36, an accumulator 37, and a first register 38. The input of the multiplier 36 is connected to the output of the data selector 34, and is configured to perform a multiplication calculation on the key feature information and / or intermediate calculation results output by the data selector 34, and output the multiplication result. The input of the accumulator 37 is connected to the output of the multiplier 36, and is configured to accumulate and sum the multiplication results output by the multiplier 36, and output the intermediate calculation results at a predetermined timing. The input of the first register 38 is connected to the output of the accumulator 37, and the output of the first register 38 is connected to the input of the data selector 34, and is configured to store the intermediate calculation results output by the accumulator 37. This embodiment implements the calculation of the power consumption model using a conventional calculation unit, thereby reducing the complexity and area of ​​the circuit structure and saving costs.

[0109] In another embodiment, Figure 5b As shown, Figure 5bSchematic diagram of a circuit of a monitoring unit, wherein the monitoring unit 31 includes: an XOR gate 51, a timing unit 52, a counter 53, and a second register 54; the XOR gate 51 corresponds one-to-one to the trigger in the key feature information (i.e., one trigger corresponds to one XOR gate 51, and one XOR gate 51 corresponds to one trigger), the first input of the XOR gate 51 is connected to the input of the corresponding trigger, and the second input of the XOR gate 51 is connected to the output of the corresponding trigger; the counter 53 corresponds one-to-one to the XOR gate 51 (i.e., one counter 53 corresponds to one XOR gate 51, and one XOR gate 51 corresponds to one counter 53), the input of the counter 53 is connected to the output of the corresponding XOR gate 51, the reset terminals of all counters 53 are connected to the timing unit 52, and the output of the counter 53 is connected to the second register 54; when the trigger does not flip, the XOR gate 51 corresponding to the trigger outputs a first signal, wherein the first signal indicates that the signal output by the XOR gate 51 at a certain moment in the first time period is different from the signal output by the XOR gate 51 at the previous moment. The signal state value of is the same, that is, the trigger has not flipped, and accordingly, the counting result of the counter 53 used to record the cumulative number of the second signal will not change at this time; when the trigger flips, the XOR gate 51 corresponding to the trigger outputs a second signal, wherein the second signal indicates that the signal output by the XOR gate 51 at a certain moment in the first time period is different from the signal state value output by the XOR gate 51 at the previous moment, that is, the trigger flips, and accordingly, the result of the counter 53 used to record the cumulative number of the second signal is increased by 1, thereby realizing the monitoring and recording of the cumulative number of flips of the trigger; the timing unit 52 is used to set the monitoring period and send a reset signal to the counter 53 at the end of the first time period corresponding to the monitoring period; the counter 53 is used to accumulate and calculate the number of second signals output by the corresponding XOR gate 51 in the first time period corresponding to the monitoring period, and output the current accumulated calculation result to the second register 54 and clear it to zero according to the received reset signal; the second register 54 is used to store the accumulated calculation result output by the counter.

[0110] For example, the working principle of the monitoring circuit is as follows: the XOR logic unit is used to determine whether the input signal of the trigger is flipped. If flipped, the XOR gate generates a "0-1" jump, causing the counter to count "1". The circuit implementation form of the timing unit is not limited. For example, it can be implemented by a counter circuit. Assuming that the counter is an M-bit counter, the sampling period is 2 M After each sampling period, the timing unit sends a reset signal to instruct the counter to restart counting and write the previous count result into the second register. This embodiment uses conventional circuit units to obtain key feature information, thereby reducing the complexity and area of ​​the circuit structure and saving costs.

[0111] It should be noted that the above embodiments can be implemented separately or in combination. The chip power consumption acquisition circuit provided in this embodiment implements the calculation of the power consumption model through hardware circuits, avoiding occupying the computing resources and running time of the processor and saving performance overhead.

[0112] Figure 6 This is a schematic diagram of the structure of a chip power consumption acquisition device provided by this application, such as Figure 6 As shown, the device includes:

[0113] An acquisition module 61 is configured to acquire key feature information of the chip under test at the end of the first period;

[0114] A processing module 62 is configured to use key characteristic information of the chip under test as input to a power consumption model, and obtain the total power consumption of the chip under test in a first time period output by the power consumption model;

[0115] Among them, the power consumption model is pre-established through regression model training, with the key characteristic information and total power consumption of the simulation system obtained by simulating the chip to be tested as input and output respectively; the key characteristic information of the simulation system is determined based on the predetermined characteristic information of the simulation system, and the predetermined characteristic information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods, and the operating voltage of the chip to be tested at the end of different time periods.

[0116] The device provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principle and technical effects are similar and will not be described in detail.

[0117] Figure 7 This is a schematic diagram of the structure of another chip power consumption acquisition device provided by this application. Figure 6 Based on the device shown, the device also includes:

[0118] The simulation module 63 is used to simulate the chip under test before the processing module 62 uses the key feature information of the chip under test as the input of the power consumption model to obtain the total power consumption of the chip under test in the first period output by the power consumption model to obtain a simulation system.

[0119] The analysis module 64 is configured to perform power consumption analysis on the simulation system to obtain predetermined characteristic information and total power consumption of the simulation system.

[0120] The determination module 65 is configured to determine key characteristic information of the simulation system based on predetermined characteristic information of the simulation system.

[0121] The training module 66 is configured to take the key feature information and the total power consumption of the simulation system as input and output respectively, and establish a power consumption model through regression model training.

[0122] In a possible example, the determining module 65 is specifically configured to: the key feature information of the simulation system is information determined by performing elastic network regression model training on predetermined feature information of the simulation system; or

[0123] The key characteristic information of the simulation system is predetermined characteristic information of the simulation system.

[0124] In a possible example, when the key feature information specifically used for the simulation system is information determined by training an elastic network regression model on predetermined feature information of the simulation system, the determination module 65 also includes a first training submodule 651, which is used to determine the key feature information of the simulation system by training an elastic network regression model combined with a first-order norm penalty on the predetermined feature information of the simulation system; wherein the key feature information is feature information in which the coefficient corresponding to the first-order norm penalty in the predetermined feature information has not converged to 0.

[0125] The key feature information is feature information in which the coefficient corresponding to the first-order norm penalty in the predetermined feature information does not converge to 0.

[0126] In one possible example, the key characteristic information of the simulation system is information determined by training an elastic network regression model on predetermined characteristic information of the simulation system; the key characteristic information of the chip under test includes the number of flip-flops of the key trigger within a first time period, the temperature of the chip under test at the end of the first time period, the substrate bias voltage of the chip under test at the end of the first time period, and the operating voltage of the chip under test at the end of the first time period; the key characteristic information of the simulation system and the total power consumption obtained by simulating the chip under test are used as input and output, respectively, and the power consumption model is pre-established through regression model training, and includes:

[0127]

[0128] Among them, P total is the total power consumption of the chip under test, V dd is the operating voltage of the chip under test at the end of the first period, V bb is the substrate bias voltage of the chip under test at the end of the first period, T is the temperature of the chip under test at the end of the first period; n represents different key triggers, Tr n N is the number of flip-flops of the nth key trigger in the first period, gates is the number of key triggers; d is the number of preset impact factors, ω l，m 、ω n and ω i，j，k are the coefficients of the power consumption model, and i, j, k and l, m are variables with values ​​ranging from 0 to d.

[0129] In a possible example, the device further includes:

[0130] The measurement module 67 is used to take the key feature information and total power consumption of the simulation system as input and output respectively in the training module 66, establish a power consumption model through regression model training, and then obtain the key feature information and total power consumption of the chip to be tested through measurement.

[0131] The correction module 68 is configured to take the key feature information and total power consumption of the chip under test obtained by measurement as input and output respectively, and correct the coefficients of the power consumption model through regression model training.

[0132] The device provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principle and technical effects are similar and will not be described in detail.

[0133] Figure 8 A schematic diagram of the structure of an electronic device provided in this application, such as Figure 8 As shown, the electronic device includes:

[0134] The electronic device includes a processor 291 and a memory 292; a communication interface 293, and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via bus 294. Communication interface 293 can be used for information transmission. The processor 291 can invoke logic instructions in memory 294 to execute the methods of the above embodiments.

[0135] In addition, the logic instructions in the memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0136] Memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. Processor 291 executes the software programs, instructions, and modules stored in memory 292 to perform functional applications and data processing, thereby implementing the methods in the above-mentioned method embodiments.

[0137] Memory 292 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Memory 292 may also include high-speed random access memory and non-volatile memory.

[0138] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method provided in the above embodiment.

[0139] An embodiment of the present application provides a computer program product, including a computer program, which implements the method provided in the above embodiment when executed by a processor.

[0140] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0141] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A chip power consumption acquisition method, characterized in that: include: At the end of the first time period, key characteristic information of the chip under test is obtained; the key characteristic information of the chip under test includes the number of flip-flops of the key trigger in the first time period, the temperature of the chip under test at the end of the first time period, the substrate bias voltage of the chip under test at the end of the first time period, and the operating voltage of the chip under test at the end of the first time period; The key triggers are some triggers screened from all triggers based on the elastic net regression model; Simulating the chip to be tested to obtain a simulation system; Performing power consumption analysis on the simulation system to obtain predetermined characteristic information and total power consumption of the simulation system; By training the elastic network regression model on the predetermined characteristic information of the simulation system, the key characteristic information of the simulation system is determined; The key feature information and total power consumption of the simulation system are used as input and output respectively, and a power consumption model is established through regression model training; Using the key feature information of the chip under test as input of a power consumption model, and obtaining the total power consumption of the chip under test in a first time period output by the power consumption model; The predetermined characteristic information includes at least the flip-flop times of all triggers in different time periods, the temperature of the chip under test at the end of different time periods, the substrate bias voltage of the chip under test at the end of different time periods, and the operating voltage of the chip under test at the end of different time periods.

2. The method according to claim 1, characterized in that By training the elastic network regression model on the predetermined characteristic information of the simulation system, the key characteristic information of the simulation system is determined, including: Determining key feature information of the simulation system by training an elastic network regression model with a first-order norm penalty in combination with predetermined feature information of the simulation system; The key feature information is feature information in which the coefficient corresponding to the first-order norm penalty in the predetermined feature information does not converge to 0.

3. The method according to claim 1, characterized in that The power consumption model includes: Among them, P total is the total power consumption of the chip under test, V dd is the operating voltage of the chip under test at the end of the first period, V bb is the substrate bias voltage of the chip under test at the end of the first period, T is the temperature of the chip under test at the end of the first period; n represents different key triggers, Tr n is the number of flip-flops of the nth key trigger in the first period, N gates is the number of key triggers; d is the number of preset impact factors, ω l,m 、ω n and ω i,j,k are the coefficients of the power consumption model, i, j, k and l, m are variables with values ​​ranging from 0 to d.

4. The method according to claim 1, wherein After the key feature information and total power consumption of the simulation system are used as input and output respectively, and the power consumption model is established through regression model training, the method further includes: Obtaining key feature information and total power consumption of the chip under test by measurement; The key feature information and total power consumption of the chip under test obtained by measurement are used as input and output respectively, and the coefficients of the power consumption model are corrected through regression model training.

5. A chip power consumption acquisition circuit, characterized in that: The chip power consumption acquisition circuit is integrated in the chip to be tested and is used to perform the calculation of the power consumption model according to any one of claims 1 to 4, including: a monitoring unit, a weight storage unit, a control unit, a data selector and a calculation unit; The output ends of the monitoring unit, the weight storage unit and the calculation unit are all connected to the input end of the data selector, the output end of the data selector is connected to the input end of the calculation unit; the data selector is connected to the control unit; The monitoring unit is used to obtain key feature information of the chip under test at the end of the first time period; the weight storage unit is used to store the coefficients of the power consumption model; the control unit is used to control the data selector to select the corresponding key feature information and / or the intermediate calculation results output by the calculation unit at different stages and output them to the calculation unit for calculation to complete the operation of the power consumption model and obtain the total power consumption of the chip under test in the first time period; the calculation unit outputs the total power consumption of the chip under test in the first time period.

6. The circuit according to claim 5, characterized in that The computing unit includes a multiplier, an accumulator and a first register; The input end of the multiplier is connected to the output end of the data selector, and is used to perform multiplication calculation on the key feature information and / or the intermediate calculation result output by the data selector, and output the multiplication calculation result; The input end of the accumulator is connected to the output end of the multiplier, and is used to perform cumulative sum calculation on the multiplication calculation results output by the multiplier, and output the intermediate calculation results at a predetermined time sequence; The input end of the first register is connected to the output end of the accumulator, and the output end of the first register is connected to the input end of the data selector, and is used to store the intermediate calculation result output by the accumulator.

7. The circuit according to claim 5, characterized in that The monitoring unit includes: an XOR gate, a timing unit, a counter and a second register; The XOR gate corresponds to the trigger in the key feature information one by one, the first input end of the XOR gate is connected to the input end of the corresponding trigger, and the second input end of the XOR gate is connected to the output end of the corresponding trigger; The counters correspond to the XOR gates one by one, the input terminals of the counters are connected to the output terminals of the corresponding XOR gates, the reset terminals of all the counters are connected to the timing unit, and the output terminals of the counters are connected to the second register; When the trigger does not flip, the XOR gate corresponding to the trigger outputs a first signal; when the trigger flips, the XOR gate corresponding to the trigger outputs a second signal; the timing unit is used to set a monitoring period and send a reset signal to the counter at the end of the first time period corresponding to the monitoring period; the counter is used to accumulate the number of times the second signal is output by the corresponding XOR gate within the first time period corresponding to the monitoring period, and output the current accumulated calculation result to the second register and clear it to zero according to the received reset signal; the second register is used to store the accumulated calculation result output by the counter.

8. A chip power consumption acquisition device, characterized in that: include: an acquisition module, configured to acquire key characteristic information of the chip under test at the end of the first time period; the key characteristic information of the chip under test including the number of flip-flops of the key trigger within the first time period, the temperature of the chip under test at the end of the first time period, the substrate bias voltage of the chip under test at the end of the first time period, and the operating voltage of the chip under test at the end of the first time period; The key triggers are some triggers screened from all triggers based on the elastic net regression model; A simulation module, used to simulate the chip to be tested to obtain a simulation system; An analysis module, configured to perform power consumption analysis on the simulation system to obtain predetermined characteristic information and total power consumption of the simulation system; A determination module, configured to determine key characteristic information of the simulation system by performing elastic network regression model training on predetermined characteristic information of the simulation system; A training module, configured to take the key feature information and total power consumption of the simulation system as input and output, respectively, and establish a power consumption model through regression model training; a processing module, configured to use the key feature information of the chip under test as an input of a power consumption model, and obtain the total power consumption of the chip under test in a first time period output by the power consumption model; Among them, the power consumption model is pre-established through regression model training, taking the key feature information and total power consumption of the simulation system obtained by simulating the chip to be tested as input and output respectively; the key feature information of the simulation system is determined based on the predetermined feature information of the simulation system, and the predetermined feature information includes at least the number of flip-flops of all triggers in different time periods, the temperature of the chip to be tested at the end of different time periods, the substrate bias voltage of the chip to be tested at the end of different time periods, and the operating voltage of the chip to be tested at the end of different time periods.

9. An electronic device, characterized in that: include: Memory, processor; Memory: a memory for storing instructions executable by the processor; The processor is configured to call program instructions in the memory to execute the chip power consumption acquisition method according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the chip power consumption acquisition method according to any one of claims 1 to 4.

11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the chip power consumption acquisition method according to any one of claims 1 to 4 is implemented.

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