A multi-chip interconnect device, debug system, and debug method

Abstract

This invention provides a multi-chip interconnect device, a debugging system, and a debugging method. The multi-chip interconnect device includes a circuit board on which at least two chips are disposed, and the at least two chips are interconnected via a chip interconnect bus. The at least two chips include a master chip and other slave chips. The master chip has a built-in input / output module, and the interface pins of the input / output module are led out to the circuit board. The master chip and each slave chip can access the input / output module to output their respective debugging information via the interface pins in a time-division multiplexing manner, thereby enabling dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared with the prior art where the input / output modules of each chip are led out to the circuit board, this application eliminates the need to lead out the input / output modules of each chip via interface pins, significantly reducing the number of interface pins and wiring of the input / output modules, and lowering costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multi-chip interconnect device, a debugging system, and a debugging method. Background Technology

[0002] With increasing demands for processor performance, multi-chip interconnect processors are becoming increasingly common. During the production and application of multi-chip interconnect processors, processor debugging is crucial for ensuring performance. Currently, debugging designs for multi-chip interconnect environments typically include an I / O module (input / output module) within each chip, connecting all I / O modules within the multi-chip system to the motherboard via traces and pins. A debugging interface needs to be designed on the motherboard for each chip's I / O module pins. During debugging, debugging information for each chip is obtained through each debugging interface and the corresponding chip's I / O module pins. However, for applications with dozens of interconnected chips, simply bringing all the I / O module pins of all chips to the motherboard and assigning them individual debugging interfaces requires a large number of interface pins and debugging interfaces, resulting in extremely high costs. Summary of the Invention

[0003] This invention provides a multi-chip interconnect device, debugging system, and debugging method, which can dynamically and effectively acquire the debugging information of the execution process of each chip in a multi-chip environment. It eliminates the need to bring out the input and output modules in each chip to the circuit board through interface pins, which can significantly reduce the number of input and output module interface pins and wiring, and greatly reduce costs.

[0004] In a first aspect, the present invention provides a multi-chip interconnect device, comprising a circuit board on which at least two chips are disposed, and the at least two chips are interconnected via a chip interconnect bus. The at least two chips include a master chip and other slave chips. The master chip has a built-in input / output module, and the interface pins of the input / output module are led out to the circuit board. Both the master chip and each slave chip can access the input / output module to output their respective debugging information via the interface pins in a time-division multiplexing manner.

[0005] In the above-described solution, only the input / output modules within the main chip are brought out to the circuit board via interface pins. In a multi-chip environment consisting of at least two chips, each chip can access the input / output modules. Furthermore, multiple chips use a time-division multiplexing approach to output their respective debugging information via interface pins, thereby enabling dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to existing interconnection methods that bring out the input / output modules of each chip to the circuit board via pins, the method in this application eliminates the need for each chip's input / output modules to be brought out via interface pins, significantly reducing the number of input / output module interface pins and wiring, and substantially lowering costs.

[0006] In one specific implementation, the input / output module has a built-in identifier register, which is used to write the logic number of the chip currently holding the right to use the input / output module. Each chip obtains the logic number of the chip currently holding the right to use the input / output module by accessing the identifier register. Each chip also determines whether its own logic number is equal to the logic number of the chip currently holding the right to use the input / output module, and if they are equal, outputs its generated debugging information through an interface pin. This facilitates notification to each chip which chip currently holds the right to use the input / output module.

[0007] In one specific implementation, the main chip is also used to write the target chip logic number that needs to have the right to use the input / output module to the identifier register, so as to facilitate writing the target chip logic number from the chip side to the identifier register and adjusting the allocation of the right to use the input / output module.

[0008] In one specific implementation, the master chip writes the target chip logic number that needs to have the right to use the input / output module to the identifier register according to its internal firmware configuration. This enables the master chip or slave chip to actively modify the chip logic number in the identifier register during the debugging process and output the debugging information generated by each of them during the debugging process.

[0009] In one specific implementation, a debugging interface is also provided on the circuit board. The debugging interface is communicatively connected to the main chip to input the logic number of the target chip for which the user needs access to the input / output modules. The main chip then writes the received target chip logic number into its identifier register. This allows debugging engineers to dynamically adjust the output of debugging information for a specific chip.

[0010] In one specific implementation, the debugging interface is a Universal Asynchronous Receiver / Transmitter Interface (UART interface) or a JTAG interface (Joint Test Action Group, a chip internal test interface), which facilitates interaction with debugging engineers and dynamic adjustment of the chip logic number stored in the identifier register.

[0011] In one specific implementation, the circuit board is also provided with a general-purpose input / output interface. The general-purpose input / output interface is communicatively connected to an identification register to write the target chip logic number that requires the right to use the input / output module into the identification register. This facilitates the output of the target chip logic number to the identification register through different types of interfaces on the circuit board, improving adaptability.

[0012] In one specific implementation, the input / output module also includes a built-in configuration selection register. This register is communicatively connected to the general-purpose input / output interface (GPIO) on the circuit board to receive a first configuration instruction and a second configuration instruction. The first configuration instruction configures the main chip to write the logical number of the chip requiring access to the input / output module to the identifier register. The second configuration instruction configures the GPIO to write the logical number of the target chip requiring access to the input / output module to the identifier register. This mutual exclusion and isolation between the chip-side adjustment operation to the identifier register and the external GPIO input operation to the target chip logical number avoids logical contradictions and confusion.

[0013] In one specific implementation, each chip integrates a control module and a computing unit (CU). The computing unit generates debugging information for its respective chip. The control module, input / output module, and computing unit in the main chip are interconnected via a parallel bus, and the control module and computing unit in each slave chip are also interconnected via a parallel bus. The chip interconnection bus is a serial bus, and the control module in each chip performs protocol conversion from parallel bus to serial bus. This facilitates each chip's access to the input / output module, and time-division multiplexing is used to output each chip's debugging information via interface pins.

[0014] Secondly, the present invention also provides a debugging system, which includes any of the aforementioned multi-chip interconnect devices and a debugging device communicatively connected to interface pins. By only bringing the input / output modules within the main chip to the circuit board via interface pins, in a multi-chip environment consisting of at least two chips, each chip can access the input / output modules. Furthermore, multiple chips use a time-division multiplexing method to output their respective debugging information via interface pins, thereby enabling dynamic and effective acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to the prior art interconnection method where the input / output modules within each chip are brought to the circuit board via pins, the method in this application eliminates the need for bringing the input / output modules within each chip to the circuit board via interface pins, significantly reducing the number of input / output module interface pins and wiring, and substantially lowering costs.

[0015] Thirdly, the present invention also provides a debugging method based on any of the above-mentioned debugging systems, the debugging method comprising: generating debugging information to be output by some or all of at least two chips; each chip accessing an input / output module to output its own debugging information through an interface pin in a time-division multiplexing manner.

[0016] In the above-described solution, only the input / output modules within the main chip are brought out to the circuit board via interface pins. In a multi-chip environment consisting of at least two chips, each chip can access the input / output modules. Furthermore, multiple chips use a time-division multiplexing approach to output their respective debugging information via interface pins, thereby enabling dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to existing interconnection methods that bring out the input / output modules of each chip to the circuit board via pins, the method in this application eliminates the need for each chip's input / output modules to be brought out via interface pins, significantly reducing the number of input / output module interface pins and wiring, and substantially lowering costs.

[0017] In one specific implementation, the input / output module has a built-in identifier register, which is used to write the logical number of the chip currently holding the right to use the input / output module. Each chip accesses the input / output module to output its own debugging information via interface pins in a time-division multiplexing manner. This includes: each chip accessing the identifier register to obtain the logical number of the chip currently holding the right to use the input / output module; each chip determining whether its own logical number is equal to the logical number of the chip currently holding the right to use the input / output module, and if they are equal, outputting its generated debugging information via the interface pins. This facilitates notification to each chip which chip currently holds the right to use the input / output module. Attached Figure Description

[0018] Figure 1 A schematic block diagram of a multi-chip interconnect device provided in an embodiment of the present invention;

[0019] Figure 2 A flowchart illustrating the time-division multiplexing of debugging information output by a master chip and each slave chip, as provided in an embodiment of the present invention;

[0020] Figure 3 A schematic block diagram of another multi-chip interconnect device provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the interconnection between a main chip and external components, provided as an embodiment of the present invention.

[0022] Figure label:

[0023] 10-Circuit Board; 11-Main Chip; 12-Slave Chip; 20-Input / Output Module

[0024] 21-Interface pins; 31-Computing unit; 32-Control module

[0025] 40 - Debugging Interface; 41 - Debugging Module; 50 - General Purpose Input / Output Interface Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] To facilitate understanding of the multi-chip interconnect device provided in the embodiments of the present invention, the application scenarios of the multi-chip interconnect device provided in the embodiments of the present invention will be described first. This multi-chip interconnect device is applied in an interconnection method consisting of multiple chips. The multi-chip interconnect device will then be described in detail below with reference to the accompanying drawings.

[0028] refer to Figure 1 , Figure 2 and Figure 4 The multi-chip interconnect device provided in this embodiment of the invention includes a circuit board 10, on which at least two chips are disposed, and the at least two chips are interconnected via a chip interconnect bus. The at least two chips include a master chip 11 and other slave chips 12. The master chip 11 has a built-in input / output module 20, and the interface pins 21 of the input / output module 20 are led out to the circuit board 10. The master chip 11 and each slave chip 12 can access the input / output module 20 to output their respective debugging information via the interface pins 21 in a time-division multiplexing manner.

[0029] In the above-described scheme, only the input / output modules 20 within the main chip 11 are brought out to the circuit board 10 via interface pins 21. In a multi-chip environment consisting of at least two chips, each chip can access the input / output modules 20, and multiple chips use a time-division multiplexing method to output their respective debugging information via interface pins 21. This allows for dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to the existing interconnection method where the input / output modules 20 within each chip are brought out to the circuit board 10 via pins, the method in this application does not require the input / output modules 20 within each chip to be brought out to the circuit board 10 via interface pins 21, which can significantly reduce the number of interface pins 21 and the wiring of the input / output modules 20, and significantly reduce costs. The above structures will be described in detail below with reference to the accompanying drawings.

[0030] refer to Figure 1 When setting up circuit board 10, circuit board 10 can specifically be a motherboard in a server, or a circuit board composed of traces and vias used in other scenarios. At least two chips are disposed on circuit board 10, and these at least two chips are interconnected via a chip interconnect bus. Each chip can be a single-chip package (SCM), a homogeneous multi-chip package (MCM), or a chip within a homogeneous MCM. Furthermore, each chip can be a heterogeneous multi-chip package (SIP), or a chip within a heterogeneous MCM. That is, each chip in this application can specifically be a package formed by a single or multiple homogeneous or heterogeneous chip packages, or a chip within a package formed by multiple homogeneous or heterogeneous chip packages. This application does not limit whether the chip is specifically a package or a bare die within a package, but rather limits the way multiple chips are connected via a chip interconnect bus. Each of the at least two chips can be a CPU (Central Processing Unit) chip, or a chip type such as, but not limited to, a GPU (Graphics Processing Unit) chip. The chip interconnect bus can be formed within the package to interconnect different dies within the same package; or it can be formed on a package substrate or circuit board 10 outside the package to connect different packages or chips within different packages. Specifically, the chip interconnect bus can be a serial bus. Of course, other types of chip interconnect buses can also be used.

[0031] At least two chips comprise a master chip 11 and other slave chips 12. For example... Figure 1The illustrated multi-chip interconnect device includes a master chip 11 and three slave chips 12, designated as a first slave chip 12, a second slave chip 12, and a third slave chip 12, respectively, with the master chip 11 and the three slave chips 12 interconnected in a ring configuration. It should be understood that the interconnection of at least two chips via a chip interconnect bus is not limited to this configuration. Figure 1 and Figure 3 In addition to the ring interconnection shown, other interconnection methods can also be used. For example, interconnection methods such as, but not limited to, linear and star interconnections can be used to interconnect at least two chips.

[0032] When configuring each chip, refer to Figure 1 Each chip can have a built-in control module 32 and a computing unit 31. The computing unit 31 generates debugging information for its respective chip, specifically by collecting debugging information through a DFx path (a debugging path) built into each chip. The control module 32, input / output module 20, and computing unit 31 in the main chip 11 are interconnected via a parallel bus, such as... Figure 1 As shown, the control module 32 in the main chip 11 is directly connected to the input / output module 20 within the main chip 11 via a parallel bus. The control module 32 in the main chip 11 is also connected to the computing unit 31 within the main chip 11 via a parallel bus, and the computing unit 31 within the main chip 11 is also connected to the input / output module 20 within the main chip 11 via a parallel bus. The control module 32 in each slave chip 12 and the computing unit 31 within the same slave chip 12 can be interconnected via a parallel bus. In one exemplary embodiment, the aforementioned parallel bus can employ the AXI4 bus protocol (a bus protocol). When the chip interconnect bus is a serial bus, the control module 32 in each chip can be used to perform protocol conversion from parallel bus to serial bus, enabling the computing units 31 in other slave chips 12 to directly access the input / output module 20 within the main chip 11 via the interconnect path. This allows each chip to output its own debugging information through the interface pin 21 connected to the input / output module 20, facilitating access to the input / output module 20 by each chip. The debugging information of each chip is output via the interface pin 21 using a time-division multiplexing method.

[0033] refer to Figure 1 The main chip 11 has a built-in input / output module 20, and the interface pins 21 of the input / output module 20 are led out to the circuit board 10. This allows the debug output interface on the circuit board 10, used for outputting debug information, to connect to the interface pins 21 of the input / output module 20, so that the debug information can be transmitted. For example... Figure 1The master chip 11 shown is heterogeneous with the other slave chips 12, and none of the slave chips 12 have input / output modules 20. It should be understood that the master chip 11 and slave chips 12 can also be homogeneous, as shown in the reference... Figure 3 That is, chip 12 also has input / output modules 20, but none of the input / output modules 20 in chip 12 are brought out to the circuit board 10 through interface pin 21, so that none of the input / output modules 20 in chip 12 can be used.

[0034] refer to Figure 1 The main chip 11 and each slave chip 12 can access the input / output module 20. Specifically, they can access the input / output module 20 within the main chip 11 through the chip interconnect bus between different chips, so that each chip can output its own debugging information via interface pin 21 in a time-division multiplexing manner. Figure 1 The multi-chip interconnect structure shown is for reference. The master chip 11 can directly access its local input / output module 20 via path 1 and output debug information from within the master chip 11 through this access path. The first slave chip 12 can access the input / output module 20 within the master chip 11 via path 3 → interconnect path 01 → path 2 and output debug information from within the first slave chip 12 through this access path. The second slave chip 12 can access the input / output module 20 within the master chip 11 via path 4 → interconnect path 12 → interconnect path 01 → path 2 and output debug information from within the second slave chip 12 through this access path. The third slave chip 12 can access the input / output module 20 within the master chip 11 via path 5 → interconnect path 03 → path 2 and output debug information from within the second slave chip 12 through this access path. It should be noted that while the above access paths can be shared, the output of debug information requires time-division multiplexing. The input / output module 20 of the master chip 11 is externally connected to the interface pin 21 on the circuit board 10, allowing each chip to output its own debug information.

[0035] The above configuration involves only bringing the input / output modules 20 within the main chip 11 out to the circuit board 10 via interface pins 21. In a multi-chip environment consisting of at least two chips, each chip can access the input / output modules 20. Furthermore, multiple chips use a time-division multiplexing method to output their respective debugging information via the interface pins 21, thereby enabling dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to the existing interconnection method where all input / output modules 20 within each chip are brought out to the circuit board 10 via pins, the method in this application eliminates the need for all input / output modules 20 within each chip to be brought out to the circuit board 10 via interface pins 21, significantly reducing the number of interface pins 21 and the amount of wiring required, thus greatly reducing costs.

[0036] When implementing time-division multiplexing of the input / output module 20 within the main chip 11, an identifier register can be built into the input / output module 20. This identifier register is used to write the logical number of the chip currently holding the right to use the input / output module 20. Each chip accesses the identifier register to obtain the logical number of the chip currently holding the right to use the input / output module 20. While each chip reads the identifier register and obtains the logical number of the chip currently holding the right to use the input / output module 20, each chip can also determine whether its own logical number is equal to the logical number of the chip currently holding the right to use the input / output module 20. If they are equal, each chip outputs its generated debugging information through interface pin 21. This facilitates notification to each chip which chip currently holds the right to use the input / output module 20.

[0037] The following is based on Figure 2 Taking an example, this paper introduces a time-multiplexed process for the main chip 11 and each slave chip 12 to output their respective debugging information. Initially, the main chip 11 is granted the right to use its input / output module 20 by default. The main chip 11 writes the target chip logic number that needs to use the input / output module 20 to the identifier register. Specifically, the main chip 11 can make a decision based on its firmware configuration to determine which chip has the right to use the input / output module 20. Afterwards, the main chip 11 writes the chip logic number corresponding to the chip that needs to use the input / output module 20 as the target chip logic number into the identifier register. Figure 4As shown, the chip logic number in the identifier register can be input by the computing unit 31 in the master chip 11 according to the firmware configuration in the control module 32. This allows the master chip 11 or slave chip 12 to actively modify the chip logic number in the identifier register during debugging, outputting the debugging information generated during their respective debugging processes. Simultaneously, both the master chip 11 and slave chip 12 prepare the debugging information to be output. After preparing the required debugging information, both the master chip 11 and slave chip 12 read the identifier register in the master chip 11 to obtain the chip logic number that currently has the right to use the input / output module 20. If the chip logic number that the master chip 11 or a certain slave chip 12 reads from the identifier register that currently has the right to use the input / output module 20 is not equal to its own chip logic number, it means that the chip currently does not have the right to use the input / output module 20 and cannot output the debugging information it generates; that is, no debugging information is input. If the logic number of the chip currently having the right to use the input / output module 20, read from the identifier register by the main chip 11 or a slave chip 12, is equal to its own logic number, then it means that the chip currently has the right to use the input / output module 20. In this case, debugging information will be output through the interface pin 21 on the circuit board 10, which connects the input / output module 20 within the main chip 11 to the external interface pin 20. (Reference) Figure 2 If the firmware configuration or hardware status remains unchanged, the chip logic number in the identifier register remains unchanged. If the firmware configuration or hardware status changes, the system re-determines which chip currently has the right to use the input / output module 20 and writes the corresponding chip logic number into the identifier register, thus changing the chip logic number in the identifier register. This allows the master chip 11 and each slave chip 12 to access the identifier register again, learn that the chip currently having the right to use the input / output module 20 has changed, and determine whether their respective chips currently have the right to use the input / output module 20, thereby determining whether to output debug information.

[0038] It should be understood that the main chip 11 is not limited to the method shown above of writing the target chip logic number to the identifier register according to its internal firmware configuration; other methods may also be used. For example, Figure 4In one embodiment, a debug interface 40 is also provided on the circuit board 10. The debug interface 40 is communicatively connected to the main chip 11. Through the debug interface 40, the target chip logic number requiring access to the input / output module 20 is input to the main chip 11. The main chip 11 then writes the target chip logic number received from the debug interface 40 into an identifier register, facilitating dynamic adjustment of the debug information output for a specific chip by the debugging engineer. Specifically, when inputting the target chip logic number through the debug interface 40, firmware containing the target chip logic number information can be input to the target chip logic number input interface, enabling the debug interface 40 to write the target chip logic number into the identifier register. For details on implementing the communication connection between the debug interface 40 and the main chip 11, refer to [reference needed]. Figure 4 The main chip 11 also has a built-in debugging module 41 that communicates with the debugging interface 40. The debugging module 41 is connected to the computing unit 31 within the main chip 11, so that the target chip logic number output by the debugging interface 40 is written into the identifier register by the computing unit 31 within the main chip 11. When setting the debugging interface 40, the debugging interface 40 can be a Universal Asynchronous Receiver / Transmitter (UART) interface or a JTAG interface. Correspondingly, the debugging module 41 can be a UART or a JTAG interface, which facilitates interaction with debugging engineers and dynamic adjustment of the chip logic number stored in the identifier register.

[0039] It should be noted that the method of initiating the writing of the chip logic number that currently has the right to use the input / output module 20 to the identifier register is not limited to the chip-side initiation method shown above. Other methods can also be used. For example, refer to... Figure 4 Furthermore, a general-purpose input / output interface 50 can be set on the circuit board 10. The general-purpose input / output interface 50 is connected to the identification register. The debugging engineer can write the target chip logic number that needs to have the right to use the input / output module 20 to the identification register through the general-purpose input / output interface 50. This makes it easy to output the target chip logic number to the identification register through different types of interfaces on the circuit board 10, thereby improving adaptability.

[0040] Additionally, a configuration selection register can be built into the input / output module 20. This register communicates with the general-purpose input / output interface 50 on the circuit board 10 to receive a first configuration instruction and a second configuration instruction generated by the debugging engineer. The first configuration instruction configures the main chip 11 or a slave chip 12 to write the chip logic number requiring access to the input / output module 20 to the identifier register. The second configuration instruction configures the general-purpose input / output interface 50 to write the target chip logic number requiring access to the input / output module 20 to the identifier register. In other words, the configuration instructions written to the configuration selection register can only be configured through the general-purpose input / output interface 50 on the circuit board 10. This takes into account the mutual exclusion between the target logic number written to the identifier register originating from the chip and from an external source, isolating the adjustment operation written to the identifier register from the chip and the adjustment operation of the target chip logic number input externally, thereby avoiding logical contradictions and confusion.

[0041] The various embodiments described above employ a method where only the input / output modules 20 within the main chip 11 are brought out to the circuit board 10 via interface pins 21. In a multi-chip environment consisting of at least two chips, each chip can access the input / output modules 20, and the multiple chips use a time-division multiplexing method to output their respective debugging information via the interface pins 21. This allows for the dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to the prior art interconnection method where the input / output modules 20 within each chip are brought out to the circuit board 10 via pins, the method in this application does not require the input / output modules 20 within each chip to be brought out to the circuit board 10 via interface pins 21, which can significantly reduce the number of interface pins 21 of the input / output modules 20 and the wiring, thereby significantly reducing costs.

[0042] Furthermore, embodiments of the present invention also provide a debugging system, see reference. Figure 1 and Figure 2The debugging system includes any of the aforementioned multi-chip interconnect devices and a debugging device communicatively connected to the interface pin 21. By only bringing the input / output modules 20 within the main chip 11 out to the circuit board 10 via the interface pin 21, in a multi-chip environment consisting of at least two chips, each chip can access the input / output module 20. Furthermore, multiple chips use a time-division multiplexing method to output their respective debugging information via the interface pin 21, thereby enabling dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared to the existing interconnection method where the input / output modules 20 within each chip are brought out to the circuit board 10 via pins, the method in this application eliminates the need for each chip's input / output modules 20 to be brought out to the circuit board 10 via the interface pin 21, significantly reducing the number of interface pins 21 and the wiring of the input / output modules 20, thus greatly reducing costs.

[0043] In addition, embodiments of the present invention also provide a debugging method based on any of the above-mentioned debugging systems, see reference. Figure 1 and Figure 2 The debugging method includes:

[0044] At least some or all of the two chips generate their respective debug information to be output;

[0045] Each chip accesses the input / output module 20 to output its own debugging information via interface pin 21 in a time-division multiplexing manner.

[0046] In the above solution, only the input / output modules 20 within the main chip 11 are brought out to the circuit board 10 via interface pins 21. In a multi-chip environment consisting of at least two chips, each chip can access the input / output modules 20, and multiple chips use a time-division multiplexing method to output their respective debugging information via interface pins 21. This allows for dynamic and efficient acquisition of the execution process debugging information of each chip in a multi-chip environment. Compared with the existing interconnection method where the input / output modules 20 within each chip are brought out to the circuit board 10 via pins, the method in this application does not require the input / output modules 20 within each chip to be brought out to the circuit board 10 via interface pins 21, which can significantly reduce the number of interface pins 21 of the input / output modules 20 and the wiring, thus significantly reducing costs.

[0047] As described above for multi-chip interconnect devices, an identification register can be built into the input / output module 20. This register is used to write the logical number of the chip currently having the right to use the input / output module 20. When each chip accesses the input / output module 20 to output its own debugging information via interface pin 21 in a time-division multiplexing manner, each chip can obtain the logical number of the chip currently having the right to use the input / output module 20 by accessing the identification register. After each chip obtains the logical number of the chip currently having the right to use the input / output module 20 by reading the identification register, each chip can determine whether its own logical number is equal to the logical number of the chip currently having the right to use the input / output module 20. If they are equal, each chip outputs its generated debugging information via interface pin 21. This facilitates notification to each chip which chip currently has the right to use the input / output module 20.

[0048] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-chip interconnect device, characterized in that, include: Circuit board; At least two chips disposed on the circuit board and interconnected via a chip interconnect bus, the at least two chips comprising a master chip and other slave chips; The main chip has a built-in input / output module, which is led out to the circuit board through interface pins. The main chip and each slave chip can access the input / output module to output their respective debugging information through the interface pins in a time-division multiplexing manner. The input / output module has a built-in identifier register, which is used to be written with the logic number of the chip that currently has the right to use the input / output module. Each chip obtains the chip logic number that currently has the right to use the input / output module by accessing the identification register; Each chip also determines whether its own chip logic number is equal to the chip logic number that currently has the right to use the input / output module, and if they are equal, outputs the debugging information generated by each chip through the interface pin; Each chip has a built-in control module and a computing unit; the computing unit is used to generate debugging information for its respective chip; the control module, input / output module and computing unit in the main chip are interconnected via a parallel bus, and the control module and computing unit in each slave chip are interconnected via a parallel bus; the chip interconnection bus is a serial bus; the control module in each chip is used to perform protocol conversion from parallel bus to serial bus.

2. The multi-chip interconnect device as described in claim 1, characterized in that, The main chip is also used to write the target chip logic number that needs to have the right to use the input / output module to the identifier register.

3. The multi-chip interconnect device as described in claim 2, characterized in that, The main chip, based on its firmware configuration, writes the target chip logic number that needs to have the right to use the input / output module into the identifier register.

4. The multi-chip interconnect device as described in claim 2, characterized in that, The circuit board is also equipped with a debugging interface; The debugging interface is communicatively connected to the main chip to input the target chip logic number that needs to have the right to use the input / output module to the main chip, so that the main chip writes the received target chip logic number into the identifier register.

5. The multi-chip interconnect device as described in claim 2, characterized in that, The circuit board is also equipped with a general-purpose input / output interface; The general-purpose input / output interface is communicatively connected to the identifier register to write the target chip logic number that needs to have the right to use the input / output module into the identifier register.

6. The multi-chip interconnect device as described in claim 5, characterized in that, The input / output module also has a built-in configuration selection register, which is communicatively connected to the general-purpose input / output interface to receive a first configuration instruction and a second configuration instruction. Wherein, the first configuration instruction is used to configure the main chip to write to the identifier register the chip logic number that needs to have the right to use the input / output module; the second configuration instruction is used to configure the general-purpose input / output interface to write to the identifier register the target chip logic number that needs to have the right to use the input / output module.

7. A debugging system, characterized in that, include: The multi-chip interconnect device as described in any one of claims 1 to 6; A debugging device that communicates with the interface pins.

8. A debugging method based on the debugging system of claim 7, characterized in that, include: Some or all of the at least two chips generate their respective debug information to be output; Each chip accesses the input / output module to output its own debugging information via the interface pins in a time-division multiplexing manner.

9. The debugging method as described in claim 8, characterized in that, The input / output module has a built-in identifier register, which is used to be written with the logic number of the chip that currently has the right to use the input / output module. Each chip accesses the input / output module to output its own debugging information via the interface pins in a time-division multiplexing manner, including: Each chip accesses the identifier register to obtain the chip logic number that currently has the right to use the input / output module; Each chip determines whether its own chip logic number is equal to the chip logic number that currently has the right to use the input / output module, and if they are equal, outputs the debugging information it generates through the interface pin.

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