Stacked electronic components

Abstract

The present invention relates to a laminated electronic component comprising: a substrate formed by laminating insulating layers and having a bottom surface serving as a mounting surface and a side surface extending in a manner intersecting the bottom surface; and a bottom electrode formed on the bottom surface of the substrate, the bottom electrode having a first electrode layer and a second electrode layer formed on a side of the substrate closer to the first electrode layer than the first electrode layer, the first electrode layer being a resin electrode laminated in a manner covering the second electrode layer, and having an extension extending along the side surface, the width of the extension being smaller than the width of the first electrode layer in the bottom surface.

Description

Technical Field

[0001] One aspect of this disclosure relates to a stacked electronic component. Background Technology

[0002] Japanese Patent Application Publication No. 2020-61409 discloses a laminated electronic component comprising: a substrate formed by laminating insulating layers and having a bottom surface serving as a mounting surface; and a bottom electrode formed on the bottom surface of the substrate. The bottom electrode comprises a first electrode layer and a second electrode layer formed closer to the substrate than the first electrode layer. In this structure, the edge of the second electrode layer is covered by an outer layer that is part of the substrate, and the first electrode layer is welded to the second electrode layer, which is simultaneously fired with the substrate. Summary of the Invention

[0003] In the aforementioned stacked electronic components, by setting the bottom electrode to a double-layer structure consisting of a first electrode layer and a second electrode layer, the generation of cracks in the substrate is suppressed. Conversely, sometimes stress on the bottom electrode is mitigated by covering the second electrode layer with a resin electrode. However, resin electrodes have low plating properties, therefore, it is necessary to ensure the electrode area. On the other hand, if the electrode area outside the bottom surface is excessively increased, the amount of solder on the bottom side will decrease. In this case, a problem arises where stress easily acts on the bottom electrode during installation.

[0004] One aspect of this disclosure is to provide a laminated electronic component that can ensure the plating properties of the bottom electrode and suppress the generation of cracks in the substrate.

[0005] The laminated electronic component according to one aspect of this disclosure includes: a substrate formed by laminating insulating layers and having a bottom surface as a mounting surface and a side surface extending in a manner intersecting with the bottom surface; and a bottom electrode formed on the bottom surface of the substrate, the bottom electrode having a first electrode layer and a second electrode layer formed on a side of the substrate closer to the first electrode layer than the first electrode layer, the first electrode layer being a resin electrode laminated in a manner covering the second electrode layer, and having an extension extending along the side surface, the width of the extension being smaller than the width of the first electrode layer in the bottom surface.

[0006] In a laminated electronic component, the bottom electrode includes a first electrode layer and a second electrode layer formed closer to the substrate than the first electrode layer. Here, the first electrode layer is a resin electrode laminated to cover the second electrode layer. By using a resin electrode as the bottom electrode, stress relative to the bottom electrode can be mitigated. The first electrode layer has an extension extending along its side. Therefore, by increasing the electrode area of ​​the resin electrode, plating performance can be improved. Furthermore, the width of the extension is smaller than the width of the first electrode layer in the bottom surface. That is, the width of the first electrode layer in the bottom surface requiring solder is larger than the width of the extension on the side. Therefore, it is possible to suppress the attraction of solder from the bottom surface to the extension side, thus suppressing the reduction of solder amount in the bottom surface. Therefore, the distance between the bottom electrode and the mounting substrate can be ensured by the solder thickness, thus suppressing stress from the mounting substrate to the bottom electrode. Based on the above, plating performance of the bottom electrode can be ensured, and the generation of cracks in the substrate can be suppressed.

[0007] Alternatively, the extension can be positioned on the side surface, separating from the upper surface opposite the bottom surface. In this case, the extension is interrupted before reaching the upper surface, thus allowing for a further reduction in the area of ​​the extension. Consequently, the amount of solder attracted to the side surface by the extension can be further reduced.

[0008] Alternatively, the edge of the second electrode layer may be covered by an outer layer that is part of the substrate. Thus, in the event of stress concentration near the end of the bottom electrode, the stress is dispersed to the outer layer via the boundary between the first electrode layer and the outer layer.

[0009] According to one aspect of this disclosure, it is possible to provide a laminated electronic component that can ensure the plating properties of the bottom electrode and suppress the generation of cracks in the substrate. Attached Figure Description

[0010] Figure 1 This is a perspective view of a stacked electronic component according to an embodiment of the present disclosure.

[0011] Figure 2 It will be along Figure 1 The enlarged cross-sectional view near the bottom electrode in the cross-sectional view along line II-II shown is an enlarged cross-sectional view.

[0012] Figure 3 An example of the structure showing the internal electrodes and through-hole conductors inside the substrate.

[0013] Figure 4 This is a schematic three-dimensional view of the first electrode layer.

[0014] Figure 5 This is an enlarged cross-sectional view showing the structure near the bottom electrode during the formation of the outer coating layer.

[0015] Figure 6 of (a), Figure 6 (b) is a schematic diagram showing the changes in the extension.

[0016] Figure 7 of (a), Figure 7 (b) is a schematic diagram showing the changes in the extension.

[0017] Figure 8 of (a), Figure 8 (b) is a schematic diagram showing the changes in the extension.

[0018] Figure 9 It is a process diagram showing the manufacturing method of stacked electronic components.

[0019] Figure 10 of (a), Figure 10 (b) and Figure 10 (c) is a schematic diagram showing the various stages of the manufacturing process of the stacked electronic components.

[0020] Figure 11 of (a), Figure 11 (b) and Figure 11 (c) is a schematic diagram showing the various stages of the manufacturing process of the stacked electronic components.

[0021] Figure 12 This is a table representing the test results.

[0022] Explanation of symbols:

[0023] 1…Layered electronic components, 2…Base body, 3…Bottom electrode, 5…Outer layer, 11…First electrode layer, 12…Second electrode layer, 25…Extension. Detailed Implementation

[0024] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the description, the same symbols are used for the same elements or elements having the same function, and repeated descriptions are omitted.

[0025] Figure 1 This is a perspective view of the stacked electronic component 1 according to an embodiment of the present disclosure. Figure 2 It will be along Figure 1 The enlarged cross-sectional view near the bottom electrode 3 in the cross-sectional view along line II-II shown is an example of this. Figure 1 As shown, the stacked electronic component 1 has a body 2 and multiple bottom electrodes 3.

[0026] As described below, the base body 2 is formed by stacking multiple insulating layers. The base body 2 has a cuboid shape. This cuboid shape includes both cuboids with chamfered corners and edges, and cuboids with rounded corners and edges. The base body 2 has a top surface 2A, a bottom surface 2B serving as a mounting surface, and four side surfaces 2C, 2D, 2E, and 2F as its outer surfaces. The top surface 2A and bottom surface 2B are opposite to each other. Side surfaces 2C and 2D are opposite to each other. Side surfaces 2E and 2F are opposite to each other. Side surfaces 2C to 2F extend along the stacking direction (the direction of the stacked insulating layers) of the top surface 2A and bottom surface 2B, and are adjacent to the top surface 2A and bottom surface 2B. In the base body 2, the top surface 2A and bottom surface 2B are located at opposite ends of the stacking direction. The material of the base body 2 (the material of the insulating layer) is not particularly limited. For example, Al2O3, SiO2, 2MgO·SiO2, xBaO·yNdO·zTiO2, (Ca,Sr)TiO2, etc., can be used. Furthermore, terms such as "upper" and "bottom" in this specification are used for ease of explanation and do not limit the orientation of the stacked electronic component 1. For example, the stacked electronic component 1 can be mounted with its upper surface 2A facing horizontally or downwards.

[0027] Bottom electrode 3 is an electrode disposed on the bottom surface 2B of the substrate 2. Viewed from the stacking direction, bottom electrode 3 has a rectangular shape. Figure 1 In the example shown, six bottom electrodes 3 are formed. These bottom electrodes 3 have the same shape. Three bottom electrodes 3 are arranged parallel to each other along the long side 2C at a position near one side extending along the long side 2C. The other three bottom electrodes 3 are arranged parallel to each other along the long side 2D at a position near another side extending along the long side 2D. Furthermore, the number of bottom electrodes 3 can be appropriately varied according to the application of the stacked electronic component 1. Another example of the shape and number of bottom electrodes 3 will be described later.

[0028] like Figure 2 As shown, the substrate 2 is constructed by stacking multiple insulating layers 4. Furthermore, multiple internal electrodes 6 and through-hole conductors 7 are formed inside the substrate 2. The substrate 2 is formed by stacking and firing sheets of insulating layers 4 on which conductor patterns of internal electrodes 6 are formed on the surface. The through-hole conductors 7 are conductors that penetrate each insulating layer 4 and connect the internal electrodes 6 formed on other insulating layers 4 to each other. Additionally, the through-hole conductors 7 connect the internal electrodes 6 and the bottom electrode 3. Furthermore, the boundaries between the insulating layers 4 are integrated to a degree that is not visually visible.

[0029] Figure 3 This is an example showing the structure of the internal electrode 6 and the through-hole conductor 7 inside the body 2. For example... Figure 3As shown, a circuit 8 performing a specified function is formed by three-dimensionally combining multiple internal electrodes 6 and multiple through-hole conductors 7 inside the substrate 2. Figure 3 The circuit 8 of the directional coupler is shown as an example. Multiple bottom electrodes 3 are electrically connected to the circuit 8. Thus, the circuit 8 and the external mounting substrate are connected via the bottom electrodes 3.

[0030] Next, the structure of the bottom electrode 3 will be described in detail. For example... Figure 2 As shown, the bottom electrode 3 includes a first electrode layer 11 and a second electrode layer 12. The first electrode layer 11 is formed to expose outwards from the bottom surface 2B. The first electrode layer 11 is formed by curing a conductive resin material containing conductive powder dispersed in a thermosetting resin relative to the base body 2 (and the second electrode layer 12) after firing the base body 2, for example, by heat treatment. Specific examples of resin materials will be described later. The first electrode layer 11 is electrically connected to an external mounting substrate via solder 16. Therefore, a plating layer 14 for improving the wettability of the solder is formed on the outer surface of the first electrode layer 11. The second electrode layer 12 is formed on the side of the base body 2 closer to the first electrode layer 11. The second electrode layer 12 is formed in such a way that it is embedded into the interior of the base body 2, and is formed by firing it simultaneously with the base body 2.

[0031] Furthermore, in the following explanations, with Figure 5 In the cross-section shown, sometimes the direction of the extension of the bottom electrode 3 is defined as the first direction D1, and the direction along the thickness of the bottom electrode 3 is defined as the second direction D2.

[0032] The second electrode layer 12 extends within the substrate 2 along the first direction D1. The second electrode layer 12 is positioned at a location separated from the side 2D along the first direction. The material of the second electrode layer 12 will be described. The second electrode layer 12 is composed of a conductive material comprising glass and sintered metal. Examples of sintered metals include Ag, Cu, Au, Pt, Pd, and their alloys. Additionally, the second electrode layer 12 may contain trace amounts of metal oxides as other inorganic components. The glass softening point of the second electrode layer 12 is 810–860°C. The glass content of the second electrode layer 12 is 3.8–10.0 wt%. Thus, by increasing the softening point of the second electrode layer 12 and reducing the amount of glass added, sintering matching with the substrate 2 can be achieved. Sintering matching balances the suppression of bending of the substrate 2 with the high density of the electrode (e.g., the electrical properties of the product, and the prevention of plating solution intrusion).

[0033] The first electrode layer 11 is a resin electrode stacked on top of the second electrode layer 12. The resin electrode contains (dispersed) conductive powder in resin. Examples of resin materials used for the resin electrode include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin. Examples of conductive powder materials used for the resin electrode include Ag and Cu. The first electrode layer 11 has a bottom portion 24 formed on the bottom surface 2B and an extension portion 25 extending along the side surface 2C. The bottom portion 24 covers the second electrode layer 12 from the bottom side and extends along the first direction D1 from the bottom surface 2B. The bottom portion 24 extends to the corner 2G between the side surface 2C and the bottom surface 2B. The extension portion 25 is electrically connected to the bottom portion 24, extending upwards from the bottom surface 2B and along the side surface 2C. The extension portion 25 is connected to the bottom portion 24 via the corner 2G.

[0034] Reference Figure 4 The first electrode will be described in more detail. Furthermore, in the following description, terms such as "width" will be used based on the view from side 2C. The bottom surface 24 is a quadrilateral shape with four sides, parallel to the sides of the bottom surface 2B (see also...). Figure 1 The extension 25 is configured as a quadrilateral shape with four sides, parallel to the sides of the side 2C (see also...). Figure 1 The bottom surface 24 has a width dimension W1 and a length dimension L1 extending from the side surface 2C toward the interior of the body 2. The extension 25 has a width dimension W2 and a height dimension H from the bottom surface 2B. Furthermore, a narrow portion 26 with a width dimension W2 is formed in the region of length dimension L2 near the side surface 2C.

[0035] The width W2 of the extension 25 is smaller than the width W1 of the first electrode layer 11 in the bottom surface 2B. Specifically, the width W1 is set to a range of 0.1 to 1.0 mm. In contrast, the width W2 is preferably set to be 30% or more, more preferably 40% or more, relative to the width W1. The width W2 is preferably set to be 90% or less, more preferably 70% or less, relative to the width W1. The extension 25 is positioned at the center of the range within the width W1 relative to the bottom surface 24, but it can also be positioned anywhere. The length L1 of the bottom surface 24 is set to a range of 0.15 to 0.50 mm. The length L2 of the narrow width portion 26 is set to a range of 0.01 to 0.20 mm.

[0036] The extension 25 is disposed in the side surface 2C (2D) at a position separated from the upper surface 2A opposite to the bottom surface 2B (see reference). Figure 1That is, the upper end portion 25a of the extension 25 does not reach the upper surface 2A, and the extension 25 is interrupted midway along the side 2C. The height dimension H of the extension 25 is not particularly limited, but from the viewpoint of improving plating performance, it is preferably 30% or more, more preferably 40% or more, relative to the dimension in the stacking direction of the substrate 2. Furthermore, the upper limit of the height dimension H is not particularly limited, and it can be 100% or less relative to the dimension in the stacking direction of the substrate 2. Furthermore, from the viewpoint of suppressing the height dimension H and reducing the area of ​​the extension 25, the height dimension H of the extension 25 relative to the dimension in the stacking direction of the substrate 2 is preferably 100% or less, more preferably 70% or less. The thickness of the bottom surface 24 and the extension 25 is set to 5 to 50 μm. The thickness of the bottom surface 24 and the thickness of the extension 25 can be the same or different from each other.

[0037] like Figure 5 As shown, the edge 22 of the second electrode layer 12 can be covered by the outer layer 5, which is part of the substrate 2. Specifically, the second electrode layer 12 has a main body 21 and an edge 22 formed on the outer periphery in the first direction D1. The edge 22 of the second electrode layer 12 is covered by the outer layer 5, which is part of the substrate 2. The upper surface 22a of the edge 22 in the second direction D2 contacts the insulating layer 4 of the substrate 2. The lower surface 22b of the edge 22 in the second direction D2 contacts the outer layer 5 of the substrate 2. Thus, the edge 22 is embedded into the interior of the substrate 2 in such a way that it is held between the insulating layer 4 and the outer layer 5. The edge 22 is formed such that it slopes upward from the outer periphery in the first direction D1 towards the upper side in the second direction D2 and tapers at its tip. Therefore, the lower surface 22b of the edge 22 separates upward from the bottom surface 2B as it moves away from the main body 21 in the first direction D1.

[0038] With the structure described above, the thickness of the outer layer 5, which contacts the surface 22b of the edge portion 22, increases as it extends from the main body portion 21 toward the outer periphery in the first direction D1. Thus, the outer layer 5 has a region that is embedded into the bottom side of the edge portion 22 and supports the surface 22a. This region constitutes a covering portion 23 that covers the edge portion 22. The covering portion 23 tapers at its tip as it moves toward the main body portion 21 in the second direction D2. The main body portion 21 of the second electrode layer 12 is configured to protrude from the covering portion 23. Furthermore, the positions of the upper surface 22a and the bottom surface 22b at the ends 12a of the second electrode layer 12 in the first direction D1 intersect each other.

[0039] The bottom surface 24 of the first electrode layer 11 is stacked on the second electrode layer 12 while the outer coating layer 5 is being held in place. As described above, the outer coating layer 5 covers the edge 22 of the second electrode layer 12 with the covering portion 23. The first electrode layer 11 is formed to cover the main body 21 of the second electrode layer 12 and the outer surface (i.e., the bottom surface 2B) of the outer coating layer 5 from the bottom side. Therefore, the covering portion 23 of the outer coating layer 5 is arranged between the bottom surface 22b of the edge 22 of the second electrode layer 12 and the first electrode layer 11 in a manner that holds the outer coating layer 5. Furthermore, even when the outer coating layer 5 is formed on the substrate 2, the first electrode layer 11 is also attached to the substrate 2. Figure 2 Similarly, it has an extension 25.

[0040] The shape, size, and arrangement of the bottom electrode 3 in the bottom surface 2B are not particularly limited; for example, it can also be used as follows: Figures 6-8 The structure shown is as described. Furthermore, the structure of the extension 25 of each bottom electrode 3 can be appropriately modified. Additionally, in... Figures 6-8 In the diagram, a bottom view showing the bottom surface 2B is shown in the center; a side view showing the side surface 2D extending along the long side is shown below the bottom view; and a side view showing the side surface 2E extending along the short side is shown to the right of the bottom view. Furthermore, the situation for side surface 2F is the same as for side surface 2E, and the situation for side surface 2C is the same as for side surface 2D. Figures 6-8 As shown, small bottom electrodes 3C and 3D are formed near sides 2C and 2D. Large bottom electrodes 3E and 3F are formed near sides 2E and 2F.

[0041] Figure 6 In the example shown in (a), extensions 25 extending from the bottom electrodes 3C and 3D to the upper surface 2A are formed on sides 2C and 2D. Width-enhanced extensions 25 extending from the bottom electrodes 3E and 3F to the upper surface 2A are formed on sides 2E and 2F. Figure 6 In the example shown in (b), extensions 25 extending from the bottom electrodes 3C and 3D to the upper surface 2A are formed on the sides 2C and 2D. Narrow extensions 25 extending from the bottom electrodes 3E and 3F to the upper surface 2A are formed on the sides 2E and 2F.

[0042] exist Figure 7 In the example shown in (a), extensions 25 extending from the bottom electrodes 3C and 3D to the upper surface 2A are formed on sides 2C and 2D. Width-enhanced extensions 25 extending from the bottom electrodes 3E and 3F to the upper surface 2A are formed on sides 2E and 2F. Figure 7 In the example shown in (b), extensions 25 extending from the bottom electrodes 3C and 3D to the upper surface 2A are formed on the sides 2C and 2D. Width-enhanced extensions 25 extending from the bottom electrodes 3E and 3F to the upper surface 2A are formed on the sides 2E and 2F.

[0043] exist Figure 8 In the example shown in (a), extensions 25 extending from the bottom electrodes 3C and 3D to the upper surface 2A are formed on sides 2C and 2D. Two narrow extensions 25, divided into two sections, extend from the bottom electrodes 3E and 3F to the upper surface 2A on sides 2E and 2F. Figure 8 In the example shown in (b), two divided extensions 25 are formed on the sides 2C and 2D, extending from the bottom electrodes 3C and 3D to the upper surface 2A. Two narrow extensions 25 are formed on the sides 2E and 2F, extending from the bottom electrodes 3E and 3F to the upper surface 2A.

[0044] Next, refer to Figures 9-11 The manufacturing method of the stacked electronic component 1 will be described. Figure 9 This is a process diagram illustrating the manufacturing method of the stacked electronic component 1. Figure 10 and Figure 11 This is a schematic diagram illustrating the various stages of the manufacturing method for the stacked electronic component 1. Furthermore, in Figure 10 and Figure 11 The example shown is when there are four bottom electrodes 3. Figure 10 The upper side view of (a)(b)(c) represents the top view, and the lower side view represents the side view. Figure 11 (c) indicates that with Figures 6-8 The same graph shows the same performance. Furthermore, Figures 9-11 Explanation as with Figure 5 The manufacturing method for forming the corresponding outer layer 5.

[0045] like Figure 9 As shown, firstly, a process for forming the insulating layer 4 sheet is performed (step S10). In this process, a sheet is formed by coating a paste constituting the insulating layer 4 onto a substrate sheet 30 such as a PET film (see reference). Figure 10 (a) Next, a process is performed to form the second electrode layer 12 of the bottom electrode 3 by screen printing on the sheet of insulating layer 4 (step S20). In this process, paste is screen printed on the outer surface of insulating layer 4 into a shape corresponding to the second electrode layer 12 (see reference). Figure 10 (b)). Furthermore, at this time, internal electrodes 6 are printed on the sheets of the other insulating layers 4. Next, a process is performed to form an outer layer 5 by screen printing on the outer surface of the insulating layer 4 (step S30). In this process, paste is screen printed on the outer surface of the insulating layer 4 into a shape corresponding to the outer layer 5 (see reference). Figure 10 (c) At this time, the outer layer 5 is printed in such a way that it covers the edge of the second electrode layer 12, and is pressed after printing.

[0046] Next, a process is performed to fabricate a sheet laminate substrate 40, which serves as the base material 2 before sintering, by laminating the printed insulating layer 4. Each insulating layer 4 is laminated onto the sheet laminate substrate 40 with the outermost layer being the outermost layer (see step S40). Figure 11 (a) Next, the sheet laminate substrate 40 is cut into a specified size by a cutting machine or a knife, and then chamfered by a green roller (step S50). Next, the sheet laminate substrate 40 is sintered to form the substrate 2, and then sintered and polished by a roller (step S60). Through these steps, a substrate 2 with a corner R is formed (see reference). Figure 11 (b)

[0047] Next, in order to perform screen printing on the bottom surface 2B, a process of neatly arranging the substrates 2 is performed (step S70). Then, a process of forming the bottom surface 24 of the first electrode layer 11 by screen printing resin electrodes on the bottom surface 2B of the substrates 2 is performed (step S80). In this process, in order to cover the second electrode layer 12, a process of forming the bottom surface 24 of the first electrode layer 11 on the bottom surface 2B by screen printing is performed (see reference). Figure 11 (c) of “A1”). Next, in order to perform screen printing on the sides 2C and 2D, a process of neatly arranging the substrate 2 is performed (step S90). Then, a process of forming the extension 25 of the first electrode layer 11 by screen printing resin electrodes on the sides 2C and 2D of the substrate 2 is performed (step S100). In this process, the process of forming the extension 25 of the first electrode layer 11 on the sides 2C and 2D by screen printing is performed (see Figure 11 (c) of “A2”). Next, in order to perform screen printing on the sides 2E and 2F, a process of arranging the substrate 2 neatly is performed (step S110). Then, a process of forming the extension 25 of the first electrode layer 11 by screen printing resin electrodes on the sides 2E and 2F of the substrate 2 is performed (step S120). In this process, the process of forming the extension 25 of the first electrode layer 11 on the sides 2E and 2F by screen printing is performed (see Figure 11 (c) of “A3”). The first electrode layer 11 is formed by curing a conductive resin material through heat treatment. Next, a process is performed to form a plating layer 14 by plating the outer surface of the first electrode layer 11 (step S130).

[0048] Furthermore, in the case of manufacturing a laminated electronic component 1 without an outer coating layer 5, step S30 is omitted. Therefore, in Figure 10 Press the second electrode layer in the state shown in (b), thereby entering the interior of the insulating layer 4.

[0049] Next, the function and effects of the stacked electronic component 1 in this embodiment will be explained.

[0050] In the stacked electronic component 1, the bottom electrode 3 includes a first electrode layer 11 and a second electrode layer 12 formed on the side closer to the substrate 2 than the first electrode layer 11. Here, the first electrode layer 11 is a resin electrode stacked to cover the second electrode layer 12. In this way, by using a resin electrode as the bottom electrode 3, the stress relative to the bottom electrode 3 can be mitigated. The first electrode layer 11 has an extension 25 extending along the side surfaces 2C, 2D, 2E, and 2F. Therefore, by increasing the electrode area of ​​the resin electrode, the plating performance can be improved. Specifically, during electroplating, the electrode of the stacked electronic component 1 is energized by contacting the cathode with a metallic medium in the solution of the drum. That is, the higher the contact probability between the medium and the electrode, the higher the frequency of energization, resulting in a higher plating efficiency. When using a resin electrode, the proportion of non-metallic (resin) on the electrode surface increases, and therefore the plating efficiency tends to decrease. However, in this embodiment, the electrode area can be increased by using the extension 25, thus improving the plating efficiency.

[0051] Furthermore, the width W2 of the extension 25 is smaller than the width W1 of the first electrode layer 11 in the bottom surface 2B. That is, the width W1 of the first electrode layer 11 in the bottom surface 2B where solder 16 is required is larger than the width W2 of the extension 25 in the sides 2C, 2D, 2E, and 2F. Therefore, it is possible to suppress the solder 16 in the bottom surface 2B from being attracted to the extension 25 in the sides 2C, 2D, 2E, and 2F, and thus, it is possible to suppress the reduction of the amount of solder in the bottom surface 2B. Therefore, the distance between the bottom electrode 3 and the mounting substrate can be ensured by the thickness of the solder 16, and thus, stress from the mounting substrate to the bottom electrode 3 can be suppressed. Based on the above, the plating performance of the bottom electrode 3 can be ensured, and the generation of cracks in the substrate 2 can be suppressed.

[0052] The extension 25 can be positioned in one of the sides 2C, 2D, 2E, or 2F, separated from the upper surface 2A opposite to the bottom surface 2B. In this case, the extension 25 is interrupted before reaching the upper surface 2A, thus further reducing the area of ​​the extension 25. Therefore, the amount of solder 16 attracted to the sides 2C, 2D, 2E, or 2F can be further reduced using the extension 25.

[0053] The edge 22 of the second electrode layer 12 can be covered by the outer layer 5, which is part of the substrate 2. As a result, in the event of stress concentration near the end of the bottom electrode 3, the stress is dispersed to the outer layer 5 via the boundary between the first electrode layer 11 and the outer layer 5.

[0054] Next, refer to Figure 12The thermal shock test of the stacked electronic component relative to the embodiment and the comparative example is explained. As a comparative example, the stacked electronic component is prepared by omitting the first electrode layer 11. Therefore, the extension 25 is not formed in the comparative example. Furthermore, in the embodiment, as... Figure 5 As shown, a structure is obtained in which the bottom portion 24 of the first electrode layer 11 of the resin electrode and a portion of the outer coating layer 5 are sandwiched between the second electrode layer 12. Additionally, as... Figure 2 The extension 25, as shown, extends laterally. These stacked electronic components are connected to the substrate via solder, and subjected to repeated heating and cooling at -40°C to 125°C. Each temperature is maintained for 30 minutes. A thermal shock test is then performed under these conditions. For the eight bottom electrodes, the occurrence of substrate cracks (cracks in the base material 2), terminal damage (peeling of the plating from the bottom electrode, etc.), and solder cracks are observed. The defects observed in several of the eight bottom electrodes are counted. The test results are presented in… Figure 12 As shown in the image.

[0055] like Figure 12 As shown, in the comparative examples, substrate cracking and terminal failure were confirmed at various cycle numbers. Furthermore, as substrate cracks, cracks extending upwards from the stress concentration point at the corner of the bottom electrode and the insulating layer, resulting in insulation layer failure, and cracks extending along the boundary between the bottom electrode and the insulating layer from the stress concentration point were observed. As terminal failure, peeling between the electrode and the plating was confirmed. Additionally, in the comparative examples, more solder cracks were confirmed than in the embodiments. As solder cracks, cracks indicating internal solder damage were confirmed. In contrast, in the embodiments, it was confirmed that even with high cycle numbers, substrate cracking and terminal failure could be prevented. Furthermore, it was confirmed that solder cracking could be suppressed at low cycle numbers.

Claims

1. A stacked electronic component, wherein, have: The base body, formed by stacking insulating layers, has a bottom surface serving as a mounting surface and side surfaces extending in a manner intersecting with the bottom surface; and Bottom electrode, which is formed on the bottom surface of the substrate. The bottom electrode has a first electrode layer and a second electrode layer formed on the body side further than the first electrode layer. The first electrode layer is a resin electrode stacked in a manner that covers the second electrode layer, and has an extension extending along the side. The width of the extension is smaller than the width of the first electrode layer in the bottom surface. The second electrode layer is not disposed in the extension.

2. The stacked electronic component according to claim 1, wherein, The extension is positioned on the side surface at a location separated from the upper surface opposite the bottom surface.

3. The stacked electronic component according to claim 1 or 2, wherein, The edge of the second electrode layer is covered by an outer layer that is part of the substrate.

4. The stacked electronic component according to claim 1 or 2, wherein, The second electrode layer does not contain resin.

Images